Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
spi: sh-msiof: SITMDR1/SIRMDR1 bitfield conversion
Convert MSIOF Transmit and Receive Mode Register 1 field accesses to use
the FIELD_PREP() bitfield access macro.
This gets rid of explicit shifts.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/9685c54e752b8ef4256c9b281e9d8292e71d222e.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>
authored by
Geert Uytterhoeven
and committed by
Mark Brown
6bae252a
74cb19c9
+24
-21
+24
-21
drivers/spi/spi-sh-msiof.c
+24
-21
drivers/spi/spi-sh-msiof.c
···
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* Copyright (C) 2014-2017 Glider bvba
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*/
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#include <linux/bitfield.h>
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#include <linux/bitmap.h>
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#include <linux/clk.h>
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#include <linux/completion.h>
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/* SITMDR1 and SIRMDR1 */
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#define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */
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#define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */
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#define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */
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#define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */
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#define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */
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#define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */
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#define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */
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#define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */
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#define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
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#define SIMDR1_FLD_SHIFT 2
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#define SIMDR1_SYNCMD GENMASK(29, 28) /* SYNC Mode */
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#define SIMDR1_SYNCMD_SPI 2U /* Level mode/SPI */
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#define SIMDR1_SYNCMD_LR 3U /* L/R mode */
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#define SIMDR1_SYNCAC BIT(25) /* Sync Polarity (1 = Active-low) */
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#define SIMDR1_BITLSB BIT(24) /* MSB/LSB First (1 = LSB first) */
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#define SIMDR1_DTDL GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
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#define SIMDR1_SYNCDL GENMASK(18, 16) /* Frame Sync Signal Timing Delay */
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#define SIMDR1_FLD GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */
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#define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */
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/* SITMDR1 */
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#define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */
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#define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */
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#define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
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#define SITMDR1_SYNCCH GENMASK(27, 26) /* Sync Signal Channel Select */
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/* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
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/* SITMDR2 and SIRMDR2 */
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#define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */
···
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return 0;
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}
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val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
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val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
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val = FIELD_PREP(SIMDR1_DTDL, sh_msiof_get_delay_bit(p->info->dtdl)) |
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FIELD_PREP(SIMDR1_SYNCDL,
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sh_msiof_get_delay_bit(p->info->syncdl));
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return val;
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}
···
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* 1 0 11 11 0 0
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* 1 1 11 11 1 1
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*/
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tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
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tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
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tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
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tmp = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_SPI) |
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FIELD_PREP(SIMDR1_FLD, 1) | SIMDR1_XXSTP |
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FIELD_PREP(SIMDR1_SYNCAC, !cs_high) |
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FIELD_PREP(SIMDR1_BITLSB, lsb_first);
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tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
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if (spi_controller_is_target(p->ctlr)) {
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sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
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} else {
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sh_msiof_write(p, SITMDR1,
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tmp | SIMDR1_TRMD | SITMDR1_PCON |
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(ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
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FIELD_PREP(SITMDR1_SYNCCH,
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ss < MAX_SS ? ss : 0));
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}
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if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
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/* These bits are reserved if RX needs TX */
···
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return 0;
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/* Configure native chip select mode/polarity early */
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clr = SIMDR1_SYNCMD_MASK;
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set = SIMDR1_SYNCMD_SPI;
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clr = SIMDR1_SYNCMD;
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set = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_SPI);
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if (spi->mode & SPI_CS_HIGH)
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clr |= BIT(SIMDR1_SYNCAC_SHIFT);
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clr |= SIMDR1_SYNCAC;
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else
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set |= BIT(SIMDR1_SYNCAC_SHIFT);
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set |= SIMDR1_SYNCAC;
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pm_runtime_get_sync(&p->pdev->dev);
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tmp = sh_msiof_read(p, SITMDR1) & ~clr;
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sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);