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arm64: tlb: Introduce __tlbi_sync_s1ish_{kernel,batch}() for TLB maintenance

Add __tlbi_sync_s1ish_kernel() similar to __tlbi_sync_s1ish() and use it
for kernel TLB maintenance. Also use this function in flush_tlb_all()
which is only used in relation to kernel mappings. Subsequent patches
can differentiate between workarounds that apply to user only or both
user and kernel.

A subsequent patch will add mm_struct to __tlbi_sync_s1ish(). Since
arch_tlbbatch_flush() is not specific to an mm, add a corresponding
__tlbi_sync_s1ish_batch() helper.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Will Deacon <will@kernel.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

+16 -4
+16 -4
arch/arm64/include/asm/tlbflush.h
··· 191 191 __repeat_tlbi_sync(vale1is, 0); 192 192 } 193 193 194 + static inline void __tlbi_sync_s1ish_batch(void) 195 + { 196 + dsb(ish); 197 + __repeat_tlbi_sync(vale1is, 0); 198 + } 199 + 200 + static inline void __tlbi_sync_s1ish_kernel(void) 201 + { 202 + dsb(ish); 203 + __repeat_tlbi_sync(vale1is, 0); 204 + } 205 + 194 206 /* 195 207 * Complete broadcast TLB maintenance issued by hyp code which invalidates 196 208 * stage 1 translation information in any translation regime. ··· 311 299 { 312 300 dsb(ishst); 313 301 __tlbi(vmalle1is); 314 - __tlbi_sync_s1ish(); 302 + __tlbi_sync_s1ish_kernel(); 315 303 isb(); 316 304 } 317 305 ··· 397 385 */ 398 386 static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) 399 387 { 400 - __tlbi_sync_s1ish(); 388 + __tlbi_sync_s1ish_batch(); 401 389 } 402 390 403 391 /* ··· 580 568 dsb(ishst); 581 569 __flush_tlb_range_op(vaale1is, start, pages, stride, 0, 582 570 TLBI_TTL_UNKNOWN, false, lpa2_is_enabled()); 583 - __tlbi_sync_s1ish(); 571 + __tlbi_sync_s1ish_kernel(); 584 572 isb(); 585 573 } 586 574 ··· 594 582 595 583 dsb(ishst); 596 584 __tlbi(vaae1is, addr); 597 - __tlbi_sync_s1ish(); 585 + __tlbi_sync_s1ish_kernel(); 598 586 isb(); 599 587 } 600 588