Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Modify xgmi block to fit for the unified ras block data and ops
1.Modify gmc block to fit for the unified ras block data and ops.
2.Change amdgpu_xgmi_ras_funcs to amdgpu_xgmi_ras, and the corresponding variable name remove _funcs suffix.
3.Remove the const flag of gmc ras variable so that gmc ras block can be able to be inserted into amdgpu device ras block link list.
4.Invoke amdgpu_ras_register_ras_block function to register gmc ras block into amdgpu device ras block link list.
5.Remove the redundant code about gmc in amdgpu_ras.c after using the unified ras block.
Signed-off-by: yipechai <YiPeng.Chai@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: John Clements <john.clements@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
yipechai
and committed by
Alex Deucher
6c245386
8b0fb0e9
+37
-30
+8
-8
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+8
-8
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
···
454
454
return r;
455
455
}
456
456
457
-
if (!adev->gmc.xgmi.connected_to_cpu)
458
-
adev->gmc.xgmi.ras_funcs = &xgmi_ras_funcs;
457
+
if (!adev->gmc.xgmi.connected_to_cpu) {
458
+
adev->gmc.xgmi.ras = &xgmi_ras;
459
+
amdgpu_ras_register_ras_block(adev, &adev->gmc.xgmi.ras->ras_block);
460
+
}
459
461
460
-
if (adev->gmc.xgmi.ras_funcs &&
461
-
adev->gmc.xgmi.ras_funcs->ras_late_init) {
462
-
r = adev->gmc.xgmi.ras_funcs->ras_late_init(adev);
462
+
if (adev->gmc.xgmi.ras && adev->gmc.xgmi.ras->ras_block.ras_late_init) {
463
+
r = adev->gmc.xgmi.ras->ras_block.ras_late_init(adev, NULL);
463
464
if (r)
464
465
return r;
465
466
}
···
506
505
adev->mmhub.ras_funcs->ras_fini)
507
506
adev->mmhub.ras_funcs->ras_fini(adev);
508
507
509
-
if (adev->gmc.xgmi.ras_funcs &&
510
-
adev->gmc.xgmi.ras_funcs->ras_fini)
511
-
adev->gmc.xgmi.ras_funcs->ras_fini(adev);
508
+
if (adev->gmc.xgmi.ras && adev->gmc.xgmi.ras->ras_block.ras_fini)
509
+
adev->gmc.xgmi.ras->ras_block.ras_fini(adev);
512
510
513
511
if (adev->hdp.ras_funcs &&
514
512
adev->hdp.ras_funcs->ras_fini)
+4
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+4
-7
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
···
29
29
#include <linux/types.h>
30
30
31
31
#include "amdgpu_irq.h"
32
+
#include "amdgpu_ras.h"
32
33
33
34
/* VA hole for 48bit addresses on Vega10 */
34
35
#define AMDGPU_GMC_HOLE_START 0x0000800000000000ULL
···
136
135
unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev);
137
136
};
138
137
139
-
struct amdgpu_xgmi_ras_funcs {
140
-
int (*ras_late_init)(struct amdgpu_device *adev);
141
-
void (*ras_fini)(struct amdgpu_device *adev);
142
-
int (*query_ras_error_count)(struct amdgpu_device *adev,
143
-
void *ras_error_status);
144
-
void (*reset_ras_error_count)(struct amdgpu_device *adev);
138
+
struct amdgpu_xgmi_ras {
139
+
struct amdgpu_ras_block_object ras_block;
145
140
};
146
141
147
142
struct amdgpu_xgmi {
···
156
159
struct ras_common_if *ras_if;
157
160
bool connected_to_cpu;
158
161
bool pending_reset;
159
-
const struct amdgpu_xgmi_ras_funcs *ras_funcs;
162
+
struct amdgpu_xgmi_ras *ras;
160
163
};
161
164
162
165
struct amdgpu_gmc {
+7
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
+7
-3
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c
···
1012
1012
adev->nbio.ras_funcs->query_ras_error_count(adev, &err_data);
1013
1013
break;
1014
1014
case AMDGPU_RAS_BLOCK__XGMI_WAFL:
1015
-
if (adev->gmc.xgmi.ras_funcs &&
1016
-
adev->gmc.xgmi.ras_funcs->query_ras_error_count)
1017
-
adev->gmc.xgmi.ras_funcs->query_ras_error_count(adev, &err_data);
1015
+
if (!block_obj || !block_obj->hw_ops) {
1016
+
dev_info(adev->dev, "%s doesn't config ras function \n",
1017
+
get_ras_block_str(&info->head));
1018
+
return -EINVAL;
1019
+
}
1020
+
if (block_obj->hw_ops->query_ras_error_count)
1021
+
block_obj->hw_ops->query_ras_error_count(adev, &err_data);
1018
1022
break;
1019
1023
case AMDGPU_RAS_BLOCK__HDP:
1020
1024
if (adev->hdp.ras_funcs &&
+16
-10
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
+16
-10
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
···
732
732
return psp_xgmi_terminate(&adev->psp);
733
733
}
734
734
735
-
static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev)
735
+
static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, void *ras_info)
736
736
{
737
737
int r;
738
738
struct ras_ih_if ih_info = {
···
746
746
adev->gmc.xgmi.num_physical_nodes == 0)
747
747
return 0;
748
748
749
-
adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev);
749
+
adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
750
750
751
751
if (!adev->gmc.xgmi.ras_if) {
752
752
adev->gmc.xgmi.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);
···
865
865
return 0;
866
866
}
867
867
868
-
static int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
868
+
static void amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
869
869
void *ras_error_status)
870
870
{
871
871
struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
···
874
874
uint32_t ue_cnt = 0, ce_cnt = 0;
875
875
876
876
if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL))
877
-
return -EINVAL;
877
+
return ;
878
878
879
879
err_data->ue_count = 0;
880
880
err_data->ce_count = 0;
···
940
940
break;
941
941
}
942
942
943
-
adev->gmc.xgmi.ras_funcs->reset_ras_error_count(adev);
943
+
adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev);
944
944
945
945
err_data->ue_count += ue_cnt;
946
946
err_data->ce_count += ce_cnt;
947
-
948
-
return 0;
949
947
}
950
948
951
-
const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs = {
952
-
.ras_late_init = amdgpu_xgmi_ras_late_init,
953
-
.ras_fini = amdgpu_xgmi_ras_fini,
949
+
struct amdgpu_ras_block_hw_ops xgmi_ras_hw_ops = {
954
950
.query_ras_error_count = amdgpu_xgmi_query_ras_error_count,
955
951
.reset_ras_error_count = amdgpu_xgmi_reset_ras_error_count,
952
+
};
953
+
954
+
struct amdgpu_xgmi_ras xgmi_ras = {
955
+
.ras_block = {
956
+
.name = "xgmi",
957
+
.block = AMDGPU_RAS_BLOCK__XGMI_WAFL,
958
+
.hw_ops = &xgmi_ras_hw_ops,
959
+
.ras_late_init = amdgpu_xgmi_ras_late_init,
960
+
.ras_fini = amdgpu_xgmi_ras_fini,
961
+
},
956
962
};
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
+2
-2
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h
···
24
24
25
25
#include <drm/task_barrier.h>
26
26
#include "amdgpu_psp.h"
27
-
27
+
#include "amdgpu_ras.h"
28
28
29
29
struct amdgpu_hive_info {
30
30
struct kobject kobj;
···
50
50
uint32_t pcs_err_shift;
51
51
};
52
52
53
-
extern const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs;
53
+
extern struct amdgpu_xgmi_ras xgmi_ras;
54
54
struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
55
55
void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);
56
56
int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);