Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"This is just a regular fixes pull apart from the qxl one, it has
radeon and intel bits in it,
The intel fixes are for a regression with the RC6 fix and a 3.10 hdmi
regression, whereas radeon is more DPM fixes, a few lockup fixes and
some rn50/r100 DAC fixes"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon/dpm: fix r600_enable_sclk_control()
drm/radeon/dpm: implement force performance levels for rv6xx
drm/radeon/dpm: fix displaygap programming on rv6xx
drm/radeon/dpm: fix a typo in the rv6xx mclk setup
drm/i915: initialize gt_lock early with other spin locks
drm/i915: fix hdmi portclock limits
drm/radeon: fix combios tables on older cards
drm/radeon: improve dac adjust heuristics for legacy pdac
drm/radeon: Another card with wrong primary dac adj
drm/radeon: fix endian issues with DP handling (v3)
drm/radeon/vm: only align the pt base to 32k
drm/radeon: wait for 3D idle before using CP DMA
+159
-128
+1
drivers/gpu/drm/i915/i915_dma.c
+1
drivers/gpu/drm/i915/i915_dma.c
···
1498
1498
spin_lock_init(&dev_priv->irq_lock);
1499
1499
spin_lock_init(&dev_priv->gpu_error.lock);
1500
1500
spin_lock_init(&dev_priv->rps.lock);
1501
+
spin_lock_init(&dev_priv->gt_lock);
1501
1502
spin_lock_init(&dev_priv->backlight.lock);
1502
1503
mutex_init(&dev_priv->dpio_lock);
1503
1504
mutex_init(&dev_priv->rps.hw_lock);
+16
-3
drivers/gpu/drm/i915/intel_hdmi.c
+16
-3
drivers/gpu/drm/i915/intel_hdmi.c
···
785
785
}
786
786
}
787
787
788
+
static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
789
+
{
790
+
struct drm_device *dev = intel_hdmi_to_dev(hdmi);
791
+
792
+
if (IS_G4X(dev))
793
+
return 165000;
794
+
else if (IS_HASWELL(dev))
795
+
return 300000;
796
+
else
797
+
return 225000;
798
+
}
799
+
788
800
static int intel_hdmi_mode_valid(struct drm_connector *connector,
789
801
struct drm_display_mode *mode)
790
802
{
791
-
if (mode->clock > 165000)
803
+
if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
792
804
return MODE_CLOCK_HIGH;
793
805
if (mode->clock < 20000)
794
806
return MODE_CLOCK_LOW;
···
818
806
struct drm_device *dev = encoder->base.dev;
819
807
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
820
808
int clock_12bpc = pipe_config->requested_mode.clock * 3 / 2;
809
+
int portclock_limit = hdmi_portclock_limit(intel_hdmi);
821
810
int desired_bpp;
822
811
823
812
if (intel_hdmi->color_range_auto) {
···
842
829
* outputs. We also need to check that the higher clock still fits
843
830
* within limits.
844
831
*/
845
-
if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= 225000
832
+
if (pipe_config->pipe_bpp > 8*3 && clock_12bpc <= portclock_limit
846
833
&& HAS_PCH_SPLIT(dev)) {
847
834
DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
848
835
desired_bpp = 12*3;
···
859
846
pipe_config->pipe_bpp = desired_bpp;
860
847
}
861
848
862
-
if (adjusted_mode->clock > 225000) {
849
+
if (adjusted_mode->clock > portclock_limit) {
863
850
DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
864
851
return false;
865
852
}
-2
drivers/gpu/drm/i915/intel_pm.c
-2
drivers/gpu/drm/i915/intel_pm.c
+39
-4
drivers/gpu/drm/radeon/atombios_dp.c
+39
-4
drivers/gpu/drm/radeon/atombios_dp.c
···
44
44
};
45
45
46
46
/***** radeon AUX functions *****/
47
+
48
+
/* Atom needs data in little endian format
49
+
* so swap as appropriate when copying data to
50
+
* or from atom. Note that atom operates on
51
+
* dw units.
52
+
*/
53
+
static void radeon_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le)
54
+
{
55
+
#ifdef __BIG_ENDIAN
56
+
u8 src_tmp[20], dst_tmp[20]; /* used for byteswapping */
57
+
u32 *dst32, *src32;
58
+
int i;
59
+
60
+
memcpy(src_tmp, src, num_bytes);
61
+
src32 = (u32 *)src_tmp;
62
+
dst32 = (u32 *)dst_tmp;
63
+
if (to_le) {
64
+
for (i = 0; i < ((num_bytes + 3) / 4); i++)
65
+
dst32[i] = cpu_to_le32(src32[i]);
66
+
memcpy(dst, dst_tmp, num_bytes);
67
+
} else {
68
+
u8 dws = num_bytes & ~3;
69
+
for (i = 0; i < ((num_bytes + 3) / 4); i++)
70
+
dst32[i] = le32_to_cpu(src32[i]);
71
+
memcpy(dst, dst_tmp, dws);
72
+
if (num_bytes % 4) {
73
+
for (i = 0; i < (num_bytes % 4); i++)
74
+
dst[dws+i] = dst_tmp[dws+i];
75
+
}
76
+
}
77
+
#else
78
+
memcpy(dst, src, num_bytes);
79
+
#endif
80
+
}
81
+
47
82
union aux_channel_transaction {
48
83
PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
49
84
PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
···
100
65
101
66
base = (unsigned char *)(rdev->mode_info.atom_context->scratch + 1);
102
67
103
-
memcpy(base, send, send_bytes);
68
+
radeon_copy_swap(base, send, send_bytes, true);
104
69
105
-
args.v1.lpAuxRequest = 0 + 4;
106
-
args.v1.lpDataOut = 16 + 4;
70
+
args.v1.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
71
+
args.v1.lpDataOut = cpu_to_le16((u16)(16 + 4));
107
72
args.v1.ucDataOutLen = 0;
108
73
args.v1.ucChannelID = chan->rec.i2c_id;
109
74
args.v1.ucDelay = delay / 10;
···
137
102
recv_bytes = recv_size;
138
103
139
104
if (recv && recv_size)
140
-
memcpy(recv, base + 16, recv_bytes);
105
+
radeon_copy_swap(recv, base + 16, recv_bytes, false);
141
106
142
107
return recv_bytes;
143
108
}
+4
-1
drivers/gpu/drm/radeon/r600.c
+4
-1
drivers/gpu/drm/radeon/r600.c
···
3166
3166
3167
3167
size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
3168
3168
num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
3169
-
r = radeon_ring_lock(rdev, ring, num_loops * 6 + 21);
3169
+
r = radeon_ring_lock(rdev, ring, num_loops * 6 + 24);
3170
3170
if (r) {
3171
3171
DRM_ERROR("radeon: moving bo (%d).\n", r);
3172
3172
radeon_semaphore_free(rdev, &sem, NULL);
···
3181
3181
radeon_semaphore_free(rdev, &sem, NULL);
3182
3182
}
3183
3183
3184
+
radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
3185
+
radeon_ring_write(ring, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
3186
+
radeon_ring_write(ring, WAIT_3D_IDLE_bit);
3184
3187
for (i = 0; i < num_loops; i++) {
3185
3188
cur_size_in_bytes = size_in_bytes;
3186
3189
if (cur_size_in_bytes > 0x1fffff)
+2
-2
drivers/gpu/drm/radeon/r600_dpm.c
+2
-2
drivers/gpu/drm/radeon/r600_dpm.c
···
278
278
void r600_enable_sclk_control(struct radeon_device *rdev, bool enable)
279
279
{
280
280
if (enable)
281
-
WREG32_P(GENERAL_PWRMGT, 0, ~SCLK_PWRMGT_OFF);
281
+
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
282
282
else
283
-
WREG32_P(GENERAL_PWRMGT, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
283
+
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
284
284
}
285
285
286
286
void r600_enable_mclk_control(struct radeon_device *rdev, bool enable)
+1
drivers/gpu/drm/radeon/radeon_asic.c
+1
drivers/gpu/drm/radeon/radeon_asic.c
···
1161
1161
.get_mclk = &rv6xx_dpm_get_mclk,
1162
1162
.print_power_state = &rv6xx_dpm_print_power_state,
1163
1163
.debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1164
+
.force_performance_level = &rv6xx_dpm_force_performance_level,
1164
1165
},
1165
1166
.pflip = {
1166
1167
.pre_page_flip = &rs600_pre_page_flip,
+2
drivers/gpu/drm/radeon/radeon_asic.h
+2
drivers/gpu/drm/radeon/radeon_asic.h
···
421
421
struct radeon_ps *ps);
422
422
void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
423
423
struct seq_file *m);
424
+
int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
425
+
enum radeon_dpm_forced_level level);
424
426
/* rs780 dpm */
425
427
int rs780_dpm_init(struct radeon_device *rdev);
426
428
int rs780_dpm_enable(struct radeon_device *rdev);
+52
-109
drivers/gpu/drm/radeon/radeon_combios.c
+52
-109
drivers/gpu/drm/radeon/radeon_combios.c
···
147
147
enum radeon_combios_table_offset table)
148
148
{
149
149
struct radeon_device *rdev = dev->dev_private;
150
-
int rev;
150
+
int rev, size;
151
151
uint16_t offset = 0, check_offset;
152
152
153
153
if (!rdev->bios)
···
156
156
switch (table) {
157
157
/* absolute offset tables */
158
158
case COMBIOS_ASIC_INIT_1_TABLE:
159
-
check_offset = RBIOS16(rdev->bios_header_start + 0xc);
160
-
if (check_offset)
161
-
offset = check_offset;
159
+
check_offset = 0xc;
162
160
break;
163
161
case COMBIOS_BIOS_SUPPORT_TABLE:
164
-
check_offset = RBIOS16(rdev->bios_header_start + 0x14);
165
-
if (check_offset)
166
-
offset = check_offset;
162
+
check_offset = 0x14;
167
163
break;
168
164
case COMBIOS_DAC_PROGRAMMING_TABLE:
169
-
check_offset = RBIOS16(rdev->bios_header_start + 0x2a);
170
-
if (check_offset)
171
-
offset = check_offset;
165
+
check_offset = 0x2a;
172
166
break;
173
167
case COMBIOS_MAX_COLOR_DEPTH_TABLE:
174
-
check_offset = RBIOS16(rdev->bios_header_start + 0x2c);
175
-
if (check_offset)
176
-
offset = check_offset;
168
+
check_offset = 0x2c;
177
169
break;
178
170
case COMBIOS_CRTC_INFO_TABLE:
179
-
check_offset = RBIOS16(rdev->bios_header_start + 0x2e);
180
-
if (check_offset)
181
-
offset = check_offset;
171
+
check_offset = 0x2e;
182
172
break;
183
173
case COMBIOS_PLL_INFO_TABLE:
184
-
check_offset = RBIOS16(rdev->bios_header_start + 0x30);
185
-
if (check_offset)
186
-
offset = check_offset;
174
+
check_offset = 0x30;
187
175
break;
188
176
case COMBIOS_TV_INFO_TABLE:
189
-
check_offset = RBIOS16(rdev->bios_header_start + 0x32);
190
-
if (check_offset)
191
-
offset = check_offset;
177
+
check_offset = 0x32;
192
178
break;
193
179
case COMBIOS_DFP_INFO_TABLE:
194
-
check_offset = RBIOS16(rdev->bios_header_start + 0x34);
195
-
if (check_offset)
196
-
offset = check_offset;
180
+
check_offset = 0x34;
197
181
break;
198
182
case COMBIOS_HW_CONFIG_INFO_TABLE:
199
-
check_offset = RBIOS16(rdev->bios_header_start + 0x36);
200
-
if (check_offset)
201
-
offset = check_offset;
183
+
check_offset = 0x36;
202
184
break;
203
185
case COMBIOS_MULTIMEDIA_INFO_TABLE:
204
-
check_offset = RBIOS16(rdev->bios_header_start + 0x38);
205
-
if (check_offset)
206
-
offset = check_offset;
186
+
check_offset = 0x38;
207
187
break;
208
188
case COMBIOS_TV_STD_PATCH_TABLE:
209
-
check_offset = RBIOS16(rdev->bios_header_start + 0x3e);
210
-
if (check_offset)
211
-
offset = check_offset;
189
+
check_offset = 0x3e;
212
190
break;
213
191
case COMBIOS_LCD_INFO_TABLE:
214
-
check_offset = RBIOS16(rdev->bios_header_start + 0x40);
215
-
if (check_offset)
216
-
offset = check_offset;
192
+
check_offset = 0x40;
217
193
break;
218
194
case COMBIOS_MOBILE_INFO_TABLE:
219
-
check_offset = RBIOS16(rdev->bios_header_start + 0x42);
220
-
if (check_offset)
221
-
offset = check_offset;
195
+
check_offset = 0x42;
222
196
break;
223
197
case COMBIOS_PLL_INIT_TABLE:
224
-
check_offset = RBIOS16(rdev->bios_header_start + 0x46);
225
-
if (check_offset)
226
-
offset = check_offset;
198
+
check_offset = 0x46;
227
199
break;
228
200
case COMBIOS_MEM_CONFIG_TABLE:
229
-
check_offset = RBIOS16(rdev->bios_header_start + 0x48);
230
-
if (check_offset)
231
-
offset = check_offset;
201
+
check_offset = 0x48;
232
202
break;
233
203
case COMBIOS_SAVE_MASK_TABLE:
234
-
check_offset = RBIOS16(rdev->bios_header_start + 0x4a);
235
-
if (check_offset)
236
-
offset = check_offset;
204
+
check_offset = 0x4a;
237
205
break;
238
206
case COMBIOS_HARDCODED_EDID_TABLE:
239
-
check_offset = RBIOS16(rdev->bios_header_start + 0x4c);
240
-
if (check_offset)
241
-
offset = check_offset;
207
+
check_offset = 0x4c;
242
208
break;
243
209
case COMBIOS_ASIC_INIT_2_TABLE:
244
-
check_offset = RBIOS16(rdev->bios_header_start + 0x4e);
245
-
if (check_offset)
246
-
offset = check_offset;
210
+
check_offset = 0x4e;
247
211
break;
248
212
case COMBIOS_CONNECTOR_INFO_TABLE:
249
-
check_offset = RBIOS16(rdev->bios_header_start + 0x50);
250
-
if (check_offset)
251
-
offset = check_offset;
213
+
check_offset = 0x50;
252
214
break;
253
215
case COMBIOS_DYN_CLK_1_TABLE:
254
-
check_offset = RBIOS16(rdev->bios_header_start + 0x52);
255
-
if (check_offset)
256
-
offset = check_offset;
216
+
check_offset = 0x52;
257
217
break;
258
218
case COMBIOS_RESERVED_MEM_TABLE:
259
-
check_offset = RBIOS16(rdev->bios_header_start + 0x54);
260
-
if (check_offset)
261
-
offset = check_offset;
219
+
check_offset = 0x54;
262
220
break;
263
221
case COMBIOS_EXT_TMDS_INFO_TABLE:
264
-
check_offset = RBIOS16(rdev->bios_header_start + 0x58);
265
-
if (check_offset)
266
-
offset = check_offset;
222
+
check_offset = 0x58;
267
223
break;
268
224
case COMBIOS_MEM_CLK_INFO_TABLE:
269
-
check_offset = RBIOS16(rdev->bios_header_start + 0x5a);
270
-
if (check_offset)
271
-
offset = check_offset;
225
+
check_offset = 0x5a;
272
226
break;
273
227
case COMBIOS_EXT_DAC_INFO_TABLE:
274
-
check_offset = RBIOS16(rdev->bios_header_start + 0x5c);
275
-
if (check_offset)
276
-
offset = check_offset;
228
+
check_offset = 0x5c;
277
229
break;
278
230
case COMBIOS_MISC_INFO_TABLE:
279
-
check_offset = RBIOS16(rdev->bios_header_start + 0x5e);
280
-
if (check_offset)
281
-
offset = check_offset;
231
+
check_offset = 0x5e;
282
232
break;
283
233
case COMBIOS_CRT_INFO_TABLE:
284
-
check_offset = RBIOS16(rdev->bios_header_start + 0x60);
285
-
if (check_offset)
286
-
offset = check_offset;
234
+
check_offset = 0x60;
287
235
break;
288
236
case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE:
289
-
check_offset = RBIOS16(rdev->bios_header_start + 0x62);
290
-
if (check_offset)
291
-
offset = check_offset;
237
+
check_offset = 0x62;
292
238
break;
293
239
case COMBIOS_COMPONENT_VIDEO_INFO_TABLE:
294
-
check_offset = RBIOS16(rdev->bios_header_start + 0x64);
295
-
if (check_offset)
296
-
offset = check_offset;
240
+
check_offset = 0x64;
297
241
break;
298
242
case COMBIOS_FAN_SPEED_INFO_TABLE:
299
-
check_offset = RBIOS16(rdev->bios_header_start + 0x66);
300
-
if (check_offset)
301
-
offset = check_offset;
243
+
check_offset = 0x66;
302
244
break;
303
245
case COMBIOS_OVERDRIVE_INFO_TABLE:
304
-
check_offset = RBIOS16(rdev->bios_header_start + 0x68);
305
-
if (check_offset)
306
-
offset = check_offset;
246
+
check_offset = 0x68;
307
247
break;
308
248
case COMBIOS_OEM_INFO_TABLE:
309
-
check_offset = RBIOS16(rdev->bios_header_start + 0x6a);
310
-
if (check_offset)
311
-
offset = check_offset;
249
+
check_offset = 0x6a;
312
250
break;
313
251
case COMBIOS_DYN_CLK_2_TABLE:
314
-
check_offset = RBIOS16(rdev->bios_header_start + 0x6c);
315
-
if (check_offset)
316
-
offset = check_offset;
252
+
check_offset = 0x6c;
317
253
break;
318
254
case COMBIOS_POWER_CONNECTOR_INFO_TABLE:
319
-
check_offset = RBIOS16(rdev->bios_header_start + 0x6e);
320
-
if (check_offset)
321
-
offset = check_offset;
255
+
check_offset = 0x6e;
322
256
break;
323
257
case COMBIOS_I2C_INFO_TABLE:
324
-
check_offset = RBIOS16(rdev->bios_header_start + 0x70);
325
-
if (check_offset)
326
-
offset = check_offset;
258
+
check_offset = 0x70;
327
259
break;
328
260
/* relative offset tables */
329
261
case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */
···
371
439
}
372
440
break;
373
441
default:
442
+
check_offset = 0;
374
443
break;
375
444
}
376
445
377
-
return offset;
446
+
size = RBIOS8(rdev->bios_header_start + 0x6);
447
+
/* check absolute offset tables */
448
+
if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size)
449
+
offset = RBIOS16(rdev->bios_header_start + check_offset);
378
450
451
+
return offset;
379
452
}
380
453
381
454
bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev)
···
902
965
dac = RBIOS8(dac_info + 0x3) & 0xf;
903
966
p_dac->ps2_pdac_adj = (bg << 8) | (dac);
904
967
}
905
-
/* if the values are all zeros, use the table */
906
-
if (p_dac->ps2_pdac_adj)
968
+
/* if the values are zeros, use the table */
969
+
if ((dac == 0) || (bg == 0))
970
+
found = 0;
971
+
else
907
972
found = 1;
908
973
}
909
974
910
975
/* quirks */
911
-
/* Radeon 9100 (R200) */
912
-
if ((dev->pdev->device == 0x514D) &&
976
+
/* Radeon 7000 (RV100) */
977
+
if (((dev->pdev->device == 0x5159) &&
913
978
(dev->pdev->subsystem_vendor == 0x174B) &&
914
-
(dev->pdev->subsystem_device == 0x7149)) {
979
+
(dev->pdev->subsystem_device == 0x7c28)) ||
980
+
/* Radeon 9100 (R200) */
981
+
((dev->pdev->device == 0x514D) &&
982
+
(dev->pdev->subsystem_vendor == 0x174B) &&
983
+
(dev->pdev->subsystem_device == 0x7149))) {
915
984
/* vbios value is bad, use the default */
916
985
found = 0;
917
986
}
+4
-4
drivers/gpu/drm/radeon/radeon_gart.c
+4
-4
drivers/gpu/drm/radeon/radeon_gart.c
···
466
466
size += rdev->vm_manager.max_pfn * 8;
467
467
size *= 2;
468
468
r = radeon_sa_bo_manager_init(rdev, &rdev->vm_manager.sa_manager,
469
-
RADEON_VM_PTB_ALIGN(size),
469
+
RADEON_GPU_PAGE_ALIGN(size),
470
470
RADEON_VM_PTB_ALIGN_SIZE,
471
471
RADEON_GEM_DOMAIN_VRAM);
472
472
if (r) {
···
621
621
}
622
622
623
623
retry:
624
-
pd_size = RADEON_VM_PTB_ALIGN(radeon_vm_directory_size(rdev));
624
+
pd_size = radeon_vm_directory_size(rdev);
625
625
r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
626
626
&vm->page_directory, pd_size,
627
627
RADEON_VM_PTB_ALIGN_SIZE, false);
···
953
953
retry:
954
954
r = radeon_sa_bo_new(rdev, &rdev->vm_manager.sa_manager,
955
955
&vm->page_tables[pt_idx],
956
-
RADEON_VM_PTB_ALIGN(RADEON_VM_PTE_COUNT * 8),
957
-
RADEON_VM_PTB_ALIGN_SIZE, false);
956
+
RADEON_VM_PTE_COUNT * 8,
957
+
RADEON_GPU_PAGE_SIZE, false);
958
958
959
959
if (r == -ENOMEM) {
960
960
r = radeon_vm_evict(rdev, vm);
+38
-3
drivers/gpu/drm/radeon/rv6xx_dpm.c
+38
-3
drivers/gpu/drm/radeon/rv6xx_dpm.c
···
819
819
POWERMODE1(calculate_memory_refresh_rate(rdev,
820
820
pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
821
821
POWERMODE2(calculate_memory_refresh_rate(rdev,
822
-
pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
822
+
pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
823
823
POWERMODE3(calculate_memory_refresh_rate(rdev,
824
824
pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
825
825
WREG32(ARB_RFSH_RATE, arb_refresh_rate);
···
1182
1182
u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
1183
1183
1184
1184
tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
1185
-
if (RREG32(AVIVO_D1CRTC_CONTROL) & AVIVO_CRTC_EN) {
1185
+
if (rdev->pm.dpm.new_active_crtcs & 1) {
1186
1186
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1187
1187
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1188
-
} else if (RREG32(AVIVO_D2CRTC_CONTROL) & AVIVO_CRTC_EN) {
1188
+
} else if (rdev->pm.dpm.new_active_crtcs & 2) {
1189
1189
tmp |= DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE);
1190
1190
tmp |= DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK);
1191
1191
} else {
···
1670
1670
struct radeon_ps *old_ps = rdev->pm.dpm.current_ps;
1671
1671
int ret;
1672
1672
1673
+
pi->restricted_levels = 0;
1674
+
1673
1675
rv6xx_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1674
1676
1675
1677
rv6xx_clear_vc(rdev);
···
1757
1755
rv6xx_program_at(rdev);
1758
1756
1759
1757
rv6xx_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1758
+
1759
+
rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
1760
1760
1761
1761
return 0;
1762
1762
}
···
2088
2084
return requested_state->low.mclk;
2089
2085
else
2090
2086
return requested_state->high.mclk;
2087
+
}
2088
+
2089
+
int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
2090
+
enum radeon_dpm_forced_level level)
2091
+
{
2092
+
struct rv6xx_power_info *pi = rv6xx_get_pi(rdev);
2093
+
2094
+
if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
2095
+
pi->restricted_levels = 3;
2096
+
} else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
2097
+
pi->restricted_levels = 2;
2098
+
} else {
2099
+
pi->restricted_levels = 0;
2100
+
}
2101
+
2102
+
rv6xx_clear_vc(rdev);
2103
+
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, true);
2104
+
r600_set_at(rdev, 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF);
2105
+
r600_wait_for_power_level(rdev, R600_POWER_LEVEL_LOW);
2106
+
r600_power_level_enable(rdev, R600_POWER_LEVEL_HIGH, false);
2107
+
r600_power_level_enable(rdev, R600_POWER_LEVEL_MEDIUM, false);
2108
+
rv6xx_enable_medium(rdev);
2109
+
rv6xx_enable_high(rdev);
2110
+
if (pi->restricted_levels == 3)
2111
+
r600_power_level_enable(rdev, R600_POWER_LEVEL_LOW, false);
2112
+
rv6xx_program_vc(rdev);
2113
+
rv6xx_program_at(rdev);
2114
+
2115
+
rdev->pm.dpm.forced_level = level;
2116
+
2117
+
return 0;
2091
2118
}