Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS fixes from Ralf Baechle:
"Fixes for a number of small glitches in various corners of the MIPS
tree. No particular areas is standing out.
With this applied all MIPS defconfigs are building fine. No merge
conflicts are expected."
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: Delete definition of SA_RESTORER.
MIPS: Fix ISA level which causes secondary cache init bypassing and more
MIPS: Fix build error cavium-octeon without CONFIG_SMP
MIPS: Kconfig: Rename SNIPROM too
MIPS: Alchemy: Fix typo "CONFIG_DEBUG_PCI"
MIPS: Unbreak function tracer for 64-bit kernel.
+28
-24
+2
-2
arch/mips/Kconfig
+2
-2
arch/mips/Kconfig
···
657
657
bool "SNI RM200/300/400"
658
658
select FW_ARC if CPU_LITTLE_ENDIAN
659
659
select FW_ARC32 if CPU_LITTLE_ENDIAN
660
-
select SNIPROM if CPU_BIG_ENDIAN
660
+
select FW_SNIPROM if CPU_BIG_ENDIAN
661
661
select ARCH_MAY_HAVE_PC_FDC
662
662
select BOOT_ELF32
663
663
select CEVT_R4K
···
1144
1144
config FW_ARC32
1145
1145
bool
1146
1146
1147
-
config SNIPROM
1147
+
config FW_SNIPROM
1148
1148
bool
1149
1149
1150
1150
config BOOT_ELF32
+4
-1
arch/mips/cavium-octeon/setup.c
+4
-1
arch/mips/cavium-octeon/setup.c
+6
-2
arch/mips/include/uapi/asm/signal.h
+6
-2
arch/mips/include/uapi/asm/signal.h
···
72
72
*
73
73
* SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
74
74
* Unix names RESETHAND and NODEFER respectively.
75
+
*
76
+
* SA_RESTORER used to be defined as 0x04000000 but only the O32 ABI ever
77
+
* supported its use and no libc was using it, so the entire sa-restorer
78
+
* functionality was removed with lmo commit 39bffc12c3580ab for 2.5.48
79
+
* retaining only the SA_RESTORER definition as a reminder to avoid
80
+
* accidental reuse of the mask bit.
75
81
*/
76
82
#define SA_ONSTACK 0x08000000
77
83
#define SA_RESETHAND 0x80000000
···
89
83
90
84
#define SA_NOMASK SA_NODEFER
91
85
#define SA_ONESHOT SA_RESETHAND
92
-
93
-
#define SA_RESTORER 0x04000000 /* Only for o32 */
94
86
95
87
#define MINSIGSTKSZ 2048
96
88
#define SIGSTKSZ 8192
+2
-4
arch/mips/kernel/cpu-probe.c
+2
-4
arch/mips/kernel/cpu-probe.c
···
1227
1227
if (c->options & MIPS_CPU_FPU) {
1228
1228
c->fpu_id = cpu_get_fpu_id();
1229
1229
1230
-
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1231
-
c->isa_level == MIPS_CPU_ISA_M32R2 ||
1232
-
c->isa_level == MIPS_CPU_ISA_M64R1 ||
1233
-
c->isa_level == MIPS_CPU_ISA_M64R2) {
1230
+
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1231
+
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1234
1232
if (c->fpu_id & MIPS_FPIR_3D)
1235
1233
c->ases |= MIPS_ASE_MIPS3D;
1236
1234
}
+7
-4
arch/mips/kernel/mcount.S
+7
-4
arch/mips/kernel/mcount.S
···
46
46
PTR_L a5, PT_R9(sp)
47
47
PTR_L a6, PT_R10(sp)
48
48
PTR_L a7, PT_R11(sp)
49
-
#else
50
-
PTR_ADDIU sp, PT_SIZE
51
49
#endif
52
-
.endm
50
+
PTR_ADDIU sp, PT_SIZE
51
+
.endm
53
52
54
53
.macro RETURN_BACK
55
54
jr ra
···
67
68
.globl _mcount
68
69
_mcount:
69
70
b ftrace_stub
70
-
addiu sp,sp,8
71
+
#ifdef CONFIG_32BIT
72
+
addiu sp,sp,8
73
+
#else
74
+
nop
75
+
#endif
71
76
72
77
/* When tracing is activated, it calls ftrace_caller+8 (aka here) */
73
78
lw t1, function_trace_stop
+1
-1
arch/mips/kernel/traps.c
+1
-1
arch/mips/kernel/traps.c
···
1571
1571
#ifdef CONFIG_64BIT
1572
1572
status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
1573
1573
#endif
1574
-
if (current_cpu_data.isa_level == MIPS_CPU_ISA_IV)
1574
+
if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
1575
1575
status_set |= ST0_XX;
1576
1576
if (cpu_has_dsp)
1577
1577
status_set |= ST0_MX;
+2
-4
arch/mips/mm/c-r4k.c
+2
-4
arch/mips/mm/c-r4k.c
···
1247
1247
return;
1248
1248
1249
1249
default:
1250
-
if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1251
-
c->isa_level == MIPS_CPU_ISA_M32R2 ||
1252
-
c->isa_level == MIPS_CPU_ISA_M64R1 ||
1253
-
c->isa_level == MIPS_CPU_ISA_M64R2) {
1250
+
if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1251
+
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1254
1252
#ifdef CONFIG_MIPS_CPU_SCACHE
1255
1253
if (mips_sc_init ()) {
1256
1254
scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+2
-4
arch/mips/mm/sc-mips.c
+2
-4
arch/mips/mm/sc-mips.c
···
98
98
c->scache.flags |= MIPS_CACHE_NOT_PRESENT;
99
99
100
100
/* Ignore anything but MIPSxx processors */
101
-
if (c->isa_level != MIPS_CPU_ISA_M32R1 &&
102
-
c->isa_level != MIPS_CPU_ISA_M32R2 &&
103
-
c->isa_level != MIPS_CPU_ISA_M64R1 &&
104
-
c->isa_level != MIPS_CPU_ISA_M64R2)
101
+
if (!(c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
102
+
MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)))
105
103
return 0;
106
104
107
105
/* Does this MIPS32/MIPS64 CPU have a config2 register? */
+2
-2
arch/mips/pci/pci-alchemy.c
+2
-2
arch/mips/pci/pci-alchemy.c
···
19
19
#include <asm/mach-au1x00/au1000.h>
20
20
#include <asm/tlbmisc.h>
21
21
22
-
#ifdef CONFIG_DEBUG_PCI
22
+
#ifdef CONFIG_PCI_DEBUG
23
23
#define DBG(x...) printk(KERN_DEBUG x)
24
24
#else
25
25
#define DBG(x...) do {} while (0)
···
162
162
if (status & (1 << 29)) {
163
163
*data = 0xffffffff;
164
164
error = -1;
165
-
DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d",
165
+
DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d\n",
166
166
access_type, bus->number, device);
167
167
} else if ((status >> 28) & 0xf) {
168
168
DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n",