Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86 fixes from Ingo Molnar:
"Fix typos in user-visible resctrl parameters, and also fix assembly
constraint bugs that might result in miscompilation"
* 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
x86/asm: Use stricter assembly constraints in bitops
x86/resctrl: Fix typos in the mba_sc mount option
+21
-26
+18
-23
arch/x86/include/asm/bitops.h
+18
-23
arch/x86/include/asm/bitops.h
···
36
36
* bit 0 is the LSB of addr; bit 32 is the LSB of (addr+1).
37
37
*/
38
38
39
-
#define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
39
+
#define RLONG_ADDR(x) "m" (*(volatile long *) (x))
40
+
#define WBYTE_ADDR(x) "+m" (*(volatile char *) (x))
40
41
41
-
#define ADDR BITOP_ADDR(addr)
42
+
#define ADDR RLONG_ADDR(addr)
42
43
43
44
/*
44
45
* We do the locked ops that don't return the old value as
45
46
* a mask operation on a byte.
46
47
*/
47
48
#define IS_IMMEDIATE(nr) (__builtin_constant_p(nr))
48
-
#define CONST_MASK_ADDR(nr, addr) BITOP_ADDR((void *)(addr) + ((nr)>>3))
49
+
#define CONST_MASK_ADDR(nr, addr) WBYTE_ADDR((void *)(addr) + ((nr)>>3))
49
50
#define CONST_MASK(nr) (1 << ((nr) & 7))
50
51
51
52
/**
···
74
73
: "memory");
75
74
} else {
76
75
asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0"
77
-
: BITOP_ADDR(addr) : "Ir" (nr) : "memory");
76
+
: : RLONG_ADDR(addr), "Ir" (nr) : "memory");
78
77
}
79
78
}
80
79
···
89
88
*/
90
89
static __always_inline void __set_bit(long nr, volatile unsigned long *addr)
91
90
{
92
-
asm volatile(__ASM_SIZE(bts) " %1,%0" : ADDR : "Ir" (nr) : "memory");
91
+
asm volatile(__ASM_SIZE(bts) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
93
92
}
94
93
95
94
/**
···
111
110
: "iq" ((u8)~CONST_MASK(nr)));
112
111
} else {
113
112
asm volatile(LOCK_PREFIX __ASM_SIZE(btr) " %1,%0"
114
-
: BITOP_ADDR(addr)
115
-
: "Ir" (nr));
113
+
: : RLONG_ADDR(addr), "Ir" (nr) : "memory");
116
114
}
117
115
}
118
116
···
131
131
132
132
static __always_inline void __clear_bit(long nr, volatile unsigned long *addr)
133
133
{
134
-
asm volatile(__ASM_SIZE(btr) " %1,%0" : ADDR : "Ir" (nr));
134
+
asm volatile(__ASM_SIZE(btr) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
135
135
}
136
136
137
137
static __always_inline bool clear_bit_unlock_is_negative_byte(long nr, volatile unsigned long *addr)
···
139
139
bool negative;
140
140
asm volatile(LOCK_PREFIX "andb %2,%1"
141
141
CC_SET(s)
142
-
: CC_OUT(s) (negative), ADDR
142
+
: CC_OUT(s) (negative), WBYTE_ADDR(addr)
143
143
: "ir" ((char) ~(1 << nr)) : "memory");
144
144
return negative;
145
145
}
···
155
155
* __clear_bit() is non-atomic and implies release semantics before the memory
156
156
* operation. It can be used for an unlock if no other CPUs can concurrently
157
157
* modify other bits in the word.
158
-
*
159
-
* No memory barrier is required here, because x86 cannot reorder stores past
160
-
* older loads. Same principle as spin_unlock.
161
158
*/
162
159
static __always_inline void __clear_bit_unlock(long nr, volatile unsigned long *addr)
163
160
{
164
-
barrier();
165
161
__clear_bit(nr, addr);
166
162
}
167
163
···
172
176
*/
173
177
static __always_inline void __change_bit(long nr, volatile unsigned long *addr)
174
178
{
175
-
asm volatile(__ASM_SIZE(btc) " %1,%0" : ADDR : "Ir" (nr));
179
+
asm volatile(__ASM_SIZE(btc) " %1,%0" : : ADDR, "Ir" (nr) : "memory");
176
180
}
177
181
178
182
/**
···
192
196
: "iq" ((u8)CONST_MASK(nr)));
193
197
} else {
194
198
asm volatile(LOCK_PREFIX __ASM_SIZE(btc) " %1,%0"
195
-
: BITOP_ADDR(addr)
196
-
: "Ir" (nr));
199
+
: : RLONG_ADDR(addr), "Ir" (nr) : "memory");
197
200
}
198
201
}
199
202
···
237
242
238
243
asm(__ASM_SIZE(bts) " %2,%1"
239
244
CC_SET(c)
240
-
: CC_OUT(c) (oldbit), ADDR
241
-
: "Ir" (nr));
245
+
: CC_OUT(c) (oldbit)
246
+
: ADDR, "Ir" (nr) : "memory");
242
247
return oldbit;
243
248
}
244
249
···
277
282
278
283
asm volatile(__ASM_SIZE(btr) " %2,%1"
279
284
CC_SET(c)
280
-
: CC_OUT(c) (oldbit), ADDR
281
-
: "Ir" (nr));
285
+
: CC_OUT(c) (oldbit)
286
+
: ADDR, "Ir" (nr) : "memory");
282
287
return oldbit;
283
288
}
284
289
···
289
294
290
295
asm volatile(__ASM_SIZE(btc) " %2,%1"
291
296
CC_SET(c)
292
-
: CC_OUT(c) (oldbit), ADDR
293
-
: "Ir" (nr) : "memory");
297
+
: CC_OUT(c) (oldbit)
298
+
: ADDR, "Ir" (nr) : "memory");
294
299
295
300
return oldbit;
296
301
}
···
321
326
asm volatile(__ASM_SIZE(bt) " %2,%1"
322
327
CC_SET(c)
323
328
: CC_OUT(c) (oldbit)
324
-
: "m" (*(unsigned long *)addr), "Ir" (nr));
329
+
: "m" (*(unsigned long *)addr), "Ir" (nr) : "memory");
325
330
326
331
return oldbit;
327
332
}
+3
-3
arch/x86/kernel/cpu/resctrl/rdtgroup.c
+3
-3
arch/x86/kernel/cpu/resctrl/rdtgroup.c
···
2039
2039
enum rdt_param {
2040
2040
Opt_cdp,
2041
2041
Opt_cdpl2,
2042
-
Opt_mba_mpbs,
2042
+
Opt_mba_mbps,
2043
2043
nr__rdt_params
2044
2044
};
2045
2045
2046
2046
static const struct fs_parameter_spec rdt_param_specs[] = {
2047
2047
fsparam_flag("cdp", Opt_cdp),
2048
2048
fsparam_flag("cdpl2", Opt_cdpl2),
2049
-
fsparam_flag("mba_mpbs", Opt_mba_mpbs),
2049
+
fsparam_flag("mba_MBps", Opt_mba_mbps),
2050
2050
{}
2051
2051
};
2052
2052
···
2072
2072
case Opt_cdpl2:
2073
2073
ctx->enable_cdpl2 = true;
2074
2074
return 0;
2075
-
case Opt_mba_mpbs:
2075
+
case Opt_mba_mbps:
2076
2076
if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2077
2077
return -EINVAL;
2078
2078
ctx->enable_mba_mbps = true;