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phy: exynos5-usbdrd: s/FIELD_PREP_CONST/FIELD_PREP where appropriate

Commit 9b6662a0f715 ("phy: exynos5-usbdrd: use GENMASK and FIELD_PREP
for Exynos5 PHY registers") added FIELD_PREP_CONST() in many cases
where FIELD_PREP() would have been more appropriate. It also switched
existing uses of FIELD_PREP() to FIELD_PREP_CONST().

FIELD_PREP() is the preferred macro to use whenever possible while
FIELD_PREP_CONST() is meant to be used in constant initialisers.

Switch (back) to FIELD_PREP().

Fixes: 7e6c2ffe6c22 ("phy: exynos5-usbdrd: convert some FIELD_PREP_CONST() to FIELD_PREP()")
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Link: https://lore.kernel.org/r/20250429-exynos5-phy-field-prep-v1-2-39eb279a3e0e@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

André Draszik and committed by
Vinod Koul 6d0e2ada b45791d4

+28 -34
+28 -34
drivers/phy/samsung/phy-exynos5-usbdrd.c
··· 540 540 541 541 /* Use EXTREFCLK as ref clock */ 542 542 reg &= ~PHYCLKRST_REFCLKSEL; 543 - reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, 544 - PHYCLKRST_REFCLKSEL_EXT_REFCLK); 543 + reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK); 545 544 546 545 /* FSEL settings corresponding to reference clock */ 547 546 reg &= ~(PHYCLKRST_FSEL_PIPE | ··· 548 549 PHYCLKRST_SSC_REFCLKSEL); 549 550 switch (phy_drd->extrefclk) { 550 551 case EXYNOS5_FSEL_50MHZ: 551 - reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 552 - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 553 - PHYCLKRST_MPLL_MULTIPLIER_50M_REF)); 552 + reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 553 + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 554 + PHYCLKRST_MPLL_MULTIPLIER_50M_REF)); 554 555 break; 555 556 case EXYNOS5_FSEL_24MHZ: 556 - reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 557 - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 558 - PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF)); 557 + reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 558 + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 559 + PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF)); 559 560 break; 560 561 case EXYNOS5_FSEL_20MHZ: 561 - reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 562 - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 563 - PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF)); 562 + reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 563 + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 564 + PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF)); 564 565 break; 565 566 case EXYNOS5_FSEL_19MHZ2: 566 - reg |= (FIELD_PREP_CONST(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 567 - FIELD_PREP_CONST(PHYCLKRST_MPLL_MULTIPLIER, 568 - PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF)); 567 + reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 568 + FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 569 + PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF)); 569 570 break; 570 571 default: 571 572 dev_dbg(phy_drd->dev, "unsupported ref clk\n"); ··· 589 590 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 590 591 591 592 reg &= ~PHYCLKRST_REFCLKSEL; 592 - reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, 593 - PHYCLKRST_REFCLKSEL_EXT_REFCLK); 593 + reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK); 594 594 595 595 reg &= ~(PHYCLKRST_FSEL_UTMI | 596 596 PHYCLKRST_MPLL_MULTIPLIER | ··· 645 647 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 646 648 /* Set Tx De-Emphasis level */ 647 649 reg &= ~PHYPARAM1_PCS_TXDEEMPH; 648 - reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, 649 - PHYPARAM1_PCS_TXDEEMPH_VAL); 650 + reg |= FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL); 650 651 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 651 652 652 653 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); ··· 666 669 667 670 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); 668 671 reg &= ~SECPMACTL_PMA_REF_FREQ_SEL; 669 - reg |= FIELD_PREP_CONST(SECPMACTL_PMA_REF_FREQ_SEL, 1); 672 + reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1); 670 673 /* SFR reset */ 671 674 reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST); 672 675 reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL | ··· 796 799 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 797 800 /* Set Loss-of-Signal Detector sensitivity */ 798 801 reg &= ~PHYPARAM0_REF_LOSLEVEL; 799 - reg |= FIELD_PREP_CONST(PHYPARAM0_REF_LOSLEVEL, 800 - PHYPARAM0_REF_LOSLEVEL_VAL); 802 + reg |= FIELD_PREP(PHYPARAM0_REF_LOSLEVEL, PHYPARAM0_REF_LOSLEVEL_VAL); 801 803 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 802 804 803 805 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 804 806 /* Set Tx De-Emphasis level */ 805 807 reg &= ~PHYPARAM1_PCS_TXDEEMPH; 806 - reg |= FIELD_PREP_CONST(PHYPARAM1_PCS_TXDEEMPH, 807 - PHYPARAM1_PCS_TXDEEMPH_VAL); 808 + reg |= FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL); 808 809 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 809 810 810 811 /* UTMI Power Control */ ··· 833 838 * See xHCI 1.0 spec, 5.2.4 834 839 */ 835 840 reg = LINKSYSTEM_XHCI_VERSION_CONTROL | 836 - FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); 841 + FIELD_PREP(LINKSYSTEM_FLADJ, 0x20); 837 842 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); 838 843 839 844 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); ··· 1140 1145 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 1141 1146 /* Use PADREFCLK as ref clock */ 1142 1147 reg &= ~PHYCLKRST_REFCLKSEL; 1143 - reg |= FIELD_PREP_CONST(PHYCLKRST_REFCLKSEL, 1144 - PHYCLKRST_REFCLKSEL_PAD_REFCLK); 1148 + reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_PAD_REFCLK); 1145 1149 /* Select ref clock rate */ 1146 1150 reg &= ~PHYCLKRST_FSEL_UTMI; 1147 1151 reg &= ~PHYCLKRST_FSEL_PIPE; ··· 1163 1169 else 1164 1170 reg &= ~HSPHYPLLTUNE_PLL_B_TUNE; 1165 1171 reg &= ~HSPHYPLLTUNE_PLL_P_TUNE; 1166 - reg |= FIELD_PREP_CONST(HSPHYPLLTUNE_PLL_P_TUNE, 14); 1172 + reg |= FIELD_PREP(HSPHYPLLTUNE_PLL_P_TUNE, 14); 1167 1173 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); 1168 1174 1169 1175 /* High-Speed PHY control */ ··· 1181 1187 */ 1182 1188 reg |= LINKSYSTEM_XHCI_VERSION_CONTROL; 1183 1189 reg &= ~LINKSYSTEM_FLADJ; 1184 - reg |= FIELD_PREP_CONST(LINKSYSTEM_FLADJ, 0x20); 1190 + reg |= FIELD_PREP(LINKSYSTEM_FLADJ, 0x20); 1185 1191 /* Set VBUSVALID signal as the VBUS pad is not used */ 1186 1192 reg |= LINKSYSTEM_FORCE_BVALID; 1187 1193 reg |= LINKSYSTEM_FORCE_VBUSVALID; ··· 1344 1350 1345 1351 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ 1346 1352 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 1347 - reg |= FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); 1353 + reg |= FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf); 1348 1354 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 1349 1355 1350 1356 if (!phy_drd->sw) { ··· 1361 1367 reg &= ~SSPPLLCTL_FSEL; 1362 1368 switch (phy_drd->extrefclk) { 1363 1369 case EXYNOS5_FSEL_50MHZ: 1364 - reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 7); 1370 + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7); 1365 1371 break; 1366 1372 case EXYNOS5_FSEL_26MHZ: 1367 - reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 6); 1373 + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6); 1368 1374 break; 1369 1375 case EXYNOS5_FSEL_24MHZ: 1370 - reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 2); 1376 + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2); 1371 1377 break; 1372 1378 case EXYNOS5_FSEL_20MHZ: 1373 - reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 1); 1379 + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1); 1374 1380 break; 1375 1381 case EXYNOS5_FSEL_19MHZ2: 1376 - reg |= FIELD_PREP_CONST(SSPPLLCTL_FSEL, 0); 1382 + reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0); 1377 1383 break; 1378 1384 default: 1379 1385 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n",