Merge tag 'drm-intel-next-2024-08-29' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next

+27 -27

drivers/gpu/drm/i915/display/intel_alpm.c

··· 139 139 _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, 140 140 const struct intel_crtc_state *crtc_state) 141 141 { 142 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 142 + struct intel_display *display = to_intel_display(intel_dp); 143 143 int aux_less_wake_time, aux_less_wake_lines, silence_period, 144 144 lfps_half_cycle; 145 145 ··· 158 158 lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK) 159 159 return false; 160 160 161 - if (i915->display.params.psr_safest_params) 161 + if (display->params.psr_safest_params) 162 162 aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; 163 163 164 164 intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines; ··· 171 171 static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, 172 172 const struct intel_crtc_state *crtc_state) 173 173 { 174 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 174 + struct intel_display *display = to_intel_display(intel_dp); 175 175 int check_entry_lines; 176 176 177 - if (DISPLAY_VER(i915) < 20) 177 + if (DISPLAY_VER(display) < 20) 178 178 return true; 179 179 180 180 /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */ ··· 187 187 if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) 188 188 return false; 189 189 190 - if (i915->display.params.psr_safest_params) 190 + if (display->params.psr_safest_params) 191 191 check_entry_lines = 15; 192 192 193 193 intel_dp->alpm_parameters.check_entry_lines = check_entry_lines; ··· 212 212 213 213 static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) 214 214 { 215 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 215 + struct intel_display *display = to_intel_display(crtc_state); 216 216 217 - if (DISPLAY_VER(i915) >= 12) 217 + if (DISPLAY_VER(display) >= 12) 218 218 return tgl_io_buffer_wake_time(); 219 219 else 220 220 return skl_io_buffer_wake_time(); ··· 223 223 bool intel_alpm_compute_params(struct intel_dp *intel_dp, 224 224 const struct intel_crtc_state *crtc_state) 225 225 { 226 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 226 + struct intel_display *display = to_intel_display(intel_dp); 227 227 int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; 228 228 int tfw_exit_latency = 20; /* eDP spec */ 229 229 int phy_wake = 4; /* eDP spec */ ··· 236 236 fast_wake_time = precharge + preamble + phy_wake + 237 237 tfw_exit_latency; 238 238 239 - if (DISPLAY_VER(i915) >= 20) 239 + if (DISPLAY_VER(display) >= 20) 240 240 max_wake_lines = 68; 241 - else if (DISPLAY_VER(i915) >= 12) 241 + else if (DISPLAY_VER(display) >= 12) 242 242 max_wake_lines = 12; 243 243 else 244 244 max_wake_lines = 8; ··· 255 255 if (!_lnl_compute_alpm_params(intel_dp, crtc_state)) 256 256 return false; 257 257 258 - if (i915->display.params.psr_safest_params) 258 + if (display->params.psr_safest_params) 259 259 io_wake_lines = fast_wake_lines = max_wake_lines; 260 260 261 261 /* According to Bspec lower limit should be set as 7 lines. */ ··· 269 269 struct intel_crtc_state *crtc_state, 270 270 struct drm_connector_state *conn_state) 271 271 { 272 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 272 + struct intel_display *display = to_intel_display(intel_dp); 273 273 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 274 274 int waketime_in_lines, first_sdp_position; 275 275 int context_latency, guardband; ··· 277 277 if (!intel_dp_is_edp(intel_dp)) 278 278 return; 279 279 280 - if (DISPLAY_VER(i915) < 20) 280 + if (DISPLAY_VER(display) < 20) 281 281 return; 282 282 283 283 if (!intel_dp->as_sdp_supported) ··· 309 309 static void lnl_alpm_configure(struct intel_dp *intel_dp, 310 310 const struct intel_crtc_state *crtc_state) 311 311 { 312 - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 312 + struct intel_display *display = to_intel_display(intel_dp); 313 313 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 314 314 enum port port = dp_to_dig_port(intel_dp)->base.port; 315 315 u32 alpm_ctl; 316 316 317 - if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && 318 - !intel_dp_is_edp(intel_dp))) 317 + if (DISPLAY_VER(display) < 20 || 318 + (!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp))) 319 319 return; 320 320 321 321 /* ··· 329 329 ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS | 330 330 ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); 331 331 332 - intel_de_write(dev_priv, 333 - PORT_ALPM_CTL(dev_priv, port), 332 + intel_de_write(display, 333 + PORT_ALPM_CTL(display, port), 334 334 PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | 335 335 PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | 336 336 PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | 337 337 PORT_ALPM_CTL_SILENCE_PERIOD( 338 338 intel_dp->alpm_parameters.silence_period_sym_clocks)); 339 339 340 - intel_de_write(dev_priv, 341 - PORT_ALPM_LFPS_CTL(dev_priv, port), 340 + intel_de_write(display, 341 + PORT_ALPM_LFPS_CTL(display, port), 342 342 PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | 343 343 PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( 344 344 intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | ··· 356 356 357 357 alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); 358 358 359 - intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl); 359 + intel_de_write(display, ALPM_CTL(display, cpu_transcoder), alpm_ctl); 360 360 } 361 361 362 362 void intel_alpm_configure(struct intel_dp *intel_dp, ··· 368 368 static int i915_edp_lobf_info_show(struct seq_file *m, void *data) 369 369 { 370 370 struct intel_connector *connector = m->private; 371 - struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 371 + struct intel_display *display = to_intel_display(connector); 372 372 struct drm_crtc *crtc; 373 373 struct intel_crtc_state *crtc_state; 374 374 enum transcoder cpu_transcoder; 375 375 u32 alpm_ctl; 376 376 int ret; 377 377 378 - ret = drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex); 378 + ret = drm_modeset_lock_single_interruptible(&display->drm->mode_config.connection_mutex); 379 379 if (ret) 380 380 return ret; 381 381 ··· 387 387 388 388 crtc_state = to_intel_crtc_state(crtc->state); 389 389 cpu_transcoder = crtc_state->cpu_transcoder; 390 - alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder)); 390 + alpm_ctl = intel_de_read(display, ALPM_CTL(display, cpu_transcoder)); 391 391 seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE)); 392 392 seq_printf(m, "Aux-wake alpm status: %s\n", 393 393 str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE))); 394 394 seq_printf(m, "Aux-less alpm status: %s\n", 395 395 str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)); 396 396 out: 397 - drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex); 397 + drm_modeset_unlock(&display->drm->mode_config.connection_mutex); 398 398 399 399 return ret; 400 400 } ··· 403 403 404 404 void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) 405 405 { 406 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 406 + struct intel_display *display = to_intel_display(connector); 407 407 struct dentry *root = connector->base.debugfs_entry; 408 408 409 - if (DISPLAY_VER(i915) < 20 || 409 + if (DISPLAY_VER(display) < 20 || 410 410 connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) 411 411 return; 412 412

+4 -2

drivers/gpu/drm/i915/display/intel_atomic.c

··· 276 276 crtc_state->do_async_flip = false; 277 277 crtc_state->fb_bits = 0; 278 278 crtc_state->update_planes = 0; 279 - crtc_state->dsb = NULL; 279 + crtc_state->dsb_color_vblank = NULL; 280 + crtc_state->dsb_color_commit = NULL; 280 281 281 282 return &crtc_state->uapi; 282 283 } ··· 311 310 { 312 311 struct intel_crtc_state *crtc_state = to_intel_crtc_state(state); 313 312 314 - drm_WARN_ON(crtc->dev, crtc_state->dsb); 313 + drm_WARN_ON(crtc->dev, crtc_state->dsb_color_vblank); 314 + drm_WARN_ON(crtc->dev, crtc_state->dsb_color_commit); 315 315 316 316 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi); 317 317 intel_crtc_free_hw_state(crtc_state);

+5 -5

drivers/gpu/drm/i915/display/intel_backlight.c

··· 1011 1011 { 1012 1012 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1013 1013 1014 - return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq), 1014 + return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), 1015 1015 pwm_freq_hz); 1016 1016 } 1017 1017 ··· 1073 1073 { 1074 1074 struct drm_i915_private *i915 = to_i915(connector->base.dev); 1075 1075 1076 - return DIV_ROUND_CLOSEST(KHz(RUNTIME_INFO(i915)->rawclk_freq), 1076 + return DIV_ROUND_CLOSEST(KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq), 1077 1077 pwm_freq_hz * 128); 1078 1078 } 1079 1079 ··· 1091 1091 int clock; 1092 1092 1093 1093 if (IS_PINEVIEW(i915)) 1094 - clock = KHz(RUNTIME_INFO(i915)->rawclk_freq); 1094 + clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); 1095 1095 else 1096 1096 clock = KHz(i915->display.cdclk.hw.cdclk); 1097 1097 ··· 1109 1109 int clock; 1110 1110 1111 1111 if (IS_G4X(i915)) 1112 - clock = KHz(RUNTIME_INFO(i915)->rawclk_freq); 1112 + clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); 1113 1113 else 1114 1114 clock = KHz(i915->display.cdclk.hw.cdclk); 1115 1115 ··· 1133 1133 clock = MHz(25); 1134 1134 mul = 16; 1135 1135 } else { 1136 - clock = KHz(RUNTIME_INFO(i915)->rawclk_freq); 1136 + clock = KHz(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq); 1137 1137 mul = 128; 1138 1138 } 1139 1139

+37 -19

drivers/gpu/drm/i915/display/intel_color.c

··· 1313 1313 { 1314 1314 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1315 1315 1316 - if (crtc_state->dsb) 1317 - intel_dsb_reg_write(crtc_state->dsb, reg, val); 1316 + if (crtc_state->dsb_color_vblank) 1317 + intel_dsb_reg_write(crtc_state->dsb_color_vblank, reg, val); 1318 1318 else 1319 1319 intel_de_write_fw(i915, reg, val); 1320 1320 } ··· 1337 1337 * unless we either write each entry twice, 1338 1338 * or use non-posted writes 1339 1339 */ 1340 - if (crtc_state->dsb) 1341 - intel_dsb_nonpost_start(crtc_state->dsb); 1340 + if (crtc_state->dsb_color_vblank) 1341 + intel_dsb_nonpost_start(crtc_state->dsb_color_vblank); 1342 1342 1343 1343 for (i = 0; i < 256; i++) 1344 1344 ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), 1345 1345 i9xx_lut_8(&lut[i])); 1346 1346 1347 - if (crtc_state->dsb) 1348 - intel_dsb_nonpost_end(crtc_state->dsb); 1347 + if (crtc_state->dsb_color_vblank) 1348 + intel_dsb_nonpost_end(crtc_state->dsb_color_vblank); 1349 1349 } 1350 1350 1351 1351 static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state, ··· 1870 1870 { 1871 1871 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1872 1872 1873 - if (crtc_state->dsb) 1873 + if (crtc_state->dsb_color_vblank) 1874 1874 return; 1875 1875 1876 1876 i915->display.funcs.color->load_luts(crtc_state); ··· 1890 1890 1891 1891 i915->display.funcs.color->color_commit_arm(crtc_state); 1892 1892 1893 - if (crtc_state->dsb) 1894 - intel_dsb_commit(crtc_state->dsb, true); 1893 + if (crtc_state->dsb_color_commit) 1894 + intel_dsb_commit(crtc_state->dsb_color_commit, false); 1895 1895 } 1896 1896 1897 1897 void intel_color_post_update(const struct intel_crtc_state *crtc_state) ··· 1919 1919 if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) 1920 1920 return; 1921 1921 1922 - crtc_state->dsb = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 1024); 1923 - if (!crtc_state->dsb) 1922 + crtc_state->dsb_color_vblank = intel_dsb_prepare(state, crtc, INTEL_DSB_1, 1024); 1923 + if (!crtc_state->dsb_color_vblank) 1924 1924 return; 1925 1925 1926 1926 i915->display.funcs.color->load_luts(crtc_state); 1927 1927 1928 - intel_dsb_finish(crtc_state->dsb); 1928 + intel_dsb_finish(crtc_state->dsb_color_vblank); 1929 + 1930 + crtc_state->dsb_color_commit = intel_dsb_prepare(state, crtc, INTEL_DSB_0, 16); 1931 + if (!crtc_state->dsb_color_commit) { 1932 + intel_dsb_cleanup(crtc_state->dsb_color_vblank); 1933 + crtc_state->dsb_color_vblank = NULL; 1934 + return; 1935 + } 1936 + 1937 + intel_dsb_chain(state, crtc_state->dsb_color_commit, 1938 + crtc_state->dsb_color_vblank, true); 1939 + 1940 + intel_dsb_finish(crtc_state->dsb_color_commit); 1929 1941 } 1930 1942 1931 1943 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state) 1932 1944 { 1933 - if (!crtc_state->dsb) 1934 - return; 1945 + if (crtc_state->dsb_color_commit) { 1946 + intel_dsb_cleanup(crtc_state->dsb_color_commit); 1947 + crtc_state->dsb_color_commit = NULL; 1948 + } 1935 1949 1936 - intel_dsb_cleanup(crtc_state->dsb); 1937 - crtc_state->dsb = NULL; 1950 + if (crtc_state->dsb_color_vblank) { 1951 + intel_dsb_cleanup(crtc_state->dsb_color_vblank); 1952 + crtc_state->dsb_color_vblank = NULL; 1953 + } 1938 1954 } 1939 1955 1940 1956 void intel_color_wait_commit(const struct intel_crtc_state *crtc_state) 1941 1957 { 1942 - if (crtc_state->dsb) 1943 - intel_dsb_wait(crtc_state->dsb); 1958 + if (crtc_state->dsb_color_commit) 1959 + intel_dsb_wait(crtc_state->dsb_color_commit); 1960 + if (crtc_state->dsb_color_vblank) 1961 + intel_dsb_wait(crtc_state->dsb_color_vblank); 1944 1962 } 1945 1963 1946 1964 bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) 1947 1965 { 1948 - return crtc_state->dsb; 1966 + return crtc_state->dsb_color_vblank; 1949 1967 } 1950 1968 1951 1969 static bool intel_can_preload_luts(struct intel_atomic_state *state,

+1 -1

drivers/gpu/drm/i915/display/intel_ddi.c

··· 4900 4900 * driver. In that case we should skip initializing the corresponding 4901 4901 * outputs. 4902 4902 */ 4903 - if (intel_hti_uses_phy(dev_priv, phy)) { 4903 + if (intel_hti_uses_phy(display, phy)) { 4904 4904 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n", 4905 4905 port_name(port), phy_name(phy)); 4906 4906 return;

+7 -4

drivers/gpu/drm/i915/display/intel_display.c

··· 1032 1032 vrr_params_changed(old_crtc_state, new_crtc_state))); 1033 1033 } 1034 1034 1035 - static bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 1036 - struct intel_crtc *crtc) 1035 + bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 1036 + struct intel_crtc *crtc) 1037 1037 { 1038 1038 const struct intel_crtc_state *old_crtc_state = 1039 1039 intel_atomic_get_old_crtc_state(state, crtc); ··· 6260 6260 case I915_FORMAT_MOD_Y_TILED: 6261 6261 case I915_FORMAT_MOD_Yf_TILED: 6262 6262 case I915_FORMAT_MOD_4_TILED: 6263 + case I915_FORMAT_MOD_4_TILED_BMG_CCS: 6264 + case I915_FORMAT_MOD_4_TILED_LNL_CCS: 6263 6265 break; 6264 6266 default: 6265 6267 drm_dbg_kms(&i915->drm, ··· 7513 7511 * 7514 7512 * FIXME get rid of this funny new->old swapping 7515 7513 */ 7516 - old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb); 7514 + old_crtc_state->dsb_color_vblank = fetch_and_zero(&new_crtc_state->dsb_color_vblank); 7515 + old_crtc_state->dsb_color_commit = fetch_and_zero(&new_crtc_state->dsb_color_commit); 7517 7516 } 7518 7517 7519 7518 /* Underruns don't always raise interrupts, so check manually */ ··· 7936 7933 g4x_dp_init(dev_priv, DP_D, PORT_D); 7937 7934 7938 7935 if (SUPPORTS_TV(dev_priv)) 7939 - intel_tv_init(dev_priv); 7936 + intel_tv_init(display); 7940 7937 } else if (DISPLAY_VER(dev_priv) == 2) { 7941 7938 if (IS_I85X(dev_priv)) 7942 7939 intel_lvds_init(dev_priv);

+3

drivers/gpu/drm/i915/display/intel_display.h

··· 532 532 533 533 void intel_update_watermarks(struct drm_i915_private *i915); 534 534 535 + bool intel_crtc_vrr_disabling(struct intel_atomic_state *state, 536 + struct intel_crtc *crtc); 537 + 535 538 /* modesetting */ 536 539 int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, 537 540 const char *reason, u8 pipe_mask);

+1 -1

drivers/gpu/drm/i915/display/intel_display_debugfs.c

··· 1073 1073 intel_opregion_debugfs_register(display); 1074 1074 intel_psr_debugfs_register(i915); 1075 1075 intel_wm_debugfs_register(i915); 1076 - intel_display_debugfs_params(i915); 1076 + intel_display_debugfs_params(display); 1077 1077 } 1078 1078 1079 1079 static int i915_hdcp_sink_capability_show(struct seq_file *m, void *data)

+4 -4

drivers/gpu/drm/i915/display/intel_display_debugfs_params.c

··· 151 151 } while (0) 152 152 153 153 /* add a subdirectory with files for each intel display param */ 154 - void intel_display_debugfs_params(struct drm_i915_private *i915) 154 + void intel_display_debugfs_params(struct intel_display *display) 155 155 { 156 - struct drm_minor *minor = i915->drm.primary; 156 + struct drm_minor *minor = display->drm->primary; 157 157 struct dentry *dir; 158 158 char dirname[16]; 159 159 160 - snprintf(dirname, sizeof(dirname), "%s_params", i915->drm.driver->name); 160 + snprintf(dirname, sizeof(dirname), "%s_params", display->drm->driver->name); 161 161 dir = debugfs_lookup(dirname, minor->debugfs_root); 162 162 if (!dir) 163 163 dir = debugfs_create_dir(dirname, minor->debugfs_root); ··· 171 171 */ 172 172 173 173 #define REGISTER(T, x, unused, mode, ...) _intel_display_param_create_file( \ 174 - dir, #x, mode, &i915->display.params.x); 174 + dir, #x, mode, &display->params.x); 175 175 INTEL_DISPLAY_PARAMS_FOR_EACH(REGISTER); 176 176 #undef REGISTER 177 177 }

+2 -2

drivers/gpu/drm/i915/display/intel_display_debugfs_params.h

··· 6 6 #ifndef __INTEL_DISPLAY_DEBUGFS_PARAMS__ 7 7 #define __INTEL_DISPLAY_DEBUGFS_PARAMS__ 8 8 9 - struct drm_i915_private; 9 + struct intel_display; 10 10 11 - void intel_display_debugfs_params(struct drm_i915_private *i915); 11 + void intel_display_debugfs_params(struct intel_display *display); 12 12 13 13 #endif /* __INTEL_DISPLAY_DEBUGFS_PARAMS__ */

+221 -11

drivers/gpu/drm/i915/display/intel_display_device.c

··· 16 16 #include "intel_display_power.h" 17 17 #include "intel_display_reg_defs.h" 18 18 #include "intel_fbc.h" 19 + #include "intel_step.h" 19 20 20 21 __diag_push(); 21 22 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); 23 + 24 + struct stepping_desc { 25 + const enum intel_step *map; /* revid to step map */ 26 + size_t size; /* map size */ 27 + }; 28 + 29 + #define STEP_INFO(_map) \ 30 + .step_info.map = _map, \ 31 + .step_info.size = ARRAY_SIZE(_map) 22 32 23 33 struct subplatform_desc { 24 34 enum intel_display_subplatform subplatform; 25 35 const char *name; 26 36 const u16 *pciidlist; 37 + struct stepping_desc step_info; 27 38 }; 28 39 29 40 struct platform_desc { ··· 42 31 const char *name; 43 32 const struct subplatform_desc *subplatforms; 44 33 const struct intel_display_device_info *info; /* NULL for GMD ID */ 34 + struct stepping_desc step_info; 45 35 }; 46 36 47 37 #define PLATFORM(_platform) \ ··· 622 610 0 623 611 }; 624 612 613 + static const enum intel_step skl_steppings[] = { 614 + [0x6] = STEP_G0, 615 + [0x7] = STEP_H0, 616 + [0x9] = STEP_J0, 617 + [0xA] = STEP_I1, 618 + }; 619 + 625 620 static const struct platform_desc skl_desc = { 626 621 PLATFORM(SKYLAKE), 627 622 .subplatforms = (const struct subplatform_desc[]) { ··· 637 618 {}, 638 619 }, 639 620 .info = &skl_display, 621 + STEP_INFO(skl_steppings), 640 622 }; 641 623 642 624 static const u16 kbl_ult_ids[] = { ··· 654 634 0 655 635 }; 656 636 637 + static const enum intel_step kbl_steppings[] = { 638 + [1] = STEP_B0, 639 + [2] = STEP_B0, 640 + [3] = STEP_B0, 641 + [4] = STEP_C0, 642 + [5] = STEP_B1, 643 + [6] = STEP_B1, 644 + [7] = STEP_C0, 645 + }; 646 + 657 647 static const struct platform_desc kbl_desc = { 658 648 PLATFORM(KABYLAKE), 659 649 .subplatforms = (const struct subplatform_desc[]) { ··· 672 642 {}, 673 643 }, 674 644 .info = &skl_display, 645 + STEP_INFO(kbl_steppings), 675 646 }; 676 647 677 648 static const u16 cfl_ult_ids[] = { ··· 737 706 BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ 738 707 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) 739 708 709 + static const enum intel_step bxt_steppings[] = { 710 + [0xA] = STEP_C0, 711 + [0xB] = STEP_C0, 712 + [0xC] = STEP_D0, 713 + [0xD] = STEP_E0, 714 + }; 715 + 740 716 static const struct platform_desc bxt_desc = { 741 717 PLATFORM(BROXTON), 742 718 .info = &(const struct intel_display_device_info) { ··· 752 714 753 715 .__runtime_defaults.ip.ver = 9, 754 716 }, 717 + STEP_INFO(bxt_steppings), 718 + }; 719 + 720 + static const enum intel_step glk_steppings[] = { 721 + [3] = STEP_B0, 755 722 }; 756 723 757 724 static const struct platform_desc glk_desc = { ··· 768 725 769 726 .__runtime_defaults.ip.ver = 10, 770 727 }, 728 + STEP_INFO(glk_steppings), 771 729 }; 772 730 773 731 #define ICL_DISPLAY \ ··· 817 773 0 818 774 }; 819 775 776 + static const enum intel_step icl_steppings[] = { 777 + [7] = STEP_D0, 778 + }; 779 + 820 780 static const struct platform_desc icl_desc = { 821 781 PLATFORM(ICELAKE), 822 782 .subplatforms = (const struct subplatform_desc[]) { ··· 832 784 833 785 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), 834 786 }, 787 + STEP_INFO(icl_steppings), 835 788 }; 836 789 837 790 static const struct intel_display_device_info jsl_ehl_display = { ··· 841 792 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), 842 793 }; 843 794 795 + static const enum intel_step jsl_ehl_steppings[] = { 796 + [0] = STEP_A0, 797 + [1] = STEP_B0, 798 + }; 799 + 844 800 static const struct platform_desc jsl_desc = { 845 801 PLATFORM(JASPERLAKE), 846 802 .info = &jsl_ehl_display, 803 + STEP_INFO(jsl_ehl_steppings), 847 804 }; 848 805 849 806 static const struct platform_desc ehl_desc = { 850 807 PLATFORM(ELKHARTLAKE), 851 808 .info = &jsl_ehl_display, 809 + STEP_INFO(jsl_ehl_steppings), 852 810 }; 853 811 854 812 #define XE_D_DISPLAY \ ··· 906 850 0 907 851 }; 908 852 853 + static const enum intel_step tgl_steppings[] = { 854 + [0] = STEP_B0, 855 + [1] = STEP_D0, 856 + }; 857 + 858 + static const enum intel_step tgl_uy_steppings[] = { 859 + [0] = STEP_A0, 860 + [1] = STEP_C0, 861 + [2] = STEP_C0, 862 + [3] = STEP_D0, 863 + }; 864 + 909 865 static const struct platform_desc tgl_desc = { 910 866 PLATFORM(TIGERLAKE), 911 867 .subplatforms = (const struct subplatform_desc[]) { 912 - { INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids }, 868 + { INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids, 869 + STEP_INFO(tgl_uy_steppings) }, 913 870 {}, 914 871 }, 915 872 .info = &(const struct intel_display_device_info) { ··· 935 866 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 936 867 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6), 937 868 }, 869 + STEP_INFO(tgl_steppings), 870 + }; 871 + 872 + static const enum intel_step dg1_steppings[] = { 873 + [0] = STEP_A0, 874 + [1] = STEP_B0, 938 875 }; 939 876 940 877 static const struct platform_desc dg1_desc = { ··· 951 876 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 952 877 BIT(PORT_TC1) | BIT(PORT_TC2), 953 878 }, 879 + STEP_INFO(dg1_steppings), 880 + }; 881 + 882 + static const enum intel_step rkl_steppings[] = { 883 + [0] = STEP_A0, 884 + [1] = STEP_B0, 885 + [4] = STEP_C0, 954 886 }; 955 887 956 888 static const struct platform_desc rkl_desc = { ··· 974 892 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | 975 893 BIT(PORT_TC1) | BIT(PORT_TC2), 976 894 }, 895 + STEP_INFO(rkl_steppings), 977 896 }; 978 897 979 898 static const u16 adls_rpls_ids[] = { ··· 982 899 0 983 900 }; 984 901 902 + static const enum intel_step adl_s_steppings[] = { 903 + [0x0] = STEP_A0, 904 + [0x1] = STEP_A2, 905 + [0x4] = STEP_B0, 906 + [0x8] = STEP_B0, 907 + [0xC] = STEP_C0, 908 + }; 909 + 910 + static const enum intel_step adl_s_rpl_s_steppings[] = { 911 + [0x4] = STEP_D0, 912 + [0xC] = STEP_C0, 913 + }; 914 + 985 915 static const struct platform_desc adl_s_desc = { 986 916 PLATFORM(ALDERLAKE_S), 987 917 .subplatforms = (const struct subplatform_desc[]) { 988 - { INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids }, 918 + { INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids, 919 + STEP_INFO(adl_s_rpl_s_steppings) }, 989 920 {}, 990 921 }, 991 922 .info = &(const struct intel_display_device_info) { ··· 1010 913 .__runtime_defaults.port_mask = BIT(PORT_A) | 1011 914 BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), 1012 915 }, 916 + STEP_INFO(adl_s_steppings), 1013 917 }; 1014 918 1015 919 #define XE_LPD_FEATURES \ ··· 1084 986 0 1085 987 }; 1086 988 989 + static const enum intel_step adl_p_steppings[] = { 990 + [0x0] = STEP_A0, 991 + [0x4] = STEP_B0, 992 + [0x8] = STEP_C0, 993 + [0xC] = STEP_D0, 994 + }; 995 + 996 + static const enum intel_step adl_p_adl_n_steppings[] = { 997 + [0x0] = STEP_D0, 998 + }; 999 + 1000 + static const enum intel_step adl_p_rpl_pu_steppings[] = { 1001 + [0x4] = STEP_E0, 1002 + }; 1003 + 1087 1004 static const struct platform_desc adl_p_desc = { 1088 1005 PLATFORM(ALDERLAKE_P), 1089 1006 .subplatforms = (const struct subplatform_desc[]) { 1090 - { INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids }, 1091 - { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids }, 1092 - { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids }, 1007 + { INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids, 1008 + STEP_INFO(adl_p_adl_n_steppings) }, 1009 + { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids, 1010 + STEP_INFO(adl_p_rpl_pu_steppings) }, 1011 + { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids, 1012 + STEP_INFO(adl_p_rpl_pu_steppings) }, 1093 1013 {}, 1094 1014 }, 1095 1015 .info = &xe_lpd_display, 1016 + STEP_INFO(adl_p_steppings), 1096 1017 }; 1097 1018 1098 1019 static const struct intel_display_device_info xe_hpd_display = { ··· 1140 1023 0 1141 1024 }; 1142 1025 1026 + static const enum intel_step dg2_g10_steppings[] = { 1027 + [0x0] = STEP_A0, 1028 + [0x1] = STEP_A0, 1029 + [0x4] = STEP_B0, 1030 + [0x8] = STEP_C0, 1031 + }; 1032 + 1033 + static const enum intel_step dg2_g11_steppings[] = { 1034 + [0x0] = STEP_B0, 1035 + [0x4] = STEP_C0, 1036 + [0x5] = STEP_C0, 1037 + }; 1038 + 1039 + static const enum intel_step dg2_g12_steppings[] = { 1040 + [0x0] = STEP_C0, 1041 + [0x1] = STEP_C0, 1042 + }; 1043 + 1143 1044 static const struct platform_desc dg2_desc = { 1144 1045 PLATFORM(DG2), 1145 1046 .subplatforms = (const struct subplatform_desc[]) { 1146 - { INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids }, 1147 - { INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids }, 1148 - { INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids }, 1047 + { INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids, 1048 + STEP_INFO(dg2_g10_steppings) }, 1049 + { INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids, 1050 + STEP_INFO(dg2_g11_steppings) }, 1051 + { INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids, 1052 + STEP_INFO(dg2_g12_steppings) }, 1149 1053 {}, 1150 1054 }, 1151 1055 .info = &xe_hpd_display, ··· 1399 1261 return NULL; 1400 1262 } 1401 1263 1264 + static enum intel_step get_pre_gmdid_step(struct intel_display *display, 1265 + const struct stepping_desc *main, 1266 + const struct stepping_desc *sub) 1267 + { 1268 + struct pci_dev *pdev = to_pci_dev(display->drm->dev); 1269 + const enum intel_step *map = main->map; 1270 + int size = main->size; 1271 + int revision = pdev->revision; 1272 + enum intel_step step; 1273 + 1274 + /* subplatform stepping info trumps main platform info */ 1275 + if (sub && sub->map && sub->size) { 1276 + map = sub->map; 1277 + size = sub->size; 1278 + } 1279 + 1280 + /* not all platforms define steppings, and it's fine */ 1281 + if (!map || !size) 1282 + return STEP_NONE; 1283 + 1284 + if (revision < size && map[revision] != STEP_NONE) { 1285 + step = map[revision]; 1286 + } else { 1287 + drm_warn(display->drm, "Unknown revision 0x%02x\n", revision); 1288 + 1289 + /* 1290 + * If we hit a gap in the revision to step map, use the information 1291 + * for the next revision. 1292 + * 1293 + * This may be wrong in all sorts of ways, especially if the 1294 + * steppings in the array are not monotonically increasing, but 1295 + * it's better than defaulting to 0. 1296 + */ 1297 + while (revision < size && map[revision] == STEP_NONE) 1298 + revision++; 1299 + 1300 + if (revision < size) { 1301 + drm_dbg_kms(display->drm, "Using display stepping for revision 0x%02x\n", 1302 + revision); 1303 + step = map[revision]; 1304 + } else { 1305 + drm_dbg_kms(display->drm, "Using future display stepping\n"); 1306 + step = STEP_FUTURE; 1307 + } 1308 + } 1309 + 1310 + drm_WARN_ON(display->drm, step == STEP_NONE); 1311 + 1312 + return step; 1313 + } 1314 + 1402 1315 void intel_display_device_probe(struct drm_i915_private *i915) 1403 1316 { 1317 + struct intel_display *display = &i915->display; 1404 1318 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 1405 1319 const struct intel_display_device_info *info; 1406 1320 struct intel_display_ip_ver ip_ver = {}; 1407 1321 const struct platform_desc *desc; 1408 1322 const struct subplatform_desc *subdesc; 1323 + enum intel_step step; 1409 1324 1410 1325 /* Add drm device backpointer as early as possible. */ 1411 1326 i915->display.drm = &i915->drm; ··· 1498 1307 DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform; 1499 1308 } 1500 1309 1501 - if (ip_ver.ver || ip_ver.rel || ip_ver.step) 1310 + if (ip_ver.ver || ip_ver.rel || ip_ver.step) { 1502 1311 DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; 1312 + step = STEP_A0 + ip_ver.step; 1313 + if (step > STEP_FUTURE) { 1314 + drm_dbg_kms(display->drm, "Using future display stepping\n"); 1315 + step = STEP_FUTURE; 1316 + } 1317 + } else { 1318 + step = get_pre_gmdid_step(display, &desc->step_info, 1319 + subdesc ? &subdesc->step_info : NULL); 1320 + } 1503 1321 1504 - drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u\n", 1322 + DISPLAY_RUNTIME_INFO(i915)->step = step; 1323 + 1324 + drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u stepping %s\n", 1505 1325 desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", 1506 1326 pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, 1507 - DISPLAY_RUNTIME_INFO(i915)->ip.rel); 1327 + DISPLAY_RUNTIME_INFO(i915)->ip.rel, 1328 + step != STEP_NONE ? intel_step_name(step) : "N/A"); 1508 1329 1509 1330 return; 1510 1331 ··· 1677 1474 } 1678 1475 } 1679 1476 1477 + display_runtime->rawclk_freq = intel_read_rawclk(i915); 1478 + drm_dbg_kms(&i915->drm, "rawclk rate: %d kHz\n", display_runtime->rawclk_freq); 1479 + 1680 1480 return; 1681 1481 1682 1482 display_fused_off: ··· 1715 1509 drm_printf(p, "display version: %u\n", 1716 1510 runtime->ip.ver); 1717 1511 1512 + drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step)); 1513 + 1718 1514 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 1719 1515 DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG); 1720 1516 #undef PRINT_FLAG ··· 1724 1516 drm_printf(p, "has_hdcp: %s\n", str_yes_no(runtime->has_hdcp)); 1725 1517 drm_printf(p, "has_dmc: %s\n", str_yes_no(runtime->has_dmc)); 1726 1518 drm_printf(p, "has_dsc: %s\n", str_yes_no(runtime->has_dsc)); 1519 + 1520 + drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 1727 1521 } 1728 1522 1729 1523 /*

+15 -6

drivers/gpu/drm/i915/display/intel_display_device.h

··· 161 161 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 162 162 163 163 /* Check that device has a display IP version within the specific range. */ 164 - #define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \ 164 + #define IS_DISPLAY_VER_FULL(__i915, from, until) ( \ 165 165 BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ 166 166 (DISPLAY_VER_FULL(__i915) >= (from) && \ 167 167 DISPLAY_VER_FULL(__i915) <= (until))) ··· 175 175 * hardware fix is present and the software workaround is no longer necessary. 176 176 * E.g., 177 177 * 178 - * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2) 179 - * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER) 178 + * IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2) 179 + * IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER) 180 180 * 181 181 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 182 182 * stepping bound for the specified IP version. 183 183 */ 184 - #define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \ 185 - (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \ 184 + #define IS_DISPLAY_VER_STEP(__i915, ipver, from, until) \ 185 + (IS_DISPLAY_VER_FULL((__i915), (ipver), (ipver)) && \ 186 186 IS_DISPLAY_STEP((__i915), (from), (until))) 187 187 188 188 #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) ··· 194 194 #define IS_DISPLAY_VER(i915, from, until) \ 195 195 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 196 196 197 + #define INTEL_DISPLAY_STEP(__i915) (DISPLAY_RUNTIME_INFO(__i915)->step) 198 + 199 + #define IS_DISPLAY_STEP(__i915, since, until) \ 200 + (drm_WARN_ON(__to_intel_display(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 201 + INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 202 + 197 203 struct intel_display_runtime_info { 198 204 enum intel_display_platform platform; 199 205 enum intel_display_subplatform subplatform; ··· 207 201 struct intel_display_ip_ver { 208 202 u16 ver; 209 203 u16 rel; 210 - u16 step; 204 + u16 step; /* hardware */ 211 205 } ip; 206 + int step; /* symbolic */ 207 + 208 + u32 rawclk_freq; 212 209 213 210 u8 pipe_mask; 214 211 u8 cpu_transcoder_mask;

+1 -1

drivers/gpu/drm/i915/display/intel_display_driver.c

··· 453 453 if (i915->display.cdclk.max_cdclk_freq == 0) 454 454 intel_update_max_cdclk(i915); 455 455 456 - intel_hti_init(i915); 456 + intel_hti_init(display); 457 457 458 458 /* Just disable it once at startup */ 459 459 intel_vga_disable(i915);

+17

drivers/gpu/drm/i915/display/intel_display_irq.c

··· 14 14 #include "intel_display_trace.h" 15 15 #include "intel_display_types.h" 16 16 #include "intel_dp_aux.h" 17 + #include "intel_dsb.h" 17 18 #include "intel_fdi_regs.h" 18 19 #include "intel_fifo_underrun.h" 19 20 #include "intel_gmbus.h" ··· 1165 1164 if (iir & gen8_de_pipe_flip_done_mask(dev_priv)) 1166 1165 flip_done_handler(dev_priv, pipe); 1167 1166 1167 + if (HAS_DSB(dev_priv)) { 1168 + if (iir & GEN12_DSB_INT(INTEL_DSB_0)) 1169 + intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_0); 1170 + 1171 + if (iir & GEN12_DSB_INT(INTEL_DSB_1)) 1172 + intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_1); 1173 + 1174 + if (iir & GEN12_DSB_INT(INTEL_DSB_2)) 1175 + intel_dsb_irq_handler(&dev_priv->display, pipe, INTEL_DSB_2); 1176 + } 1177 + 1168 1178 if (iir & GEN8_PIPE_CDCLK_CRC_DONE) 1169 1179 hsw_pipe_crc_irq_handler(dev_priv, pipe); 1170 1180 ··· 1747 1735 if (intel_bios_is_dsi_present(display, &port)) 1748 1736 de_port_masked |= DSI0_TE | DSI1_TE; 1749 1737 } 1738 + 1739 + if (HAS_DSB(dev_priv)) 1740 + de_pipe_masked |= GEN12_DSB_INT(INTEL_DSB_0) | 1741 + GEN12_DSB_INT(INTEL_DSB_1) | 1742 + GEN12_DSB_INT(INTEL_DSB_2); 1750 1743 1751 1744 de_pipe_enables = de_pipe_masked | 1752 1745 GEN8_PIPE_VBLANK |

+3 -3

drivers/gpu/drm/i915/display/intel_display_params.c

··· 173 173 174 174 /** 175 175 * intel_display_params_dump - dump intel display modparams 176 - * @i915: i915 device 176 + * @display: display device 177 177 * @p: the &drm_printer 178 178 * 179 179 * Pretty printer for i915 modparams. 180 180 */ 181 - void intel_display_params_dump(struct drm_i915_private *i915, struct drm_printer *p) 181 + void intel_display_params_dump(struct intel_display *display, struct drm_printer *p) 182 182 { 183 - #define PRINT(T, x, ...) _param_print(p, i915->drm.driver->name, #x, i915->display.params.x); 183 + #define PRINT(T, x, ...) _param_print(p, display->drm->driver->name, #x, display->params.x); 184 184 INTEL_DISPLAY_PARAMS_FOR_EACH(PRINT); 185 185 #undef PRINT 186 186 }

+2 -2

drivers/gpu/drm/i915/display/intel_display_params.h

··· 9 9 #include <linux/types.h> 10 10 11 11 struct drm_printer; 12 - struct drm_i915_private; 12 + struct intel_display; 13 13 14 14 /* 15 15 * Invoke param, a function-like macro, for each intel display param, with ··· 56 56 }; 57 57 #undef MEMBER 58 58 59 - void intel_display_params_dump(struct drm_i915_private *i915, 59 + void intel_display_params_dump(struct intel_display *display, 60 60 struct drm_printer *p); 61 61 void intel_display_params_copy(struct intel_display_params *dest); 62 62 void intel_display_params_free(struct intel_display_params *params);

+4 -16

drivers/gpu/drm/i915/display/intel_display_power.c

··· 36 36 for_each_power_well_reverse(__dev_priv, __power_well) \ 37 37 for_each_if(test_bit((__domain), (__power_well)->domains.bits)) 38 38 39 - const char * 39 + static const char * 40 40 intel_display_power_domain_str(enum intel_display_power_domain domain) 41 41 { 42 42 switch (domain) { ··· 198 198 } 199 199 } 200 200 201 - /** 202 - * __intel_display_power_is_enabled - unlocked check for a power domain 203 - * @dev_priv: i915 device instance 204 - * @domain: power domain to check 205 - * 206 - * This is the unlocked version of intel_display_power_is_enabled() and should 207 - * only be used from error capture and recovery code where deadlocks are 208 - * possible. 209 - * 210 - * Returns: 211 - * True when the power domain is enabled, false otherwise. 212 - */ 213 - bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 214 - enum intel_display_power_domain domain) 201 + static bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 202 + enum intel_display_power_domain domain) 215 203 { 216 204 struct i915_power_well *power_well; 217 205 bool is_enabled; ··· 1684 1696 intel_dmc_load_program(dev_priv); 1685 1697 1686 1698 /* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p,dg2 */ 1687 - if (IS_DISPLAY_IP_RANGE(dev_priv, IP_VER(12, 0), IP_VER(13, 0))) 1699 + if (IS_DISPLAY_VER_FULL(dev_priv, IP_VER(12, 0), IP_VER(13, 0))) 1688 1700 intel_de_rmw(dev_priv, GEN11_CHICKEN_DCPR_2, 0, 1689 1701 DCPR_CLEAR_MEMSTAT_DIS | DCPR_SEND_RESP_IMM | 1690 1702 DCPR_MASK_LPMODE | DCPR_MASK_MAXLATENCY_MEMUP_CLR);

-5

drivers/gpu/drm/i915/display/intel_display_power.h

··· 183 183 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv, 184 184 u32 state); 185 185 186 - const char * 187 - intel_display_power_domain_str(enum intel_display_power_domain domain); 188 - 189 186 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 190 187 enum intel_display_power_domain domain); 191 - bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv, 192 - enum intel_display_power_domain domain); 193 188 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv, 194 189 enum intel_display_power_domain domain); 195 190 intel_wakeref_t

+2 -2

drivers/gpu/drm/i915/display/intel_display_power_well.c

··· 1176 1176 MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); 1177 1177 intel_de_write(dev_priv, CBR1_VLV, 0); 1178 1178 1179 - drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0); 1179 + drm_WARN_ON(&dev_priv->drm, DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq == 0); 1180 1180 intel_de_write(dev_priv, RAWCLK_FREQ_VLV, 1181 - DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 1181 + DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq, 1182 1182 1000)); 1183 1183 } 1184 1184

+5 -2

drivers/gpu/drm/i915/display/intel_display_types.h

··· 1396 1396 /* Only valid on TGL+ */ 1397 1397 enum transcoder mst_master_transcoder; 1398 1398 1399 - /* For DSB related info */ 1400 - struct intel_dsb *dsb; 1399 + /* For DSB based color LUT updates */ 1400 + struct intel_dsb *dsb_color_vblank, *dsb_color_commit; 1401 1401 1402 1402 u32 psr2_man_track_ctl; 1403 1403 ··· 2206 2206 */ 2207 2207 #define __drm_device_to_intel_display(p) \ 2208 2208 (&to_i915(p)->display) 2209 + #define __intel_atomic_state_to_intel_display(p) \ 2210 + __drm_device_to_intel_display((p)->base.dev) 2209 2211 #define __intel_connector_to_intel_display(p) \ 2210 2212 __drm_device_to_intel_display((p)->base.dev) 2211 2213 #define __intel_crtc_to_intel_display(p) \ ··· 2231 2229 #define to_intel_display(p) \ 2232 2230 _Generic(*p, \ 2233 2231 __assoc(drm_device, p), \ 2232 + __assoc(intel_atomic_state, p), \ 2234 2233 __assoc(intel_connector, p), \ 2235 2234 __assoc(intel_crtc, p), \ 2236 2235 __assoc(intel_crtc_state, p), \

+1 -1

drivers/gpu/drm/i915/display/intel_dmc.c

··· 391 391 intel_get_stepping_info(struct drm_i915_private *i915, 392 392 struct stepping_info *si) 393 393 { 394 - const char *step_name = intel_display_step_name(i915); 394 + const char *step_name = intel_step_name(INTEL_DISPLAY_STEP(i915)); 395 395 396 396 si->stepping = step_name[0]; 397 397 si->substepping = step_name[1];

+12

drivers/gpu/drm/i915/display/intel_dp.c

··· 5999 5999 else 6000 6000 status = connector_status_disconnected; 6001 6001 6002 + if (status != connector_status_disconnected && 6003 + !intel_dp_mst_verify_dpcd_state(intel_dp)) 6004 + /* 6005 + * This requires retrying detection for instance to re-enable 6006 + * the MST mode that got reset via a long HPD pulse. The retry 6007 + * will happen either via the hotplug handler's retry logic, 6008 + * ensured by setting the connector here to SST/disconnected, 6009 + * or via a userspace connector probing in response to the 6010 + * hotplug uevent sent when removing the MST connectors. 6011 + */ 6012 + status = connector_status_disconnected; 6013 + 6002 6014 if (status == connector_status_disconnected) { 6003 6015 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 6004 6016 memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd));

+2 -2

drivers/gpu/drm/i915/display/intel_dp_aux.c

··· 83 83 * The clock divider is based off the hrawclk, and would like to run at 84 84 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 85 85 */ 86 - return DIV_ROUND_CLOSEST(RUNTIME_INFO(i915)->rawclk_freq, 2000); 86 + return DIV_ROUND_CLOSEST(DISPLAY_RUNTIME_INFO(i915)->rawclk_freq, 2000); 87 87 } 88 88 89 89 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) ··· 103 103 if (dig_port->aux_ch == AUX_CH_A) 104 104 freq = i915->display.cdclk.hw.cdclk; 105 105 else 106 - freq = RUNTIME_INFO(i915)->rawclk_freq; 106 + freq = DISPLAY_RUNTIME_INFO(i915)->rawclk_freq; 107 107 return DIV_ROUND_CLOSEST(freq, 2000); 108 108 } 109 109

+40 -30

drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c

··· 109 109 static bool 110 110 intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) 111 111 { 112 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 112 + struct intel_display *display = to_intel_display(connector); 113 113 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 114 114 struct drm_dp_aux *aux = &intel_dp->aux; 115 115 struct intel_panel *panel = &connector->panel; ··· 122 122 if (ret != sizeof(tcon_cap)) 123 123 return false; 124 124 125 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Detected %s HDR backlight interface version %d\n", 125 + drm_dbg_kms(display->drm, 126 + "[CONNECTOR:%d:%s] Detected %s HDR backlight interface version %d\n", 126 127 connector->base.base.id, connector->base.name, 127 128 is_intel_tcon_cap(tcon_cap) ? "Intel" : "unsupported", tcon_cap[0]); 128 129 ··· 142 141 * HDR static metadata we need to start maintaining table of 143 142 * ranges for such panels. 144 143 */ 145 - if (i915->display.params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL && 144 + if (display->params.enable_dpcd_backlight != INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL && 146 145 !(connector->base.hdr_sink_metadata.hdmi_type1.metadata_type & 147 146 BIT(HDMI_STATIC_METADATA_TYPE1))) { 148 - drm_info(&i915->drm, 147 + drm_info(display->drm, 149 148 "[CONNECTOR:%d:%s] Panel is missing HDR static metadata. Possible support for Intel HDR backlight interface is not used. If your backlight controls don't work try booting with i915.enable_dpcd_backlight=%d. needs this, please file a _new_ bug report on drm/i915, see " FDO_BUG_URL " for details.\n", 150 149 connector->base.base.id, connector->base.name, 151 150 INTEL_DP_AUX_BACKLIGHT_FORCE_INTEL); ··· 171 170 static u32 172 171 intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe) 173 172 { 174 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 173 + struct intel_display *display = to_intel_display(connector); 175 174 struct intel_panel *panel = &connector->panel; 176 175 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 177 176 u8 tmp; 178 177 u8 buf[2] = {}; 179 178 180 179 if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) { 181 - drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read current backlight mode from DPCD\n", 180 + drm_err(display->drm, 181 + "[CONNECTOR:%d:%s] Failed to read current backlight mode from DPCD\n", 182 182 connector->base.base.id, connector->base.name); 183 183 return 0; 184 184 } ··· 197 195 198 196 if (drm_dp_dpcd_read(&intel_dp->aux, INTEL_EDP_BRIGHTNESS_NITS_LSB, buf, 199 197 sizeof(buf)) != sizeof(buf)) { 200 - drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read brightness from DPCD\n", 198 + drm_err(display->drm, 199 + "[CONNECTOR:%d:%s] Failed to read brightness from DPCD\n", 201 200 connector->base.base.id, connector->base.name); 202 201 return 0; 203 202 } ··· 256 253 intel_dp_aux_write_content_luminance(struct intel_connector *connector, 257 254 struct hdr_output_metadata *hdr_metadata) 258 255 { 256 + struct intel_display *display = to_intel_display(connector); 259 257 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 260 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 261 258 int ret; 262 259 u8 buf[4]; 263 260 ··· 273 270 INTEL_EDP_HDR_CONTENT_LUMINANCE, 274 271 buf, sizeof(buf)); 275 272 if (ret < 0) 276 - drm_dbg_kms(&i915->drm, 273 + drm_dbg_kms(display->drm, 277 274 "Content Luminance DPCD reg write failed, err:-%d\n", 278 275 ret); 279 276 } ··· 283 280 { 284 281 struct intel_connector *connector = to_intel_connector(conn_state->connector); 285 282 struct intel_panel *panel = &connector->panel; 286 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 283 + struct intel_display *display = to_intel_display(connector); 287 284 288 285 /* 289 286 * According to spec segmented backlight needs to be set whenever panel is in ··· 294 291 *ctrl |= INTEL_EDP_HDR_TCON_2084_DECODE_ENABLE; 295 292 } 296 293 297 - if (DISPLAY_VER(i915) < 11) 294 + if (DISPLAY_VER(display) < 11) 298 295 *ctrl &= ~INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE; 299 296 300 297 if (panel->backlight.edp.intel_cap.supports_2020_gamut && ··· 314 311 intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state, 315 312 const struct drm_connector_state *conn_state, u32 level) 316 313 { 314 + struct intel_display *display = to_intel_display(crtc_state); 317 315 struct intel_connector *connector = to_intel_connector(conn_state->connector); 318 316 struct intel_panel *panel = &connector->panel; 319 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 320 317 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 321 318 struct hdr_output_metadata *hdr_metadata; 322 319 int ret; ··· 326 323 327 324 ret = drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &old_ctrl); 328 325 if (ret != 1) { 329 - drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read current backlight control mode: %d\n", 326 + drm_err(display->drm, 327 + "[CONNECTOR:%d:%s] Failed to read current backlight control mode: %d\n", 330 328 connector->base.base.id, connector->base.name, ret); 331 329 return; 332 330 } ··· 350 346 351 347 if (ctrl != old_ctrl && 352 348 drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1) 353 - drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to configure DPCD brightness controls\n", 349 + drm_err(display->drm, 350 + "[CONNECTOR:%d:%s] Failed to configure DPCD brightness controls\n", 354 351 connector->base.base.id, connector->base.name); 355 352 356 353 if (intel_dp_in_hdr_mode(conn_state)) { ··· 382 377 static void 383 378 intel_dp_aux_write_panel_luminance_override(struct intel_connector *connector) 384 379 { 385 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 380 + struct intel_display *display = to_intel_display(connector); 386 381 struct intel_panel *panel = &connector->panel; 387 382 struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 388 383 int ret; ··· 397 392 INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE, 398 393 buf, sizeof(buf)); 399 394 if (ret < 0) 400 - drm_dbg_kms(&i915->drm, 395 + drm_dbg_kms(display->drm, 401 396 "Panel Luminance DPCD reg write failed, err:-%d\n", 402 397 ret); 403 398 } ··· 405 400 static int 406 401 intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pipe) 407 402 { 408 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 403 + struct intel_display *display = to_intel_display(connector); 409 404 struct intel_panel *panel = &connector->panel; 410 405 struct drm_luminance_range_info *luminance_range = 411 406 &connector->base.display_info.luminance_range; 412 407 int ret; 413 408 414 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDR backlight is controlled through %s\n", 409 + drm_dbg_kms(display->drm, 410 + "[CONNECTOR:%d:%s] SDR backlight is controlled through %s\n", 415 411 connector->base.base.id, connector->base.name, 416 412 dpcd_vs_pwm_str(panel->backlight.edp.intel_cap.sdr_uses_aux)); 417 413 418 414 if (!panel->backlight.edp.intel_cap.sdr_uses_aux) { 419 415 ret = panel->backlight.pwm_funcs->setup(connector, pipe); 420 416 if (ret < 0) { 421 - drm_err(&i915->drm, 417 + drm_err(display->drm, 422 418 "[CONNECTOR:%d:%s] Failed to setup SDR backlight controls through PWM: %d\n", 423 419 connector->base.base.id, connector->base.name, ret); 424 420 return ret; ··· 436 430 437 431 intel_dp_aux_write_panel_luminance_override(connector); 438 432 439 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Using AUX HDR interface for backlight control (range %d..%d)\n", 433 + drm_dbg_kms(display->drm, 434 + "[CONNECTOR:%d:%s] Using AUX HDR interface for backlight control (range %d..%d)\n", 440 435 connector->base.base.id, connector->base.name, 441 436 panel->backlight.min, panel->backlight.max); 442 437 ··· 508 501 509 502 static int intel_dp_aux_vesa_setup_backlight(struct intel_connector *connector, enum pipe pipe) 510 503 { 504 + struct intel_display *display = to_intel_display(connector); 511 505 struct intel_dp *intel_dp = intel_attached_dp(connector); 512 506 struct intel_panel *panel = &connector->panel; 513 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 514 507 u16 current_level; 515 508 u8 current_mode; 516 509 int ret; ··· 521 514 if (ret < 0) 522 515 return ret; 523 516 524 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] AUX VESA backlight enable is controlled through %s\n", 517 + drm_dbg_kms(display->drm, 518 + "[CONNECTOR:%d:%s] AUX VESA backlight enable is controlled through %s\n", 525 519 connector->base.base.id, connector->base.name, 526 520 dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_enable)); 527 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] AUX VESA backlight level is controlled through %s\n", 521 + drm_dbg_kms(display->drm, 522 + "[CONNECTOR:%d:%s] AUX VESA backlight level is controlled through %s\n", 528 523 connector->base.base.id, connector->base.name, 529 524 dpcd_vs_pwm_str(panel->backlight.edp.vesa.info.aux_set)); 530 525 531 526 if (!panel->backlight.edp.vesa.info.aux_set || !panel->backlight.edp.vesa.info.aux_enable) { 532 527 ret = panel->backlight.pwm_funcs->setup(connector, pipe); 533 528 if (ret < 0) { 534 - drm_err(&i915->drm, 529 + drm_err(display->drm, 535 530 "[CONNECTOR:%d:%s] Failed to setup PWM backlight controls for eDP backlight: %d\n", 536 531 connector->base.base.id, connector->base.name, ret); 537 532 return ret; ··· 562 553 } 563 554 } 564 555 565 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Using AUX VESA interface for backlight control\n", 556 + drm_dbg_kms(display->drm, 557 + "[CONNECTOR:%d:%s] Using AUX VESA interface for backlight control\n", 566 558 connector->base.base.id, connector->base.name); 567 559 568 560 return 0; ··· 572 562 static bool 573 563 intel_dp_aux_supports_vesa_backlight(struct intel_connector *connector) 574 564 { 565 + struct intel_display *display = to_intel_display(connector); 575 566 struct intel_dp *intel_dp = intel_attached_dp(connector); 576 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 577 567 578 568 if (drm_edp_backlight_supported(intel_dp->edp_dpcd)) { 579 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] AUX Backlight Control Supported!\n", 569 + drm_dbg_kms(display->drm, 570 + "[CONNECTOR:%d:%s] AUX Backlight Control Supported!\n", 580 571 connector->base.base.id, connector->base.name); 581 572 return true; 582 573 } ··· 602 591 603 592 int intel_dp_aux_init_backlight_funcs(struct intel_connector *connector) 604 593 { 594 + struct intel_display *display = to_intel_display(connector); 605 595 struct drm_device *dev = connector->base.dev; 606 596 struct intel_panel *panel = &connector->panel; 607 - struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); 608 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 609 597 bool try_intel_interface = false, try_vesa_interface = false; 610 598 611 599 /* Check the VBT and user's module parameters to figure out which 612 600 * interfaces to probe 613 601 */ 614 - switch (i915->display.params.enable_dpcd_backlight) { 602 + switch (display->params.enable_dpcd_backlight) { 615 603 case INTEL_DP_AUX_BACKLIGHT_OFF: 616 604 return -ENODEV; 617 605 case INTEL_DP_AUX_BACKLIGHT_AUTO:

+40

drivers/gpu/drm/i915/display/intel_dp_mst.c

··· 2062 2062 2063 2063 intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count); 2064 2064 } 2065 + 2066 + /* 2067 + * intel_dp_mst_verify_dpcd_state - verify the MST SW enabled state wrt. the DPCD 2068 + * @intel_dp: DP port object 2069 + * 2070 + * Verify if @intel_dp's MST enabled SW state matches the corresponding DPCD 2071 + * state. A long HPD pulse - not long enough to be detected as a disconnected 2072 + * state - could've reset the DPCD state, which requires tearing 2073 + * down/recreating the MST topology. 2074 + * 2075 + * Returns %true if the SW MST enabled and DPCD states match, %false 2076 + * otherwise. 2077 + */ 2078 + bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp) 2079 + { 2080 + struct intel_display *display = to_intel_display(intel_dp); 2081 + struct intel_connector *connector = intel_dp->attached_connector; 2082 + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2083 + struct intel_encoder *encoder = &dig_port->base; 2084 + int ret; 2085 + u8 val; 2086 + 2087 + if (!intel_dp->is_mst) 2088 + return true; 2089 + 2090 + ret = drm_dp_dpcd_readb(intel_dp->mst_mgr.aux, DP_MSTM_CTRL, &val); 2091 + 2092 + /* Adjust the expected register value for SST + SideBand. */ 2093 + if (ret < 0 || val != (DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC)) { 2094 + drm_dbg_kms(display->drm, 2095 + "[CONNECTOR:%d:%s][ENCODER:%d:%s] MST mode got reset, removing topology (ret=%d, ctrl=0x%02x)\n", 2096 + connector->base.base.id, connector->base.name, 2097 + encoder->base.base.id, encoder->base.name, 2098 + ret, val); 2099 + 2100 + return false; 2101 + } 2102 + 2103 + return true; 2104 + }

+1

drivers/gpu/drm/i915/display/intel_dp_mst.h

··· 28 28 bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state, 29 29 struct intel_crtc *crtc); 30 30 void intel_dp_mst_prepare_probe(struct intel_dp *intel_dp); 31 + bool intel_dp_mst_verify_dpcd_state(struct intel_dp *intel_dp); 31 32 32 33 #endif /* __INTEL_DP_MST_H__ */

+2 -1

drivers/gpu/drm/i915/display/intel_dpll_mgr.c

··· 3339 3339 struct intel_crtc *crtc, 3340 3340 struct intel_encoder *encoder) 3341 3341 { 3342 + struct intel_display *display = to_intel_display(crtc); 3342 3343 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 3343 3344 struct intel_crtc_state *crtc_state = 3344 3345 intel_atomic_get_new_crtc_state(state, crtc); ··· 3380 3379 } 3381 3380 3382 3381 /* Eliminate DPLLs from consideration if reserved by HTI */ 3383 - dpll_mask &= ~intel_hti_dpll_mask(i915); 3382 + dpll_mask &= ~intel_hti_dpll_mask(display); 3384 3383 3385 3384 port_dpll->pll = intel_find_shared_dpll(state, crtc, 3386 3385 &port_dpll->hw_state,

+293 -32

drivers/gpu/drm/i915/display/intel_dsb.c

··· 6 6 7 7 #include "i915_drv.h" 8 8 #include "i915_irq.h" 9 + #include "i915_reg.h" 9 10 #include "intel_crtc.h" 10 11 #include "intel_de.h" 11 12 #include "intel_display_types.h" ··· 43 42 */ 44 43 unsigned int ins_start_offset; 45 44 46 - int dewake_scanline; 45 + u32 chicken; 46 + int hw_dewake_scanline; 47 47 }; 48 48 49 49 /** ··· 83 81 /* see DSB_REG_VALUE_MASK */ 84 82 #define DSB_OPCODE_POLL 0xA 85 83 /* see DSB_REG_VALUE_MASK */ 84 + 85 + static bool pre_commit_is_vrr_active(struct intel_atomic_state *state, 86 + struct intel_crtc *crtc) 87 + { 88 + const struct intel_crtc_state *old_crtc_state = 89 + intel_atomic_get_old_crtc_state(state, crtc); 90 + const struct intel_crtc_state *new_crtc_state = 91 + intel_atomic_get_new_crtc_state(state, crtc); 92 + 93 + /* VRR will be enabled afterwards, if necessary */ 94 + if (intel_crtc_needs_modeset(new_crtc_state)) 95 + return false; 96 + 97 + /* VRR will have been disabled during intel_pre_plane_update() */ 98 + return old_crtc_state->vrr.enable && !intel_crtc_vrr_disabling(state, crtc); 99 + } 100 + 101 + static const struct intel_crtc_state * 102 + pre_commit_crtc_state(struct intel_atomic_state *state, 103 + struct intel_crtc *crtc) 104 + { 105 + const struct intel_crtc_state *old_crtc_state = 106 + intel_atomic_get_old_crtc_state(state, crtc); 107 + const struct intel_crtc_state *new_crtc_state = 108 + intel_atomic_get_new_crtc_state(state, crtc); 109 + 110 + /* 111 + * During fastsets/etc. the transcoder is still 112 + * running with the old timings at this point. 113 + */ 114 + if (intel_crtc_needs_modeset(new_crtc_state)) 115 + return new_crtc_state; 116 + else 117 + return old_crtc_state; 118 + } 119 + 120 + static int dsb_vtotal(struct intel_atomic_state *state, 121 + struct intel_crtc *crtc) 122 + { 123 + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); 124 + 125 + if (pre_commit_is_vrr_active(state, crtc)) 126 + return crtc_state->vrr.vmax; 127 + else 128 + return intel_mode_vtotal(&crtc_state->hw.adjusted_mode); 129 + } 130 + 131 + static int dsb_dewake_scanline_start(struct intel_atomic_state *state, 132 + struct intel_crtc *crtc) 133 + { 134 + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); 135 + struct drm_i915_private *i915 = to_i915(state->base.dev); 136 + unsigned int latency = skl_watermark_max_latency(i915, 0); 137 + 138 + return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode) - 139 + intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, latency); 140 + } 141 + 142 + static int dsb_dewake_scanline_end(struct intel_atomic_state *state, 143 + struct intel_crtc *crtc) 144 + { 145 + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); 146 + 147 + return intel_mode_vdisplay(&crtc_state->hw.adjusted_mode); 148 + } 149 + 150 + static int dsb_scanline_to_hw(struct intel_atomic_state *state, 151 + struct intel_crtc *crtc, int scanline) 152 + { 153 + const struct intel_crtc_state *crtc_state = pre_commit_crtc_state(state, crtc); 154 + int vtotal = dsb_vtotal(state, crtc); 155 + 156 + return (scanline + vtotal - intel_crtc_scanline_offset(crtc_state)) % vtotal; 157 + } 158 + 159 + static u32 dsb_chicken(struct intel_atomic_state *state, 160 + struct intel_crtc *crtc) 161 + { 162 + if (pre_commit_is_vrr_active(state, crtc)) 163 + return DSB_SKIP_WAITS_EN | 164 + DSB_CTRL_WAIT_SAFE_WINDOW | 165 + DSB_CTRL_NO_WAIT_VBLANK | 166 + DSB_INST_WAIT_SAFE_WINDOW | 167 + DSB_INST_NO_WAIT_VBLANK; 168 + else 169 + return DSB_SKIP_WAITS_EN; 170 + } 86 171 87 172 static bool assert_dsb_has_room(struct intel_dsb *dsb) 88 173 { ··· 370 281 intel_dsb_noop(dsb, 4); 371 282 } 372 283 284 + static void intel_dsb_emit_wait_dsl(struct intel_dsb *dsb, 285 + u32 opcode, int lower, int upper) 286 + { 287 + u64 window = ((u64)upper << DSB_SCANLINE_UPPER_SHIFT) | 288 + ((u64)lower << DSB_SCANLINE_LOWER_SHIFT); 289 + 290 + intel_dsb_emit(dsb, lower_32_bits(window), 291 + (opcode << DSB_OPCODE_SHIFT) | 292 + upper_32_bits(window)); 293 + } 294 + 295 + static void intel_dsb_wait_dsl(struct intel_atomic_state *state, 296 + struct intel_dsb *dsb, 297 + int lower_in, int upper_in, 298 + int lower_out, int upper_out) 299 + { 300 + struct intel_crtc *crtc = dsb->crtc; 301 + 302 + lower_in = dsb_scanline_to_hw(state, crtc, lower_in); 303 + upper_in = dsb_scanline_to_hw(state, crtc, upper_in); 304 + 305 + lower_out = dsb_scanline_to_hw(state, crtc, lower_out); 306 + upper_out = dsb_scanline_to_hw(state, crtc, upper_out); 307 + 308 + if (upper_in >= lower_in) 309 + intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_IN, 310 + lower_in, upper_in); 311 + else if (upper_out >= lower_out) 312 + intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 313 + lower_out, upper_out); 314 + else 315 + drm_WARN_ON(crtc->base.dev, 1); /* assert_dsl_ok() should have caught it already */ 316 + } 317 + 318 + static void assert_dsl_ok(struct intel_atomic_state *state, 319 + struct intel_dsb *dsb, 320 + int start, int end) 321 + { 322 + struct intel_crtc *crtc = dsb->crtc; 323 + int vtotal = dsb_vtotal(state, crtc); 324 + 325 + /* 326 + * Waiting for the entire frame doesn't make sense, 327 + * (IN==don't wait, OUT=wait forever). 328 + */ 329 + drm_WARN(crtc->base.dev, (end - start + vtotal) % vtotal == vtotal - 1, 330 + "[CRTC:%d:%s] DSB %d bad scanline window wait: %d-%d (vt=%d)\n", 331 + crtc->base.base.id, crtc->base.name, dsb->id, 332 + start, end, vtotal); 333 + } 334 + 335 + void intel_dsb_wait_scanline_in(struct intel_atomic_state *state, 336 + struct intel_dsb *dsb, 337 + int start, int end) 338 + { 339 + assert_dsl_ok(state, dsb, start, end); 340 + 341 + intel_dsb_wait_dsl(state, dsb, 342 + start, end, 343 + end + 1, start - 1); 344 + } 345 + 346 + void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, 347 + struct intel_dsb *dsb, 348 + int start, int end) 349 + { 350 + assert_dsl_ok(state, dsb, start, end); 351 + 352 + intel_dsb_wait_dsl(state, dsb, 353 + end + 1, start - 1, 354 + start, end); 355 + } 356 + 373 357 static void intel_dsb_align_tail(struct intel_dsb *dsb) 374 358 { 375 359 u32 aligned_tail, tail; ··· 464 302 /* 465 303 * DSB_FORCE_DEWAKE remains active even after DSB is 466 304 * disabled, so make sure to clear it (if set during 467 - * intel_dsb_commit()). 305 + * intel_dsb_commit()). And clear DSB_ENABLE_DEWAKE as 306 + * well for good measure. 468 307 */ 308 + intel_dsb_reg_write(dsb, DSB_PMCTRL(crtc->pipe, dsb->id), 0); 469 309 intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(crtc->pipe, dsb->id), 470 310 DSB_FORCE_DEWAKE, 0); 471 311 ··· 476 312 intel_dsb_buffer_flush_map(&dsb->dsb_buf); 477 313 } 478 314 479 - static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) 315 + static u32 dsb_error_int_status(struct intel_display *display) 480 316 { 481 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 482 - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 483 - unsigned int latency = skl_watermark_max_latency(i915, 0); 484 - int vblank_start; 317 + u32 errors; 485 318 486 - if (crtc_state->vrr.enable) 487 - vblank_start = intel_vrr_vmin_vblank_start(crtc_state); 488 - else 489 - vblank_start = intel_mode_vblank_start(adjusted_mode); 319 + errors = DSB_GTT_FAULT_INT_STATUS | 320 + DSB_RSPTIMEOUT_INT_STATUS | 321 + DSB_POLL_ERR_INT_STATUS; 490 322 491 - return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency)); 323 + /* 324 + * All the non-existing status bits operate as 325 + * normal r/w bits, so any attempt to clear them 326 + * will just end up setting them. Never do that so 327 + * we won't mistake them for actual error interrupts. 328 + */ 329 + if (DISPLAY_VER(display) >= 14) 330 + errors |= DSB_ATS_FAULT_INT_STATUS; 331 + 332 + return errors; 492 333 } 493 334 494 - static u32 dsb_chicken(struct intel_crtc *crtc) 335 + static u32 dsb_error_int_en(struct intel_display *display) 495 336 { 496 - if (crtc->mode_flags & I915_MODE_FLAG_VRR) 497 - return DSB_SKIP_WAITS_EN | 498 - DSB_CTRL_WAIT_SAFE_WINDOW | 499 - DSB_CTRL_NO_WAIT_VBLANK | 500 - DSB_INST_WAIT_SAFE_WINDOW | 501 - DSB_INST_NO_WAIT_VBLANK; 502 - else 503 - return DSB_SKIP_WAITS_EN; 337 + u32 errors; 338 + 339 + errors = DSB_GTT_FAULT_INT_EN | 340 + DSB_RSPTIMEOUT_INT_EN | 341 + DSB_POLL_ERR_INT_EN; 342 + 343 + if (DISPLAY_VER(display) >= 14) 344 + errors |= DSB_ATS_FAULT_INT_EN; 345 + 346 + return errors; 347 + } 348 + 349 + static void _intel_dsb_chain(struct intel_atomic_state *state, 350 + struct intel_dsb *dsb, 351 + struct intel_dsb *chained_dsb, 352 + u32 ctrl) 353 + { 354 + struct intel_display *display = to_intel_display(state->base.dev); 355 + struct intel_crtc *crtc = dsb->crtc; 356 + enum pipe pipe = crtc->pipe; 357 + u32 tail; 358 + 359 + if (drm_WARN_ON(display->drm, dsb->id == chained_dsb->id)) 360 + return; 361 + 362 + tail = chained_dsb->free_pos * 4; 363 + if (drm_WARN_ON(display->drm, !IS_ALIGNED(tail, CACHELINE_BYTES))) 364 + return; 365 + 366 + intel_dsb_reg_write(dsb, DSB_CTRL(pipe, chained_dsb->id), 367 + ctrl | DSB_ENABLE); 368 + 369 + intel_dsb_reg_write(dsb, DSB_CHICKEN(pipe, chained_dsb->id), 370 + dsb_chicken(state, crtc)); 371 + 372 + intel_dsb_reg_write(dsb, DSB_INTERRUPT(pipe, chained_dsb->id), 373 + dsb_error_int_status(display) | DSB_PROG_INT_STATUS | 374 + dsb_error_int_en(display)); 375 + 376 + if (ctrl & DSB_WAIT_FOR_VBLANK) { 377 + int dewake_scanline = dsb_dewake_scanline_start(state, crtc); 378 + int hw_dewake_scanline = dsb_scanline_to_hw(state, crtc, dewake_scanline); 379 + 380 + intel_dsb_reg_write(dsb, DSB_PMCTRL(pipe, chained_dsb->id), 381 + DSB_ENABLE_DEWAKE | 382 + DSB_SCANLINE_FOR_DEWAKE(hw_dewake_scanline)); 383 + } 384 + 385 + intel_dsb_reg_write(dsb, DSB_HEAD(pipe, chained_dsb->id), 386 + intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf)); 387 + 388 + intel_dsb_reg_write(dsb, DSB_TAIL(pipe, chained_dsb->id), 389 + intel_dsb_buffer_ggtt_offset(&chained_dsb->dsb_buf) + tail); 390 + 391 + if (ctrl & DSB_WAIT_FOR_VBLANK) { 392 + /* 393 + * Keep DEwake alive via the first DSB, in 394 + * case we're already past dewake_scanline, 395 + * and thus DSB_ENABLE_DEWAKE on the second 396 + * DSB won't do its job. 397 + */ 398 + intel_dsb_reg_write_masked(dsb, DSB_PMCTRL_2(pipe, dsb->id), 399 + DSB_FORCE_DEWAKE, DSB_FORCE_DEWAKE); 400 + 401 + intel_dsb_wait_scanline_out(state, dsb, 402 + dsb_dewake_scanline_start(state, crtc), 403 + dsb_dewake_scanline_end(state, crtc)); 404 + } 405 + } 406 + 407 + void intel_dsb_chain(struct intel_atomic_state *state, 408 + struct intel_dsb *dsb, 409 + struct intel_dsb *chained_dsb, 410 + bool wait_for_vblank) 411 + { 412 + _intel_dsb_chain(state, dsb, chained_dsb, 413 + wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0); 504 414 } 505 415 506 416 static void _intel_dsb_commit(struct intel_dsb *dsb, u32 ctrl, 507 - int dewake_scanline) 417 + int hw_dewake_scanline) 508 418 { 509 419 struct intel_crtc *crtc = dsb->crtc; 510 420 struct intel_display *display = to_intel_display(crtc->base.dev); ··· 599 361 ctrl | DSB_ENABLE); 600 362 601 363 intel_de_write_fw(display, DSB_CHICKEN(pipe, dsb->id), 602 - dsb_chicken(crtc)); 364 + dsb->chicken); 365 + 366 + intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), 367 + dsb_error_int_status(display) | DSB_PROG_INT_STATUS | 368 + dsb_error_int_en(display)); 603 369 604 370 intel_de_write_fw(display, DSB_HEAD(pipe, dsb->id), 605 371 intel_dsb_buffer_ggtt_offset(&dsb->dsb_buf)); 606 372 607 - if (dewake_scanline >= 0) { 608 - int diff, hw_dewake_scanline; 609 - 610 - hw_dewake_scanline = intel_crtc_scanline_to_hw(crtc, dewake_scanline); 373 + if (hw_dewake_scanline >= 0) { 374 + int diff, position; 611 375 612 376 intel_de_write_fw(display, DSB_PMCTRL(pipe, dsb->id), 613 377 DSB_ENABLE_DEWAKE | ··· 619 379 * Force DEwake immediately if we're already past 620 380 * or close to racing past the target scanline. 621 381 */ 622 - diff = dewake_scanline - intel_get_crtc_scanline(crtc); 382 + position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK; 383 + 384 + diff = hw_dewake_scanline - position; 623 385 intel_de_write_fw(display, DSB_PMCTRL_2(pipe, dsb->id), 624 386 (diff >= 0 && diff < 5 ? DSB_FORCE_DEWAKE : 0) | 625 387 DSB_BLOCK_DEWAKE_EXTENSION); ··· 643 401 { 644 402 _intel_dsb_commit(dsb, 645 403 wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0, 646 - wait_for_vblank ? dsb->dewake_scanline : -1); 404 + wait_for_vblank ? dsb->hw_dewake_scanline : -1); 647 405 } 648 406 649 407 void intel_dsb_wait(struct intel_dsb *dsb) ··· 672 430 dsb->free_pos = 0; 673 431 dsb->ins_start_offset = 0; 674 432 intel_de_write_fw(display, DSB_CTRL(pipe, dsb->id), 0); 433 + 434 + intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb->id), 435 + dsb_error_int_status(display) | DSB_PROG_INT_STATUS); 675 436 } 676 437 677 438 /** ··· 696 451 unsigned int max_cmds) 697 452 { 698 453 struct drm_i915_private *i915 = to_i915(state->base.dev); 699 - const struct intel_crtc_state *crtc_state = 700 - intel_atomic_get_new_crtc_state(state, crtc); 701 454 intel_wakeref_t wakeref; 702 455 struct intel_dsb *dsb; 703 456 unsigned int size; ··· 729 486 dsb->size = size / 4; /* in dwords */ 730 487 dsb->free_pos = 0; 731 488 dsb->ins_start_offset = 0; 732 - dsb->dewake_scanline = intel_dsb_dewake_scanline(crtc_state); 489 + 490 + dsb->chicken = dsb_chicken(state, crtc); 491 + dsb->hw_dewake_scanline = 492 + dsb_scanline_to_hw(state, crtc, dsb_dewake_scanline_start(state, crtc)); 733 493 734 494 return dsb; 735 495 ··· 758 512 { 759 513 intel_dsb_buffer_cleanup(&dsb->dsb_buf); 760 514 kfree(dsb); 515 + } 516 + 517 + void intel_dsb_irq_handler(struct intel_display *display, 518 + enum pipe pipe, enum intel_dsb_id dsb_id) 519 + { 520 + struct intel_crtc *crtc = intel_crtc_for_pipe(to_i915(display->drm), pipe); 521 + u32 tmp, errors; 522 + 523 + tmp = intel_de_read_fw(display, DSB_INTERRUPT(pipe, dsb_id)); 524 + intel_de_write_fw(display, DSB_INTERRUPT(pipe, dsb_id), tmp); 525 + 526 + errors = tmp & dsb_error_int_status(display); 527 + if (errors) 528 + drm_err(display->drm, "[CRTC:%d:%s] DSB %d error interrupt: 0x%x\n", 529 + crtc->base.base.id, crtc->base.name, dsb_id, errors); 761 530 }

+16

drivers/gpu/drm/i915/display/intel_dsb.h

··· 13 13 struct intel_atomic_state; 14 14 struct intel_crtc; 15 15 struct intel_crtc_state; 16 + struct intel_display; 16 17 struct intel_dsb; 18 + 19 + enum pipe; 17 20 18 21 enum intel_dsb_id { 19 22 INTEL_DSB_0, ··· 39 36 void intel_dsb_noop(struct intel_dsb *dsb, int count); 40 37 void intel_dsb_nonpost_start(struct intel_dsb *dsb); 41 38 void intel_dsb_nonpost_end(struct intel_dsb *dsb); 39 + void intel_dsb_wait_scanline_in(struct intel_atomic_state *state, 40 + struct intel_dsb *dsb, 41 + int lower, int upper); 42 + void intel_dsb_wait_scanline_out(struct intel_atomic_state *state, 43 + struct intel_dsb *dsb, 44 + int lower, int upper); 45 + void intel_dsb_chain(struct intel_atomic_state *state, 46 + struct intel_dsb *dsb, 47 + struct intel_dsb *chained_dsb, 48 + bool wait_for_vblank); 42 49 43 50 void intel_dsb_commit(struct intel_dsb *dsb, 44 51 bool wait_for_vblank); 45 52 void intel_dsb_wait(struct intel_dsb *dsb); 53 + 54 + void intel_dsb_irq_handler(struct intel_display *display, 55 + enum pipe pipe, enum intel_dsb_id dsb_id); 46 56 47 57 #endif

+36

drivers/gpu/drm/i915/display/intel_fb.c

··· 163 163 164 164 static const struct intel_modifier_desc intel_modifiers[] = { 165 165 { 166 + .modifier = I915_FORMAT_MOD_4_TILED_LNL_CCS, 167 + .display_ver = { 20, -1 }, 168 + .plane_caps = INTEL_PLANE_CAP_TILING_4, 169 + }, { 170 + .modifier = I915_FORMAT_MOD_4_TILED_BMG_CCS, 171 + .display_ver = { 14, -1 }, 172 + .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_NEED64K_PHYS, 173 + }, { 166 174 .modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS, 167 175 .display_ver = { 14, 14 }, 168 176 .plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC, ··· 420 412 INTEL_PLANE_CAP_CCS_MC); 421 413 } 422 414 415 + /** 416 + * intel_fb_needs_64k_phys: Check if modifier requires 64k physical placement. 417 + * @modifier: Modifier to check 418 + * 419 + * Returns: 420 + * Returns %true if @modifier requires 64k aligned physical pages. 421 + */ 422 + bool intel_fb_needs_64k_phys(u64 modifier) 423 + { 424 + const struct intel_modifier_desc *md = lookup_modifier_or_null(modifier); 425 + 426 + if (!md) 427 + return false; 428 + 429 + return plane_caps_contain_any(md->plane_caps, 430 + INTEL_PLANE_CAP_NEED64K_PHYS); 431 + } 432 + 423 433 static bool check_modifier_display_ver_range(const struct intel_modifier_desc *md, 424 434 u8 display_ver_from, u8 display_ver_until) 425 435 { ··· 461 435 */ 462 436 if (intel_fb_is_ccs_modifier(md->modifier) && 463 437 HAS_FLAT_CCS(i915) != !md->ccs.packed_aux_planes) 438 + return false; 439 + 440 + if (md->modifier == I915_FORMAT_MOD_4_TILED_BMG_CCS && 441 + (GRAPHICS_VER(i915) < 20 || !IS_DGFX(i915))) 442 + return false; 443 + 444 + if (md->modifier == I915_FORMAT_MOD_4_TILED_LNL_CCS && 445 + (GRAPHICS_VER(i915) < 20 || IS_DGFX(i915))) 464 446 return false; 465 447 466 448 return true; ··· 687 653 return 128; 688 654 else 689 655 return 512; 656 + case I915_FORMAT_MOD_4_TILED_BMG_CCS: 657 + case I915_FORMAT_MOD_4_TILED_LNL_CCS: 690 658 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 691 659 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 692 660 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:

+2

drivers/gpu/drm/i915/display/intel_fb.h

··· 28 28 #define INTEL_PLANE_CAP_TILING_Y BIT(4) 29 29 #define INTEL_PLANE_CAP_TILING_Yf BIT(5) 30 30 #define INTEL_PLANE_CAP_TILING_4 BIT(6) 31 + #define INTEL_PLANE_CAP_NEED64K_PHYS BIT(7) 31 32 32 33 bool intel_fb_is_tiled_modifier(u64 modifier); 33 34 bool intel_fb_is_ccs_modifier(u64 modifier); 34 35 bool intel_fb_is_rc_ccs_cc_modifier(u64 modifier); 35 36 bool intel_fb_is_mc_ccs_modifier(u64 modifier); 37 + bool intel_fb_needs_64k_phys(u64 modifier); 36 38 37 39 bool intel_fb_is_ccs_aux_plane(const struct drm_framebuffer *fb, int color_plane); 38 40 int intel_fb_rc_ccs_cc_plane(const struct drm_framebuffer *fb);

+1 -1

drivers/gpu/drm/i915/display/intel_fbc.c

··· 1346 1346 1347 1347 /* Wa_14016291713 */ 1348 1348 if ((IS_DISPLAY_VER(display, 12, 13) || 1349 - IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) && 1349 + IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) && 1350 1350 crtc_state->has_psr && !crtc_state->has_panel_replay) { 1351 1351 plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; 1352 1352 return 0;

+3 -3

drivers/gpu/drm/i915/display/intel_hdcp.c

··· 42 42 return; 43 43 44 44 if (DISPLAY_VER(dev_priv) >= 14) { 45 - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER)) 45 + if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER)) 46 46 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), 47 47 0, HDCP_LINE_REKEY_DISABLE); 48 - else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || 49 - IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) 48 + else if (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || 49 + IS_DISPLAY_VER_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) 50 50 intel_de_rmw(dev_priv, 51 51 TRANS_DDI_FUNC_CTL(dev_priv, hdcp->cpu_transcoder), 52 52 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE);

+10 -10

drivers/gpu/drm/i915/display/intel_hti.c

··· 9 9 #include "intel_hti.h" 10 10 #include "intel_hti_regs.h" 11 11 12 - void intel_hti_init(struct drm_i915_private *i915) 12 + void intel_hti_init(struct intel_display *display) 13 13 { 14 14 /* 15 15 * If the platform has HTI, we need to find out whether it has reserved 16 16 * any display resources before we create our display outputs. 17 17 */ 18 - if (DISPLAY_INFO(i915)->has_hti) 19 - i915->display.hti.state = intel_de_read(i915, HDPORT_STATE); 18 + if (DISPLAY_INFO(display)->has_hti) 19 + display->hti.state = intel_de_read(display, HDPORT_STATE); 20 20 } 21 21 22 - bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy) 22 + bool intel_hti_uses_phy(struct intel_display *display, enum phy phy) 23 23 { 24 - if (drm_WARN_ON(&i915->drm, phy == PHY_NONE)) 24 + if (drm_WARN_ON(display->drm, phy == PHY_NONE)) 25 25 return false; 26 26 27 - return i915->display.hti.state & HDPORT_ENABLED && 28 - i915->display.hti.state & HDPORT_DDI_USED(phy); 27 + return display->hti.state & HDPORT_ENABLED && 28 + display->hti.state & HDPORT_DDI_USED(phy); 29 29 } 30 30 31 - u32 intel_hti_dpll_mask(struct drm_i915_private *i915) 31 + u32 intel_hti_dpll_mask(struct intel_display *display) 32 32 { 33 - if (!(i915->display.hti.state & HDPORT_ENABLED)) 33 + if (!(display->hti.state & HDPORT_ENABLED)) 34 34 return 0; 35 35 36 36 /* 37 37 * Note: This is subtle. The values must coincide with what's defined 38 38 * for the platform. 39 39 */ 40 - return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, i915->display.hti.state); 40 + return REG_FIELD_GET(HDPORT_DPLL_USED_MASK, display->hti.state); 41 41 }

+4 -4

drivers/gpu/drm/i915/display/intel_hti.h

··· 8 8 9 9 #include <linux/types.h> 10 10 11 - struct drm_i915_private; 11 + struct intel_display; 12 12 enum phy; 13 13 14 - void intel_hti_init(struct drm_i915_private *i915); 15 - bool intel_hti_uses_phy(struct drm_i915_private *i915, enum phy phy); 16 - u32 intel_hti_dpll_mask(struct drm_i915_private *i915); 14 + void intel_hti_init(struct intel_display *display); 15 + bool intel_hti_uses_phy(struct intel_display *display, enum phy phy); 16 + u32 intel_hti_dpll_mask(struct intel_display *display); 17 17 18 18 #endif /* __INTEL_HTI_H__ */

+13 -12

drivers/gpu/drm/i915/display/intel_link_bw.c

··· 25 25 void intel_link_bw_init_limits(struct intel_atomic_state *state, 26 26 struct intel_link_bw_limits *limits) 27 27 { 28 + struct intel_display *display = to_intel_display(state); 28 29 struct drm_i915_private *i915 = to_i915(state->base.dev); 29 30 enum pipe pipe; 30 31 31 32 limits->force_fec_pipes = 0; 32 33 limits->bpp_limit_reached_pipes = 0; 33 - for_each_pipe(i915, pipe) { 34 + for_each_pipe(display, pipe) { 34 35 const struct intel_crtc_state *crtc_state = 35 36 intel_atomic_get_new_crtc_state(state, 36 37 intel_crtc_for_pipe(i915, pipe)); ··· 70 69 u8 pipe_mask, 71 70 const char *reason) 72 71 { 73 - struct drm_i915_private *i915 = to_i915(state->base.dev); 72 + struct intel_display *display = to_intel_display(state); 74 73 enum pipe max_bpp_pipe = INVALID_PIPE; 75 74 struct intel_crtc *crtc; 76 75 int max_bpp_x16 = 0; 77 76 78 - for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { 77 + for_each_intel_crtc_in_pipe_mask(display->drm, crtc, pipe_mask) { 79 78 struct intel_crtc_state *crtc_state; 80 79 int link_bpp_x16; 81 80 ··· 137 136 struct intel_link_bw_limits *new_limits, 138 137 enum pipe pipe) 139 138 { 140 - struct drm_i915_private *i915 = to_i915(state->base.dev); 139 + struct intel_display *display = to_intel_display(state); 141 140 142 141 if (pipe == INVALID_PIPE) 143 142 return false; ··· 146 145 old_limits->max_bpp_x16[pipe]) 147 146 return false; 148 147 149 - if (drm_WARN_ON(&i915->drm, 148 + if (drm_WARN_ON(display->drm, 150 149 new_limits->bpp_limit_reached_pipes & BIT(pipe))) 151 150 return false; 152 151 ··· 179 178 } 180 179 181 180 static bool 182 - assert_link_limit_change_valid(struct drm_i915_private *i915, 181 + assert_link_limit_change_valid(struct intel_display *display, 183 182 const struct intel_link_bw_limits *old_limits, 184 183 const struct intel_link_bw_limits *new_limits) 185 184 { ··· 187 186 enum pipe pipe; 188 187 189 188 /* FEC can't be forced off after it was forced on. */ 190 - if (drm_WARN_ON(&i915->drm, 189 + if (drm_WARN_ON(display->drm, 191 190 (old_limits->force_fec_pipes & new_limits->force_fec_pipes) != 192 191 old_limits->force_fec_pipes)) 193 192 return false; 194 193 195 - for_each_pipe(i915, pipe) { 194 + for_each_pipe(display, pipe) { 196 195 /* The bpp limit can only decrease. */ 197 - if (drm_WARN_ON(&i915->drm, 196 + if (drm_WARN_ON(display->drm, 198 197 new_limits->max_bpp_x16[pipe] > 199 198 old_limits->max_bpp_x16[pipe])) 200 199 return false; ··· 205 204 } 206 205 207 206 /* At least one limit must change. */ 208 - if (drm_WARN_ON(&i915->drm, 207 + if (drm_WARN_ON(display->drm, 209 208 !bpps_changed && 210 209 new_limits->force_fec_pipes == 211 210 old_limits->force_fec_pipes)) ··· 233 232 int intel_link_bw_atomic_check(struct intel_atomic_state *state, 234 233 struct intel_link_bw_limits *new_limits) 235 234 { 236 - struct drm_i915_private *i915 = to_i915(state->base.dev); 235 + struct intel_display *display = to_intel_display(state); 237 236 struct intel_link_bw_limits old_limits = *new_limits; 238 237 int ret; 239 238 ··· 241 240 if (ret != -EAGAIN) 242 241 return ret; 243 242 244 - if (!assert_link_limit_change_valid(i915, &old_limits, new_limits)) 243 + if (!assert_link_limit_change_valid(display, &old_limits, new_limits)) 245 244 return -EINVAL; 246 245 247 246 return -EAGAIN;

-2

drivers/gpu/drm/i915/display/intel_link_bw.h

··· 10 10 11 11 #include "intel_display_limits.h" 12 12 13 - struct drm_i915_private; 14 - 15 13 struct intel_atomic_state; 16 14 struct intel_crtc_state; 17 15

+13 -14

drivers/gpu/drm/i915/display/intel_load_detect.c

··· 48 48 intel_load_detect_get_pipe(struct drm_connector *connector, 49 49 struct drm_modeset_acquire_ctx *ctx) 50 50 { 51 + struct intel_display *display = to_intel_display(connector->dev); 51 52 struct intel_encoder *encoder = 52 53 intel_attached_encoder(to_intel_connector(connector)); 53 54 struct intel_crtc *possible_crtc; 54 55 struct intel_crtc *crtc = NULL; 55 - struct drm_device *dev = encoder->base.dev; 56 - struct drm_i915_private *dev_priv = to_i915(dev); 57 - struct drm_mode_config *config = &dev->mode_config; 56 + struct drm_mode_config *config = &display->drm->mode_config; 58 57 struct drm_atomic_state *state = NULL, *restore_state = NULL; 59 58 struct drm_connector_state *connector_state; 60 59 struct intel_crtc_state *crtc_state; 61 60 int ret; 62 61 63 - drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 62 + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 64 63 connector->base.id, connector->name, 65 64 encoder->base.base.id, encoder->base.name); 66 65 67 - drm_WARN_ON(dev, !drm_modeset_is_locked(&config->connection_mutex)); 66 + drm_WARN_ON(display->drm, !drm_modeset_is_locked(&config->connection_mutex)); 68 67 69 68 /* 70 69 * Algorithm gets a little messy: ··· 88 89 } 89 90 90 91 /* Find an unused one (if possible) */ 91 - for_each_intel_crtc(dev, possible_crtc) { 92 + for_each_intel_crtc(display->drm, possible_crtc) { 92 93 if (!(encoder->base.possible_crtcs & 93 94 drm_crtc_mask(&possible_crtc->base))) 94 95 continue; ··· 110 111 * If we didn't find an unused CRTC, don't use any. 111 112 */ 112 113 if (!crtc) { 113 - drm_dbg_kms(&dev_priv->drm, 114 + drm_dbg_kms(display->drm, 114 115 "no pipe available for load-detect\n"); 115 116 ret = -ENODEV; 116 117 goto fail; 117 118 } 118 119 119 120 found: 120 - state = drm_atomic_state_alloc(dev); 121 - restore_state = drm_atomic_state_alloc(dev); 121 + state = drm_atomic_state_alloc(display->drm); 122 + restore_state = drm_atomic_state_alloc(display->drm); 122 123 if (!state || !restore_state) { 123 124 ret = -ENOMEM; 124 125 goto fail; ··· 163 164 if (!ret) 164 165 ret = drm_atomic_add_affected_planes(restore_state, &crtc->base); 165 166 if (ret) { 166 - drm_dbg_kms(&dev_priv->drm, 167 + drm_dbg_kms(display->drm, 167 168 "Failed to create a copy of old state to restore: %i\n", 168 169 ret); 169 170 goto fail; ··· 171 172 172 173 ret = drm_atomic_commit(state); 173 174 if (ret) { 174 - drm_dbg_kms(&dev_priv->drm, 175 + drm_dbg_kms(display->drm, 175 176 "failed to set mode on load-detect pipe\n"); 176 177 goto fail; 177 178 } ··· 203 204 struct drm_atomic_state *state, 204 205 struct drm_modeset_acquire_ctx *ctx) 205 206 { 207 + struct intel_display *display = to_intel_display(connector->dev); 206 208 struct intel_encoder *intel_encoder = 207 209 intel_attached_encoder(to_intel_connector(connector)); 208 - struct drm_i915_private *i915 = to_i915(intel_encoder->base.dev); 209 210 struct drm_encoder *encoder = &intel_encoder->base; 210 211 int ret; 211 212 212 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 213 + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", 213 214 connector->base.id, connector->name, 214 215 encoder->base.id, encoder->name); 215 216 ··· 218 219 219 220 ret = drm_atomic_helper_commit_duplicated_state(state, ctx); 220 221 if (ret) 221 - drm_dbg_kms(&i915->drm, 222 + drm_dbg_kms(display->drm, 222 223 "Couldn't release load detect pipe: %i\n", ret); 223 224 drm_atomic_state_put(state); 224 225 }

+57 -58

drivers/gpu/drm/i915/display/intel_lspcon.c

··· 79 79 80 80 static bool lspcon_detect_vendor(struct intel_lspcon *lspcon) 81 81 { 82 - struct intel_dp *dp = lspcon_to_intel_dp(lspcon); 83 - struct drm_i915_private *i915 = dp_to_i915(dp); 82 + struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 83 + struct intel_display *display = to_intel_display(intel_dp); 84 84 struct drm_dp_dpcd_ident *ident; 85 85 u32 vendor_oui; 86 86 87 - if (drm_dp_read_desc(&dp->aux, &dp->desc, drm_dp_is_branch(dp->dpcd))) { 88 - drm_err(&i915->drm, "Can't read description\n"); 87 + if (drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, drm_dp_is_branch(intel_dp->dpcd))) { 88 + drm_err(display->drm, "Can't read description\n"); 89 89 return false; 90 90 } 91 91 92 - ident = &dp->desc.ident; 92 + ident = &intel_dp->desc.ident; 93 93 vendor_oui = (ident->oui[0] << 16) | (ident->oui[1] << 8) | 94 94 ident->oui[2]; 95 95 96 96 switch (vendor_oui) { 97 97 case LSPCON_VENDOR_MCA_OUI: 98 98 lspcon->vendor = LSPCON_VENDOR_MCA; 99 - drm_dbg_kms(&i915->drm, "Vendor: Mega Chips\n"); 99 + drm_dbg_kms(display->drm, "Vendor: Mega Chips\n"); 100 100 break; 101 101 102 102 case LSPCON_VENDOR_PARADE_OUI: 103 103 lspcon->vendor = LSPCON_VENDOR_PARADE; 104 - drm_dbg_kms(&i915->drm, "Vendor: Parade Tech\n"); 104 + drm_dbg_kms(display->drm, "Vendor: Parade Tech\n"); 105 105 break; 106 106 107 107 default: 108 - drm_err(&i915->drm, "Invalid/Unknown vendor OUI\n"); 108 + drm_err(display->drm, "Invalid/Unknown vendor OUI\n"); 109 109 return false; 110 110 } 111 111 ··· 123 123 void lspcon_detect_hdr_capability(struct intel_lspcon *lspcon) 124 124 { 125 125 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 126 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 126 + struct intel_display *display = to_intel_display(intel_dp); 127 127 u8 hdr_caps; 128 128 int ret; 129 129 ··· 131 131 &hdr_caps, 1); 132 132 133 133 if (ret < 0) { 134 - drm_dbg_kms(&i915->drm, "HDR capability detection failed\n"); 134 + drm_dbg_kms(display->drm, "HDR capability detection failed\n"); 135 135 lspcon->hdr_supported = false; 136 136 } else if (hdr_caps & 0x1) { 137 - drm_dbg_kms(&i915->drm, "LSPCON capable of HDR\n"); 137 + drm_dbg_kms(display->drm, "LSPCON capable of HDR\n"); 138 138 lspcon->hdr_supported = true; 139 139 } 140 140 } ··· 142 142 static enum drm_lspcon_mode lspcon_get_current_mode(struct intel_lspcon *lspcon) 143 143 { 144 144 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 145 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 145 + struct intel_display *display = to_intel_display(intel_dp); 146 146 enum drm_lspcon_mode current_mode; 147 147 struct i2c_adapter *ddc = &intel_dp->aux.ddc; 148 148 149 149 if (drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode)) { 150 - drm_dbg_kms(&i915->drm, "Error reading LSPCON mode\n"); 150 + drm_dbg_kms(display->drm, "Error reading LSPCON mode\n"); 151 151 return DRM_LSPCON_MODE_INVALID; 152 152 } 153 153 return current_mode; ··· 169 169 enum drm_lspcon_mode mode) 170 170 { 171 171 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 172 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 172 + struct intel_display *display = to_intel_display(intel_dp); 173 173 enum drm_lspcon_mode current_mode; 174 174 175 175 current_mode = lspcon_get_current_mode(lspcon); 176 176 if (current_mode == mode) 177 177 goto out; 178 178 179 - drm_dbg_kms(&i915->drm, "Waiting for LSPCON mode %s to settle\n", 179 + drm_dbg_kms(display->drm, "Waiting for LSPCON mode %s to settle\n", 180 180 lspcon_mode_name(mode)); 181 181 182 182 wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 183 183 lspcon_get_mode_settle_timeout(lspcon)); 184 184 if (current_mode != mode) 185 - drm_err(&i915->drm, "LSPCON mode hasn't settled\n"); 185 + drm_err(display->drm, "LSPCON mode hasn't settled\n"); 186 186 187 187 out: 188 - drm_dbg_kms(&i915->drm, "Current LSPCON mode %s\n", 188 + drm_dbg_kms(display->drm, "Current LSPCON mode %s\n", 189 189 lspcon_mode_name(current_mode)); 190 190 191 191 return current_mode; ··· 195 195 enum drm_lspcon_mode mode) 196 196 { 197 197 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 198 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 198 + struct intel_display *display = to_intel_display(intel_dp); 199 199 int err; 200 200 enum drm_lspcon_mode current_mode; 201 201 struct i2c_adapter *ddc = &intel_dp->aux.ddc; 202 202 203 203 err = drm_lspcon_get_mode(intel_dp->aux.drm_dev, ddc, &current_mode); 204 204 if (err) { 205 - drm_err(&i915->drm, "Error reading LSPCON mode\n"); 205 + drm_err(display->drm, "Error reading LSPCON mode\n"); 206 206 return err; 207 207 } 208 208 209 209 if (current_mode == mode) { 210 - drm_dbg_kms(&i915->drm, "Current mode = desired LSPCON mode\n"); 210 + drm_dbg_kms(display->drm, "Current mode = desired LSPCON mode\n"); 211 211 return 0; 212 212 } 213 213 214 214 err = drm_lspcon_set_mode(intel_dp->aux.drm_dev, ddc, mode); 215 215 if (err < 0) { 216 - drm_err(&i915->drm, "LSPCON mode change failed\n"); 216 + drm_err(display->drm, "LSPCON mode change failed\n"); 217 217 return err; 218 218 } 219 219 220 220 lspcon->mode = mode; 221 - drm_dbg_kms(&i915->drm, "LSPCON mode changed done\n"); 221 + drm_dbg_kms(display->drm, "LSPCON mode changed done\n"); 222 222 return 0; 223 223 } 224 224 225 225 static bool lspcon_wake_native_aux_ch(struct intel_lspcon *lspcon) 226 226 { 227 227 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 228 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 228 + struct intel_display *display = to_intel_display(intel_dp); 229 229 u8 rev; 230 230 231 231 if (drm_dp_dpcd_readb(&lspcon_to_intel_dp(lspcon)->aux, DP_DPCD_REV, 232 232 &rev) != 1) { 233 - drm_dbg_kms(&i915->drm, "Native AUX CH down\n"); 233 + drm_dbg_kms(display->drm, "Native AUX CH down\n"); 234 234 return false; 235 235 } 236 236 237 - drm_dbg_kms(&i915->drm, "Native AUX CH up, DPCD version: %d.%d\n", 237 + drm_dbg_kms(display->drm, "Native AUX CH up, DPCD version: %d.%d\n", 238 238 rev >> 4, rev & 0xf); 239 239 240 240 return true; ··· 242 242 243 243 static bool lspcon_probe(struct intel_lspcon *lspcon) 244 244 { 245 - int retry; 246 - enum drm_dp_dual_mode_type adaptor_type; 247 245 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 248 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 246 + struct intel_display *display = to_intel_display(intel_dp); 249 247 struct i2c_adapter *ddc = &intel_dp->aux.ddc; 248 + enum drm_dp_dual_mode_type adaptor_type; 250 249 enum drm_lspcon_mode expected_mode; 250 + int retry; 251 251 252 252 expected_mode = lspcon_wake_native_aux_ch(lspcon) ? 253 253 DRM_LSPCON_MODE_PCON : DRM_LSPCON_MODE_LS; ··· 263 263 } 264 264 265 265 if (adaptor_type != DRM_DP_DUAL_MODE_LSPCON) { 266 - drm_dbg_kms(&i915->drm, "No LSPCON detected, found %s\n", 266 + drm_dbg_kms(display->drm, "No LSPCON detected, found %s\n", 267 267 drm_dp_get_dual_mode_type_name(adaptor_type)); 268 268 return false; 269 269 } 270 270 271 271 /* Yay ... got a LSPCON device */ 272 - drm_dbg_kms(&i915->drm, "LSPCON detected\n"); 272 + drm_dbg_kms(display->drm, "LSPCON detected\n"); 273 273 lspcon->mode = lspcon_wait_mode(lspcon, expected_mode); 274 274 275 275 /* ··· 279 279 */ 280 280 if (lspcon->mode != DRM_LSPCON_MODE_PCON) { 281 281 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON) < 0) { 282 - drm_err(&i915->drm, "LSPCON mode change to PCON failed\n"); 282 + drm_err(display->drm, "LSPCON mode change to PCON failed\n"); 283 283 return false; 284 284 } 285 285 } ··· 289 289 static void lspcon_resume_in_pcon_wa(struct intel_lspcon *lspcon) 290 290 { 291 291 struct intel_dp *intel_dp = lspcon_to_intel_dp(lspcon); 292 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 292 + struct intel_display *display = to_intel_display(intel_dp); 293 293 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 294 294 unsigned long start = jiffies; 295 295 296 296 while (1) { 297 297 if (intel_digital_port_connected(&dig_port->base)) { 298 - drm_dbg_kms(&i915->drm, "LSPCON recovering in PCON mode after %u ms\n", 298 + drm_dbg_kms(display->drm, "LSPCON recovering in PCON mode after %u ms\n", 299 299 jiffies_to_msecs(jiffies - start)); 300 300 return; 301 301 } ··· 306 306 usleep_range(10000, 15000); 307 307 } 308 308 309 - drm_dbg_kms(&i915->drm, "LSPCON DP descriptor mismatch after resume\n"); 309 + drm_dbg_kms(display->drm, "LSPCON DP descriptor mismatch after resume\n"); 310 310 } 311 311 312 312 static bool lspcon_parade_fw_ready(struct drm_dp_aux *aux) ··· 477 477 unsigned int type, 478 478 const void *frame, ssize_t len) 479 479 { 480 - bool ret = true; 480 + struct intel_display *display = to_intel_display(encoder); 481 481 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 482 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 483 482 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); 483 + bool ret = true; 484 484 485 485 switch (type) { 486 486 case HDMI_INFOFRAME_TYPE_AVI: ··· 492 492 frame, len); 493 493 break; 494 494 case HDMI_PACKET_TYPE_GAMUT_METADATA: 495 - drm_dbg_kms(&i915->drm, "Update HDR metadata for lspcon\n"); 495 + drm_dbg_kms(display->drm, "Update HDR metadata for lspcon\n"); 496 496 /* It uses the legacy hsw implementation for the same */ 497 497 hsw_write_infoframe(encoder, crtc_state, type, frame, len); 498 498 break; ··· 501 501 } 502 502 503 503 if (!ret) { 504 - drm_err(&i915->drm, "Failed to write infoframes\n"); 504 + drm_err(display->drm, "Failed to write infoframes\n"); 505 505 return; 506 506 } 507 507 } ··· 522 522 const struct intel_crtc_state *crtc_state, 523 523 const struct drm_connector_state *conn_state) 524 524 { 525 - ssize_t ret; 526 - union hdmi_infoframe frame; 527 - u8 buf[VIDEO_DIP_DATA_SIZE]; 525 + struct intel_display *display = to_intel_display(encoder); 528 526 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 529 527 struct intel_lspcon *lspcon = &dig_port->lspcon; 530 - struct drm_i915_private *i915 = to_i915(encoder->base.dev); 531 528 const struct drm_display_mode *adjusted_mode = 532 529 &crtc_state->hw.adjusted_mode; 530 + union hdmi_infoframe frame; 531 + u8 buf[VIDEO_DIP_DATA_SIZE]; 532 + ssize_t ret; 533 533 534 534 if (!lspcon->active) { 535 - drm_err(&i915->drm, "Writing infoframes while LSPCON disabled ?\n"); 535 + drm_err(display->drm, "Writing infoframes while LSPCON disabled ?\n"); 536 536 return; 537 537 } 538 538 ··· 542 542 conn_state->connector, 543 543 adjusted_mode); 544 544 if (ret < 0) { 545 - drm_err(&i915->drm, "couldn't fill AVI infoframe\n"); 545 + drm_err(display->drm, "couldn't fill AVI infoframe\n"); 546 546 return; 547 547 } 548 548 ··· 583 583 584 584 ret = hdmi_infoframe_pack(&frame, buf, sizeof(buf)); 585 585 if (ret < 0) { 586 - drm_err(&i915->drm, "Failed to pack AVI IF\n"); 586 + drm_err(display->drm, "Failed to pack AVI IF\n"); 587 587 return; 588 588 } 589 589 ··· 624 624 u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, 625 625 const struct intel_crtc_state *pipe_config) 626 626 { 627 + struct intel_display *display = to_intel_display(encoder); 627 628 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 628 629 struct intel_lspcon *lspcon = enc_to_intel_lspcon(encoder); 629 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 630 630 bool infoframes_enabled; 631 631 u32 val = 0; 632 632 u32 mask, tmp; ··· 640 640 val |= intel_hdmi_infoframe_enable(HDMI_INFOFRAME_TYPE_AVI); 641 641 642 642 if (lspcon->hdr_supported) { 643 - tmp = intel_de_read(dev_priv, 644 - HSW_TVIDEO_DIP_CTL(dev_priv, pipe_config->cpu_transcoder)); 643 + tmp = intel_de_read(display, 644 + HSW_TVIDEO_DIP_CTL(display, pipe_config->cpu_transcoder)); 645 645 mask = VIDEO_DIP_ENABLE_GMP_HSW; 646 646 647 647 if (tmp & mask) ··· 658 658 659 659 bool lspcon_init(struct intel_digital_port *dig_port) 660 660 { 661 + struct intel_display *display = to_intel_display(dig_port); 661 662 struct intel_dp *intel_dp = &dig_port->dp; 662 663 struct intel_lspcon *lspcon = &dig_port->lspcon; 663 - struct drm_i915_private *i915 = dp_to_i915(intel_dp); 664 664 struct drm_connector *connector = &intel_dp->attached_connector->base; 665 665 666 666 lspcon->active = false; 667 667 lspcon->mode = DRM_LSPCON_MODE_INVALID; 668 668 669 669 if (!lspcon_probe(lspcon)) { 670 - drm_err(&i915->drm, "Failed to probe lspcon\n"); 670 + drm_err(display->drm, "Failed to probe lspcon\n"); 671 671 return false; 672 672 } 673 673 674 674 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) { 675 - drm_err(&i915->drm, "LSPCON DPCD read failed\n"); 675 + drm_err(display->drm, "LSPCON DPCD read failed\n"); 676 676 return false; 677 677 } 678 678 679 679 if (!lspcon_detect_vendor(lspcon)) { 680 - drm_err(&i915->drm, "LSPCON vendor detection failed\n"); 680 + drm_err(display->drm, "LSPCON vendor detection failed\n"); 681 681 return false; 682 682 } 683 683 684 684 connector->ycbcr_420_allowed = true; 685 685 lspcon->active = true; 686 - drm_dbg_kms(&i915->drm, "Success: LSPCON init\n"); 686 + drm_dbg_kms(display->drm, "Success: LSPCON init\n"); 687 687 return true; 688 688 } 689 689 ··· 697 697 698 698 void lspcon_resume(struct intel_digital_port *dig_port) 699 699 { 700 + struct intel_display *display = to_intel_display(dig_port); 700 701 struct intel_lspcon *lspcon = &dig_port->lspcon; 701 - struct drm_device *dev = dig_port->base.base.dev; 702 - struct drm_i915_private *i915 = to_i915(dev); 703 702 enum drm_lspcon_mode expected_mode; 704 703 705 704 if (!intel_bios_encoder_is_lspcon(dig_port->base.devdata)) ··· 706 707 707 708 if (!lspcon->active) { 708 709 if (!lspcon_init(dig_port)) { 709 - drm_err(&i915->drm, "LSPCON init failed on port %c\n", 710 + drm_err(display->drm, "LSPCON init failed on port %c\n", 710 711 port_name(dig_port->base.port)); 711 712 return; 712 713 } ··· 723 724 return; 724 725 725 726 if (lspcon_change_mode(lspcon, DRM_LSPCON_MODE_PCON)) 726 - drm_err(&i915->drm, "LSPCON resume failed\n"); 727 + drm_err(display->drm, "LSPCON resume failed\n"); 727 728 else 728 - drm_dbg_kms(&i915->drm, "LSPCON resume success\n"); 729 + drm_dbg_kms(display->drm, "LSPCON resume success\n"); 729 730 }

+26 -5

drivers/gpu/drm/i915/display/intel_modeset_setup.c

··· 326 326 327 327 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) 328 328 { 329 + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 330 + 329 331 if (intel_crtc_is_joiner_secondary(crtc_state)) 330 332 return; 331 333 ··· 339 337 crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode; 340 338 crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter; 341 339 342 - /* assume 1:1 mapping */ 343 - drm_property_replace_blob(&crtc_state->hw.degamma_lut, 344 - crtc_state->pre_csc_lut); 345 - drm_property_replace_blob(&crtc_state->hw.gamma_lut, 346 - crtc_state->post_csc_lut); 340 + if (DISPLAY_INFO(i915)->color.degamma_lut_size) { 341 + /* assume 1:1 mapping */ 342 + drm_property_replace_blob(&crtc_state->hw.degamma_lut, 343 + crtc_state->pre_csc_lut); 344 + drm_property_replace_blob(&crtc_state->hw.gamma_lut, 345 + crtc_state->post_csc_lut); 346 + } else { 347 + /* 348 + * ilk/snb hw may be configured for either pre_csc_lut 349 + * or post_csc_lut, but we don't advertise degamma_lut as 350 + * being available in the uapi since there is only one 351 + * hardware LUT. Always assign the result of the readout 352 + * to gamma_lut as that is the only valid source of LUTs 353 + * in the uapi. 354 + */ 355 + drm_WARN_ON(&i915->drm, crtc_state->post_csc_lut && 356 + crtc_state->pre_csc_lut); 357 + 358 + drm_property_replace_blob(&crtc_state->hw.degamma_lut, 359 + NULL); 360 + drm_property_replace_blob(&crtc_state->hw.gamma_lut, 361 + crtc_state->post_csc_lut ?: 362 + crtc_state->pre_csc_lut); 363 + } 347 364 348 365 drm_property_replace_blob(&crtc_state->uapi.degamma_lut, 349 366 crtc_state->hw.degamma_lut);

+1 -1

drivers/gpu/drm/i915/display/intel_pmdemand.c

··· 92 92 &pmdemand_state->base, 93 93 &intel_pmdemand_funcs); 94 94 95 - if (IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) 95 + if (IS_DISPLAY_VER_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) 96 96 /* Wa_14016740474 */ 97 97 intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); 98 98

+13 -1

drivers/gpu/drm/i915/display/intel_pps.c

··· 951 951 intel_de_posting_read(dev_priv, pp_ctrl_reg); 952 952 } 953 953 954 + /* 955 + * WA: 22019252566 956 + * Disable DPLS gating around power sequence. 957 + */ 958 + if (IS_DISPLAY_VER(dev_priv, 13, 14)) 959 + intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 960 + 0, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); 961 + 954 962 pp |= PANEL_POWER_ON; 955 963 if (!IS_IRONLAKE(dev_priv)) 956 964 pp |= PANEL_POWER_RESET; ··· 968 960 969 961 wait_panel_on(intel_dp); 970 962 intel_dp->pps.last_power_on = jiffies; 963 + 964 + if (IS_DISPLAY_VER(dev_priv, 13, 14)) 965 + intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 966 + PCH_DPLSUNIT_CLOCK_GATE_DISABLE, 0); 971 967 972 968 if (IS_IRONLAKE(dev_priv)) { 973 969 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ ··· 1483 1471 { 1484 1472 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1485 1473 u32 pp_on, pp_off, port_sel = 0; 1486 - int div = RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; 1474 + int div = DISPLAY_RUNTIME_INFO(dev_priv)->rawclk_freq / 1000; 1487 1475 struct pps_registers regs; 1488 1476 enum port port = dp_to_dig_port(intel_dp)->base.port; 1489 1477 const struct edp_power_seq *seq = &intel_dp->pps.pps_delays;

+10 -4

drivers/gpu/drm/i915/display/intel_psr.c

··· 1586 1586 if (!alpm_config_valid(intel_dp, crtc_state, true)) 1587 1587 return false; 1588 1588 1589 + if (crtc_state->crc_enabled) { 1590 + drm_dbg_kms(&i915->drm, 1591 + "Panel Replay not enabled because it would inhibit pipe CRC calculation\n"); 1592 + return false; 1593 + } 1594 + 1589 1595 return true; 1590 1596 } 1591 1597 ··· 1868 1862 * cause issues if non-supported panels are used. 1869 1863 */ 1870 1864 if (!intel_dp->psr.panel_replay_enabled && 1871 - (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || 1865 + (IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || 1872 1866 IS_ALDERLAKE_P(dev_priv))) 1873 1867 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 1874 1868 0, ADLP_1_BASED_X_GRANULARITY); 1875 1869 1876 1870 /* Wa_16012604467:adlp,mtl[a0,b0] */ 1877 1871 if (!intel_dp->psr.panel_replay_enabled && 1878 - IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) 1872 + IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) 1879 1873 intel_de_rmw(dev_priv, 1880 1874 MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder), 1881 1875 0, ··· 2057 2051 if (intel_dp->psr.sel_update_enabled) { 2058 2052 /* Wa_16012604467:adlp,mtl[a0,b0] */ 2059 2053 if (!intel_dp->psr.panel_replay_enabled && 2060 - IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) 2054 + IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) 2061 2055 intel_de_rmw(dev_priv, 2062 2056 MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder), 2063 2057 MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); ··· 2542 2536 2543 2537 /* Wa_14014971492 */ 2544 2538 if (!crtc_state->has_panel_replay && 2545 - ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || 2539 + ((IS_DISPLAY_VER_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || 2546 2540 IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) && 2547 2541 crtc_state->splitter.enable) 2548 2542 crtc_state->psr2_su_area.y1 = 0;

+112 -97

drivers/gpu/drm/i915/display/intel_sprite.c

··· 48 48 #include "intel_sprite.h" 49 49 #include "intel_sprite_regs.h" 50 50 51 - static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite) 51 + static char sprite_name(struct intel_display *display, enum pipe pipe, int sprite) 52 52 { 53 - return pipe * DISPLAY_RUNTIME_INFO(i915)->num_sprites[pipe] + sprite + 'A'; 53 + return pipe * DISPLAY_RUNTIME_INFO(display)->num_sprites[pipe] + sprite + 'A'; 54 54 } 55 55 56 56 static void i9xx_plane_linear_gamma(u16 gamma[8]) ··· 67 67 chv_sprite_update_csc(const struct intel_plane_state *plane_state) 68 68 { 69 69 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 70 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 70 + struct intel_display *display = to_intel_display(plane->base.dev); 71 71 const struct drm_framebuffer *fb = plane_state->hw.fb; 72 72 enum plane_id plane_id = plane->id; 73 73 /* ··· 100 100 if (!fb->format->is_yuv) 101 101 return; 102 102 103 - intel_de_write_fw(dev_priv, SPCSCYGOFF(plane_id), 103 + intel_de_write_fw(display, SPCSCYGOFF(plane_id), 104 104 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 105 - intel_de_write_fw(dev_priv, SPCSCCBOFF(plane_id), 105 + intel_de_write_fw(display, SPCSCCBOFF(plane_id), 106 106 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 107 - intel_de_write_fw(dev_priv, SPCSCCROFF(plane_id), 107 + intel_de_write_fw(display, SPCSCCROFF(plane_id), 108 108 SPCSC_OOFF(0) | SPCSC_IOFF(0)); 109 109 110 - intel_de_write_fw(dev_priv, SPCSCC01(plane_id), 110 + intel_de_write_fw(display, SPCSCC01(plane_id), 111 111 SPCSC_C1(csc[1]) | SPCSC_C0(csc[0])); 112 - intel_de_write_fw(dev_priv, SPCSCC23(plane_id), 112 + intel_de_write_fw(display, SPCSCC23(plane_id), 113 113 SPCSC_C1(csc[3]) | SPCSC_C0(csc[2])); 114 - intel_de_write_fw(dev_priv, SPCSCC45(plane_id), 114 + intel_de_write_fw(display, SPCSCC45(plane_id), 115 115 SPCSC_C1(csc[5]) | SPCSC_C0(csc[4])); 116 - intel_de_write_fw(dev_priv, SPCSCC67(plane_id), 116 + intel_de_write_fw(display, SPCSCC67(plane_id), 117 117 SPCSC_C1(csc[7]) | SPCSC_C0(csc[6])); 118 - intel_de_write_fw(dev_priv, SPCSCC8(plane_id), SPCSC_C0(csc[8])); 118 + intel_de_write_fw(display, SPCSCC8(plane_id), SPCSC_C0(csc[8])); 119 119 120 - intel_de_write_fw(dev_priv, SPCSCYGICLAMP(plane_id), 120 + intel_de_write_fw(display, SPCSCYGICLAMP(plane_id), 121 121 SPCSC_IMAX(1023) | SPCSC_IMIN(0)); 122 - intel_de_write_fw(dev_priv, SPCSCCBICLAMP(plane_id), 122 + intel_de_write_fw(display, SPCSCCBICLAMP(plane_id), 123 123 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 124 - intel_de_write_fw(dev_priv, SPCSCCRICLAMP(plane_id), 124 + intel_de_write_fw(display, SPCSCCRICLAMP(plane_id), 125 125 SPCSC_IMAX(512) | SPCSC_IMIN(-512)); 126 126 127 - intel_de_write_fw(dev_priv, SPCSCYGOCLAMP(plane_id), 127 + intel_de_write_fw(display, SPCSCYGOCLAMP(plane_id), 128 128 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 129 - intel_de_write_fw(dev_priv, SPCSCCBOCLAMP(plane_id), 129 + intel_de_write_fw(display, SPCSCCBOCLAMP(plane_id), 130 130 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 131 - intel_de_write_fw(dev_priv, SPCSCCROCLAMP(plane_id), 131 + intel_de_write_fw(display, SPCSCCROCLAMP(plane_id), 132 132 SPCSC_OMAX(1023) | SPCSC_OMIN(0)); 133 133 } 134 134 ··· 139 139 vlv_sprite_update_clrc(const struct intel_plane_state *plane_state) 140 140 { 141 141 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 142 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 142 + struct intel_display *display = to_intel_display(plane->base.dev); 143 143 const struct drm_framebuffer *fb = plane_state->hw.fb; 144 144 enum pipe pipe = plane->pipe; 145 145 enum plane_id plane_id = plane->id; ··· 168 168 } 169 169 170 170 /* FIXME these register are single buffered :( */ 171 - intel_de_write_fw(dev_priv, SPCLRC0(pipe, plane_id), 171 + intel_de_write_fw(display, SPCLRC0(pipe, plane_id), 172 172 SP_CONTRAST(contrast) | SP_BRIGHTNESS(brightness)); 173 - intel_de_write_fw(dev_priv, SPCLRC1(pipe, plane_id), 173 + intel_de_write_fw(display, SPCLRC1(pipe, plane_id), 174 174 SP_SH_SIN(sh_sin) | SP_SH_COS(sh_cos)); 175 175 } 176 176 ··· 357 357 static void vlv_sprite_update_gamma(const struct intel_plane_state *plane_state) 358 358 { 359 359 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 360 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 360 + struct intel_display *display = to_intel_display(plane->base.dev); 361 361 const struct drm_framebuffer *fb = plane_state->hw.fb; 362 362 enum pipe pipe = plane->pipe; 363 363 enum plane_id plane_id = plane->id; ··· 373 373 /* FIXME these register are single buffered :( */ 374 374 /* The two end points are implicit (0.0 and 1.0) */ 375 375 for (i = 1; i < 8 - 1; i++) 376 - intel_de_write_fw(dev_priv, SPGAMC(pipe, plane_id, i - 1), 376 + intel_de_write_fw(display, SPGAMC(pipe, plane_id, i - 1), 377 377 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 378 378 } 379 379 ··· 382 382 const struct intel_crtc_state *crtc_state, 383 383 const struct intel_plane_state *plane_state) 384 384 { 385 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 385 + struct intel_display *display = to_intel_display(plane->base.dev); 386 386 enum pipe pipe = plane->pipe; 387 387 enum plane_id plane_id = plane->id; 388 388 int crtc_x = plane_state->uapi.dst.x1; ··· 390 390 u32 crtc_w = drm_rect_width(&plane_state->uapi.dst); 391 391 u32 crtc_h = drm_rect_height(&plane_state->uapi.dst); 392 392 393 - intel_de_write_fw(dev_priv, SPSTRIDE(pipe, plane_id), 393 + intel_de_write_fw(display, SPSTRIDE(pipe, plane_id), 394 394 plane_state->view.color_plane[0].mapping_stride); 395 - intel_de_write_fw(dev_priv, SPPOS(pipe, plane_id), 395 + intel_de_write_fw(display, SPPOS(pipe, plane_id), 396 396 SP_POS_Y(crtc_y) | SP_POS_X(crtc_x)); 397 - intel_de_write_fw(dev_priv, SPSIZE(pipe, plane_id), 397 + intel_de_write_fw(display, SPSIZE(pipe, plane_id), 398 398 SP_HEIGHT(crtc_h - 1) | SP_WIDTH(crtc_w - 1)); 399 399 } 400 400 ··· 403 403 const struct intel_crtc_state *crtc_state, 404 404 const struct intel_plane_state *plane_state) 405 405 { 406 + struct intel_display *display = to_intel_display(plane->base.dev); 406 407 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 407 408 enum pipe pipe = plane->pipe; 408 409 enum plane_id plane_id = plane->id; ··· 421 420 chv_sprite_update_csc(plane_state); 422 421 423 422 if (key->flags) { 424 - intel_de_write_fw(dev_priv, SPKEYMINVAL(pipe, plane_id), 423 + intel_de_write_fw(display, SPKEYMINVAL(pipe, plane_id), 425 424 key->min_value); 426 - intel_de_write_fw(dev_priv, SPKEYMSK(pipe, plane_id), 425 + intel_de_write_fw(display, SPKEYMSK(pipe, plane_id), 427 426 key->channel_mask); 428 - intel_de_write_fw(dev_priv, SPKEYMAXVAL(pipe, plane_id), 427 + intel_de_write_fw(display, SPKEYMAXVAL(pipe, plane_id), 429 428 key->max_value); 430 429 } 431 430 432 - intel_de_write_fw(dev_priv, SPCONSTALPHA(pipe, plane_id), 0); 431 + intel_de_write_fw(display, SPCONSTALPHA(pipe, plane_id), 0); 433 432 434 - intel_de_write_fw(dev_priv, SPLINOFF(pipe, plane_id), linear_offset); 435 - intel_de_write_fw(dev_priv, SPTILEOFF(pipe, plane_id), 433 + intel_de_write_fw(display, SPLINOFF(pipe, plane_id), linear_offset); 434 + intel_de_write_fw(display, SPTILEOFF(pipe, plane_id), 436 435 SP_OFFSET_Y(y) | SP_OFFSET_X(x)); 437 436 438 437 /* ··· 440 439 * disabled. Try to make the plane enable atomic by writing 441 440 * the control register just before the surface register. 442 441 */ 443 - intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), sprctl); 444 - intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 442 + intel_de_write_fw(display, SPCNTR(pipe, plane_id), sprctl); 443 + intel_de_write_fw(display, SPSURF(pipe, plane_id), 445 444 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 446 445 447 446 vlv_sprite_update_clrc(plane_state); ··· 452 451 vlv_sprite_disable_arm(struct intel_plane *plane, 453 452 const struct intel_crtc_state *crtc_state) 454 453 { 455 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 454 + struct intel_display *display = to_intel_display(plane->base.dev); 456 455 enum pipe pipe = plane->pipe; 457 456 enum plane_id plane_id = plane->id; 458 457 459 - intel_de_write_fw(dev_priv, SPCNTR(pipe, plane_id), 0); 460 - intel_de_write_fw(dev_priv, SPSURF(pipe, plane_id), 0); 458 + intel_de_write_fw(display, SPCNTR(pipe, plane_id), 0); 459 + intel_de_write_fw(display, SPSURF(pipe, plane_id), 0); 461 460 } 462 461 463 462 static bool 464 463 vlv_sprite_get_hw_state(struct intel_plane *plane, 465 464 enum pipe *pipe) 466 465 { 466 + struct intel_display *display = to_intel_display(plane->base.dev); 467 467 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 468 468 enum intel_display_power_domain power_domain; 469 469 enum plane_id plane_id = plane->id; ··· 476 474 if (!wakeref) 477 475 return false; 478 476 479 - ret = intel_de_read(dev_priv, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 477 + ret = intel_de_read(display, SPCNTR(plane->pipe, plane_id)) & SP_ENABLE; 480 478 481 479 *pipe = plane->pipe; 482 480 ··· 768 766 static void ivb_sprite_update_gamma(const struct intel_plane_state *plane_state) 769 767 { 770 768 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 771 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 769 + struct intel_display *display = to_intel_display(plane->base.dev); 772 770 enum pipe pipe = plane->pipe; 773 771 u16 gamma[18]; 774 772 int i; ··· 780 778 781 779 /* FIXME these register are single buffered :( */ 782 780 for (i = 0; i < 16; i++) 783 - intel_de_write_fw(dev_priv, SPRGAMC(pipe, i), 781 + intel_de_write_fw(display, SPRGAMC(pipe, i), 784 782 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 785 783 786 - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 0), gamma[i]); 787 - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 1), gamma[i]); 788 - intel_de_write_fw(dev_priv, SPRGAMC16(pipe, 2), gamma[i]); 784 + intel_de_write_fw(display, SPRGAMC16(pipe, 0), gamma[i]); 785 + intel_de_write_fw(display, SPRGAMC16(pipe, 1), gamma[i]); 786 + intel_de_write_fw(display, SPRGAMC16(pipe, 2), gamma[i]); 789 787 i++; 790 788 791 - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 0), gamma[i]); 792 - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 1), gamma[i]); 793 - intel_de_write_fw(dev_priv, SPRGAMC17(pipe, 2), gamma[i]); 789 + intel_de_write_fw(display, SPRGAMC17(pipe, 0), gamma[i]); 790 + intel_de_write_fw(display, SPRGAMC17(pipe, 1), gamma[i]); 791 + intel_de_write_fw(display, SPRGAMC17(pipe, 2), gamma[i]); 794 792 i++; 795 793 } 796 794 ··· 799 797 const struct intel_crtc_state *crtc_state, 800 798 const struct intel_plane_state *plane_state) 801 799 { 800 + struct intel_display *display = to_intel_display(plane->base.dev); 802 801 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 803 802 enum pipe pipe = plane->pipe; 804 803 int crtc_x = plane_state->uapi.dst.x1; ··· 815 812 SPRITE_SRC_WIDTH(src_w - 1) | 816 813 SPRITE_SRC_HEIGHT(src_h - 1); 817 814 818 - intel_de_write_fw(dev_priv, SPRSTRIDE(pipe), 815 + intel_de_write_fw(display, SPRSTRIDE(pipe), 819 816 plane_state->view.color_plane[0].mapping_stride); 820 - intel_de_write_fw(dev_priv, SPRPOS(pipe), 817 + intel_de_write_fw(display, SPRPOS(pipe), 821 818 SPRITE_POS_Y(crtc_y) | SPRITE_POS_X(crtc_x)); 822 - intel_de_write_fw(dev_priv, SPRSIZE(pipe), 819 + intel_de_write_fw(display, SPRSIZE(pipe), 823 820 SPRITE_HEIGHT(crtc_h - 1) | SPRITE_WIDTH(crtc_w - 1)); 824 821 if (IS_IVYBRIDGE(dev_priv)) 825 - intel_de_write_fw(dev_priv, SPRSCALE(pipe), sprscale); 822 + intel_de_write_fw(display, SPRSCALE(pipe), sprscale); 826 823 } 827 824 828 825 static void ··· 830 827 const struct intel_crtc_state *crtc_state, 831 828 const struct intel_plane_state *plane_state) 832 829 { 830 + struct intel_display *display = to_intel_display(plane->base.dev); 833 831 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 834 832 enum pipe pipe = plane->pipe; 835 833 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; ··· 844 840 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 845 841 846 842 if (key->flags) { 847 - intel_de_write_fw(dev_priv, SPRKEYVAL(pipe), key->min_value); 848 - intel_de_write_fw(dev_priv, SPRKEYMSK(pipe), 843 + intel_de_write_fw(display, SPRKEYVAL(pipe), key->min_value); 844 + intel_de_write_fw(display, SPRKEYMSK(pipe), 849 845 key->channel_mask); 850 - intel_de_write_fw(dev_priv, SPRKEYMAX(pipe), key->max_value); 846 + intel_de_write_fw(display, SPRKEYMAX(pipe), key->max_value); 851 847 } 852 848 853 849 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET 854 850 * register */ 855 851 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { 856 - intel_de_write_fw(dev_priv, SPROFFSET(pipe), 852 + intel_de_write_fw(display, SPROFFSET(pipe), 857 853 SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); 858 854 } else { 859 - intel_de_write_fw(dev_priv, SPRLINOFF(pipe), linear_offset); 860 - intel_de_write_fw(dev_priv, SPRTILEOFF(pipe), 855 + intel_de_write_fw(display, SPRLINOFF(pipe), linear_offset); 856 + intel_de_write_fw(display, SPRTILEOFF(pipe), 861 857 SPRITE_OFFSET_Y(y) | SPRITE_OFFSET_X(x)); 862 858 } 863 859 ··· 866 862 * disabled. Try to make the plane enable atomic by writing 867 863 * the control register just before the surface register. 868 864 */ 869 - intel_de_write_fw(dev_priv, SPRCTL(pipe), sprctl); 870 - intel_de_write_fw(dev_priv, SPRSURF(pipe), 865 + intel_de_write_fw(display, SPRCTL(pipe), sprctl); 866 + intel_de_write_fw(display, SPRSURF(pipe), 871 867 intel_plane_ggtt_offset(plane_state) + sprsurf_offset); 872 868 873 869 ivb_sprite_update_gamma(plane_state); ··· 877 873 ivb_sprite_disable_arm(struct intel_plane *plane, 878 874 const struct intel_crtc_state *crtc_state) 879 875 { 876 + struct intel_display *display = to_intel_display(plane->base.dev); 880 877 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 881 878 enum pipe pipe = plane->pipe; 882 879 883 - intel_de_write_fw(dev_priv, SPRCTL(pipe), 0); 880 + intel_de_write_fw(display, SPRCTL(pipe), 0); 884 881 /* Disable the scaler */ 885 882 if (IS_IVYBRIDGE(dev_priv)) 886 - intel_de_write_fw(dev_priv, SPRSCALE(pipe), 0); 887 - intel_de_write_fw(dev_priv, SPRSURF(pipe), 0); 883 + intel_de_write_fw(display, SPRSCALE(pipe), 0); 884 + intel_de_write_fw(display, SPRSURF(pipe), 0); 888 885 } 889 886 890 887 static bool 891 888 ivb_sprite_get_hw_state(struct intel_plane *plane, 892 889 enum pipe *pipe) 893 890 { 891 + struct intel_display *display = to_intel_display(plane->base.dev); 894 892 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 895 893 enum intel_display_power_domain power_domain; 896 894 intel_wakeref_t wakeref; ··· 903 897 if (!wakeref) 904 898 return false; 905 899 906 - ret = intel_de_read(dev_priv, SPRCTL(plane->pipe)) & SPRITE_ENABLE; 900 + ret = intel_de_read(display, SPRCTL(plane->pipe)) & SPRITE_ENABLE; 907 901 908 902 *pipe = plane->pipe; 909 903 ··· 1079 1073 static void g4x_sprite_update_gamma(const struct intel_plane_state *plane_state) 1080 1074 { 1081 1075 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1082 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1076 + struct intel_display *display = to_intel_display(plane->base.dev); 1083 1077 const struct drm_framebuffer *fb = plane_state->hw.fb; 1084 1078 enum pipe pipe = plane->pipe; 1085 1079 u16 gamma[8]; ··· 1094 1088 /* FIXME these register are single buffered :( */ 1095 1089 /* The two end points are implicit (0.0 and 1.0) */ 1096 1090 for (i = 1; i < 8 - 1; i++) 1097 - intel_de_write_fw(dev_priv, DVSGAMC_G4X(pipe, i - 1), 1091 + intel_de_write_fw(display, DVSGAMC_G4X(pipe, i - 1), 1098 1092 gamma[i] << 16 | gamma[i] << 8 | gamma[i]); 1099 1093 } 1100 1094 ··· 1109 1103 static void ilk_sprite_update_gamma(const struct intel_plane_state *plane_state) 1110 1104 { 1111 1105 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1112 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1106 + struct intel_display *display = to_intel_display(plane->base.dev); 1113 1107 const struct drm_framebuffer *fb = plane_state->hw.fb; 1114 1108 enum pipe pipe = plane->pipe; 1115 1109 u16 gamma[17]; ··· 1123 1117 1124 1118 /* FIXME these register are single buffered :( */ 1125 1119 for (i = 0; i < 16; i++) 1126 - intel_de_write_fw(dev_priv, DVSGAMC_ILK(pipe, i), 1120 + intel_de_write_fw(display, DVSGAMC_ILK(pipe, i), 1127 1121 gamma[i] << 20 | gamma[i] << 10 | gamma[i]); 1128 1122 1129 - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 1130 - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 1131 - intel_de_write_fw(dev_priv, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 1123 + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 0), gamma[i]); 1124 + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 1), gamma[i]); 1125 + intel_de_write_fw(display, DVSGAMCMAX_ILK(pipe, 2), gamma[i]); 1132 1126 i++; 1133 1127 } 1134 1128 ··· 1137 1131 const struct intel_crtc_state *crtc_state, 1138 1132 const struct intel_plane_state *plane_state) 1139 1133 { 1140 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1134 + struct intel_display *display = to_intel_display(plane->base.dev); 1141 1135 enum pipe pipe = plane->pipe; 1142 1136 int crtc_x = plane_state->uapi.dst.x1; 1143 1137 int crtc_y = plane_state->uapi.dst.y1; ··· 1152 1146 DVS_SRC_WIDTH(src_w - 1) | 1153 1147 DVS_SRC_HEIGHT(src_h - 1); 1154 1148 1155 - intel_de_write_fw(dev_priv, DVSSTRIDE(pipe), 1149 + intel_de_write_fw(display, DVSSTRIDE(pipe), 1156 1150 plane_state->view.color_plane[0].mapping_stride); 1157 - intel_de_write_fw(dev_priv, DVSPOS(pipe), 1151 + intel_de_write_fw(display, DVSPOS(pipe), 1158 1152 DVS_POS_Y(crtc_y) | DVS_POS_X(crtc_x)); 1159 - intel_de_write_fw(dev_priv, DVSSIZE(pipe), 1153 + intel_de_write_fw(display, DVSSIZE(pipe), 1160 1154 DVS_HEIGHT(crtc_h - 1) | DVS_WIDTH(crtc_w - 1)); 1161 - intel_de_write_fw(dev_priv, DVSSCALE(pipe), dvsscale); 1155 + intel_de_write_fw(display, DVSSCALE(pipe), dvsscale); 1162 1156 } 1163 1157 1164 1158 static void ··· 1166 1160 const struct intel_crtc_state *crtc_state, 1167 1161 const struct intel_plane_state *plane_state) 1168 1162 { 1163 + struct intel_display *display = to_intel_display(plane->base.dev); 1169 1164 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1170 1165 enum pipe pipe = plane->pipe; 1171 1166 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; ··· 1180 1173 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); 1181 1174 1182 1175 if (key->flags) { 1183 - intel_de_write_fw(dev_priv, DVSKEYVAL(pipe), key->min_value); 1184 - intel_de_write_fw(dev_priv, DVSKEYMSK(pipe), 1176 + intel_de_write_fw(display, DVSKEYVAL(pipe), key->min_value); 1177 + intel_de_write_fw(display, DVSKEYMSK(pipe), 1185 1178 key->channel_mask); 1186 - intel_de_write_fw(dev_priv, DVSKEYMAX(pipe), key->max_value); 1179 + intel_de_write_fw(display, DVSKEYMAX(pipe), key->max_value); 1187 1180 } 1188 1181 1189 - intel_de_write_fw(dev_priv, DVSLINOFF(pipe), linear_offset); 1190 - intel_de_write_fw(dev_priv, DVSTILEOFF(pipe), 1182 + intel_de_write_fw(display, DVSLINOFF(pipe), linear_offset); 1183 + intel_de_write_fw(display, DVSTILEOFF(pipe), 1191 1184 DVS_OFFSET_Y(y) | DVS_OFFSET_X(x)); 1192 1185 1193 1186 /* ··· 1195 1188 * disabled. Try to make the plane enable atomic by writing 1196 1189 * the control register just before the surface register. 1197 1190 */ 1198 - intel_de_write_fw(dev_priv, DVSCNTR(pipe), dvscntr); 1199 - intel_de_write_fw(dev_priv, DVSSURF(pipe), 1191 + intel_de_write_fw(display, DVSCNTR(pipe), dvscntr); 1192 + intel_de_write_fw(display, DVSSURF(pipe), 1200 1193 intel_plane_ggtt_offset(plane_state) + dvssurf_offset); 1201 1194 1202 1195 if (IS_G4X(dev_priv)) ··· 1209 1202 g4x_sprite_disable_arm(struct intel_plane *plane, 1210 1203 const struct intel_crtc_state *crtc_state) 1211 1204 { 1212 - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1205 + struct intel_display *display = to_intel_display(plane->base.dev); 1213 1206 enum pipe pipe = plane->pipe; 1214 1207 1215 - intel_de_write_fw(dev_priv, DVSCNTR(pipe), 0); 1208 + intel_de_write_fw(display, DVSCNTR(pipe), 0); 1216 1209 /* Disable the scaler */ 1217 - intel_de_write_fw(dev_priv, DVSSCALE(pipe), 0); 1218 - intel_de_write_fw(dev_priv, DVSSURF(pipe), 0); 1210 + intel_de_write_fw(display, DVSSCALE(pipe), 0); 1211 + intel_de_write_fw(display, DVSSURF(pipe), 0); 1219 1212 } 1220 1213 1221 1214 static bool 1222 1215 g4x_sprite_get_hw_state(struct intel_plane *plane, 1223 1216 enum pipe *pipe) 1224 1217 { 1218 + struct intel_display *display = to_intel_display(plane->base.dev); 1225 1219 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1226 1220 enum intel_display_power_domain power_domain; 1227 1221 intel_wakeref_t wakeref; ··· 1233 1225 if (!wakeref) 1234 1226 return false; 1235 1227 1236 - ret = intel_de_read(dev_priv, DVSCNTR(plane->pipe)) & DVS_ENABLE; 1228 + ret = intel_de_read(display, DVSCNTR(plane->pipe)) & DVS_ENABLE; 1237 1229 1238 1230 *pipe = plane->pipe; 1239 1231 ··· 1263 1255 g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state, 1264 1256 struct intel_plane_state *plane_state) 1265 1257 { 1266 - struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev); 1258 + struct intel_display *display = to_intel_display(crtc_state); 1267 1259 const struct drm_framebuffer *fb = plane_state->hw.fb; 1268 1260 const struct drm_rect *src = &plane_state->uapi.src; 1269 1261 const struct drm_rect *dst = &plane_state->uapi.dst; ··· 1289 1281 1290 1282 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { 1291 1283 if (src_h & 1) { 1292 - drm_dbg_kms(&i915->drm, "Source height must be even with interlaced modes\n"); 1284 + drm_dbg_kms(display->drm, 1285 + "Source height must be even with interlaced modes\n"); 1293 1286 return -EINVAL; 1294 1287 } 1295 1288 min_height = 6; ··· 1302 1293 1303 1294 if (src_w < min_width || src_h < min_height || 1304 1295 src_w > 2048 || src_h > 2048) { 1305 - drm_dbg_kms(&i915->drm, "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 1296 + drm_dbg_kms(display->drm, 1297 + "Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n", 1306 1298 src_w, src_h, min_width, min_height, 2048, 2048); 1307 1299 return -EINVAL; 1308 1300 } 1309 1301 1310 1302 if (width_bytes > 4096) { 1311 - drm_dbg_kms(&i915->drm, "Fetch width (%d) exceeds hardware max with scaling (%u)\n", 1303 + drm_dbg_kms(display->drm, 1304 + "Fetch width (%d) exceeds hardware max with scaling (%u)\n", 1312 1305 width_bytes, 4096); 1313 1306 return -EINVAL; 1314 1307 } 1315 1308 1316 1309 if (stride > 4096) { 1317 - drm_dbg_kms(&i915->drm, "Stride (%u) exceeds hardware max with scaling (%u)\n", 1310 + drm_dbg_kms(display->drm, 1311 + "Stride (%u) exceeds hardware max with scaling (%u)\n", 1318 1312 stride, 4096); 1319 1313 return -EINVAL; 1320 1314 } ··· 1329 1317 g4x_sprite_check(struct intel_crtc_state *crtc_state, 1330 1318 struct intel_plane_state *plane_state) 1331 1319 { 1320 + struct intel_display *display = to_intel_display(crtc_state); 1332 1321 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1333 1322 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1334 1323 int min_scale = DRM_PLANE_NO_SCALING; ··· 1337 1324 int ret; 1338 1325 1339 1326 if (g4x_fb_scalable(plane_state->hw.fb)) { 1340 - if (DISPLAY_VER(dev_priv) < 7) { 1327 + if (DISPLAY_VER(display) < 7) { 1341 1328 min_scale = 1; 1342 1329 max_scale = 16 << 16; 1343 1330 } else if (IS_IVYBRIDGE(dev_priv)) { ··· 1366 1353 if (ret) 1367 1354 return ret; 1368 1355 1369 - if (DISPLAY_VER(dev_priv) >= 7) 1356 + if (DISPLAY_VER(display) >= 7) 1370 1357 plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state); 1371 1358 else 1372 1359 plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state); ··· 1377 1364 int chv_plane_check_rotation(const struct intel_plane_state *plane_state) 1378 1365 { 1379 1366 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); 1367 + struct intel_display *display = to_intel_display(plane->base.dev); 1380 1368 struct drm_i915_private *dev_priv = to_i915(plane->base.dev); 1381 1369 unsigned int rotation = plane_state->hw.rotation; 1382 1370 ··· 1385 1371 if (IS_CHERRYVIEW(dev_priv) && 1386 1372 rotation & DRM_MODE_ROTATE_180 && 1387 1373 rotation & DRM_MODE_REFLECT_X) { 1388 - drm_dbg_kms(&dev_priv->drm, 1374 + drm_dbg_kms(display->drm, 1389 1375 "Cannot rotate and reflect at the same time\n"); 1390 1376 return -EINVAL; 1391 1377 } ··· 1587 1573 intel_sprite_plane_create(struct drm_i915_private *dev_priv, 1588 1574 enum pipe pipe, int sprite) 1589 1575 { 1576 + struct intel_display *display = &dev_priv->display; 1590 1577 struct intel_plane *plane; 1591 1578 const struct drm_plane_funcs *plane_funcs; 1592 1579 unsigned int supported_rotations; ··· 1619 1604 } 1620 1605 1621 1606 plane_funcs = &vlv_sprite_funcs; 1622 - } else if (DISPLAY_VER(dev_priv) >= 7) { 1607 + } else if (DISPLAY_VER(display) >= 7) { 1623 1608 plane->update_noarm = ivb_sprite_update_noarm; 1624 1609 plane->update_arm = ivb_sprite_update_arm; 1625 1610 plane->disable_arm = ivb_sprite_disable_arm; ··· 1678 1663 1679 1664 modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_TILING_X); 1680 1665 1681 - ret = drm_universal_plane_init(&dev_priv->drm, &plane->base, 1666 + ret = drm_universal_plane_init(display->drm, &plane->base, 1682 1667 0, plane_funcs, 1683 1668 formats, num_formats, modifiers, 1684 1669 DRM_PLANE_TYPE_OVERLAY, 1685 - "sprite %c", sprite_name(dev_priv, pipe, sprite)); 1670 + "sprite %c", sprite_name(display, pipe, sprite)); 1686 1671 kfree(modifiers); 1687 1672 1688 1673 if (ret)

+104 -99

drivers/gpu/drm/i915/display/intel_tv.c

··· 914 914 static bool 915 915 intel_tv_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe) 916 916 { 917 - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 918 - u32 tmp = intel_de_read(dev_priv, TV_CTL); 917 + struct intel_display *display = to_intel_display(encoder); 918 + u32 tmp = intel_de_read(display, TV_CTL); 919 919 920 920 *pipe = (tmp & TV_ENC_PIPE_SEL_MASK) >> TV_ENC_PIPE_SEL_SHIFT; 921 921 ··· 928 928 const struct intel_crtc_state *pipe_config, 929 929 const struct drm_connector_state *conn_state) 930 930 { 931 - struct drm_device *dev = encoder->base.dev; 932 - struct drm_i915_private *dev_priv = to_i915(dev); 931 + struct intel_display *display = to_intel_display(state); 933 932 934 933 /* Prevents vblank waits from timing out in intel_tv_detect_type() */ 935 934 intel_crtc_wait_for_next_vblank(to_intel_crtc(pipe_config->uapi.crtc)); 936 935 937 - intel_de_rmw(dev_priv, TV_CTL, 0, TV_ENC_ENABLE); 936 + intel_de_rmw(display, TV_CTL, 0, TV_ENC_ENABLE); 938 937 } 939 938 940 939 static void ··· 942 943 const struct intel_crtc_state *old_crtc_state, 943 944 const struct drm_connector_state *old_conn_state) 944 945 { 945 - struct drm_device *dev = encoder->base.dev; 946 - struct drm_i915_private *dev_priv = to_i915(dev); 946 + struct intel_display *display = to_intel_display(state); 947 947 948 - intel_de_rmw(dev_priv, TV_CTL, TV_ENC_ENABLE, 0); 948 + intel_de_rmw(display, TV_CTL, TV_ENC_ENABLE, 0); 949 949 } 950 950 951 951 static const struct tv_mode *intel_tv_mode_find(const struct drm_connector_state *conn_state) ··· 958 960 intel_tv_mode_valid(struct drm_connector *connector, 959 961 struct drm_display_mode *mode) 960 962 { 963 + struct intel_display *display = to_intel_display(connector->dev); 961 964 struct drm_i915_private *i915 = to_i915(connector->dev); 962 965 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 963 - int max_dotclk = i915->display.cdclk.max_dotclk_freq; 966 + int max_dotclk = display->cdclk.max_dotclk_freq; 964 967 enum drm_mode_status status; 965 968 966 969 status = intel_cpu_transcoder_mode_valid(i915, mode); ··· 1091 1092 intel_tv_get_config(struct intel_encoder *encoder, 1092 1093 struct intel_crtc_state *pipe_config) 1093 1094 { 1095 + struct intel_display *display = to_intel_display(encoder); 1094 1096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1095 1097 struct drm_display_mode *adjusted_mode = 1096 1098 &pipe_config->hw.adjusted_mode; ··· 1104 1104 1105 1105 pipe_config->output_types |= BIT(INTEL_OUTPUT_TVOUT); 1106 1106 1107 - tv_ctl = intel_de_read(dev_priv, TV_CTL); 1108 - hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); 1109 - hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); 1110 - vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); 1111 - vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); 1107 + tv_ctl = intel_de_read(display, TV_CTL); 1108 + hctl1 = intel_de_read(display, TV_H_CTL_1); 1109 + hctl3 = intel_de_read(display, TV_H_CTL_3); 1110 + vctl1 = intel_de_read(display, TV_V_CTL_1); 1111 + vctl2 = intel_de_read(display, TV_V_CTL_2); 1112 1112 1113 1113 tv_mode.htotal = (hctl1 & TV_HTOTAL_MASK) >> TV_HTOTAL_SHIFT; 1114 1114 tv_mode.hsync_end = (hctl1 & TV_HSYNC_END_MASK) >> TV_HSYNC_END_SHIFT; ··· 1143 1143 break; 1144 1144 } 1145 1145 1146 - tmp = intel_de_read(dev_priv, TV_WIN_POS); 1146 + tmp = intel_de_read(display, TV_WIN_POS); 1147 1147 xpos = tmp >> 16; 1148 1148 ypos = tmp & 0xffff; 1149 1149 1150 - tmp = intel_de_read(dev_priv, TV_WIN_SIZE); 1150 + tmp = intel_de_read(display, TV_WIN_SIZE); 1151 1151 xsize = tmp >> 16; 1152 1152 ysize = tmp & 0xffff; 1153 1153 1154 1154 intel_tv_mode_to_mode(&mode, &tv_mode, pipe_config->port_clock); 1155 1155 1156 - drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1156 + drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n", 1157 1157 DRM_MODE_ARG(&mode)); 1158 1158 1159 1159 intel_tv_scale_mode_horiz(&mode, hdisplay, ··· 1171 1171 I915_MODE_FLAG_USE_SCANLINE_COUNTER; 1172 1172 } 1173 1173 1174 - static bool intel_tv_source_too_wide(struct drm_i915_private *dev_priv, 1174 + static bool intel_tv_source_too_wide(struct intel_display *display, 1175 1175 int hdisplay) 1176 1176 { 1177 - return DISPLAY_VER(dev_priv) == 3 && hdisplay > 1024; 1177 + return DISPLAY_VER(display) == 3 && hdisplay > 1024; 1178 1178 } 1179 1179 1180 1180 static bool intel_tv_vert_scaling(const struct drm_display_mode *tv_mode, ··· 1192 1192 struct intel_crtc_state *pipe_config, 1193 1193 struct drm_connector_state *conn_state) 1194 1194 { 1195 + struct intel_display *display = to_intel_display(encoder); 1195 1196 struct intel_atomic_state *state = 1196 1197 to_intel_atomic_state(pipe_config->uapi.state); 1197 1198 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); ··· 1215 1214 pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; 1216 1215 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 1217 1216 1218 - drm_dbg_kms(&dev_priv->drm, "forcing bpc to 8 for TV\n"); 1217 + drm_dbg_kms(display->drm, "forcing bpc to 8 for TV\n"); 1219 1218 pipe_config->pipe_bpp = 8*3; 1220 1219 1221 1220 pipe_config->port_clock = tv_mode->clock; ··· 1229 1228 intel_tv_mode_to_mode(adjusted_mode, tv_mode, pipe_config->port_clock); 1230 1229 drm_mode_set_crtcinfo(adjusted_mode, 0); 1231 1230 1232 - if (intel_tv_source_too_wide(dev_priv, hdisplay) || 1231 + if (intel_tv_source_too_wide(display, hdisplay) || 1233 1232 !intel_tv_vert_scaling(adjusted_mode, conn_state, vdisplay)) { 1234 1233 int extra, top, bottom; 1235 1234 1236 1235 extra = adjusted_mode->crtc_vdisplay - vdisplay; 1237 1236 1238 1237 if (extra < 0) { 1239 - drm_dbg_kms(&dev_priv->drm, 1238 + drm_dbg_kms(display->drm, 1240 1239 "No vertical scaling for >1024 pixel wide modes\n"); 1241 1240 return -EINVAL; 1242 1241 } ··· 1270 1269 tv_conn_state->bypass_vfilter = false; 1271 1270 } 1272 1271 1273 - drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1272 + drm_dbg_kms(display->drm, "TV mode: " DRM_MODE_FMT "\n", 1274 1273 DRM_MODE_ARG(adjusted_mode)); 1275 1274 1276 1275 /* ··· 1356 1355 } 1357 1356 1358 1357 static void 1359 - set_tv_mode_timings(struct drm_i915_private *dev_priv, 1358 + set_tv_mode_timings(struct intel_display *display, 1360 1359 const struct tv_mode *tv_mode, 1361 1360 bool burst_ena) 1362 1361 { ··· 1402 1401 vctl7 = (tv_mode->vburst_start_f4 << TV_VBURST_START_F4_SHIFT) | 1403 1402 (tv_mode->vburst_end_f4 << TV_VBURST_END_F4_SHIFT); 1404 1403 1405 - intel_de_write(dev_priv, TV_H_CTL_1, hctl1); 1406 - intel_de_write(dev_priv, TV_H_CTL_2, hctl2); 1407 - intel_de_write(dev_priv, TV_H_CTL_3, hctl3); 1408 - intel_de_write(dev_priv, TV_V_CTL_1, vctl1); 1409 - intel_de_write(dev_priv, TV_V_CTL_2, vctl2); 1410 - intel_de_write(dev_priv, TV_V_CTL_3, vctl3); 1411 - intel_de_write(dev_priv, TV_V_CTL_4, vctl4); 1412 - intel_de_write(dev_priv, TV_V_CTL_5, vctl5); 1413 - intel_de_write(dev_priv, TV_V_CTL_6, vctl6); 1414 - intel_de_write(dev_priv, TV_V_CTL_7, vctl7); 1404 + intel_de_write(display, TV_H_CTL_1, hctl1); 1405 + intel_de_write(display, TV_H_CTL_2, hctl2); 1406 + intel_de_write(display, TV_H_CTL_3, hctl3); 1407 + intel_de_write(display, TV_V_CTL_1, vctl1); 1408 + intel_de_write(display, TV_V_CTL_2, vctl2); 1409 + intel_de_write(display, TV_V_CTL_3, vctl3); 1410 + intel_de_write(display, TV_V_CTL_4, vctl4); 1411 + intel_de_write(display, TV_V_CTL_5, vctl5); 1412 + intel_de_write(display, TV_V_CTL_6, vctl6); 1413 + intel_de_write(display, TV_V_CTL_7, vctl7); 1415 1414 } 1416 1415 1417 - static void set_color_conversion(struct drm_i915_private *dev_priv, 1416 + static void set_color_conversion(struct intel_display *display, 1418 1417 const struct color_conversion *color_conversion) 1419 1418 { 1420 - intel_de_write(dev_priv, TV_CSC_Y, 1419 + intel_de_write(display, TV_CSC_Y, 1421 1420 (color_conversion->ry << 16) | color_conversion->gy); 1422 - intel_de_write(dev_priv, TV_CSC_Y2, 1421 + intel_de_write(display, TV_CSC_Y2, 1423 1422 (color_conversion->by << 16) | color_conversion->ay); 1424 - intel_de_write(dev_priv, TV_CSC_U, 1423 + intel_de_write(display, TV_CSC_U, 1425 1424 (color_conversion->ru << 16) | color_conversion->gu); 1426 - intel_de_write(dev_priv, TV_CSC_U2, 1425 + intel_de_write(display, TV_CSC_U2, 1427 1426 (color_conversion->bu << 16) | color_conversion->au); 1428 - intel_de_write(dev_priv, TV_CSC_V, 1427 + intel_de_write(display, TV_CSC_V, 1429 1428 (color_conversion->rv << 16) | color_conversion->gv); 1430 - intel_de_write(dev_priv, TV_CSC_V2, 1429 + intel_de_write(display, TV_CSC_V2, 1431 1430 (color_conversion->bv << 16) | color_conversion->av); 1432 1431 } 1433 1432 ··· 1436 1435 const struct intel_crtc_state *pipe_config, 1437 1436 const struct drm_connector_state *conn_state) 1438 1437 { 1438 + struct intel_display *display = to_intel_display(encoder); 1439 1439 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1440 1440 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc); 1441 1441 struct intel_tv *intel_tv = enc_to_tv(encoder); ··· 1452 1450 int xpos, ypos; 1453 1451 unsigned int xsize, ysize; 1454 1452 1455 - tv_ctl = intel_de_read(dev_priv, TV_CTL); 1453 + tv_ctl = intel_de_read(display, TV_CTL); 1456 1454 tv_ctl &= TV_CTL_SAVE; 1457 1455 1458 1456 switch (intel_tv->type) { ··· 1527 1525 if (IS_I915GM(dev_priv)) 1528 1526 tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX; 1529 1527 1530 - set_tv_mode_timings(dev_priv, tv_mode, burst_ena); 1528 + set_tv_mode_timings(display, tv_mode, burst_ena); 1531 1529 1532 - intel_de_write(dev_priv, TV_SC_CTL_1, scctl1); 1533 - intel_de_write(dev_priv, TV_SC_CTL_2, scctl2); 1534 - intel_de_write(dev_priv, TV_SC_CTL_3, scctl3); 1530 + intel_de_write(display, TV_SC_CTL_1, scctl1); 1531 + intel_de_write(display, TV_SC_CTL_2, scctl2); 1532 + intel_de_write(display, TV_SC_CTL_3, scctl3); 1535 1533 1536 - set_color_conversion(dev_priv, color_conversion); 1534 + set_color_conversion(display, color_conversion); 1537 1535 1538 - if (DISPLAY_VER(dev_priv) >= 4) 1539 - intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00404000); 1536 + if (DISPLAY_VER(display) >= 4) 1537 + intel_de_write(display, TV_CLR_KNOBS, 0x00404000); 1540 1538 else 1541 - intel_de_write(dev_priv, TV_CLR_KNOBS, 0x00606000); 1539 + intel_de_write(display, TV_CLR_KNOBS, 0x00606000); 1542 1540 1543 1541 if (video_levels) 1544 - intel_de_write(dev_priv, TV_CLR_LEVEL, 1542 + intel_de_write(display, TV_CLR_LEVEL, 1545 1543 ((video_levels->black << TV_BLACK_LEVEL_SHIFT) | (video_levels->blank << TV_BLANK_LEVEL_SHIFT))); 1546 1544 1547 1545 assert_transcoder_disabled(dev_priv, pipe_config->cpu_transcoder); ··· 1550 1548 tv_filter_ctl = TV_AUTO_SCALE; 1551 1549 if (tv_conn_state->bypass_vfilter) 1552 1550 tv_filter_ctl |= TV_V_FILTER_BYPASS; 1553 - intel_de_write(dev_priv, TV_FILTER_CTL_1, tv_filter_ctl); 1551 + intel_de_write(display, TV_FILTER_CTL_1, tv_filter_ctl); 1554 1552 1555 1553 xsize = tv_mode->hblank_start - tv_mode->hblank_end; 1556 1554 ysize = intel_tv_mode_vdisplay(tv_mode); ··· 1561 1559 conn_state->tv.margins.right); 1562 1560 ysize -= (tv_conn_state->margins.top + 1563 1561 tv_conn_state->margins.bottom); 1564 - intel_de_write(dev_priv, TV_WIN_POS, (xpos << 16) | ypos); 1565 - intel_de_write(dev_priv, TV_WIN_SIZE, (xsize << 16) | ysize); 1562 + intel_de_write(display, TV_WIN_POS, (xpos << 16) | ypos); 1563 + intel_de_write(display, TV_WIN_SIZE, (xsize << 16) | ysize); 1566 1564 1567 1565 j = 0; 1568 1566 for (i = 0; i < 60; i++) 1569 - intel_de_write(dev_priv, TV_H_LUMA(i), 1567 + intel_de_write(display, TV_H_LUMA(i), 1570 1568 tv_mode->filter_table[j++]); 1571 1569 for (i = 0; i < 60; i++) 1572 - intel_de_write(dev_priv, TV_H_CHROMA(i), 1570 + intel_de_write(display, TV_H_CHROMA(i), 1573 1571 tv_mode->filter_table[j++]); 1574 1572 for (i = 0; i < 43; i++) 1575 - intel_de_write(dev_priv, TV_V_LUMA(i), 1573 + intel_de_write(display, TV_V_LUMA(i), 1576 1574 tv_mode->filter_table[j++]); 1577 1575 for (i = 0; i < 43; i++) 1578 - intel_de_write(dev_priv, TV_V_CHROMA(i), 1576 + intel_de_write(display, TV_V_CHROMA(i), 1579 1577 tv_mode->filter_table[j++]); 1580 - intel_de_write(dev_priv, TV_DAC, 1581 - intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE); 1582 - intel_de_write(dev_priv, TV_CTL, tv_ctl); 1578 + intel_de_write(display, TV_DAC, 1579 + intel_de_read(display, TV_DAC) & TV_DAC_SAVE); 1580 + intel_de_write(display, TV_CTL, tv_ctl); 1583 1581 } 1584 1582 1585 1583 static int 1586 1584 intel_tv_detect_type(struct intel_tv *intel_tv, 1587 1585 struct drm_connector *connector) 1588 1586 { 1587 + struct intel_display *display = to_intel_display(connector->dev); 1589 1588 struct intel_crtc *crtc = to_intel_crtc(connector->state->crtc); 1590 1589 struct drm_device *dev = connector->dev; 1591 1590 struct drm_i915_private *dev_priv = to_i915(dev); ··· 1603 1600 spin_unlock_irq(&dev_priv->irq_lock); 1604 1601 } 1605 1602 1606 - save_tv_dac = tv_dac = intel_de_read(dev_priv, TV_DAC); 1607 - save_tv_ctl = tv_ctl = intel_de_read(dev_priv, TV_CTL); 1603 + save_tv_dac = tv_dac = intel_de_read(display, TV_DAC); 1604 + save_tv_ctl = tv_ctl = intel_de_read(display, TV_CTL); 1608 1605 1609 1606 /* Poll for TV detection */ 1610 1607 tv_ctl &= ~(TV_ENC_ENABLE | TV_ENC_PIPE_SEL_MASK | TV_TEST_MODE_MASK); ··· 1630 1627 tv_dac &= ~(TVDAC_STATE_CHG_EN | TVDAC_A_SENSE_CTL | 1631 1628 TVDAC_B_SENSE_CTL | TVDAC_C_SENSE_CTL); 1632 1629 1633 - intel_de_write(dev_priv, TV_CTL, tv_ctl); 1634 - intel_de_write(dev_priv, TV_DAC, tv_dac); 1635 - intel_de_posting_read(dev_priv, TV_DAC); 1630 + intel_de_write(display, TV_CTL, tv_ctl); 1631 + intel_de_write(display, TV_DAC, tv_dac); 1632 + intel_de_posting_read(display, TV_DAC); 1636 1633 1637 1634 intel_crtc_wait_for_next_vblank(crtc); 1638 1635 1639 1636 type = -1; 1640 - tv_dac = intel_de_read(dev_priv, TV_DAC); 1641 - drm_dbg_kms(&dev_priv->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac); 1637 + tv_dac = intel_de_read(display, TV_DAC); 1638 + drm_dbg_kms(display->drm, "TV detected: %x, %x\n", tv_ctl, tv_dac); 1642 1639 /* 1643 1640 * A B C 1644 1641 * 0 1 1 Composite ··· 1646 1643 * 0 0 0 Component 1647 1644 */ 1648 1645 if ((tv_dac & TVDAC_SENSE_MASK) == (TVDAC_B_SENSE | TVDAC_C_SENSE)) { 1649 - drm_dbg_kms(&dev_priv->drm, 1646 + drm_dbg_kms(display->drm, 1650 1647 "Detected Composite TV connection\n"); 1651 1648 type = DRM_MODE_CONNECTOR_Composite; 1652 1649 } else if ((tv_dac & (TVDAC_A_SENSE|TVDAC_B_SENSE)) == TVDAC_A_SENSE) { 1653 - drm_dbg_kms(&dev_priv->drm, 1650 + drm_dbg_kms(display->drm, 1654 1651 "Detected S-Video TV connection\n"); 1655 1652 type = DRM_MODE_CONNECTOR_SVIDEO; 1656 1653 } else if ((tv_dac & TVDAC_SENSE_MASK) == 0) { 1657 - drm_dbg_kms(&dev_priv->drm, 1654 + drm_dbg_kms(display->drm, 1658 1655 "Detected Component TV connection\n"); 1659 1656 type = DRM_MODE_CONNECTOR_Component; 1660 1657 } else { 1661 - drm_dbg_kms(&dev_priv->drm, "Unrecognised TV connection\n"); 1658 + drm_dbg_kms(display->drm, "Unrecognised TV connection\n"); 1662 1659 type = -1; 1663 1660 } 1664 1661 1665 - intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1666 - intel_de_write(dev_priv, TV_CTL, save_tv_ctl); 1667 - intel_de_posting_read(dev_priv, TV_CTL); 1662 + intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1663 + intel_de_write(display, TV_CTL, save_tv_ctl); 1664 + intel_de_posting_read(display, TV_CTL); 1668 1665 1669 1666 /* For unknown reasons the hw barfs if we don't do this vblank wait. */ 1670 1667 intel_crtc_wait_for_next_vblank(crtc); ··· 1714 1711 struct drm_modeset_acquire_ctx *ctx, 1715 1712 bool force) 1716 1713 { 1714 + struct intel_display *display = to_intel_display(connector->dev); 1717 1715 struct drm_i915_private *i915 = to_i915(connector->dev); 1718 1716 struct intel_tv *intel_tv = intel_attached_tv(to_intel_connector(connector)); 1719 1717 enum drm_connector_status status; 1720 1718 int type; 1721 1719 1722 - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] force=%d\n", 1720 + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n", 1723 1721 connector->base.id, connector->name, force); 1724 1722 1725 1723 if (!intel_display_device_enabled(i915)) ··· 1795 1791 static int 1796 1792 intel_tv_get_modes(struct drm_connector *connector) 1797 1793 { 1798 - struct drm_i915_private *dev_priv = to_i915(connector->dev); 1794 + struct intel_display *display = to_intel_display(connector->dev); 1799 1795 const struct tv_mode *tv_mode = intel_tv_mode_find(connector->state); 1800 1796 int i, count = 0; 1801 1797 ··· 1809 1805 continue; 1810 1806 1811 1807 /* no vertical scaling with wide sources on gen3 */ 1812 - if (DISPLAY_VER(dev_priv) == 3 && input->w > 1024 && 1808 + if (DISPLAY_VER(display) == 3 && input->w > 1024 && 1813 1809 input->h > intel_tv_mode_vdisplay(tv_mode)) 1814 1810 continue; 1815 1811 ··· 1826 1822 */ 1827 1823 intel_tv_mode_to_mode(mode, tv_mode, tv_mode->clock); 1828 1824 if (count == 0) { 1829 - drm_dbg_kms(&dev_priv->drm, "TV mode: " DRM_MODE_FMT "\n", 1825 + drm_dbg_kms(display->drm, 1826 + "TV mode: " DRM_MODE_FMT "\n", 1830 1827 DRM_MODE_ARG(mode)); 1831 1828 } 1832 1829 intel_tv_scale_mode_horiz(mode, input->w, 0, 0); ··· 1892 1887 1893 1888 static void intel_tv_add_properties(struct drm_connector *connector) 1894 1889 { 1895 - struct drm_i915_private *i915 = to_i915(connector->dev); 1890 + struct intel_display *display = to_intel_display(connector->dev); 1896 1891 struct drm_connector_state *conn_state = connector->state; 1897 1892 const char *tv_format_names[ARRAY_SIZE(tv_modes)]; 1898 1893 int i; ··· 1908 1903 /* Create TV properties then attach current values */ 1909 1904 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) { 1910 1905 /* 1080p50/1080p60 not supported on gen3 */ 1911 - if (DISPLAY_VER(i915) == 3 && tv_modes[i].oversample == 1) 1906 + if (DISPLAY_VER(display) == 3 && tv_modes[i].oversample == 1) 1912 1907 break; 1913 1908 1914 1909 tv_format_names[i] = tv_modes[i].name; 1915 1910 } 1916 - drm_mode_create_tv_properties_legacy(&i915->drm, i, tv_format_names); 1911 + drm_mode_create_tv_properties_legacy(display->drm, i, tv_format_names); 1917 1912 1918 1913 drm_object_attach_property(&connector->base, 1919 - i915->drm.mode_config.legacy_tv_mode_property, 1914 + display->drm->mode_config.legacy_tv_mode_property, 1920 1915 conn_state->tv.legacy_mode); 1921 1916 drm_object_attach_property(&connector->base, 1922 - i915->drm.mode_config.tv_left_margin_property, 1917 + display->drm->mode_config.tv_left_margin_property, 1923 1918 conn_state->tv.margins.left); 1924 1919 drm_object_attach_property(&connector->base, 1925 - i915->drm.mode_config.tv_top_margin_property, 1920 + display->drm->mode_config.tv_top_margin_property, 1926 1921 conn_state->tv.margins.top); 1927 1922 drm_object_attach_property(&connector->base, 1928 - i915->drm.mode_config.tv_right_margin_property, 1923 + display->drm->mode_config.tv_right_margin_property, 1929 1924 conn_state->tv.margins.right); 1930 1925 drm_object_attach_property(&connector->base, 1931 - i915->drm.mode_config.tv_bottom_margin_property, 1926 + display->drm->mode_config.tv_bottom_margin_property, 1932 1927 conn_state->tv.margins.bottom); 1933 1928 } 1934 1929 1935 1930 void 1936 - intel_tv_init(struct drm_i915_private *dev_priv) 1931 + intel_tv_init(struct intel_display *display) 1937 1932 { 1938 - struct intel_display *display = &dev_priv->display; 1939 1933 struct drm_connector *connector; 1940 1934 struct intel_tv *intel_tv; 1941 1935 struct intel_encoder *intel_encoder; 1942 1936 struct intel_connector *intel_connector; 1943 1937 u32 tv_dac_on, tv_dac_off, save_tv_dac; 1944 1938 1945 - if ((intel_de_read(dev_priv, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1939 + if ((intel_de_read(display, TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED) 1946 1940 return; 1947 1941 1948 1942 if (!intel_bios_is_tv_present(display)) { 1949 - drm_dbg_kms(&dev_priv->drm, "Integrated TV is not present.\n"); 1943 + drm_dbg_kms(display->drm, "Integrated TV is not present.\n"); 1950 1944 return; 1951 1945 } 1952 1946 ··· 1953 1949 * Sanity check the TV output by checking to see if the 1954 1950 * DAC register holds a value 1955 1951 */ 1956 - save_tv_dac = intel_de_read(dev_priv, TV_DAC); 1952 + save_tv_dac = intel_de_read(display, TV_DAC); 1957 1953 1958 - intel_de_write(dev_priv, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); 1959 - tv_dac_on = intel_de_read(dev_priv, TV_DAC); 1954 + intel_de_write(display, TV_DAC, save_tv_dac | TVDAC_STATE_CHG_EN); 1955 + tv_dac_on = intel_de_read(display, TV_DAC); 1960 1956 1961 - intel_de_write(dev_priv, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1962 - tv_dac_off = intel_de_read(dev_priv, TV_DAC); 1957 + intel_de_write(display, TV_DAC, save_tv_dac & ~TVDAC_STATE_CHG_EN); 1958 + tv_dac_off = intel_de_read(display, TV_DAC); 1963 1959 1964 - intel_de_write(dev_priv, TV_DAC, save_tv_dac); 1960 + intel_de_write(display, TV_DAC, save_tv_dac); 1965 1961 1966 1962 /* 1967 1963 * If the register does not hold the state change enable ··· 1999 1995 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; 2000 1996 intel_connector->base.polled = intel_connector->polled; 2001 1997 2002 - drm_connector_init(&dev_priv->drm, connector, &intel_tv_connector_funcs, 1998 + drm_connector_init(display->drm, connector, &intel_tv_connector_funcs, 2003 1999 DRM_MODE_CONNECTOR_SVIDEO); 2004 2000 2005 - drm_encoder_init(&dev_priv->drm, &intel_encoder->base, &intel_tv_enc_funcs, 2001 + drm_encoder_init(display->drm, &intel_encoder->base, 2002 + &intel_tv_enc_funcs, 2006 2003 DRM_MODE_ENCODER_TVDAC, "TV"); 2007 2004 2008 2005 intel_encoder->compute_config = intel_tv_compute_config;

+3 -3

drivers/gpu/drm/i915/display/intel_tv.h

··· 6 6 #ifndef __INTEL_TV_H__ 7 7 #define __INTEL_TV_H__ 8 8 9 - struct drm_i915_private; 9 + struct intel_display; 10 10 11 11 #ifdef I915 12 - void intel_tv_init(struct drm_i915_private *dev_priv); 12 + void intel_tv_init(struct intel_display *display); 13 13 #else 14 - static inline void intel_tv_init(struct drm_i915_private *dev_priv) 14 + static inline void intel_tv_init(struct intel_display *display) 15 15 { 16 16 } 17 17 #endif

+61 -61

drivers/gpu/drm/i915/display/intel_vblank.c

··· 67 67 */ 68 68 u32 i915_get_vblank_counter(struct drm_crtc *crtc) 69 69 { 70 - struct drm_i915_private *dev_priv = to_i915(crtc->dev); 71 - struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 70 + struct intel_display *display = to_intel_display(crtc->dev); 71 + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); 72 72 const struct drm_display_mode *mode = &vblank->hwmode; 73 73 enum pipe pipe = to_intel_crtc(crtc)->pipe; 74 74 u32 pixel, vbl_start, hsync_start, htotal; ··· 103 103 * we get a low value that's stable across two reads of the high 104 104 * register. 105 105 */ 106 - frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe), 107 - PIPEFRAME(dev_priv, pipe)); 106 + frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe), 107 + PIPEFRAME(display, pipe)); 108 108 109 109 pixel = frame & PIPE_PIXEL_MASK; 110 110 frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff; ··· 119 119 120 120 u32 g4x_get_vblank_counter(struct drm_crtc *crtc) 121 121 { 122 - struct drm_i915_private *dev_priv = to_i915(crtc->dev); 123 - struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[drm_crtc_index(crtc)]; 122 + struct intel_display *display = to_intel_display(crtc->dev); 123 + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc); 124 124 enum pipe pipe = to_intel_crtc(crtc)->pipe; 125 125 126 126 if (!vblank->max_vblank_count) 127 127 return 0; 128 128 129 - return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe)); 129 + return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe)); 130 130 } 131 131 132 132 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc) 133 133 { 134 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 134 + struct intel_display *display = to_intel_display(crtc); 135 135 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 136 136 const struct drm_display_mode *mode = &vblank->hwmode; 137 137 u32 htotal = mode->crtc_htotal; ··· 150 150 * pipe frame time stamp. The time stamp value 151 151 * is sampled at every start of vertical blank. 152 152 */ 153 - scan_prev_time = intel_de_read_fw(dev_priv, 153 + scan_prev_time = intel_de_read_fw(display, 154 154 PIPE_FRMTMSTMP(crtc->pipe)); 155 155 156 156 /* 157 157 * The TIMESTAMP_CTR register has the current 158 158 * time stamp value. 159 159 */ 160 - scan_curr_time = intel_de_read_fw(dev_priv, IVB_TIMESTAMP_CTR); 160 + scan_curr_time = intel_de_read_fw(display, IVB_TIMESTAMP_CTR); 161 161 162 - scan_post_time = intel_de_read_fw(dev_priv, 162 + scan_post_time = intel_de_read_fw(display, 163 163 PIPE_FRMTMSTMP(crtc->pipe)); 164 164 } while (scan_post_time != scan_prev_time); 165 165 ··· 190 190 return scanline; 191 191 } 192 192 193 - static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) 193 + int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) 194 194 { 195 + struct intel_display *display = to_intel_display(crtc_state); 195 196 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 196 197 197 198 /* ··· 221 220 * However if queried just before the start of vblank we'll get an 222 221 * answer that's slightly in the future. 223 222 */ 224 - if (DISPLAY_VER(i915) == 2) 223 + if (DISPLAY_VER(display) == 2) 225 224 return -1; 226 225 else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 227 226 return 2; ··· 235 234 */ 236 235 static int __intel_get_crtc_scanline(struct intel_crtc *crtc) 237 236 { 238 - struct drm_device *dev = crtc->base.dev; 239 - struct drm_i915_private *dev_priv = to_i915(dev); 237 + struct intel_display *display = to_intel_display(crtc); 240 238 struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 241 239 const struct drm_display_mode *mode = &vblank->hwmode; 242 240 enum pipe pipe = crtc->pipe; ··· 249 249 250 250 vtotal = intel_mode_vtotal(mode); 251 251 252 - position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK; 252 + position = intel_de_read_fw(display, PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK; 253 253 254 254 /* 255 255 * On HSW, the DSL reg (0x70000) appears to return 0 if we ··· 263 263 * problem. We may need to extend this to include other platforms, 264 264 * but so far testing only shows the problem on HSW. 265 265 */ 266 - if (HAS_DDI(dev_priv) && !position) { 266 + if (HAS_DDI(display) && !position) { 267 267 int i, temp; 268 268 269 269 for (i = 0; i < 100; i++) { 270 270 udelay(1); 271 - temp = intel_de_read_fw(dev_priv, 272 - PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK; 271 + temp = intel_de_read_fw(display, 272 + PIPEDSL(display, pipe)) & PIPEDSL_LINE_MASK; 273 273 if (temp != position) { 274 274 position = temp; 275 275 break; ··· 284 284 return (position + vtotal + crtc->scanline_offset) % vtotal; 285 285 } 286 286 287 - int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline) 288 - { 289 - const struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); 290 - const struct drm_display_mode *mode = &vblank->hwmode; 291 - int vtotal = intel_mode_vtotal(mode); 292 - 293 - return (scanline + vtotal - crtc->scanline_offset) % vtotal; 294 - } 295 - 296 287 /* 297 288 * The uncore version of the spin lock functions is used to decide 298 289 * whether we need to lock the uncore lock or not. This is only ··· 294 303 * all register accesses to the same cacheline to be serialized, 295 304 * otherwise they may hang. 296 305 */ 297 - static void intel_vblank_section_enter(struct drm_i915_private *i915) 306 + #ifdef I915 307 + static void intel_vblank_section_enter(struct intel_display *display) 298 308 __acquires(i915->uncore.lock) 299 309 { 300 - #ifdef I915 310 + struct drm_i915_private *i915 = to_i915(display->drm); 301 311 spin_lock(&i915->uncore.lock); 302 - #endif 303 312 } 304 313 305 - static void intel_vblank_section_exit(struct drm_i915_private *i915) 314 + static void intel_vblank_section_exit(struct intel_display *display) 306 315 __releases(i915->uncore.lock) 307 316 { 308 - #ifdef I915 317 + struct drm_i915_private *i915 = to_i915(display->drm); 309 318 spin_unlock(&i915->uncore.lock); 310 - #endif 311 319 } 320 + #else 321 + static void intel_vblank_section_enter(struct intel_display *display) 322 + { 323 + } 324 + 325 + static void intel_vblank_section_exit(struct intel_display *display) 326 + { 327 + } 328 + #endif 312 329 313 330 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, 314 331 bool in_vblank_irq, ··· 324 325 ktime_t *stime, ktime_t *etime, 325 326 const struct drm_display_mode *mode) 326 327 { 327 - struct drm_device *dev = _crtc->dev; 328 - struct drm_i915_private *dev_priv = to_i915(dev); 328 + struct intel_display *display = to_intel_display(_crtc->dev); 329 + struct drm_i915_private *dev_priv = to_i915(display->drm); 329 330 struct intel_crtc *crtc = to_intel_crtc(_crtc); 330 331 enum pipe pipe = crtc->pipe; 331 332 int position; 332 333 int vbl_start, vbl_end, hsync_start, htotal, vtotal; 333 334 unsigned long irqflags; 334 - bool use_scanline_counter = DISPLAY_VER(dev_priv) >= 5 || 335 - IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) == 2 || 335 + bool use_scanline_counter = DISPLAY_VER(display) >= 5 || 336 + IS_G4X(dev_priv) || DISPLAY_VER(display) == 2 || 336 337 crtc->mode_flags & I915_MODE_FLAG_USE_SCANLINE_COUNTER; 337 338 338 - if (drm_WARN_ON(&dev_priv->drm, !mode->crtc_clock)) { 339 - drm_dbg(&dev_priv->drm, 339 + if (drm_WARN_ON(display->drm, !mode->crtc_clock)) { 340 + drm_dbg(display->drm, 340 341 "trying to get scanoutpos for disabled pipe %c\n", 341 342 pipe_name(pipe)); 342 343 return false; ··· 354 355 * preemption disabled, so the following code must not block. 355 356 */ 356 357 local_irq_save(irqflags); 357 - intel_vblank_section_enter(dev_priv); 358 + intel_vblank_section_enter(display); 358 359 359 360 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 360 361 ··· 386 387 * We can split this into vertical and horizontal 387 388 * scanout position. 388 389 */ 389 - position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 390 + position = (intel_de_read_fw(display, PIPEFRAMEPIXEL(display, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; 390 391 391 392 /* convert to pixel counts */ 392 393 vbl_start *= htotal; ··· 422 423 423 424 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 424 425 425 - intel_vblank_section_exit(dev_priv); 426 + intel_vblank_section_exit(display); 426 427 local_irq_restore(irqflags); 427 428 428 429 /* ··· 457 458 458 459 int intel_get_crtc_scanline(struct intel_crtc *crtc) 459 460 { 460 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 461 + struct intel_display *display = to_intel_display(crtc); 461 462 unsigned long irqflags; 462 463 int position; 463 464 464 465 local_irq_save(irqflags); 465 - intel_vblank_section_enter(dev_priv); 466 + intel_vblank_section_enter(display); 466 467 467 468 position = __intel_get_crtc_scanline(crtc); 468 469 469 - intel_vblank_section_exit(dev_priv); 470 + intel_vblank_section_exit(display); 470 471 local_irq_restore(irqflags); 471 472 472 473 return position; 473 474 } 474 475 475 - static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, 476 + static bool pipe_scanline_is_moving(struct intel_display *display, 476 477 enum pipe pipe) 477 478 { 478 - i915_reg_t reg = PIPEDSL(dev_priv, pipe); 479 + i915_reg_t reg = PIPEDSL(display, pipe); 479 480 u32 line1, line2; 480 481 481 - line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 482 + line1 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK; 482 483 msleep(5); 483 - line2 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; 484 + line2 = intel_de_read(display, reg) & PIPEDSL_LINE_MASK; 484 485 485 486 return line1 != line2; 486 487 } 487 488 488 489 static void wait_for_pipe_scanline_moving(struct intel_crtc *crtc, bool state) 489 490 { 490 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 491 + struct intel_display *display = to_intel_display(crtc); 491 492 enum pipe pipe = crtc->pipe; 492 493 493 494 /* Wait for the display line to settle/start moving */ 494 - if (wait_for(pipe_scanline_is_moving(dev_priv, pipe) == state, 100)) 495 - drm_err(&dev_priv->drm, 495 + if (wait_for(pipe_scanline_is_moving(display, pipe) == state, 100)) 496 + drm_err(display->drm, 496 497 "pipe %c scanline %s wait timed out\n", 497 498 pipe_name(pipe), str_on_off(state)); 498 499 } ··· 510 511 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, 511 512 bool vrr_enable) 512 513 { 514 + struct intel_display *display = to_intel_display(crtc_state); 513 515 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 514 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 515 516 u8 mode_flags = crtc_state->mode_flags; 516 517 struct drm_display_mode adjusted_mode; 517 518 int vmax_vblank_start = 0; ··· 520 521 drm_mode_init(&adjusted_mode, &crtc_state->hw.adjusted_mode); 521 522 522 523 if (vrr_enable) { 523 - drm_WARN_ON(&i915->drm, (mode_flags & I915_MODE_FLAG_VRR) == 0); 524 + drm_WARN_ON(display->drm, 525 + (mode_flags & I915_MODE_FLAG_VRR) == 0); 524 526 525 527 adjusted_mode.crtc_vtotal = crtc_state->vrr.vmax; 526 528 adjusted_mode.crtc_vblank_end = crtc_state->vrr.vmax; ··· 543 543 * __intel_get_crtc_scanline()) with vblank_time_lock? 544 544 * Need to audit everything to make sure it's safe. 545 545 */ 546 - spin_lock_irqsave(&i915->drm.vblank_time_lock, irqflags); 547 - intel_vblank_section_enter(i915); 546 + spin_lock_irqsave(&display->drm->vblank_time_lock, irqflags); 547 + intel_vblank_section_enter(display); 548 548 549 549 drm_calc_timestamping_constants(&crtc->base, &adjusted_mode); 550 550 ··· 553 553 crtc->mode_flags = mode_flags; 554 554 555 555 crtc->scanline_offset = intel_crtc_scanline_offset(crtc_state); 556 - intel_vblank_section_exit(i915); 557 - spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags); 556 + intel_vblank_section_exit(display); 557 + spin_unlock_irqrestore(&display->drm->vblank_time_lock, irqflags); 558 558 } 559 559 560 560 int intel_mode_vdisplay(const struct drm_display_mode *mode) ··· 660 660 int intel_vblank_evade(struct intel_vblank_evade_ctx *evade) 661 661 { 662 662 struct intel_crtc *crtc = evade->crtc; 663 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 663 + struct intel_display *display = to_intel_display(crtc); 664 664 long timeout = msecs_to_jiffies_timeout(1); 665 665 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base); 666 666 DEFINE_WAIT(wait); ··· 682 682 break; 683 683 684 684 if (!timeout) { 685 - drm_err(&i915->drm, 685 + drm_err(display->drm, 686 686 "Potential atomic update failure on pipe %c\n", 687 687 pipe_name(crtc->pipe)); 688 688 break;

+1 -1

drivers/gpu/drm/i915/display/intel_vblank.h

··· 40 40 void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc); 41 41 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, 42 42 bool vrr_enable); 43 - int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline); 43 + int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state); 44 44 45 45 #endif /* __INTEL_VBLANK_H__ */

+61 -66

drivers/gpu/drm/i915/display/intel_vrr.c

··· 17 17 18 18 bool intel_vrr_is_capable(struct intel_connector *connector) 19 19 { 20 + struct intel_display *display = to_intel_display(connector); 20 21 const struct drm_display_info *info = &connector->base.display_info; 21 - struct drm_i915_private *i915 = to_i915(connector->base.dev); 22 22 struct intel_dp *intel_dp; 23 23 24 24 /* ··· 43 43 return false; 44 44 } 45 45 46 - return HAS_VRR(i915) && 46 + return HAS_VRR(display) && 47 47 info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10; 48 48 } 49 49 ··· 89 89 */ 90 90 static int intel_vrr_vblank_exit_length(const struct intel_crtc_state *crtc_state) 91 91 { 92 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 93 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 92 + struct intel_display *display = to_intel_display(crtc_state); 94 93 95 - if (DISPLAY_VER(i915) >= 13) 94 + if (DISPLAY_VER(display) >= 13) 96 95 return crtc_state->vrr.guardband; 97 96 else 98 97 /* The hw imposes the extra scanline before frame start */ ··· 112 113 static bool 113 114 is_cmrr_frac_required(struct intel_crtc_state *crtc_state) 114 115 { 116 + struct intel_display *display = to_intel_display(crtc_state); 115 117 int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; 116 118 struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; 117 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 118 119 119 - if (!HAS_CMRR(i915)) 120 + if (!HAS_CMRR(display)) 120 121 return false; 121 122 122 123 actual_refresh_k = ··· 160 161 intel_vrr_compute_config(struct intel_crtc_state *crtc_state, 161 162 struct drm_connector_state *conn_state) 162 163 { 163 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 164 - struct drm_i915_private *i915 = to_i915(crtc->base.dev); 164 + struct intel_display *display = to_intel_display(crtc_state); 165 165 struct intel_connector *connector = 166 166 to_intel_connector(conn_state->connector); 167 167 struct intel_dp *intel_dp = intel_attached_dp(connector); ··· 184 186 if (!crtc_state->vrr.in_range) 185 187 return; 186 188 187 - if (HAS_LRR(i915)) 189 + if (HAS_LRR(display)) 188 190 crtc_state->update_lrr = true; 189 191 190 192 vmin = DIV_ROUND_UP(adjusted_mode->crtc_clock * 1000, ··· 244 246 * For XE_LPD+, we use guardband and pipeline override 245 247 * is deprecated. 246 248 */ 247 - if (DISPLAY_VER(i915) >= 13) { 249 + if (DISPLAY_VER(display) >= 13) { 248 250 crtc_state->vrr.guardband = 249 251 crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; 250 252 } else { ··· 256 258 257 259 static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) 258 260 { 259 - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 261 + struct intel_display *display = to_intel_display(crtc_state); 260 262 261 - if (DISPLAY_VER(i915) >= 13) 263 + if (DISPLAY_VER(display) >= 13) 262 264 return VRR_CTL_IGN_MAX_SHIFT | VRR_CTL_FLIP_LINE_EN | 263 265 XELPD_VRR_CTL_VRR_GUARDBAND(crtc_state->vrr.guardband); 264 266 else ··· 269 271 270 272 void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 271 273 { 272 - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 274 + struct intel_display *display = to_intel_display(crtc_state); 273 275 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 274 276 275 277 /* ··· 277 279 * TGL: generate VRR "safe window" for DSB vblank waits 278 280 * ADL/DG2: make TRANS_SET_CONTEXT_LATENCY effective with VRR 279 281 */ 280 - if (IS_DISPLAY_VER(dev_priv, 12, 13)) 281 - intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 282 + if (IS_DISPLAY_VER(display, 12, 13)) 283 + intel_de_rmw(display, CHICKEN_TRANS(cpu_transcoder), 282 284 0, PIPE_VBLANK_WITH_DELAY); 283 285 284 286 if (!crtc_state->vrr.flipline) { 285 - intel_de_write(dev_priv, 286 - TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0); 287 + intel_de_write(display, 288 + TRANS_VRR_CTL(display, cpu_transcoder), 0); 287 289 return; 288 290 } 289 291 290 292 if (crtc_state->cmrr.enable) { 291 - intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder), 293 + intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 292 294 upper_32_bits(crtc_state->cmrr.cmrr_m)); 293 - intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), 295 + intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 294 296 lower_32_bits(crtc_state->cmrr.cmrr_m)); 295 - intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder), 297 + intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 296 298 upper_32_bits(crtc_state->cmrr.cmrr_n)); 297 - intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), 299 + intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 298 300 lower_32_bits(crtc_state->cmrr.cmrr_n)); 299 301 } 300 302 301 - intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder), 303 + intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), 302 304 crtc_state->vrr.vmin - 1); 303 - intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder), 305 + intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), 304 306 crtc_state->vrr.vmax - 1); 305 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 307 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 306 308 trans_vrr_ctl(crtc_state)); 307 - intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder), 309 + intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder), 308 310 crtc_state->vrr.flipline - 1); 309 311 } 310 312 311 313 void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) 312 314 { 313 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 314 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 315 + struct intel_display *display = to_intel_display(crtc_state); 315 316 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 316 317 317 318 if (!crtc_state->vrr.enable) 318 319 return; 319 320 320 - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 321 + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 321 322 TRANS_PUSH_EN | TRANS_PUSH_SEND); 322 323 } 323 324 324 325 bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) 325 326 { 326 - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 327 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 327 + struct intel_display *display = to_intel_display(crtc_state); 328 328 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 329 329 330 330 if (!crtc_state->vrr.enable) 331 331 return false; 332 332 333 - return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & TRANS_PUSH_SEND; 333 + return intel_de_read(display, TRANS_PUSH(display, cpu_transcoder)) & TRANS_PUSH_SEND; 334 334 } 335 335 336 336 void intel_vrr_enable(const struct intel_crtc_state *crtc_state) 337 337 { 338 - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 338 + struct intel_display *display = to_intel_display(crtc_state); 339 339 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 340 340 341 341 if (!crtc_state->vrr.enable) 342 342 return; 343 343 344 - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 344 + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 345 345 TRANS_PUSH_EN); 346 346 347 - if (HAS_AS_SDP(dev_priv)) 348 - intel_de_write(dev_priv, 349 - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 347 + if (HAS_AS_SDP(display)) 348 + intel_de_write(display, 349 + TRANS_VRR_VSYNC(display, cpu_transcoder), 350 350 VRR_VSYNC_END(crtc_state->vrr.vsync_end) | 351 351 VRR_VSYNC_START(crtc_state->vrr.vsync_start)); 352 352 353 353 if (crtc_state->cmrr.enable) { 354 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 354 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 355 355 VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | 356 356 trans_vrr_ctl(crtc_state)); 357 357 } else { 358 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 358 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 359 359 VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); 360 360 } 361 361 } 362 362 363 363 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) 364 364 { 365 - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 366 - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 365 + struct intel_display *display = to_intel_display(old_crtc_state); 367 366 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; 368 367 369 368 if (!old_crtc_state->vrr.enable) 370 369 return; 371 370 372 - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), 371 + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), 373 372 trans_vrr_ctl(old_crtc_state)); 374 - intel_de_wait_for_clear(dev_priv, 375 - TRANS_VRR_STATUS(dev_priv, cpu_transcoder), 373 + intel_de_wait_for_clear(display, 374 + TRANS_VRR_STATUS(display, cpu_transcoder), 376 375 VRR_STATUS_VRR_EN_LIVE, 1000); 377 - intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0); 376 + intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); 378 377 379 - if (HAS_AS_SDP(dev_priv)) 380 - intel_de_write(dev_priv, 381 - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0); 378 + if (HAS_AS_SDP(display)) 379 + intel_de_write(display, 380 + TRANS_VRR_VSYNC(display, cpu_transcoder), 0); 382 381 } 383 382 384 383 void intel_vrr_get_config(struct intel_crtc_state *crtc_state) 385 384 { 386 - struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 385 + struct intel_display *display = to_intel_display(crtc_state); 387 386 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 388 387 u32 trans_vrr_ctl, trans_vrr_vsync; 389 388 390 - trans_vrr_ctl = intel_de_read(dev_priv, 391 - TRANS_VRR_CTL(dev_priv, cpu_transcoder)); 389 + trans_vrr_ctl = intel_de_read(display, 390 + TRANS_VRR_CTL(display, cpu_transcoder)); 392 391 393 392 crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; 394 - if (HAS_CMRR(dev_priv)) 393 + if (HAS_CMRR(display)) 395 394 crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); 396 395 397 396 if (crtc_state->cmrr.enable) { 398 397 crtc_state->cmrr.cmrr_n = 399 - intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), 400 - TRANS_CMRR_N_HI(dev_priv, cpu_transcoder)); 398 + intel_de_read64_2x32(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 399 + TRANS_CMRR_N_HI(display, cpu_transcoder)); 401 400 crtc_state->cmrr.cmrr_m = 402 - intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), 403 - TRANS_CMRR_M_HI(dev_priv, cpu_transcoder)); 401 + intel_de_read64_2x32(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 402 + TRANS_CMRR_M_HI(display, cpu_transcoder)); 404 403 } 405 404 406 - if (DISPLAY_VER(dev_priv) >= 13) 405 + if (DISPLAY_VER(display) >= 13) 407 406 crtc_state->vrr.guardband = 408 407 REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); 409 408 else ··· 409 414 REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); 410 415 411 416 if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) { 412 - crtc_state->vrr.flipline = intel_de_read(dev_priv, 413 - TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1; 414 - crtc_state->vrr.vmax = intel_de_read(dev_priv, 415 - TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1; 416 - crtc_state->vrr.vmin = intel_de_read(dev_priv, 417 - TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1; 417 + crtc_state->vrr.flipline = intel_de_read(display, 418 + TRANS_VRR_FLIPLINE(display, cpu_transcoder)) + 1; 419 + crtc_state->vrr.vmax = intel_de_read(display, 420 + TRANS_VRR_VMAX(display, cpu_transcoder)) + 1; 421 + crtc_state->vrr.vmin = intel_de_read(display, 422 + TRANS_VRR_VMIN(display, cpu_transcoder)) + 1; 418 423 } 419 424 420 425 if (crtc_state->vrr.enable) { 421 426 crtc_state->mode_flags |= I915_MODE_FLAG_VRR; 422 427 423 - if (HAS_AS_SDP(dev_priv)) { 428 + if (HAS_AS_SDP(display)) { 424 429 trans_vrr_vsync = 425 - intel_de_read(dev_priv, 426 - TRANS_VRR_VSYNC(dev_priv, cpu_transcoder)); 430 + intel_de_read(display, 431 + TRANS_VRR_VSYNC(display, cpu_transcoder)); 427 432 crtc_state->vrr.vsync_start = 428 433 REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync); 429 434 crtc_state->vrr.vsync_end =

+5 -5

drivers/gpu/drm/i915/display/skl_universal_plane.c

··· 538 538 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: 539 539 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC: 540 540 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: 541 + case I915_FORMAT_MOD_4_TILED_BMG_CCS: 542 + case I915_FORMAT_MOD_4_TILED_LNL_CCS: 541 543 /* 542 544 * Align to at least 4x1 main surface 543 545 * tiles (16K) to match 64B of AUX. ··· 951 949 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 952 950 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: 953 951 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE; 952 + case I915_FORMAT_MOD_4_TILED_BMG_CCS: 953 + case I915_FORMAT_MOD_4_TILED_LNL_CCS: 954 + return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 954 955 case I915_FORMAT_MOD_Y_TILED_CCS: 955 956 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC: 956 957 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; ··· 1090 1085 /* Wa_22012358565:adl-p */ 1091 1086 if (DISPLAY_VER(dev_priv) == 13) 1092 1087 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state); 1093 - 1094 - if (GRAPHICS_VER(dev_priv) >= 20 && 1095 - fb->modifier == I915_FORMAT_MOD_4_TILED) { 1096 - plane_ctl |= PLANE_CTL_RENDER_DECOMPRESSION_ENABLE; 1097 - } 1098 1088 1099 1089 return plane_ctl; 1100 1090 }

-1

drivers/gpu/drm/i915/display/vlv_dsi.c

··· 1870 1870 /* Lenovo Yoga Tab 3 Pro YT3-X90F */ 1871 1871 .matches = { 1872 1872 DMI_MATCH(DMI_SYS_VENDOR, "Intel Corporation"), 1873 - DMI_MATCH(DMI_PRODUCT_NAME, "CHERRYVIEW D1 PLATFORM"), 1874 1873 DMI_MATCH(DMI_PRODUCT_VERSION, "Blade3-10A-001"), 1875 1874 }, 1876 1875 .driver_data = (void *)vlv_dsi_lenovo_yoga_tab3_backlight_fixup,

-2

drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c

··· 12 12 #include <drm/drm_auth.h> 13 13 #include <drm/drm_syncobj.h> 14 14 15 - #include "display/intel_frontbuffer.h" 16 - 17 15 #include "gem/i915_gem_ioctls.h" 18 16 #include "gt/intel_context.h" 19 17 #include "gt/intel_gpu_commands.h"

-1

drivers/gpu/drm/i915/gt/intel_ggtt.c

··· 12 12 #include <drm/intel/i915_drm.h> 13 13 #include <drm/intel/intel-gtt.h> 14 14 15 - #include "display/intel_display.h" 16 15 #include "gem/i915_gem_lmem.h" 17 16 18 17 #include "intel_context.h"

+31

drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.c

··· 212 212 } 213 213 } 214 214 215 + if (IS_ARROWLAKE(gt->i915)) { 216 + bool too_old = false; 217 + 218 + /* 219 + * ARL requires a newer firmware than MTL did (102.0.10.1878) but the 220 + * firmware is actually common. So, need to do an explicit version check 221 + * here rather than using a separate table entry. And if the older 222 + * MTL-only version is found, then just don't use GSC rather than aborting 223 + * the driver load. 224 + */ 225 + if (gsc->release.major < 102) { 226 + too_old = true; 227 + } else if (gsc->release.major == 102) { 228 + if (gsc->release.minor == 0) { 229 + if (gsc->release.patch < 10) { 230 + too_old = true; 231 + } else if (gsc->release.patch == 10) { 232 + if (gsc->release.build < 1878) 233 + too_old = true; 234 + } 235 + } 236 + } 237 + 238 + if (too_old) { 239 + gt_info(gt, "GSC firmware too old for ARL, got %d.%d.%d.%d but need at least 102.0.10.1878", 240 + gsc->release.major, gsc->release.minor, 241 + gsc->release.patch, gsc->release.build); 242 + return -EINVAL; 243 + } 244 + } 245 + 215 246 return 0; 216 247 } 217 248

+8 -2

drivers/gpu/drm/i915/gt/uc/intel_uc_fw.c

··· 698 698 const struct firmware *fw, 699 699 struct intel_uc_fw *uc_fw) 700 700 { 701 + int ret; 702 + 701 703 switch (uc_fw->type) { 702 704 case INTEL_UC_FW_TYPE_HUC: 703 - intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size); 705 + ret = intel_huc_fw_get_binary_info(uc_fw, fw->data, fw->size); 706 + if (ret) 707 + return ret; 704 708 break; 705 709 case INTEL_UC_FW_TYPE_GSC: 706 - intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size); 710 + ret = intel_gsc_fw_get_binary_info(uc_fw, fw->data, fw->size); 711 + if (ret) 712 + return ret; 707 713 break; 708 714 default: 709 715 MISSING_CASE(uc_fw->type);

+2 -1

drivers/gpu/drm/i915/i915_debugfs.c

··· 66 66 static int i915_capabilities(struct seq_file *m, void *data) 67 67 { 68 68 struct drm_i915_private *i915 = node_to_i915(m->private); 69 + struct intel_display *display = &i915->display; 69 70 struct drm_printer p = drm_seq_file_printer(m); 70 71 71 72 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915)); ··· 78 77 79 78 kernel_param_lock(THIS_MODULE); 80 79 i915_params_dump(&i915->params, &p); 81 - intel_display_params_dump(i915, &p); 80 + intel_display_params_dump(display, &p); 82 81 kernel_param_unlock(THIS_MODULE); 83 82 84 83 return 0;

+1 -3

drivers/gpu/drm/i915/i915_driver.c

··· 49 49 #include "display/intel_bw.h" 50 50 #include "display/intel_cdclk.h" 51 51 #include "display/intel_display_driver.h" 52 - #include "display/intel_display_types.h" 52 + #include "display/intel_display.h" 53 53 #include "display/intel_dmc.h" 54 54 #include "display/intel_dp.h" 55 55 #include "display/intel_dpt.h" ··· 58 58 #include "display/intel_hotplug.h" 59 59 #include "display/intel_overlay.h" 60 60 #include "display/intel_pch_refclk.h" 61 - #include "display/intel_pipe_crc.h" 62 61 #include "display/intel_pps.h" 63 62 #include "display/intel_sprite.h" 64 - #include "display/intel_vga.h" 65 63 #include "display/skl_watermark.h" 66 64 67 65 #include "gem/i915_gem_context.h"

+2 -10

drivers/gpu/drm/i915/i915_drv.h

··· 408 408 409 409 #define INTEL_REVID(i915) (to_pci_dev((i915)->drm.dev)->revision) 410 410 411 - #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step) 412 411 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step) 413 412 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step) 414 - #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step) 415 - 416 - #define IS_DISPLAY_STEP(__i915, since, until) \ 417 - (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \ 418 - INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until)) 419 413 420 414 #define IS_GRAPHICS_STEP(__i915, since, until) \ 421 415 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \ ··· 418 424 #define IS_MEDIA_STEP(__i915, since, until) \ 419 425 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \ 420 426 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until)) 421 - 422 - #define IS_BASEDIE_STEP(__i915, since, until) \ 423 - (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \ 424 - INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until)) 425 427 426 428 static __always_inline unsigned int 427 429 __platform_mask_index(const struct intel_runtime_info *info, ··· 536 546 #define IS_LUNARLAKE(i915) (0 && i915) 537 547 #define IS_BATTLEMAGE(i915) (0 && i915) 538 548 549 + #define IS_ARROWLAKE(i915) \ 550 + IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_ARL) 539 551 #define IS_DG2_G10(i915) \ 540 552 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) 541 553 #define IS_DG2_G11(i915) \

-2

drivers/gpu/drm/i915/i915_gem.c

··· 39 39 #include <drm/drm_cache.h> 40 40 #include <drm/drm_vma_manager.h> 41 41 42 - #include "display/intel_display.h" 43 - 44 42 #include "gem/i915_gem_clflush.h" 45 43 #include "gem/i915_gem_context.h" 46 44 #include "gem/i915_gem_ioctls.h"

-1

drivers/gpu/drm/i915/i915_gem_gtt.c

··· 15 15 #include <asm/set_memory.h> 16 16 #include <asm/smp.h> 17 17 18 - #include "display/intel_frontbuffer.h" 19 18 #include "gt/intel_gt.h" 20 19 #include "gt/intel_gt_requests.h" 21 20

+2 -1

drivers/gpu/drm/i915/i915_gpu_error.c

··· 660 660 const struct i915_params *params) 661 661 { 662 662 struct drm_printer p = i915_error_printer(m); 663 + struct intel_display *display = &m->i915->display; 663 664 664 665 i915_params_dump(params, &p); 665 - intel_display_params_dump(m->i915, &p); 666 + intel_display_params_dump(display, &p); 666 667 } 667 668 668 669 static void err_print_pciid(struct drm_i915_error_state_buf *m,

-1

drivers/gpu/drm/i915/i915_irq.c

··· 34 34 #include <drm/drm_drv.h> 35 35 36 36 #include "display/intel_display_irq.h" 37 - #include "display/intel_display_types.h" 38 37 #include "display/intel_hotplug.h" 39 38 #include "display/intel_hotplug_irq.h" 40 39 #include "display/intel_lpe_audio.h"

-1

drivers/gpu/drm/i915/i915_pci.c

··· 26 26 #include <drm/drm_drv.h> 27 27 #include <drm/intel/i915_pciids.h> 28 28 29 - #include "display/intel_display.h" 30 29 #include "display/intel_display_driver.h" 31 30 #include "gt/intel_gt_regs.h" 32 31 #include "gt/intel_sa_media.h"

+4

drivers/gpu/drm/i915/i915_reg.h

··· 2516 2516 #define GEN11_PIPE_PLANE7_FLIP_DONE REG_BIT(18) /* icl/tgl */ 2517 2517 #define GEN11_PIPE_PLANE6_FLIP_DONE REG_BIT(17) /* icl/tgl */ 2518 2518 #define GEN11_PIPE_PLANE5_FLIP_DONE REG_BIT(16) /* icl+ */ 2519 + #define GEN12_DSB_2_INT REG_BIT(15) /* tgl+ */ 2520 + #define GEN12_DSB_1_INT REG_BIT(14) /* tgl+ */ 2521 + #define GEN12_DSB_0_INT REG_BIT(13) /* tgl+ */ 2522 + #define GEN12_DSB_INT(dsb_id) REG_BIT(13 + (dsb_id)) 2519 2523 #define GEN9_PIPE_CURSOR_FAULT REG_BIT(11) /* skl+ */ 2520 2524 #define GEN9_PIPE_PLANE4_FAULT REG_BIT(10) /* skl+ */ 2521 2525 #define GEN8_PIPE_CURSOR_FAULT REG_BIT(10) /* bdw */

+7 -7

drivers/gpu/drm/i915/intel_device_info.c

··· 108 108 109 109 drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step)); 110 110 drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step)); 111 - drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step)); 112 - drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step)); 113 111 114 112 drm_printf(p, "gt: %d\n", info->gt); 115 113 drm_printf(p, "memory-regions: 0x%x\n", info->memory_regions); ··· 122 124 #undef PRINT_FLAG 123 125 124 126 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu)); 125 - drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); 126 127 } 127 128 128 129 #define ID(id) (id) ··· 200 203 INTEL_DG2_G12_IDS(ID), 201 204 }; 202 205 206 + static const u16 subplatform_arl_ids[] = { 207 + INTEL_ARL_IDS(ID), 208 + }; 209 + 203 210 static bool find_devid(u16 id, const u16 *p, unsigned int num) 204 211 { 205 212 for (; num; num--, p++) { ··· 261 260 } else if (find_devid(devid, subplatform_g12_ids, 262 261 ARRAY_SIZE(subplatform_g12_ids))) { 263 262 mask = BIT(INTEL_SUBPLATFORM_G12); 263 + } else if (find_devid(devid, subplatform_arl_ids, 264 + ARRAY_SIZE(subplatform_arl_ids))) { 265 + mask = BIT(INTEL_SUBPLATFORM_ARL); 264 266 } 265 267 266 268 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); ··· 374 370 "Disabling ppGTT for VT-d support\n"); 375 371 runtime->ppgtt_type = INTEL_PPGTT_NONE; 376 372 } 377 - 378 - runtime->rawclk_freq = intel_read_rawclk(dev_priv); 379 - drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq); 380 - 381 373 } 382 374 383 375 /*

+3 -2

drivers/gpu/drm/i915/intel_device_info.h

··· 127 127 #define INTEL_SUBPLATFORM_N 1 128 128 #define INTEL_SUBPLATFORM_RPLU 2 129 129 130 + /* MTL */ 131 + #define INTEL_SUBPLATFORM_ARL 0 132 + 130 133 enum intel_ppgtt_type { 131 134 INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE, 132 135 INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING, ··· 206 203 u32 platform_mask[2]; 207 204 208 205 u16 device_id; 209 - 210 - u32 rawclk_freq; 211 206 212 207 struct intel_step_info step; 213 208

+36 -48

drivers/gpu/drm/i915/intel_step.c

··· 23 23 * use a macro to define these to make it easier to identify the platforms 24 24 * where the two steppings can deviate. 25 25 */ 26 - #define COMMON_STEP(x) .graphics_step = STEP_##x, .display_step = STEP_##x, .media_step = STEP_##x 27 - #define COMMON_GT_MEDIA_STEP(x) .graphics_step = STEP_##x, .media_step = STEP_##x 26 + #define COMMON_STEP(x) .graphics_step = STEP_##x, .media_step = STEP_##x 28 27 29 28 static const struct intel_step_info skl_revids[] = { 30 29 [0x6] = { COMMON_STEP(G0) }, ··· 33 34 }; 34 35 35 36 static const struct intel_step_info kbl_revids[] = { 36 - [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 37 - [2] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 }, 38 - [3] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_B0 }, 39 - [4] = { COMMON_GT_MEDIA_STEP(F0), .display_step = STEP_C0 }, 40 - [5] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B1 }, 41 - [6] = { COMMON_GT_MEDIA_STEP(D1), .display_step = STEP_B1 }, 42 - [7] = { COMMON_GT_MEDIA_STEP(G0), .display_step = STEP_C0 }, 37 + [1] = { COMMON_STEP(B0) }, 38 + [2] = { COMMON_STEP(C0) }, 39 + [3] = { COMMON_STEP(D0) }, 40 + [4] = { COMMON_STEP(F0) }, 41 + [5] = { COMMON_STEP(C0) }, 42 + [6] = { COMMON_STEP(D1) }, 43 + [7] = { COMMON_STEP(G0) }, 43 44 }; 44 45 45 46 static const struct intel_step_info bxt_revids[] = { ··· 63 64 }; 64 65 65 66 static const struct intel_step_info tgl_uy_revids[] = { 66 - [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 67 - [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 }, 68 - [2] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 }, 69 - [3] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 }, 67 + [0] = { COMMON_STEP(A0) }, 68 + [1] = { COMMON_STEP(B0) }, 69 + [2] = { COMMON_STEP(B1) }, 70 + [3] = { COMMON_STEP(C0) }, 70 71 }; 71 72 72 73 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ 73 74 static const struct intel_step_info tgl_revids[] = { 74 - [0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 }, 75 - [1] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_D0 }, 75 + [0] = { COMMON_STEP(A0) }, 76 + [1] = { COMMON_STEP(B0) }, 76 77 }; 77 78 78 79 static const struct intel_step_info rkl_revids[] = { ··· 87 88 }; 88 89 89 90 static const struct intel_step_info adls_revids[] = { 90 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 91 - [0x1] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A2 }, 92 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 93 - [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_B0 }, 94 - [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 }, 91 + [0x0] = { COMMON_STEP(A0) }, 92 + [0x1] = { COMMON_STEP(A0) }, 93 + [0x4] = { COMMON_STEP(B0) }, 94 + [0x8] = { COMMON_STEP(C0) }, 95 + [0xC] = { COMMON_STEP(D0) }, 95 96 }; 96 97 97 98 static const struct intel_step_info adlp_revids[] = { 98 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 99 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 100 - [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 }, 101 - [0xC] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_D0 }, 99 + [0x0] = { COMMON_STEP(A0) }, 100 + [0x4] = { COMMON_STEP(B0) }, 101 + [0x8] = { COMMON_STEP(C0) }, 102 + [0xC] = { COMMON_STEP(C0) }, 102 103 }; 103 104 104 105 static const struct intel_step_info dg2_g10_revid_step_tbl[] = { 105 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_A0 }, 106 - [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_A0 }, 107 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_B0 }, 108 - [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_C0 }, 106 + [0x0] = { COMMON_STEP(A0) }, 107 + [0x1] = { COMMON_STEP(A1) }, 108 + [0x4] = { COMMON_STEP(B0) }, 109 + [0x8] = { COMMON_STEP(C0) }, 109 110 }; 110 111 111 112 static const struct intel_step_info dg2_g11_revid_step_tbl[] = { 112 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_B0 }, 113 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display_step = STEP_C0 }, 114 - [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display_step = STEP_C0 }, 113 + [0x0] = { COMMON_STEP(A0) }, 114 + [0x4] = { COMMON_STEP(B0) }, 115 + [0x5] = { COMMON_STEP(B1) }, 115 116 }; 116 117 117 118 static const struct intel_step_info dg2_g12_revid_step_tbl[] = { 118 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_C0 }, 119 - [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display_step = STEP_C0 }, 119 + [0x0] = { COMMON_STEP(A0) }, 120 + [0x1] = { COMMON_STEP(A1) }, 120 121 }; 121 122 122 123 static const struct intel_step_info adls_rpls_revids[] = { 123 - [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_D0 }, 124 - [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display_step = STEP_C0 }, 124 + [0x4] = { COMMON_STEP(D0) }, 125 + [0xC] = { COMMON_STEP(D0) }, 125 126 }; 126 127 127 128 static const struct intel_step_info adlp_rplp_revids[] = { 128 - [0x4] = { COMMON_GT_MEDIA_STEP(C0), .display_step = STEP_E0 }, 129 + [0x4] = { COMMON_STEP(C0) }, 129 130 }; 130 131 131 132 static const struct intel_step_info adlp_n_revids[] = { 132 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display_step = STEP_D0 }, 133 + [0x0] = { COMMON_STEP(A0) }, 133 134 }; 134 135 135 136 static u8 gmd_to_intel_step(struct drm_i915_private *i915, ··· 157 158 &RUNTIME_INFO(i915)->graphics.ip); 158 159 step.media_step = gmd_to_intel_step(i915, 159 160 &RUNTIME_INFO(i915)->media.ip); 160 - step.display_step = STEP_A0 + DISPLAY_RUNTIME_INFO(i915)->ip.step; 161 - if (step.display_step >= STEP_FUTURE) { 162 - drm_dbg(&i915->drm, "Using future display steppings\n"); 163 - step.display_step = STEP_FUTURE; 164 - } 165 161 166 162 RUNTIME_INFO(i915)->step = step; 167 163 ··· 246 252 } else { 247 253 drm_dbg(&i915->drm, "Using future steppings\n"); 248 254 step.graphics_step = STEP_FUTURE; 249 - step.display_step = STEP_FUTURE; 250 255 } 251 256 } 252 257 ··· 267 274 default: 268 275 return "**"; 269 276 } 270 - } 271 - 272 - const char *intel_display_step_name(struct drm_i915_private *i915) 273 - { 274 - return intel_step_name(RUNTIME_INFO(i915)->step.display_step); 275 277 }

-3

drivers/gpu/drm/i915/intel_step.h

··· 16 16 * the expectation breaks gmd_to_intel_step(). 17 17 */ 18 18 u8 graphics_step; /* Represents the compute tile on Xe_HPC */ 19 - u8 display_step; 20 19 u8 media_step; 21 - u8 basedie_step; 22 20 }; 23 21 24 22 #define STEP_ENUM_VAL(name) STEP_##name, ··· 76 78 77 79 void intel_step_init(struct drm_i915_private *i915); 78 80 const char *intel_step_name(enum intel_step step); 79 - const char *intel_display_step_name(struct drm_i915_private *i915); 80 81 81 82 #endif /* __INTEL_STEP_H__ */

-6

drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h

··· 80 80 81 81 #define IS_MOBILE(xe) (xe && 0) 82 82 83 - #define HAS_GMD_ID(xe) GRAPHICS_VERx100(xe) >= 1270 84 - 85 - /* Workarounds not handled yet */ 86 - #define IS_DISPLAY_STEP(xe, first, last) ({u8 __step = (xe)->info.step.display; first <= __step && __step <= last; }) 87 - 88 83 #define IS_LP(xe) (0) 89 84 #define IS_GEN9_LP(xe) (0) 90 85 #define IS_GEN9_BC(xe) (0) ··· 111 116 #define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0) 112 117 113 118 #define pdev_to_i915 pdev_to_xe_device 114 - #define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime) 115 119 116 120 #define FORCEWAKE_ALL XE_FORCEWAKE_ALL 117 121

+2 -8

drivers/gpu/drm/xe/compat-i915-headers/intel_step.h

··· 6 6 #ifndef __INTEL_STEP_H__ 7 7 #define __INTEL_STEP_H__ 8 8 9 - #include "xe_device_types.h" 10 9 #include "xe_step.h" 11 10 12 - #define intel_display_step_name xe_display_step_name 13 - 14 - static inline 15 - const char *xe_display_step_name(struct xe_device *xe) 16 - { 17 - return xe_step_name(xe->info.step.display); 18 - } 11 + #define intel_step xe_step 12 + #define intel_step_name xe_step_name 19 13 20 14 #endif /* __INTEL_STEP_H__ */

+9

drivers/gpu/drm/xe/display/intel_fb_bo.c

··· 7 7 #include <drm/ttm/ttm_bo.h> 8 8 9 9 #include "intel_display_types.h" 10 + #include "intel_fb.h" 10 11 #include "intel_fb_bo.h" 11 12 #include "xe_bo.h" 12 13 ··· 28 27 { 29 28 struct xe_device *xe = to_xe_device(bo->ttm.base.dev); 30 29 int ret; 30 + 31 + /* 32 + * Some modifiers require physical alignment of 64KiB VRAM pages; 33 + * require that the BO in those cases is created correctly. 34 + */ 35 + if (XE_IOCTL_DBG(xe, intel_fb_needs_64k_phys(mode_cmd->modifier[0]) && 36 + !(bo->flags & XE_BO_FLAG_NEEDS_64K))) 37 + return -EINVAL; 31 38 32 39 xe_bo_get(bo); 33 40

+7

drivers/gpu/drm/xe/xe_bo.c

··· 1997 1997 1998 1998 bo_flags |= args->placement << (ffs(XE_BO_FLAG_SYSTEM) - 1); 1999 1999 2000 + /* CCS formats need physical placement at a 64K alignment in VRAM. */ 2001 + if ((bo_flags & XE_BO_FLAG_VRAM_MASK) && 2002 + (bo_flags & XE_BO_FLAG_SCANOUT) && 2003 + !(xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K) && 2004 + IS_ALIGNED(args->size, SZ_64K)) 2005 + bo_flags |= XE_BO_FLAG_NEEDS_64K; 2006 + 2000 2007 if (args->flags & DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM) { 2001 2008 if (XE_IOCTL_DBG(xe, !(bo_flags & XE_BO_FLAG_VRAM_MASK))) 2002 2009 return -EINVAL;

+1 -2

drivers/gpu/drm/xe/xe_debugfs.c

··· 47 47 48 48 drm_printf(&p, "graphics_verx100 %d\n", xe->info.graphics_verx100); 49 49 drm_printf(&p, "media_verx100 %d\n", xe->info.media_verx100); 50 - drm_printf(&p, "stepping G:%s M:%s D:%s B:%s\n", 50 + drm_printf(&p, "stepping G:%s M:%s B:%s\n", 51 51 xe_step_name(xe->info.step.graphics), 52 52 xe_step_name(xe->info.step.media), 53 - xe_step_name(xe->info.step.display), 54 53 xe_step_name(xe->info.step.basedie)); 55 54 drm_printf(&p, "is_dgfx %s\n", str_yes_no(xe->info.is_dgfx)); 56 55 drm_printf(&p, "platform %d\n", xe->info.platform);

-6

drivers/gpu/drm/xe/xe_device_types.h

··· 305 305 u8 has_atomic_enable_pte_bit:1; 306 306 /** @info.has_device_atomics_on_smem: Supports device atomics on SMEM */ 307 307 u8 has_device_atomics_on_smem:1; 308 - 309 - #if IS_ENABLED(CONFIG_DRM_XE_DISPLAY) 310 - struct { 311 - u32 rawclk_freq; 312 - } i915_runtime; 313 - #endif 314 308 } info; 315 309 316 310 /** @irq: device interrupt state */

+1 -2

drivers/gpu/drm/xe/xe_pci.c

··· 831 831 xe->info.dma_mask_size, xe->info.tile_count, 832 832 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi); 833 833 834 - drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, D:%s, B:%s)\n", 834 + drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n", 835 835 xe_step_name(xe->info.step.graphics), 836 836 xe_step_name(xe->info.step.media), 837 - xe_step_name(xe->info.step.display), 838 837 xe_step_name(xe->info.step.basedie)); 839 838 840 839 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",

+25 -32

drivers/gpu/drm/xe/xe_step.c

··· 28 28 * use a macro to define these to make it easier to identify the platforms 29 29 * where the two steppings can deviate. 30 30 */ 31 - #define COMMON_GT_MEDIA_STEP(x_) \ 31 + #define COMMON_STEP(x_) \ 32 32 .graphics = STEP_##x_, \ 33 33 .media = STEP_##x_ 34 - 35 - #define COMMON_STEP(x_) \ 36 - COMMON_GT_MEDIA_STEP(x_), \ 37 - .graphics = STEP_##x_, \ 38 - .media = STEP_##x_, \ 39 - .display = STEP_##x_ 40 34 41 35 __diag_push(); 42 36 __diag_ignore_all("-Woverride-init", "Allow field overrides in table"); 43 37 44 38 /* Same GT stepping between tgl_uy_revids and tgl_revids don't mean the same HW */ 45 39 static const struct xe_step_info tgl_revids[] = { 46 - [0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_B0 }, 47 - [1] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_D0 }, 40 + [0] = { COMMON_STEP(A0) }, 41 + [1] = { COMMON_STEP(B0) }, 48 42 }; 49 43 50 44 static const struct xe_step_info dg1_revids[] = { ··· 47 53 }; 48 54 49 55 static const struct xe_step_info adls_revids[] = { 50 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 }, 51 - [0x1] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A2 }, 52 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 }, 53 - [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_B0 }, 54 - [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 }, 56 + [0x0] = { COMMON_STEP(A0) }, 57 + [0x1] = { COMMON_STEP(A0) }, 58 + [0x4] = { COMMON_STEP(B0) }, 59 + [0x8] = { COMMON_STEP(C0) }, 60 + [0xC] = { COMMON_STEP(D0) }, 55 61 }; 56 62 57 63 static const struct xe_step_info adls_rpls_revids[] = { 58 - [0x4] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_D0 }, 59 - [0xC] = { COMMON_GT_MEDIA_STEP(D0), .display = STEP_C0 }, 64 + [0x4] = { COMMON_STEP(D0) }, 65 + [0xC] = { COMMON_STEP(D0) }, 60 66 }; 61 67 62 68 static const struct xe_step_info adlp_revids[] = { 63 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 }, 64 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 }, 65 - [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_C0 }, 66 - [0xC] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_D0 }, 69 + [0x0] = { COMMON_STEP(A0) }, 70 + [0x4] = { COMMON_STEP(B0) }, 71 + [0x8] = { COMMON_STEP(C0) }, 72 + [0xC] = { COMMON_STEP(C0) }, 67 73 }; 68 74 69 75 static const struct xe_step_info adlp_rpl_revids[] = { 70 - [0x4] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_E0 }, 76 + [0x4] = { COMMON_STEP(C0) }, 71 77 }; 72 78 73 79 static const struct xe_step_info adln_revids[] = { 74 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_D0 }, 80 + [0x0] = { COMMON_STEP(A0) }, 75 81 }; 76 82 77 83 static const struct xe_step_info dg2_g10_revid_step_tbl[] = { 78 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_A0 }, 79 - [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display = STEP_A0 }, 80 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_B0 }, 81 - [0x8] = { COMMON_GT_MEDIA_STEP(C0), .display = STEP_C0 }, 84 + [0x0] = { COMMON_STEP(A0) }, 85 + [0x1] = { COMMON_STEP(A1) }, 86 + [0x4] = { COMMON_STEP(B0) }, 87 + [0x8] = { COMMON_STEP(C0) }, 82 88 }; 83 89 84 90 static const struct xe_step_info dg2_g11_revid_step_tbl[] = { 85 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_B0 }, 86 - [0x4] = { COMMON_GT_MEDIA_STEP(B0), .display = STEP_C0 }, 87 - [0x5] = { COMMON_GT_MEDIA_STEP(B1), .display = STEP_C0 }, 91 + [0x0] = { COMMON_STEP(A0) }, 92 + [0x4] = { COMMON_STEP(B0) }, 93 + [0x5] = { COMMON_STEP(B1) }, 88 94 }; 89 95 90 96 static const struct xe_step_info dg2_g12_revid_step_tbl[] = { 91 - [0x0] = { COMMON_GT_MEDIA_STEP(A0), .display = STEP_C0 }, 92 - [0x1] = { COMMON_GT_MEDIA_STEP(A1), .display = STEP_C0 }, 97 + [0x0] = { COMMON_STEP(A0) }, 98 + [0x1] = { COMMON_STEP(A1) }, 93 99 }; 94 100 95 101 static const struct xe_step_info pvc_revid_step_tbl[] = { ··· 189 195 } else { 190 196 drm_dbg(&xe->drm, "Using future steppings\n"); 191 197 step.graphics = STEP_FUTURE; 192 - step.display = STEP_FUTURE; 193 198 } 194 199 } 195 200

+28 -2

drivers/gpu/drm/xe/xe_step_types.h

··· 11 11 struct xe_step_info { 12 12 u8 graphics; 13 13 u8 media; 14 - u8 display; 15 14 u8 basedie; 16 15 }; 17 16 18 17 #define STEP_ENUM_VAL(name) STEP_##name, 19 18 19 + /* 20 + * Always define four minor steppings 0-3 for each stepping to match GMD ID 21 + * spacing of values. See xe_step_gmdid_get(). 22 + */ 20 23 #define STEP_NAME_LIST(func) \ 21 24 func(A0) \ 22 25 func(A1) \ ··· 37 34 func(D1) \ 38 35 func(D2) \ 39 36 func(D3) \ 40 - func(E0) 37 + func(E0) \ 38 + func(E1) \ 39 + func(E2) \ 40 + func(E3) \ 41 + func(F0) \ 42 + func(F1) \ 43 + func(F2) \ 44 + func(F3) \ 45 + func(G0) \ 46 + func(G1) \ 47 + func(G2) \ 48 + func(G3) \ 49 + func(H0) \ 50 + func(H1) \ 51 + func(H2) \ 52 + func(H3) \ 53 + func(I0) \ 54 + func(I1) \ 55 + func(I2) \ 56 + func(I3) \ 57 + func(J0) \ 58 + func(J1) \ 59 + func(J2) \ 60 + func(J3) 41 61 42 62 /* 43 63 * Symbolic steppings that do not match the hardware. These are valid both as gt

+10 -1

drivers/gpu/drm/xe/xe_vm.c

··· 2878 2878 return -EINVAL; 2879 2879 } 2880 2880 2881 - if (bo->flags & XE_BO_FLAG_INTERNAL_64K) { 2881 + /* 2882 + * Some platforms require 64k VM_BIND alignment, 2883 + * specifically those with XE_VRAM_FLAGS_NEED64K. 2884 + * 2885 + * Other platforms may have BO's set to 64k physical placement, 2886 + * but can be mapped at 4k offsets anyway. This check is only 2887 + * there for the former case. 2888 + */ 2889 + if ((bo->flags & XE_BO_FLAG_INTERNAL_64K) && 2890 + (xe->info.vram_flags & XE_VRAM_FLAGS_NEED64K)) { 2882 2891 if (XE_IOCTL_DBG(xe, obj_offset & 2883 2892 XE_64K_PAGE_MASK) || 2884 2893 XE_IOCTL_DBG(xe, addr & XE_64K_PAGE_MASK) ||

+8 -5

include/drm/intel/i915_pciids.h

··· 772 772 INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) 773 773 774 774 /* MTL */ 775 - #define INTEL_MTL_IDS(MACRO__, ...) \ 776 - MACRO__(0x7D40, ## __VA_ARGS__), \ 775 + #define INTEL_ARL_IDS(MACRO__, ...) \ 777 776 MACRO__(0x7D41, ## __VA_ARGS__), \ 778 - MACRO__(0x7D45, ## __VA_ARGS__), \ 779 777 MACRO__(0x7D51, ## __VA_ARGS__), \ 778 + MACRO__(0x7D67, ## __VA_ARGS__), \ 779 + MACRO__(0x7DD1, ## __VA_ARGS__) 780 + 781 + #define INTEL_MTL_IDS(MACRO__, ...) \ 782 + INTEL_ARL_IDS(MACRO__, ## __VA_ARGS__), \ 783 + MACRO__(0x7D40, ## __VA_ARGS__), \ 784 + MACRO__(0x7D45, ## __VA_ARGS__), \ 780 785 MACRO__(0x7D55, ## __VA_ARGS__), \ 781 786 MACRO__(0x7D60, ## __VA_ARGS__), \ 782 - MACRO__(0x7D67, ## __VA_ARGS__), \ 783 - MACRO__(0x7DD1, ## __VA_ARGS__), \ 784 787 MACRO__(0x7DD5, ## __VA_ARGS__) 785 788 786 789 /* LNL */

+25

include/uapi/drm/drm_fourcc.h

··· 703 703 #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15) 704 704 705 705 /* 706 + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 707 + * on integrated graphics 708 + * 709 + * The main surface is Tile 4 and at plane index 0. For semi-planar formats 710 + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 711 + * 0 and 1, respectively. The CCS for all planes are stored outside of the 712 + * GEM object in a reserved memory area dedicated for the storage of the 713 + * CCS data for all compressible GEM objects. 714 + */ 715 + #define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16) 716 + 717 + /* 718 + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression 719 + * on discrete graphics 720 + * 721 + * The main surface is Tile 4 and at plane index 0. For semi-planar formats 722 + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices 723 + * 0 and 1, respectively. The CCS for all planes are stored outside of the 724 + * GEM object in a reserved memory area dedicated for the storage of the 725 + * CCS data for all compressible GEM objects. The GEM object must be stored in 726 + * contiguous memory with a size aligned to 64KB 727 + */ 728 + #define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17) 729 + 730 + /* 706 731 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks 707 732 * 708 733 * Macroblocks are laid in a Z-shape, and each pixel data is following the

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