Merge tag 'drm-fixes-2020-01-10' of git://anongit.freedesktop.org/drm/drm

+4 -3

drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

··· 142 142 int amdgpu_mcbp = 0; 143 143 int amdgpu_discovery = -1; 144 144 int amdgpu_mes = 0; 145 - int amdgpu_noretry = 1; 145 + int amdgpu_noretry; 146 146 int amdgpu_force_asic_type = -1; 147 147 148 148 struct amdgpu_mgpu_info mgpu_info = { ··· 588 588 module_param_named(mes, amdgpu_mes, int, 0444); 589 589 590 590 MODULE_PARM_DESC(noretry, 591 - "Disable retry faults (0 = retry enabled, 1 = retry disabled (default))"); 591 + "Disable retry faults (0 = retry enabled (default), 1 = retry disabled)"); 592 592 module_param_named(noretry, amdgpu_noretry, int, 0644); 593 593 594 594 /** ··· 1359 1359 .driver_features = 1360 1360 DRIVER_USE_AGP | DRIVER_ATOMIC | 1361 1361 DRIVER_GEM | 1362 - DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ, 1362 + DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | 1363 + DRIVER_SYNCOBJ_TIMELINE, 1363 1364 .load = amdgpu_driver_load_kms, 1364 1365 .open = amdgpu_driver_open_kms, 1365 1366 .postclose = amdgpu_driver_postclose_kms,

+23 -22

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 3356 3356 return color_space; 3357 3357 } 3358 3358 3359 - static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out) 3359 + static bool adjust_colour_depth_from_display_info( 3360 + struct dc_crtc_timing *timing_out, 3361 + const struct drm_display_info *info) 3360 3362 { 3361 - if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3362 - return; 3363 - 3364 - timing_out->display_color_depth--; 3365 - } 3366 - 3367 - static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out, 3368 - const struct drm_display_info *info) 3369 - { 3363 + enum dc_color_depth depth = timing_out->display_color_depth; 3370 3364 int normalized_clk; 3371 - if (timing_out->display_color_depth <= COLOR_DEPTH_888) 3372 - return; 3373 3365 do { 3374 3366 normalized_clk = timing_out->pix_clk_100hz / 10; 3375 3367 /* YCbCr 4:2:0 requires additional adjustment of 1/2 */ 3376 3368 if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420) 3377 3369 normalized_clk /= 2; 3378 3370 /* Adjusting pix clock following on HDMI spec based on colour depth */ 3379 - switch (timing_out->display_color_depth) { 3371 + switch (depth) { 3372 + case COLOR_DEPTH_888: 3373 + break; 3380 3374 case COLOR_DEPTH_101010: 3381 3375 normalized_clk = (normalized_clk * 30) / 24; 3382 3376 break; ··· 3381 3387 normalized_clk = (normalized_clk * 48) / 24; 3382 3388 break; 3383 3389 default: 3384 - return; 3390 + /* The above depths are the only ones valid for HDMI. */ 3391 + return false; 3385 3392 } 3386 - if (normalized_clk <= info->max_tmds_clock) 3387 - return; 3388 - reduce_mode_colour_depth(timing_out); 3389 - 3390 - } while (timing_out->display_color_depth > COLOR_DEPTH_888); 3391 - 3393 + if (normalized_clk <= info->max_tmds_clock) { 3394 + timing_out->display_color_depth = depth; 3395 + return true; 3396 + } 3397 + } while (--depth > COLOR_DEPTH_666); 3398 + return false; 3392 3399 } 3393 3400 3394 3401 static void fill_stream_properties_from_drm_display_mode( ··· 3469 3474 3470 3475 stream->out_transfer_func->type = TF_TYPE_PREDEFINED; 3471 3476 stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; 3472 - if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) 3473 - adjust_colour_depth_from_display_info(timing_out, info); 3477 + if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { 3478 + if (!adjust_colour_depth_from_display_info(timing_out, info) && 3479 + drm_mode_is_420_also(info, mode_in) && 3480 + timing_out->pixel_encoding != PIXEL_ENCODING_YCBCR420) { 3481 + timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420; 3482 + adjust_colour_depth_from_display_info(timing_out, info); 3483 + } 3484 + } 3474 3485 } 3475 3486 3476 3487 static void fill_audio_info(struct audio_info *audio_info,

+1 -1

drivers/gpu/drm/drm_dp_mst_topology.c

··· 393 393 memcpy(&buf[idx], req->u.i2c_read.transactions[i].bytes, req->u.i2c_read.transactions[i].num_bytes); 394 394 idx += req->u.i2c_read.transactions[i].num_bytes; 395 395 396 - buf[idx] = (req->u.i2c_read.transactions[i].no_stop_bit & 0x1) << 5; 396 + buf[idx] = (req->u.i2c_read.transactions[i].no_stop_bit & 0x1) << 4; 397 397 buf[idx] |= (req->u.i2c_read.transactions[i].i2c_transaction_delay & 0xf); 398 398 idx++; 399 399 }

+6 -1

drivers/gpu/drm/drm_fb_helper.c

··· 1283 1283 * Changes struct fb_var_screeninfo are currently not pushed back 1284 1284 * to KMS, hence fail if different settings are requested. 1285 1285 */ 1286 - if (var->bits_per_pixel != fb->format->cpp[0] * 8 || 1286 + if (var->bits_per_pixel > fb->format->cpp[0] * 8 || 1287 1287 var->xres > fb->width || var->yres > fb->height || 1288 1288 var->xres_virtual > fb->width || var->yres_virtual > fb->height) { 1289 1289 DRM_DEBUG("fb requested width/height/bpp can't fit in current fb " ··· 1307 1307 !var->blue.msb_right && !var->transp.msb_right) { 1308 1308 drm_fb_helper_fill_pixel_fmt(var, fb->format->depth); 1309 1309 } 1310 + 1311 + /* 1312 + * Likewise, bits_per_pixel should be rounded up to a supported value. 1313 + */ 1314 + var->bits_per_pixel = fb->format->cpp[0] * 8; 1310 1315 1311 1316 /* 1312 1317 * drm fbdev emulation doesn't support changing the pixel format at all,

+2 -2

drivers/gpu/drm/i915/display/intel_audio.c

··· 856 856 } 857 857 858 858 /* Force CDCLK to 2*BCLK as long as we need audio powered. */ 859 - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 859 + if (IS_GEMINILAKE(dev_priv)) 860 860 glk_force_audio_cdclk(dev_priv, true); 861 861 862 862 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) ··· 875 875 876 876 /* Stop forcing CDCLK to 2*BCLK if no need for audio to be powered. */ 877 877 if (--dev_priv->audio_power_refcount == 0) 878 - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 878 + if (IS_GEMINILAKE(dev_priv)) 879 879 glk_force_audio_cdclk(dev_priv, false); 880 880 881 881 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO, cookie);

+1 -6

drivers/gpu/drm/i915/display/intel_display.c

··· 4515 4515 { 4516 4516 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 4517 4517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 4518 - i915_reg_t reg; 4519 - u32 trans_ddi_func_ctl2_val; 4520 4518 4521 4519 if (old_crtc_state->master_transcoder == INVALID_TRANSCODER) 4522 4520 return; ··· 4522 4524 DRM_DEBUG_KMS("Disabling Transcoder Port Sync on Slave Transcoder %s\n", 4523 4525 transcoder_name(old_crtc_state->cpu_transcoder)); 4524 4526 4525 - reg = TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder); 4526 - trans_ddi_func_ctl2_val = ~(PORT_SYNC_MODE_ENABLE | 4527 - PORT_SYNC_MODE_MASTER_SELECT_MASK); 4528 - I915_WRITE(reg, trans_ddi_func_ctl2_val); 4527 + I915_WRITE(TRANS_DDI_FUNC_CTL2(old_crtc_state->cpu_transcoder), 0); 4529 4528 } 4530 4529 4531 4530 static void intel_fdi_normal_train(struct intel_crtc *crtc)

+2

drivers/gpu/drm/i915/gt/intel_lrc.c

··· 4416 4416 ve->base.gt = siblings[0]->gt; 4417 4417 ve->base.uncore = siblings[0]->uncore; 4418 4418 ve->base.id = -1; 4419 + 4419 4420 ve->base.class = OTHER_CLASS; 4420 4421 ve->base.uabi_class = I915_ENGINE_CLASS_INVALID; 4421 4422 ve->base.instance = I915_ENGINE_CLASS_INVALID_VIRTUAL; 4423 + ve->base.uabi_instance = I915_ENGINE_CLASS_INVALID_VIRTUAL; 4422 4424 4423 4425 /* 4424 4426 * The decision on whether to submit a request using semaphores

+11 -20

drivers/gpu/drm/i915/gt/intel_ring_submission.c

··· 1413 1413 int len; 1414 1414 u32 *cs; 1415 1415 1416 - flags |= MI_MM_SPACE_GTT; 1417 - if (IS_HASWELL(i915)) 1418 - /* These flags are for resource streamer on HSW+ */ 1419 - flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN; 1420 - else 1421 - /* We need to save the extended state for powersaving modes */ 1422 - flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN; 1423 - 1424 1416 len = 4; 1425 1417 if (IS_GEN(i915, 7)) 1426 1418 len += 2 + (num_engines ? 4 * num_engines + 6 : 0); ··· 1581 1589 } 1582 1590 1583 1591 if (ce->state) { 1584 - u32 hw_flags; 1592 + u32 flags; 1585 1593 1586 1594 GEM_BUG_ON(rq->engine->id != RCS0); 1587 1595 1588 - /* 1589 - * The kernel context(s) is treated as pure scratch and is not 1590 - * expected to retain any state (as we sacrifice it during 1591 - * suspend and on resume it may be corrupted). This is ok, 1592 - * as nothing actually executes using the kernel context; it 1593 - * is purely used for flushing user contexts. 1594 - */ 1595 - hw_flags = 0; 1596 - if (i915_gem_context_is_kernel(rq->gem_context)) 1597 - hw_flags = MI_RESTORE_INHIBIT; 1596 + /* For resource streamer on HSW+ and power context elsewhere */ 1597 + BUILD_BUG_ON(HSW_MI_RS_SAVE_STATE_EN != MI_SAVE_EXT_STATE_EN); 1598 + BUILD_BUG_ON(HSW_MI_RS_RESTORE_STATE_EN != MI_RESTORE_EXT_STATE_EN); 1598 1599 1599 - ret = mi_set_context(rq, hw_flags); 1600 + flags = MI_SAVE_EXT_STATE_EN | MI_MM_SPACE_GTT; 1601 + if (!i915_gem_context_is_kernel(rq->gem_context)) 1602 + flags |= MI_RESTORE_EXT_STATE_EN; 1603 + else 1604 + flags |= MI_RESTORE_INHIBIT; 1605 + 1606 + ret = mi_set_context(rq, flags); 1600 1607 if (ret) 1601 1608 return ret; 1602 1609 }

+4 -2

drivers/gpu/drm/i915/i915_drv.h

··· 1660 1660 (IS_BROADWELL(dev_priv) || IS_GEN(dev_priv, 9)) 1661 1661 1662 1662 /* WaRsDisableCoarsePowerGating:skl,cnl */ 1663 - #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1664 - (IS_CANNONLAKE(dev_priv) || IS_GEN(dev_priv, 9)) 1663 + #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ 1664 + (IS_CANNONLAKE(dev_priv) || \ 1665 + IS_SKL_GT3(dev_priv) || \ 1666 + IS_SKL_GT4(dev_priv)) 1665 1667 1666 1668 #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) 1667 1669 #define HAS_GMBUS_BURST_READ(dev_priv) (INTEL_GEN(dev_priv) >= 10 || \

+7 -1

drivers/gpu/drm/i915/i915_reg.h

··· 4177 4177 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 4178 4178 4179 4179 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) 4180 - #define VFUNIT_CLKGATE_DIS (1 << 20) 4180 + #define VFUNIT_CLKGATE_DIS REG_BIT(20) 4181 + #define HSUNIT_CLKGATE_DIS REG_BIT(8) 4182 + #define VSUNIT_CLKGATE_DIS REG_BIT(3) 4183 + 4184 + #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) 4185 + #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19) 4186 + #define PSDUNIT_CLKGATE_DIS REG_BIT(5) 4181 4187 4182 4188 #define INF_UNIT_LEVEL_CLKGATE _MMIO(0x9560) 4183 4189 #define CGPSF_CLKGATE_DIS (1 << 3)

+11

drivers/gpu/drm/i915/intel_pm.c

··· 6565 6565 /* WaEnable32PlaneMode:icl */ 6566 6566 I915_WRITE(GEN9_CSFE_CHICKEN1_RCS, 6567 6567 _MASKED_BIT_ENABLE(GEN11_ENABLE_32_PLANE_MODE)); 6568 + 6569 + /* 6570 + * Wa_1408615072:icl,ehl (vsunit) 6571 + * Wa_1407596294:icl,ehl (hsunit) 6572 + */ 6573 + intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE, 6574 + 0, VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); 6575 + 6576 + /* Wa_1407352427:icl,ehl */ 6577 + intel_uncore_rmw(&dev_priv->uncore, UNSLICE_UNIT_LEVEL_CLKGATE2, 6578 + 0, PSDUNIT_CLKGATE_DIS); 6568 6579 } 6569 6580 6570 6581 static void tgl_init_clock_gating(struct drm_i915_private *dev_priv)

+12 -3

drivers/gpu/drm/sun4i/sun4i_tcon.c

··· 489 489 490 490 WARN_ON(!tcon->quirks->has_channel_0); 491 491 492 - tcon->dclk_min_div = 1; 492 + tcon->dclk_min_div = tcon->quirks->dclk_min_div; 493 493 tcon->dclk_max_div = 127; 494 494 sun4i_tcon0_mode_set_common(tcon, mode); 495 495 ··· 1426 1426 static const struct sun4i_tcon_quirks sun4i_a10_quirks = { 1427 1427 .has_channel_0 = true, 1428 1428 .has_channel_1 = true, 1429 + .dclk_min_div = 4, 1429 1430 .set_mux = sun4i_a10_tcon_set_mux, 1430 1431 }; 1431 1432 1432 1433 static const struct sun4i_tcon_quirks sun5i_a13_quirks = { 1433 1434 .has_channel_0 = true, 1434 1435 .has_channel_1 = true, 1436 + .dclk_min_div = 4, 1435 1437 .set_mux = sun5i_a13_tcon_set_mux, 1436 1438 }; 1437 1439 ··· 1442 1440 .has_channel_1 = true, 1443 1441 .has_lvds_alt = true, 1444 1442 .needs_de_be_mux = true, 1443 + .dclk_min_div = 1, 1445 1444 .set_mux = sun6i_tcon_set_mux, 1446 1445 }; 1447 1446 ··· 1450 1447 .has_channel_0 = true, 1451 1448 .has_channel_1 = true, 1452 1449 .needs_de_be_mux = true, 1450 + .dclk_min_div = 1, 1453 1451 }; 1454 1452 1455 1453 static const struct sun4i_tcon_quirks sun7i_a20_quirks = { 1456 1454 .has_channel_0 = true, 1457 1455 .has_channel_1 = true, 1456 + .dclk_min_div = 4, 1458 1457 /* Same display pipeline structure as A10 */ 1459 1458 .set_mux = sun4i_a10_tcon_set_mux, 1460 1459 }; ··· 1464 1459 static const struct sun4i_tcon_quirks sun8i_a33_quirks = { 1465 1460 .has_channel_0 = true, 1466 1461 .has_lvds_alt = true, 1462 + .dclk_min_div = 1, 1467 1463 }; 1468 1464 1469 1465 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { 1470 1466 .supports_lvds = true, 1471 1467 .has_channel_0 = true, 1468 + .dclk_min_div = 1, 1472 1469 }; 1473 1470 1474 1471 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { ··· 1484 1477 1485 1478 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = { 1486 1479 .has_channel_0 = true, 1480 + .dclk_min_div = 1, 1487 1481 }; 1488 1482 1489 1483 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = { 1490 - .has_channel_0 = true, 1491 - .needs_edp_reset = true, 1484 + .has_channel_0 = true, 1485 + .needs_edp_reset = true, 1486 + .dclk_min_div = 1, 1492 1487 }; 1493 1488 1494 1489 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = {

+1

drivers/gpu/drm/sun4i/sun4i_tcon.h

··· 224 224 bool needs_de_be_mux; /* sun6i needs mux to select backend */ 225 225 bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */ 226 226 bool supports_lvds; /* Does the TCON support an LVDS output? */ 227 + u8 dclk_min_div; /* minimum divider for TCON0 DCLK */ 227 228 228 229 /* callback to handle tcon muxing options */ 229 230 int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);

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