tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'ata-6.2-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata

Pull ata fixes from Damien Le Moal:
"Three small fixes for 6.2 final:

- Disable READ LOG DMA EXT for Samsung MZ7LH drives as these drives
choke on that command, from Patrick.

- Add Intel Tiger Lake UP{3,4} to the list of supported AHCI
controllers (this is not technically a bug fix, but it is trivial
enough that I add it here), from Simon.

- Fix code comments in the pata_octeon_cf driver as incorrect
formatting was causing warnings from kernel-doc, from Randy"

* tag 'ata-6.2-rc8' of git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata:
ata: pata_octeon_cf: drop kernel-doc notation
ata: ahci: Add Tiger Lake UP{3,4} AHCI controller
ata: libata-core: Disable READ LOG DMA EXT for Samsung MZ7LH

Linus Torvalds 6d2e62e1 bda6cfae

+12 -8
+1
drivers/ata/ahci.c
··· 421 421 { PCI_VDEVICE(INTEL, 0x34d3), board_ahci_low_power }, /* Ice Lake LP AHCI */ 422 422 { PCI_VDEVICE(INTEL, 0x02d3), board_ahci_low_power }, /* Comet Lake PCH-U AHCI */ 423 423 { PCI_VDEVICE(INTEL, 0x02d7), board_ahci_low_power }, /* Comet Lake PCH RAID */ 424 + { PCI_VDEVICE(INTEL, 0xa0d3), board_ahci_low_power }, /* Tiger Lake UP{3,4} AHCI */ 424 425 425 426 /* JMicron 360/1/3/5/6, match class to avoid IDE function */ 426 427 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
+3
drivers/ata/libata-core.c
··· 4045 4045 { "Samsung SSD 870*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | 4046 4046 ATA_HORKAGE_ZERO_AFTER_TRIM | 4047 4047 ATA_HORKAGE_NO_NCQ_ON_ATI }, 4048 + { "SAMSUNG*MZ7LH*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | 4049 + ATA_HORKAGE_ZERO_AFTER_TRIM | 4050 + ATA_HORKAGE_NO_NCQ_ON_ATI, }, 4048 4051 { "FCCT*M500*", NULL, ATA_HORKAGE_NO_NCQ_TRIM | 4049 4052 ATA_HORKAGE_ZERO_AFTER_TRIM }, 4050 4053
+8 -8
drivers/ata/pata_octeon_cf.c
··· 67 67 MODULE_PARM_DESC(enable_dma, 68 68 "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)"); 69 69 70 - /** 70 + /* 71 71 * Convert nanosecond based time to setting used in the 72 72 * boot bus timing register, based on timing multiple 73 73 */ ··· 114 114 cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64); 115 115 } 116 116 117 - /** 117 + /* 118 118 * Called after libata determines the needed PIO mode. This 119 119 * function programs the Octeon bootbus regions to support the 120 120 * timing requirements of the PIO mode. ··· 278 278 cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64); 279 279 } 280 280 281 - /** 281 + /* 282 282 * Handle an 8 bit I/O request. 283 283 * 284 284 * @qc: Queued command ··· 317 317 return buflen; 318 318 } 319 319 320 - /** 320 + /* 321 321 * Handle a 16 bit I/O request. 322 322 * 323 323 * @qc: Queued command ··· 372 372 return buflen; 373 373 } 374 374 375 - /** 375 + /* 376 376 * Read the taskfile for 16bit non-True IDE only. 377 377 */ 378 378 static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf) ··· 453 453 return 0; 454 454 } 455 455 456 - /** 456 + /* 457 457 * Load the taskfile for 16bit non-True IDE only. The device_addr is 458 458 * not loaded, we do this as part of octeon_cf_exec_command16. 459 459 */ ··· 525 525 ap->ops->sff_exec_command(ap, &qc->tf); 526 526 } 527 527 528 - /** 528 + /* 529 529 * Start a DMA transfer that was already setup 530 530 * 531 531 * @qc: Information about the DMA ··· 580 580 cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64); 581 581 } 582 582 583 - /** 583 + /* 584 584 * 585 585 * LOCKING: 586 586 * spin_lock_irqsave(host lock)