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drm/msm/dpu: handle perf mode in _dpu_core_perf_crtc_update_bus()

Move perf mode handling for the bandwidth to
_dpu_core_perf_crtc_update_bus() rather than overriding per-CRTC data
and then aggregating known values.

Note, this changes the fix_core_ab_vote. Previously it would be
multiplied per the CRTC number, now it will be used directly for
interconnect voting. This better reflects user requirements in the case
of different resolutions being set on different CRTCs: instead of using
the same bandwidth for each CRTC (which is incorrect) user can now
calculate overall bandwidth required by all outputs and use that value.

Note #2: this also disables threshold checks for user-entered bandwidth
values. First of all, it doesn't make sense to fail atomic commits
because of the debugfs input. Compositors have no way to correlate
failing commits with debugfs settings. Second, it makes sense to allow
users to go beyond these values and check whether this makes any
difference or fixes the issue.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/636072/
Link: https://lore.kernel.org/r/20250209-dpu-perf-rework-v5-8-87e936cf3004@linaro.org

Dmitry Baryshkov 6d3175a7 e7e24955

+18 -18
+18 -18
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c
··· 118 118 return; 119 119 } 120 120 121 - memset(perf, 0, sizeof(struct dpu_core_perf_params)); 122 - 123 - if (core_perf->perf_tune.mode == DPU_PERF_MODE_MINIMUM) { 124 - perf->bw_ctl = 0; 125 - perf->max_per_pipe_ib = 0; 126 - } else if (core_perf->perf_tune.mode == DPU_PERF_MODE_FIXED) { 127 - perf->bw_ctl = core_perf->fix_core_ab_vote * 1000ULL; 128 - perf->max_per_pipe_ib = core_perf->fix_core_ib_vote; 129 - } else { 130 - perf->bw_ctl = _dpu_core_perf_calc_bw(perf_cfg, crtc); 131 - perf->max_per_pipe_ib = perf_cfg->min_dram_ib; 132 - } 121 + perf->bw_ctl = _dpu_core_perf_calc_bw(perf_cfg, crtc); 122 + perf->max_per_pipe_ib = perf_cfg->min_dram_ib; 133 123 perf->core_clk_rate = _dpu_core_perf_calc_clk(perf_cfg, crtc, state); 134 - 135 124 DRM_DEBUG_ATOMIC( 136 125 "crtc=%d clk_rate=%llu core_ib=%u core_ab=%u\n", 137 126 crtc->base.id, perf->core_clk_rate, ··· 209 220 { 210 221 struct dpu_core_perf_params perf = { 0 }; 211 222 int i, ret = 0; 212 - u64 avg_bw; 223 + u32 avg_bw; 224 + u32 peak_bw; 213 225 214 226 if (!kms->num_paths) 215 227 return 0; 216 228 217 - dpu_core_perf_aggregate(crtc->dev, dpu_crtc_get_client_type(crtc), &perf); 229 + if (kms->perf.perf_tune.mode == DPU_PERF_MODE_MINIMUM) { 230 + avg_bw = 0; 231 + peak_bw = 0; 232 + } else if (kms->perf.perf_tune.mode == DPU_PERF_MODE_FIXED) { 233 + avg_bw = kms->perf.fix_core_ab_vote; 234 + peak_bw = kms->perf.fix_core_ib_vote; 235 + } else { 236 + dpu_core_perf_aggregate(crtc->dev, dpu_crtc_get_client_type(crtc), &perf); 218 237 219 - avg_bw = perf.bw_ctl; 220 - do_div(avg_bw, (kms->num_paths * 1000)); /*Bps_to_icc*/ 238 + avg_bw = div_u64(perf.bw_ctl, 1000); /*Bps_to_icc*/ 239 + peak_bw = perf.max_per_pipe_ib; 240 + } 241 + 242 + avg_bw /= kms->num_paths; 221 243 222 244 for (i = 0; i < kms->num_paths; i++) 223 - icc_set_bw(kms->path[i], avg_bw, perf.max_per_pipe_ib); 245 + icc_set_bw(kms->path[i], avg_bw, peak_bw); 224 246 225 247 return ret; 226 248 }