Merge branch 'bnxt_en-error-recovery-improvements'

+171 -57

drivers/net/ethernet/broadcom/bnxt/bnxt.c

··· 255 255 ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE, 256 256 ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY, 257 257 ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY, 258 + ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION, 258 259 ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG, 259 260 }; 260 261 ··· 2022 2021 goto async_event_process_exit; 2023 2022 set_bit(BNXT_RESET_TASK_SILENT_SP_EVENT, &bp->sp_event); 2024 2023 break; 2025 - case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: 2026 - if (netif_msg_hw(bp)) 2027 - netdev_warn(bp->dev, "Received RESET_NOTIFY event, data1: 0x%x, data2: 0x%x\n", 2028 - data1, data2); 2024 + case ASYNC_EVENT_CMPL_EVENT_ID_RESET_NOTIFY: { 2025 + char *fatal_str = "non-fatal"; 2026 + 2029 2027 if (!bp->fw_health) 2030 2028 goto async_event_process_exit; 2031 2029 ··· 2036 2036 if (!bp->fw_reset_max_dsecs) 2037 2037 bp->fw_reset_max_dsecs = BNXT_DFLT_FW_RST_MAX_DSECS; 2038 2038 if (EVENT_DATA1_RESET_NOTIFY_FATAL(data1)) { 2039 - netdev_warn(bp->dev, "Firmware fatal reset event received\n"); 2039 + fatal_str = "fatal"; 2040 2040 set_bit(BNXT_STATE_FW_FATAL_COND, &bp->state); 2041 - } else { 2042 - netdev_warn(bp->dev, "Firmware non-fatal reset event received, max wait time %d msec\n", 2041 + } 2042 + if (netif_msg_hw(bp)) { 2043 + netdev_warn(bp->dev, "Firmware %s reset event, data1: 0x%x, data2: 0x%x, min wait %u ms, max wait %u ms\n", 2044 + fatal_str, data1, data2, 2045 + bp->fw_reset_min_dsecs * 100, 2043 2046 bp->fw_reset_max_dsecs * 100); 2044 2047 } 2045 2048 set_bit(BNXT_FW_RESET_NOTIFY_SP_EVENT, &bp->sp_event); 2046 2049 break; 2050 + } 2047 2051 case ASYNC_EVENT_CMPL_EVENT_ID_ERROR_RECOVERY: { 2048 2052 struct bnxt_fw_health *fw_health = bp->fw_health; 2049 2053 ··· 2076 2072 bnxt_fw_health_readl(bp, BNXT_FW_RESET_CNT_REG); 2077 2073 goto async_event_process_exit; 2078 2074 } 2075 + case ASYNC_EVENT_CMPL_EVENT_ID_DEBUG_NOTIFICATION: 2076 + if (netif_msg_hw(bp)) { 2077 + netdev_notice(bp->dev, 2078 + "Received firmware debug notification, data1: 0x%x, data2: 0x%x\n", 2079 + data1, data2); 2080 + } 2081 + goto async_event_process_exit; 2079 2082 case ASYNC_EVENT_CMPL_EVENT_ID_RING_MONITOR_MSG: { 2080 2083 struct bnxt_rx_ring_info *rxr; 2081 2084 u16 grp_idx; ··· 2405 2394 struct bnxt_cp_ring_info *cpr = &bnapi->cp_ring; 2406 2395 int work_done = 0; 2407 2396 2397 + if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) { 2398 + napi_complete(napi); 2399 + return 0; 2400 + } 2408 2401 while (1) { 2409 2402 work_done += bnxt_poll_work(bp, cpr, budget - work_done); 2410 2403 ··· 2483 2468 int work_done = 0; 2484 2469 u32 cons; 2485 2470 2471 + if (unlikely(test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state))) { 2472 + napi_complete(napi); 2473 + return 0; 2474 + } 2486 2475 if (cpr->has_more_work) { 2487 2476 cpr->has_more_work = 0; 2488 2477 work_done = __bnxt_poll_cqs(bp, bnapi, budget); ··· 4291 4272 { 4292 4273 int i; 4293 4274 4275 + if (!bp->irq_tbl) 4276 + return; 4277 + 4294 4278 atomic_inc(&bp->intr_sem); 4295 4279 4296 4280 bnxt_disable_int(bp); ··· 4447 4425 4448 4426 if (!timeout) 4449 4427 timeout = DFLT_HWRM_CMD_TIMEOUT; 4428 + /* Limit timeout to an upper limit */ 4429 + timeout = min(timeout, HWRM_CMD_MAX_TIMEOUT); 4450 4430 /* convert timeout to usec */ 4451 4431 timeout *= 1000; 4452 4432 ··· 6869 6845 struct hwrm_func_backing_store_cfg_input req = {0}; 6870 6846 struct bnxt_ctx_mem_info *ctx = bp->ctx; 6871 6847 struct bnxt_ctx_pg_info *ctx_pg; 6848 + u32 req_len = sizeof(req); 6872 6849 __le32 *num_entries; 6873 6850 __le64 *pg_dir; 6874 6851 u32 flags = 0; ··· 6880 6855 if (!ctx) 6881 6856 return 0; 6882 6857 6858 + if (req_len > bp->hwrm_max_ext_req_len) 6859 + req_len = BNXT_BACKING_STORE_CFG_LEGACY_LEN; 6883 6860 bnxt_hwrm_cmd_hdr_init(bp, &req, HWRM_FUNC_BACKING_STORE_CFG, -1, -1); 6884 6861 req.enables = cpu_to_le32(enables); 6885 6862 ··· 6965 6938 bnxt_hwrm_set_pg_attr(&ctx_pg->ring_mem, pg_attr, pg_dir); 6966 6939 } 6967 6940 req.flags = cpu_to_le32(flags); 6968 - return hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 6941 + return hwrm_send_message(bp, &req, req_len, HWRM_CMD_TIMEOUT); 6969 6942 } 6970 6943 6971 6944 static int bnxt_alloc_ctx_mem_blk(struct bnxt *bp, ··· 7465 7438 7466 7439 sig = readl(hs + offsetof(struct hcomm_status, sig_ver)); 7467 7440 if ((sig & HCOMM_STATUS_SIGNATURE_MASK) != HCOMM_STATUS_SIGNATURE_VAL) { 7468 - if (bp->fw_health) 7469 - bp->fw_health->status_reliable = false; 7470 - return; 7441 + if (!bp->chip_num) { 7442 + __bnxt_map_fw_health_reg(bp, BNXT_GRC_REG_BASE); 7443 + bp->chip_num = readl(bp->bar0 + 7444 + BNXT_FW_HEALTH_WIN_BASE + 7445 + BNXT_GRC_REG_CHIP_NUM); 7446 + } 7447 + if (!BNXT_CHIP_P5(bp)) { 7448 + if (bp->fw_health) 7449 + bp->fw_health->status_reliable = false; 7450 + return; 7451 + } 7452 + status_loc = BNXT_GRC_REG_STATUS_P5 | 7453 + BNXT_FW_HEALTH_REG_TYPE_BAR0; 7454 + } else { 7455 + status_loc = readl(hs + offsetof(struct hcomm_status, 7456 + fw_status_loc)); 7471 7457 } 7472 7458 7473 7459 if (__bnxt_alloc_fw_health(bp)) { ··· 7488 7448 return; 7489 7449 } 7490 7450 7491 - status_loc = readl(hs + offsetof(struct hcomm_status, fw_status_loc)); 7492 7451 bp->fw_health->regs[BNXT_FW_HEALTH_REG] = status_loc; 7493 7452 reg_type = BNXT_FW_HEALTH_REG_TYPE(status_loc); 7494 7453 if (reg_type == BNXT_FW_HEALTH_REG_TYPE_GRC) { ··· 8850 8811 { 8851 8812 int i; 8852 8813 8853 - if (!bp->bnapi) 8814 + if (!bp->bnapi || 8815 + test_and_set_bit(BNXT_STATE_NAPI_DISABLED, &bp->state)) 8854 8816 return; 8855 8817 8856 8818 for (i = 0; i < bp->cp_nr_rings; i++) { ··· 8868 8828 { 8869 8829 int i; 8870 8830 8831 + clear_bit(BNXT_STATE_NAPI_DISABLED, &bp->state); 8871 8832 for (i = 0; i < bp->cp_nr_rings; i++) { 8872 8833 struct bnxt_napi *bnapi = bp->bnapi[i]; 8873 8834 struct bnxt_cp_ring_info *cpr; ··· 9375 9334 9376 9335 static int bnxt_fw_init_one(struct bnxt *bp); 9377 9336 9337 + static int bnxt_fw_reset_via_optee(struct bnxt *bp) 9338 + { 9339 + #ifdef CONFIG_TEE_BNXT_FW 9340 + int rc = tee_bnxt_fw_load(); 9341 + 9342 + if (rc) 9343 + netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc); 9344 + 9345 + return rc; 9346 + #else 9347 + netdev_err(bp->dev, "OP-TEE not supported\n"); 9348 + return -ENODEV; 9349 + #endif 9350 + } 9351 + 9352 + static int bnxt_try_recover_fw(struct bnxt *bp) 9353 + { 9354 + if (bp->fw_health && bp->fw_health->status_reliable) { 9355 + int retry = 0, rc; 9356 + u32 sts; 9357 + 9358 + mutex_lock(&bp->hwrm_cmd_lock); 9359 + do { 9360 + rc = __bnxt_hwrm_ver_get(bp, true); 9361 + sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 9362 + if (!sts || !BNXT_FW_IS_BOOTING(sts)) 9363 + break; 9364 + retry++; 9365 + } while (rc == -EBUSY && retry < BNXT_FW_RETRY); 9366 + mutex_unlock(&bp->hwrm_cmd_lock); 9367 + 9368 + if (!BNXT_FW_IS_HEALTHY(sts)) { 9369 + netdev_err(bp->dev, 9370 + "Firmware not responding, status: 0x%x\n", 9371 + sts); 9372 + rc = -ENODEV; 9373 + } 9374 + if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) { 9375 + netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n"); 9376 + return bnxt_fw_reset_via_optee(bp); 9377 + } 9378 + return rc; 9379 + } 9380 + 9381 + return -ENODEV; 9382 + } 9383 + 9378 9384 static int bnxt_hwrm_if_change(struct bnxt *bp, bool up) 9379 9385 { 9380 9386 struct hwrm_func_drv_if_change_output *resp = bp->hwrm_cmd_resp_addr; 9381 9387 struct hwrm_func_drv_if_change_input req = {0}; 9382 9388 bool resc_reinit = false, fw_reset = false; 9389 + int rc, retry = 0; 9383 9390 u32 flags = 0; 9384 - int rc; 9385 9391 9386 9392 if (!(bp->fw_cap & BNXT_FW_CAP_IF_CHANGE)) 9387 9393 return 0; ··· 9437 9349 if (up) 9438 9350 req.flags = cpu_to_le32(FUNC_DRV_IF_CHANGE_REQ_FLAGS_UP); 9439 9351 mutex_lock(&bp->hwrm_cmd_lock); 9440 - rc = _hwrm_send_message(bp, &req, sizeof(req), HWRM_CMD_TIMEOUT); 9352 + while (retry < BNXT_FW_IF_RETRY) { 9353 + rc = _hwrm_send_message(bp, &req, sizeof(req), 9354 + HWRM_CMD_TIMEOUT); 9355 + if (rc != -EAGAIN) 9356 + break; 9357 + 9358 + msleep(50); 9359 + retry++; 9360 + } 9441 9361 if (!rc) 9442 9362 flags = le32_to_cpu(resp->flags); 9443 9363 mutex_unlock(&bp->hwrm_cmd_lock); 9364 + 9365 + if (rc == -EAGAIN) 9366 + return rc; 9367 + if (rc && up) { 9368 + rc = bnxt_try_recover_fw(bp); 9369 + fw_reset = true; 9370 + } 9444 9371 if (rc) 9445 9372 return rc; 9446 9373 ··· 9795 9692 9796 9693 static int bnxt_init_dflt_ring_mode(struct bnxt *bp); 9797 9694 9695 + static int bnxt_reinit_after_abort(struct bnxt *bp) 9696 + { 9697 + int rc; 9698 + 9699 + if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 9700 + return -EBUSY; 9701 + 9702 + rc = bnxt_fw_init_one(bp); 9703 + if (!rc) { 9704 + bnxt_clear_int_mode(bp); 9705 + rc = bnxt_init_int_mode(bp); 9706 + if (!rc) { 9707 + clear_bit(BNXT_STATE_ABORT_ERR, &bp->state); 9708 + set_bit(BNXT_STATE_FW_RESET_DET, &bp->state); 9709 + } 9710 + } 9711 + return rc; 9712 + } 9713 + 9798 9714 static int __bnxt_open_nic(struct bnxt *bp, bool irq_re_init, bool link_re_init) 9799 9715 { 9800 9716 int rc = 0; ··· 9972 9850 int rc; 9973 9851 9974 9852 if (test_bit(BNXT_STATE_ABORT_ERR, &bp->state)) { 9975 - netdev_err(bp->dev, "A previous firmware reset did not complete, aborting\n"); 9976 - return -ENODEV; 9853 + rc = bnxt_reinit_after_abort(bp); 9854 + if (rc) { 9855 + if (rc == -EBUSY) 9856 + netdev_err(bp->dev, "A previous firmware reset has not completed, aborting\n"); 9857 + else 9858 + netdev_err(bp->dev, "Failed to reinitialize after aborted firmware reset\n"); 9859 + return -ENODEV; 9860 + } 9977 9861 } 9978 9862 9979 9863 rc = bnxt_hwrm_if_change(bp, true); ··· 10916 10788 static void bnxt_fw_reset_close(struct bnxt *bp) 10917 10789 { 10918 10790 bnxt_ulp_stop(bp); 10919 - /* When firmware is fatal state, disable PCI device to prevent 10920 - * any potential bad DMAs before freeing kernel memory. 10791 + /* When firmware is in fatal state, quiesce device and disable 10792 + * bus master to prevent any potential bad DMAs before freeing 10793 + * kernel memory. 10921 10794 */ 10922 - if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) 10795 + if (test_bit(BNXT_STATE_FW_FATAL_COND, &bp->state)) { 10796 + bnxt_tx_disable(bp); 10797 + bnxt_disable_napi(bp); 10798 + bnxt_disable_int_sync(bp); 10799 + bnxt_free_irq(bp); 10800 + bnxt_clear_int_mode(bp); 10923 10801 pci_disable_device(bp->pdev); 10802 + } 10924 10803 __bnxt_close_nic(bp, true, false); 10925 10804 bnxt_clear_int_mode(bp); 10926 10805 bnxt_hwrm_func_drv_unrgtr(bp); ··· 11315 11180 bp->stats_coal_ticks = BNXT_DEF_STATS_COAL_TICKS; 11316 11181 } 11317 11182 11318 - static int bnxt_fw_reset_via_optee(struct bnxt *bp) 11319 - { 11320 - #ifdef CONFIG_TEE_BNXT_FW 11321 - int rc = tee_bnxt_fw_load(); 11322 - 11323 - if (rc) 11324 - netdev_err(bp->dev, "Failed FW reset via OP-TEE, rc=%d\n", rc); 11325 - 11326 - return rc; 11327 - #else 11328 - netdev_err(bp->dev, "OP-TEE not supported\n"); 11329 - return -ENODEV; 11330 - #endif 11331 - } 11332 - 11333 11183 static int bnxt_fw_init_one_p1(struct bnxt *bp) 11334 11184 { 11335 11185 int rc; ··· 11323 11203 rc = bnxt_hwrm_ver_get(bp); 11324 11204 bnxt_try_map_fw_health_reg(bp); 11325 11205 if (rc) { 11326 - if (bp->fw_health && bp->fw_health->status_reliable) { 11327 - u32 sts = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 11328 - 11329 - netdev_err(bp->dev, 11330 - "Firmware not responding, status: 0x%x\n", 11331 - sts); 11332 - if (sts & FW_STATUS_REG_CRASHED_NO_MASTER) { 11333 - netdev_warn(bp->dev, "Firmware recover via OP-TEE requested\n"); 11334 - rc = bnxt_fw_reset_via_optee(bp); 11335 - if (!rc) 11336 - rc = bnxt_hwrm_ver_get(bp); 11337 - } 11338 - } 11206 + rc = bnxt_try_recover_fw(bp); 11207 + if (rc) 11208 + return rc; 11209 + rc = bnxt_hwrm_ver_get(bp); 11339 11210 if (rc) 11340 11211 return rc; 11341 11212 } ··· 11526 11415 bp->fw_reset_timestamp = jiffies; 11527 11416 } 11528 11417 11418 + static bool bnxt_fw_reset_timeout(struct bnxt *bp) 11419 + { 11420 + return time_after(jiffies, bp->fw_reset_timestamp + 11421 + (bp->fw_reset_max_dsecs * HZ / 10)); 11422 + } 11423 + 11529 11424 static void bnxt_fw_reset_task(struct work_struct *work) 11530 11425 { 11531 11426 struct bnxt *bp = container_of(work, struct bnxt, fw_reset_task.work); ··· 11553 11436 bp->fw_reset_timestamp)); 11554 11437 goto fw_reset_abort; 11555 11438 } else if (n > 0) { 11556 - if (time_after(jiffies, bp->fw_reset_timestamp + 11557 - (bp->fw_reset_max_dsecs * HZ / 10))) { 11439 + if (bnxt_fw_reset_timeout(bp)) { 11558 11440 clear_bit(BNXT_STATE_IN_FW_RESET, &bp->state); 11559 11441 bp->fw_reset_state = 0; 11560 11442 netdev_err(bp->dev, "Firmware reset aborted, bnxt_get_registered_vfs() returns %d\n", ··· 11582 11466 11583 11467 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 11584 11468 if (!(val & BNXT_FW_STATUS_SHUTDOWN) && 11585 - !time_after(jiffies, bp->fw_reset_timestamp + 11586 - (bp->fw_reset_max_dsecs * HZ / 10))) { 11469 + !bnxt_fw_reset_timeout(bp)) { 11587 11470 bnxt_queue_fw_reset_work(bp, HZ / 5); 11588 11471 return; 11589 11472 } ··· 11624 11509 bp->hwrm_cmd_timeout = SHORT_HWRM_CMD_TIMEOUT; 11625 11510 rc = __bnxt_hwrm_ver_get(bp, true); 11626 11511 if (rc) { 11627 - if (time_after(jiffies, bp->fw_reset_timestamp + 11628 - (bp->fw_reset_max_dsecs * HZ / 10))) { 11512 + if (bnxt_fw_reset_timeout(bp)) { 11629 11513 netdev_err(bp->dev, "Firmware reset aborted\n"); 11630 11514 goto fw_reset_abort_status; 11631 11515 } ··· 12656 12542 dev->ethtool_ops = &bnxt_ethtool_ops; 12657 12543 pci_set_drvdata(pdev, dev); 12658 12544 12659 - if (BNXT_PF(bp)) 12660 - bnxt_vpd_read_info(bp); 12661 - 12662 12545 rc = bnxt_alloc_hwrm_resources(bp); 12663 12546 if (rc) 12664 12547 goto init_err_pci_clean; ··· 12666 12555 rc = bnxt_fw_init_one_p1(bp); 12667 12556 if (rc) 12668 12557 goto init_err_pci_clean; 12558 + 12559 + if (BNXT_PF(bp)) 12560 + bnxt_vpd_read_info(bp); 12669 12561 12670 12562 if (BNXT_CHIP_P5(bp)) { 12671 12563 bp->flags |= BNXT_FLAG_CHIP_P5;

+22

drivers/net/ethernet/broadcom/bnxt/bnxt.h

··· 656 656 #define BNXT_HWRM_MAX_REQ_LEN (bp->hwrm_max_req_len) 657 657 #define BNXT_HWRM_SHORT_REQ_LEN sizeof(struct hwrm_short_input) 658 658 #define DFLT_HWRM_CMD_TIMEOUT 500 659 + #define HWRM_CMD_MAX_TIMEOUT 40000 659 660 #define SHORT_HWRM_CMD_TIMEOUT 20 660 661 #define HWRM_CMD_TIMEOUT (bp->hwrm_cmd_timeout) 661 662 #define HWRM_RESET_TIMEOUT ((HWRM_CMD_TIMEOUT) * 4) ··· 1346 1345 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 1347 1346 #define BNXT_CAG_REG_BASE 0x300000 1348 1347 1348 + #define BNXT_GRC_REG_STATUS_P5 0x520 1349 + 1349 1350 #define BNXT_GRCPF_REG_KONG_COMM 0xA00 1350 1351 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 1352 + 1353 + #define BNXT_GRC_REG_CHIP_NUM 0x48 1354 + #define BNXT_GRC_REG_BASE 0x260000 1351 1355 1352 1356 #define BNXT_GRC_BASE_MASK 0xfffff000 1353 1357 #define BNXT_GRC_OFFSET_MASK 0x00000ffc ··· 1447 1441 #define BNXT_MAX_TQM_RINGS \ 1448 1442 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 1449 1443 1444 + #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 1445 + 1450 1446 struct bnxt_ctx_mem_info { 1451 1447 u32 qp_max_entries; 1452 1448 u16 qp_min_qp1_entries; ··· 1540 1532 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \ 1541 1533 ((reg) & BNXT_GRC_OFFSET_MASK)) 1542 1534 1535 + #define BNXT_FW_STATUS_HEALTH_MSK 0xffff 1543 1536 #define BNXT_FW_STATUS_HEALTHY 0x8000 1544 1537 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 1538 + 1539 + #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\ 1540 + BNXT_FW_STATUS_HEALTHY) 1541 + 1542 + #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \ 1543 + BNXT_FW_STATUS_HEALTHY) 1544 + 1545 + #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \ 1546 + BNXT_FW_STATUS_HEALTHY) 1547 + 1548 + #define BNXT_FW_RETRY 5 1549 + #define BNXT_FW_IF_RETRY 10 1545 1550 1546 1551 struct bnxt { 1547 1552 void __iomem *bar0; ··· 1809 1788 #define BNXT_STATE_FW_FATAL_COND 6 1810 1789 #define BNXT_STATE_DRV_REGISTERED 7 1811 1790 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 1791 + #define BNXT_STATE_NAPI_DISABLED 9 1812 1792 1813 1793 #define BNXT_NO_FW_ACCESS(bp) \ 1814 1794 (test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) || \

+3 -4

drivers/net/ethernet/broadcom/bnxt/bnxt_devlink.c

··· 44 44 struct netlink_ext_ack *extack) 45 45 { 46 46 struct bnxt *bp = devlink_health_reporter_priv(reporter); 47 - u32 val, health_status; 47 + u32 val; 48 48 int rc; 49 49 50 50 if (test_bit(BNXT_STATE_IN_FW_RESET, &bp->state)) 51 51 return 0; 52 52 53 53 val = bnxt_fw_health_readl(bp, BNXT_FW_HEALTH_REG); 54 - health_status = val & 0xffff; 55 54 56 - if (health_status < BNXT_FW_STATUS_HEALTHY) { 55 + if (BNXT_FW_IS_BOOTING(val)) { 57 56 rc = devlink_fmsg_string_pair_put(fmsg, "Description", 58 57 "Not yet completed initialization"); 59 58 if (rc) 60 59 return rc; 61 - } else if (health_status > BNXT_FW_STATUS_HEALTHY) { 60 + } else if (BNXT_FW_IS_ERR(val)) { 62 61 rc = devlink_fmsg_string_pair_put(fmsg, "Description", 63 62 "Encountered fatal error and cannot recover"); 64 63 if (rc)

+197 -52

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

··· 2 2 * 3 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 4 * Copyright (c) 2014-2018 Broadcom Limited 5 - * Copyright (c) 2018-2020 Broadcom Inc. 5 + * Copyright (c) 2018-2021 Broadcom Inc. 6 6 * 7 7 * This program is free software; you can redistribute it and/or modify 8 8 * it under the terms of the GNU General Public License as published by ··· 164 164 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 165 165 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 166 166 #define HWRM_VNIC_QCAPS 0x4aUL 167 + #define HWRM_VNIC_UPDATE 0x4bUL 167 168 #define HWRM_RING_ALLOC 0x50UL 168 169 #define HWRM_RING_FREE 0x51UL 169 170 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL ··· 185 184 #define HWRM_QUEUE_MPLS_QCAPS 0x80UL 186 185 #define HWRM_QUEUE_MPLSTC2PRI_QCFG 0x81UL 187 186 #define HWRM_QUEUE_MPLSTC2PRI_CFG 0x82UL 187 + #define HWRM_QUEUE_VLANPRI_QCAPS 0x83UL 188 + #define HWRM_QUEUE_VLANPRI2PRI_QCFG 0x84UL 189 + #define HWRM_QUEUE_VLANPRI2PRI_CFG 0x85UL 188 190 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 189 191 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 190 192 #define HWRM_CFA_L2_FILTER_CFG 0x92UL ··· 221 217 #define HWRM_PORT_TX_FIR_CFG 0xbbUL 222 218 #define HWRM_PORT_TX_FIR_QCFG 0xbcUL 223 219 #define HWRM_PORT_ECN_QSTATS 0xbdUL 220 + #define HWRM_FW_LIVEPATCH_QUERY 0xbeUL 221 + #define HWRM_FW_LIVEPATCH 0xbfUL 224 222 #define HWRM_FW_RESET 0xc0UL 225 223 #define HWRM_FW_QSTATUS 0xc1UL 226 224 #define HWRM_FW_HEALTH_CHECK 0xc2UL ··· 353 347 #define HWRM_FUNC_HOST_PF_IDS_QUERY 0x197UL 354 348 #define HWRM_FUNC_QSTATS_EXT 0x198UL 355 349 #define HWRM_STAT_EXT_CTX_QUERY 0x199UL 350 + #define HWRM_FUNC_SPD_CFG 0x19aUL 351 + #define HWRM_FUNC_SPD_QCFG 0x19bUL 356 352 #define HWRM_SELFTEST_QLIST 0x200UL 357 353 #define HWRM_SELFTEST_EXEC 0x201UL 358 354 #define HWRM_SELFTEST_IRQ 0x202UL ··· 367 359 #define HWRM_MFG_HDMA_TEST 0x209UL 368 360 #define HWRM_MFG_FRU_EEPROM_WRITE 0x20aUL 369 361 #define HWRM_MFG_FRU_EEPROM_READ 0x20bUL 362 + #define HWRM_MFG_SOC_IMAGE 0x20cUL 363 + #define HWRM_MFG_SOC_QSTATUS 0x20dUL 364 + #define HWRM_MFG_PARAM_SEEPROM_SYNC 0x20eUL 365 + #define HWRM_MFG_PARAM_SEEPROM_READ 0x20fUL 366 + #define HWRM_MFG_PARAM_SEEPROM_HEALTH 0x210UL 370 367 #define HWRM_TF 0x2bcUL 371 368 #define HWRM_TF_VERSION_GET 0x2bdUL 372 369 #define HWRM_TF_SESSION_OPEN 0x2c6UL ··· 397 384 #define HWRM_TF_EXT_EM_QCFG 0x2e9UL 398 385 #define HWRM_TF_EM_INSERT 0x2eaUL 399 386 #define HWRM_TF_EM_DELETE 0x2ebUL 387 + #define HWRM_TF_EM_HASH_INSERT 0x2ecUL 400 388 #define HWRM_TF_TCAM_SET 0x2f8UL 401 389 #define HWRM_TF_TCAM_GET 0x2f9UL 402 390 #define HWRM_TF_TCAM_MOVE 0x2faUL ··· 500 486 #define HWRM_TARGET_ID_TOOLS 0xFFFD 501 487 #define HWRM_VERSION_MAJOR 1 502 488 #define HWRM_VERSION_MINOR 10 503 - #define HWRM_VERSION_UPDATE 1 504 - #define HWRM_VERSION_RSVD 68 505 - #define HWRM_VERSION_STR "1.10.1.68" 489 + #define HWRM_VERSION_UPDATE 2 490 + #define HWRM_VERSION_RSVD 11 491 + #define HWRM_VERSION_STR "1.10.2.11" 506 492 507 493 /* hwrm_ver_get_input (size:192b/24B) */ 508 494 struct hwrm_ver_get_input { ··· 577 563 __le16 max_resp_len; 578 564 __le16 def_req_timeout; 579 565 u8 flags; 580 - #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 581 - #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 566 + #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 567 + #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 568 + #define VER_GET_RESP_FLAGS_DEV_NOT_RDY_BACKING_STORE 0x4UL 582 569 u8 unused_0[2]; 583 570 u8 always_1; 584 571 __le16 hwrm_intf_major; ··· 723 708 #define ASYNC_EVENT_CMPL_EVENT_ID_QUIESCE_DONE 0x3fUL 724 709 #define ASYNC_EVENT_CMPL_EVENT_ID_DEFERRED_RESPONSE 0x40UL 725 710 #define ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE 0x41UL 711 + #define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID 0x42UL 726 712 #define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG 0xfeUL 727 713 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 728 714 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR ··· 831 815 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 0x8UL 832 816 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY 833 817 __le32 event_data2; 818 + #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK 0xffffUL 819 + #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT 0 834 820 u8 opaque_v; 835 821 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_V 0x1UL 836 822 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_OPAQUE_MASK 0xfeUL ··· 850 832 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MANAGEMENT_RESET_REQUEST (0x1UL << 8) 851 833 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL (0x2UL << 8) 852 834 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL (0x3UL << 8) 853 - #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL 835 + #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET (0x4UL << 8) 836 + #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET 854 837 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_MASK 0xffff0000UL 855 838 #define ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_DELAY_IN_100MS_TICKS_SFT 16 856 839 }; ··· 1290 1271 #define FUNC_QCAPS_RESP_FLAGS_EXT_TX_PROXY_SRC_INTF_OVERRIDE_SUPPORT 0x20UL 1291 1272 #define FUNC_QCAPS_RESP_FLAGS_EXT_SCHQ_SUPPORTED 0x40UL 1292 1273 #define FUNC_QCAPS_RESP_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED 0x80UL 1274 + #define FUNC_QCAPS_RESP_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED 0x100UL 1275 + #define FUNC_QCAPS_RESP_FLAGS_EXT_SOC_SPD_SUPPORTED 0x200UL 1276 + #define FUNC_QCAPS_RESP_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED 0x400UL 1277 + #define FUNC_QCAPS_RESP_FLAGS_EXT_FAST_RESET_CAPABLE 0x800UL 1293 1278 u8 max_schqs; 1294 1279 u8 mpc_chnls_cap; 1295 1280 #define FUNC_QCAPS_RESP_MPC_CHNLS_CAP_TCE 0x1UL ··· 1338 1315 #define FUNC_QCFG_RESP_FLAGS_HOT_RESET_ALLOWED 0x200UL 1339 1316 #define FUNC_QCFG_RESP_FLAGS_PPP_PUSH_MODE_ENABLED 0x400UL 1340 1317 #define FUNC_QCFG_RESP_FLAGS_RING_MONITOR_ENABLED 0x800UL 1318 + #define FUNC_QCFG_RESP_FLAGS_FAST_RESET_ALLOWED 0x1000UL 1341 1319 u8 mac_address[6]; 1342 1320 __le16 pci_id; 1343 1321 __le16 alloc_rsscos_ctx; ··· 1755 1731 #define FUNC_DRV_RGTR_REQ_FLAGS_HOT_RESET_SUPPORT 0x10UL 1756 1732 #define FUNC_DRV_RGTR_REQ_FLAGS_ERROR_RECOVERY_SUPPORT 0x20UL 1757 1733 #define FUNC_DRV_RGTR_REQ_FLAGS_MASTER_SUPPORT 0x40UL 1734 + #define FUNC_DRV_RGTR_REQ_FLAGS_FAST_RESET_SUPPORT 0x80UL 1758 1735 __le32 enables; 1759 1736 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1760 1737 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL ··· 2018 1993 __le64 resp_addr; 2019 1994 }; 2020 1995 2021 - /* hwrm_func_backing_store_qcaps_output (size:640b/80B) */ 1996 + /* hwrm_func_backing_store_qcaps_output (size:704b/88B) */ 2022 1997 struct hwrm_func_backing_store_qcaps_output { 2023 1998 __le16 error_code; 2024 1999 __le16 req_type; ··· 2049 2024 __le16 mrav_num_entries_units; 2050 2025 u8 tqm_entries_multiple; 2051 2026 u8 ctx_kind_initializer; 2052 - __le32 rsvd; 2053 - __le16 rsvd1; 2027 + __le16 ctx_init_mask; 2028 + #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_QP 0x1UL 2029 + #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_SRQ 0x2UL 2030 + #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_CQ 0x4UL 2031 + #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_VNIC 0x8UL 2032 + #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_STAT 0x10UL 2033 + #define FUNC_BACKING_STORE_QCAPS_RESP_CTX_INIT_MASK_MRAV 0x20UL 2034 + u8 qp_init_offset; 2035 + u8 srq_init_offset; 2036 + u8 cq_init_offset; 2037 + u8 vnic_init_offset; 2054 2038 u8 tqm_fp_rings_count; 2039 + u8 stat_init_offset; 2040 + u8 mrav_init_offset; 2041 + u8 rsvd[6]; 2055 2042 u8 valid; 2056 2043 }; 2057 2044 2058 - /* hwrm_func_backing_store_cfg_input (size:2048b/256B) */ 2045 + /* hwrm_func_backing_store_cfg_input (size:2432b/304B) */ 2059 2046 struct hwrm_func_backing_store_cfg_input { 2060 2047 __le16 req_type; 2061 2048 __le16 cmpl_ring; ··· 2078 2041 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_PREBOOT_MODE 0x1UL 2079 2042 #define FUNC_BACKING_STORE_CFG_REQ_FLAGS_MRAV_RESERVATION_SPLIT 0x2UL 2080 2043 __le32 enables; 2081 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2082 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2083 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2084 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2085 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2086 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2087 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2088 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2089 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2090 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2091 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2092 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2093 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2094 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2095 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2096 - #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2044 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_QP 0x1UL 2045 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_SRQ 0x2UL 2046 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_CQ 0x4UL 2047 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_VNIC 0x8UL 2048 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_STAT 0x10UL 2049 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_SP 0x20UL 2050 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING0 0x40UL 2051 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING1 0x80UL 2052 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING2 0x100UL 2053 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING3 0x200UL 2054 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING4 0x400UL 2055 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING5 0x800UL 2056 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING6 0x1000UL 2057 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING7 0x2000UL 2058 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV 0x4000UL 2059 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TIM 0x8000UL 2060 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING8 0x10000UL 2061 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING9 0x20000UL 2062 + #define FUNC_BACKING_STORE_CFG_REQ_ENABLES_TQM_RING10 0x40000UL 2097 2063 u8 qpc_pg_size_qpc_lvl; 2098 2064 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_MASK 0xfUL 2099 2065 #define FUNC_BACKING_STORE_CFG_REQ_QPC_LVL_SFT 0 ··· 2398 2358 __le16 tqm_entry_size; 2399 2359 __le16 mrav_entry_size; 2400 2360 __le16 tim_entry_size; 2361 + u8 tqm_ring8_pg_size_tqm_ring_lvl; 2362 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_MASK 0xfUL 2363 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_SFT 0 2364 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_0 0x0UL 2365 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_1 0x1UL 2366 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 0x2UL 2367 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_LVL_LVL_2 2368 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_MASK 0xf0UL 2369 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_SFT 4 2370 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2371 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2372 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2373 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2374 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2375 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2376 + #define FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING8_TQM_RING_PG_SIZE_PG_1G 2377 + u8 ring8_unused[3]; 2378 + __le32 tqm_ring8_num_entries; 2379 + __le64 tqm_ring8_page_dir; 2380 + u8 tqm_ring9_pg_size_tqm_ring_lvl; 2381 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_MASK 0xfUL 2382 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_SFT 0 2383 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_0 0x0UL 2384 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_1 0x1UL 2385 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 0x2UL 2386 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_LVL_LVL_2 2387 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_MASK 0xf0UL 2388 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_SFT 4 2389 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2390 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2391 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2392 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2393 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2394 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2395 + #define FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING9_TQM_RING_PG_SIZE_PG_1G 2396 + u8 ring9_unused[3]; 2397 + __le32 tqm_ring9_num_entries; 2398 + __le64 tqm_ring9_page_dir; 2399 + u8 tqm_ring10_pg_size_tqm_ring_lvl; 2400 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_MASK 0xfUL 2401 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_SFT 0 2402 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_0 0x0UL 2403 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_1 0x1UL 2404 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 0x2UL 2405 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_LVL_LVL_2 2406 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_MASK 0xf0UL 2407 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_SFT 4 2408 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_4K (0x0UL << 4) 2409 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8K (0x1UL << 4) 2410 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_64K (0x2UL << 4) 2411 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_2M (0x3UL << 4) 2412 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_8M (0x4UL << 4) 2413 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G (0x5UL << 4) 2414 + #define FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_LAST FUNC_BACKING_STORE_CFG_REQ_RING10_TQM_RING_PG_SIZE_PG_1G 2415 + u8 ring10_unused[3]; 2416 + __le32 tqm_ring10_num_entries; 2417 + __le64 tqm_ring10_page_dir; 2401 2418 }; 2402 2419 2403 2420 /* hwrm_func_backing_store_cfg_output (size:128b/16B) */ ··· 3027 2930 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 3028 2931 u8 option_flags; 3029 2932 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 2933 + #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_SIGNAL_MODE_KNOWN 0x2UL 3030 2934 char phy_vendor_name[16]; 3031 2935 char phy_vendor_partnumber[16]; 3032 2936 __le16 support_pam4_speeds; ··· 3626 3528 #define PORT_PHY_QCAPS_RESP_FLAGS_SHARED_PHY_CFG_SUPPORTED 0x8UL 3627 3529 #define PORT_PHY_QCAPS_RESP_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 0x10UL 3628 3530 #define PORT_PHY_QCAPS_RESP_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 0x20UL 3629 - #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xc0UL 3630 - #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 6 3531 + #define PORT_PHY_QCAPS_RESP_FLAGS_FW_MANAGED_LINK_DOWN 0x40UL 3532 + #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1 0x80UL 3631 3533 u8 port_cnt; 3632 3534 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 3633 3535 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL ··· 4217 4119 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 4218 4120 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 4219 4121 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 4220 - u8 unused_0; 4122 + u8 queue_id0_service_profile_type; 4123 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4124 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC 0x2UL 4125 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP 0x4UL 4221 4126 char qid0_name[16]; 4222 4127 char qid1_name[16]; 4223 4128 char qid2_name[16]; ··· 4229 4128 char qid5_name[16]; 4230 4129 char qid6_name[16]; 4231 4130 char qid7_name[16]; 4232 - u8 unused_1[7]; 4131 + u8 queue_id1_service_profile_type; 4132 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4133 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC 0x2UL 4134 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP 0x4UL 4135 + u8 queue_id2_service_profile_type; 4136 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4137 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC 0x2UL 4138 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP 0x4UL 4139 + u8 queue_id3_service_profile_type; 4140 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4141 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC 0x2UL 4142 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP 0x4UL 4143 + u8 queue_id4_service_profile_type; 4144 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4145 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC 0x2UL 4146 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP 0x4UL 4147 + u8 queue_id5_service_profile_type; 4148 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4149 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC 0x2UL 4150 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP 0x4UL 4151 + u8 queue_id6_service_profile_type; 4152 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4153 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC 0x2UL 4154 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP 0x4UL 4155 + u8 queue_id7_service_profile_type; 4156 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE 0x1UL 4157 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC 0x2UL 4158 + #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP 0x4UL 4233 4159 u8 valid; 4234 4160 }; 4235 4161 ··· 5270 5142 __le16 target_id; 5271 5143 __le64 resp_addr; 5272 5144 __le32 flags; 5273 - #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5274 - u8 unused_0[4]; 5145 + #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 5146 + #define VNIC_ALLOC_REQ_FLAGS_VIRTIO_NET_FID_VALID 0x2UL 5147 + __le16 virtio_net_fid; 5148 + u8 unused_0[2]; 5275 5149 }; 5276 5150 5277 5151 /* hwrm_vnic_alloc_output (size:128b/16B) */ ··· 5390 5260 #define VNIC_QCAPS_RESP_FLAGS_OUTERMOST_RSS_CAP 0x80UL 5391 5261 #define VNIC_QCAPS_RESP_FLAGS_COS_ASSIGNMENT_CAP 0x100UL 5392 5262 #define VNIC_QCAPS_RESP_FLAGS_RX_CMPL_V2_CAP 0x200UL 5263 + #define VNIC_QCAPS_RESP_FLAGS_VNIC_STATE_CAP 0x400UL 5264 + #define VNIC_QCAPS_RESP_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP 0x800UL 5393 5265 __le16 max_aggs_supported; 5394 5266 u8 unused_1[5]; 5395 5267 u8 valid; ··· 5717 5585 __le16 resp_len; 5718 5586 __le16 ring_id; 5719 5587 __le16 logical_ring_id; 5720 - u8 unused_0[3]; 5588 + u8 push_buffer_index; 5589 + #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5590 + #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5591 + #define RING_ALLOC_RESP_PUSH_BUFFER_INDEX_LAST RING_ALLOC_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5592 + u8 unused_0[2]; 5721 5593 u8 valid; 5722 5594 }; 5723 5595 ··· 5780 5644 __le16 req_type; 5781 5645 __le16 seq_id; 5782 5646 __le16 resp_len; 5783 - u8 unused_0[4]; 5647 + u8 push_buffer_index; 5648 + #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PING_BUFFER 0x0UL 5649 + #define RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 0x1UL 5650 + #define RING_RESET_RESP_PUSH_BUFFER_INDEX_LAST RING_RESET_RESP_PUSH_BUFFER_INDEX_PONG_BUFFER 5651 + u8 unused_0[3]; 5784 5652 u8 consumer_idx[3]; 5785 5653 u8 valid; 5786 5654 }; ··· 7128 6988 __le16 seq_id; 7129 6989 __le16 resp_len; 7130 6990 __le32 flags; 7131 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 7132 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 7133 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 7134 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 7135 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 7136 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 7137 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 7138 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 7139 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7140 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7141 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7142 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7143 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7144 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7145 - #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 6991 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_16BIT_SUPPORTED 0x1UL 6992 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_HND_64BIT_SUPPORTED 0x2UL 6993 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_BATCH_DELETE_SUPPORTED 0x4UL 6994 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_RESET_ALL_SUPPORTED 0x8UL 6995 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED 0x10UL 6996 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TX_EEM_FLOW_SUPPORTED 0x20UL 6997 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RX_EEM_FLOW_SUPPORTED 0x40UL 6998 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED 0x80UL 6999 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_SUPPORTED 0x100UL 7000 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_UNTAGGED_VLAN_SUPPORTED 0x200UL 7001 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_XDP_SUPPORTED 0x400UL 7002 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_HEADER_SOURCE_FIELDS_SUPPORTED 0x800UL 7003 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ARP_SUPPORTED 0x1000UL 7004 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_RFS_RING_TBL_IDX_V2_SUPPORTED 0x2000UL 7005 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED 0x4000UL 7006 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_TRUFLOW_CAPABLE 0x8000UL 7007 + #define CFA_ADV_FLOW_MGNT_QCAPS_RESP_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED 0x10000UL 7146 7008 u8 unused_0[3]; 7147 7009 u8 valid; 7148 7010 }; ··· 7614 7472 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 7615 7473 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 7616 7474 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 7617 - #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 7475 + #define STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 0xc8UL 7476 + #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_MSIX_PER_VF 7618 7477 __le16 len; 7619 7478 u8 version; 7620 7479 u8 count; ··· 8143 8000 struct coredump_data_hdr { 8144 8001 __le32 address; 8145 8002 __le32 flags_length; 8003 + #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_MASK 0xffffffUL 8004 + #define COREDUMP_DATA_HDR_FLAGS_LENGTH_ACTUAL_LEN_SFT 0 8005 + #define COREDUMP_DATA_HDR_FLAGS_LENGTH_INDIRECT_ACCESS 0x1000000UL 8146 8006 __le32 instance; 8147 8007 __le32 next_offset; 8148 8008 }; ··· 8815 8669 #define HCOMM_STATUS_TRUE_OFFSET_MASK 0xfffffffcUL 8816 8670 #define HCOMM_STATUS_TRUE_OFFSET_SFT 2 8817 8671 }; 8818 - 8819 8672 #define HCOMM_STATUS_STRUCT_LOC 0x31001F0UL 8820 8673 8821 8674 #endif /* _BNXT_HSI_H_ */

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