Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-bindings: usb: snps,dwc3: Split core description
The Synopsys DWC3 core is found either as a standalone block or
integrated with vendor glue logic. So far the latter has been described
as two separate IP blocks in DeviceTree, but the two parts are not
separate.
In the case where the core is integrated together with vendor glue,
resources such as clock and resets are often customized by the vendor,
such that the standard properties doesn't make sense.
Split the snps,dwc3 binding in a description of the core properties and
the standard "glue" properties, in order to allow vendor bindings to
inherit the core properties.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250113-dwc3-refactor-v3-1-d1722075df7b@oss.qualcomm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Bjorn Andersson
and committed by
Greg Kroah-Hartman
6d7965fb
cde1e61d
+416
-390
+415
Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
+415
Documentation/devicetree/bindings/usb/snps,dwc3-common.yaml
···
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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/usb/snps,dwc3-common.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare USB3 Controller common properties
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maintainers:
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- Felipe Balbi <balbi@kernel.org>
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description:
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Defines the properties of the DWC3 core as being embedded in either an
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vendor-specific implementation or as a standalone component.
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allOf:
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- $ref: usb-drd.yaml#
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- if:
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properties:
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dr_mode:
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const: peripheral
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required:
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- dr_mode
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then:
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$ref: usb.yaml#
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else:
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$ref: usb-xhci.yaml#
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properties:
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extcon:
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maxItems: 1
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deprecated: true
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+
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usb-phy:
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minItems: 1
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items:
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- description: USB2/HS PHY
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- description: USB3/SS PHY
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+
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phys:
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minItems: 1
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maxItems: 19
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+
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phy-names:
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minItems: 1
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maxItems: 19
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oneOf:
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- items:
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enum: [ usb2-phy, usb3-phy ]
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- items:
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pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
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snps,usb2-lpm-disable:
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description: Indicate if we don't want to enable USB2 HW LPM for host
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mode.
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type: boolean
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+
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snps,usb3_lpm_capable:
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description: Determines if platform is USB3 LPM capable
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type: boolean
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+
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snps,usb2-gadget-lpm-disable:
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description: Indicate if we don't want to enable USB2 HW LPM for gadget
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mode.
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type: boolean
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+
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snps,dis-start-transfer-quirk:
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description:
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When set, disable isoc START TRANSFER command failure SW work-around
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for DWC_usb31 version 1.70a-ea06 and prior.
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type: boolean
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+
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snps,disable_scramble_quirk:
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description:
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True when SW should disable data scrambling. Only really useful for FPGA
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builds.
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type: boolean
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+
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snps,has-lpm-erratum:
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description: True when DWC3 was configured with LPM Erratum enabled
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type: boolean
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+
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snps,lpm-nyet-threshold:
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description: LPM NYET threshold
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$ref: /schemas/types.yaml#/definitions/uint8
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+
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snps,u2exit_lfps_quirk:
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description: Set if we want to enable u2exit lfps quirk
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type: boolean
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+
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snps,u2ss_inp3_quirk:
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description: Set if we enable P3 OK for U2/SS Inactive quirk
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type: boolean
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+
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snps,req_p1p2p3_quirk:
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description:
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When set, the core will always request for P1/P2/P3 transition sequence.
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type: boolean
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+
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snps,del_p1p2p3_quirk:
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description:
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When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
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occur.
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type: boolean
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+
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snps,del_phy_power_chg_quirk:
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description: When set core will delay PHY power change from P0 to P1/P2/P3.
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type: boolean
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+
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snps,lfps_filter_quirk:
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description: When set core will filter LFPS reception.
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type: boolean
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+
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snps,rx_detect_poll_quirk:
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description:
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when set core will disable a 400us delay to start Polling LFPS after
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RX.Detect.
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type: boolean
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+
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snps,tx_de_emphasis_quirk:
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description: When set core will set Tx de-emphasis value
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type: boolean
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+
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snps,tx_de_emphasis:
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description:
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The value driven to the PHY is controlled by the LTSSM during USB3
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Compliance mode.
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$ref: /schemas/types.yaml#/definitions/uint8
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enum:
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- 0 # -6dB de-emphasis
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- 1 # -3.5dB de-emphasis
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- 2 # No de-emphasis
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snps,dis_u3_susphy_quirk:
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description: When set core will disable USB3 suspend phy
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type: boolean
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+
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snps,dis_u2_susphy_quirk:
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description: When set core will disable USB2 suspend phy
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type: boolean
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+
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snps,dis_enblslpm_quirk:
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description:
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When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
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to the PHY.
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type: boolean
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+
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snps,dis-u1-entry-quirk:
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description: Set if link entering into U1 needs to be disabled
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type: boolean
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snps,dis-u2-entry-quirk:
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description: Set if link entering into U2 needs to be disabled
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type: boolean
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+
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snps,dis_rxdet_inp3_quirk:
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description:
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When set core will disable receiver detection in PHY P3 power state.
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type: boolean
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+
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snps,dis-u2-freeclk-exists-quirk:
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description:
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When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
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PHY doesn't provide a free-running PHY clock.
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type: boolean
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+
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snps,dis-del-phy-power-chg-quirk:
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description:
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When set core will change PHY power from P0 to P1/P2/P3 without delay.
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type: boolean
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+
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snps,dis-tx-ipgap-linecheck-quirk:
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description: When set, disable u2mac linestate check during HS transmit
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type: boolean
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+
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snps,parkmode-disable-ss-quirk:
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description:
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When set, all SuperSpeed bus instances in park mode are disabled.
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type: boolean
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+
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snps,parkmode-disable-hs-quirk:
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description:
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When set, all HighSpeed bus instances in park mode are disabled.
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type: boolean
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+
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snps,dis_metastability_quirk:
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description:
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When set, disable metastability workaround. CAUTION! Use only if you are
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absolutely sure of it.
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type: boolean
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+
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snps,dis-split-quirk:
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description:
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When set, change the way URBs are handled by the driver. Needed to
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avoid -EPROTO errors with usbhid on some devices (Hikey 970).
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type: boolean
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+
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snps,gfladj-refclk-lpm-sel-quirk:
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description:
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When set, run the SOF/ITP counter based on ref_clk.
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type: boolean
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+
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snps,resume-hs-terminations:
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description:
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Fix the issue of HS terminations CRC error on resume by enabling this
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quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
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of resume. This option is to support certain legacy ULPI PHYs.
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type: boolean
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+
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snps,ulpi-ext-vbus-drv:
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description:
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Some ULPI USB PHY does not support internal VBUS supply, and driving
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the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
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bit. When set, the xhci host will configure the USB2 PHY drives VBUS
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with an external supply.
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type: boolean
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+
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snps,is-utmi-l1-suspend:
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description:
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True when DWC3 asserts output signal utmi_l1_suspend_n, false when
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asserts utmi_sleep_n.
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type: boolean
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+
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snps,hird-threshold:
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description: HIRD threshold
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$ref: /schemas/types.yaml#/definitions/uint8
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+
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snps,hsphy_interface:
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description:
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High-Speed PHY interface selection between UTMI+ and ULPI when the
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DWC_USB3_HSPHY_INTERFACE has value 3.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [utmi, ulpi]
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snps,quirk-frame-length-adjustment:
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description:
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Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
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length adjustment when the fladj_30mhz_sdbnd signal is invalid or
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incorrect.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 0x3f
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+
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snps,ref-clock-period-ns:
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description:
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Value for REFCLKPER field of GUCTL register for reference clock period in
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nanoseconds, when the hardware set default does not match the actual
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clock.
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This binding is deprecated. Instead, provide an appropriate reference clock.
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minimum: 8
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maximum: 62
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deprecated: true
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+
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snps,rx-thr-num-pkt:
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description:
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USB RX packet threshold count. In host mode, this field specifies
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the space that must be available in the RX FIFO before the core can
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start the corresponding USB RX transaction (burst).
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In device mode, this field specifies the space that must be
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available in the RX FIFO before the core can send ERDY for a
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flow-controlled endpoint. It is only used for SuperSpeed.
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The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
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USB 3.0 Controller Databook)
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 15
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+
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snps,rx-max-burst:
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description:
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Max USB RX burst size. In host mode, this field specifies the
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Maximum Bulk IN burst the DWC_usb3 core can perform. When the system
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bus is slower than the USB, RX FIFO can overrun during a long burst.
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You can program a smaller value to this field to limit the RX burst
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size that the core can perform. It only applies to SS Bulk,
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Isochronous, and Interrupt IN endpoints in the host mode.
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In device mode, this field specifies the NUMP value that is sent in
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ERDY for an OUT endpoint.
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The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
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USB 3.0 Controller Databook)
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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+
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snps,tx-thr-num-pkt:
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description:
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USB TX packet threshold count. This field specifies the number of
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packets that must be in the TXFIFO before the core can start
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transmission for the corresponding USB transaction (burst).
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This count is valid in both host and device modes. It is only used
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for SuperSpeed operation.
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Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
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Databook)
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 15
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snps,tx-max-burst:
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description:
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Max USB TX burst size. When the system bus is slower than the USB,
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TX FIFO can underrun during a long burst. Program a smaller value
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to this field to limit the TX burst size that the core can execute.
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In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
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OUT endpoints. This value is not used in device mode.
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Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
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Databook)
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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+
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snps,rx-thr-num-pkt-prd:
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description:
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Periodic ESS RX packet threshold count (host mode only). Set this and
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snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.4) to enable periodic ESS RX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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+
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snps,rx-max-burst-prd:
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description:
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Max periodic ESS RX burst size (host mode only). Set this and
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snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.4) to enable periodic ESS RX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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+
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snps,tx-thr-num-pkt-prd:
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description:
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Periodic ESS TX packet threshold count (host mode only). Set this and
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snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.3) to enable periodic ESS TX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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+
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snps,tx-max-burst-prd:
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description:
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Max periodic ESS TX burst size (host mode only). Set this and
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snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
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programming guide section 1.2.3) to enable periodic ESS TX threshold.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 1
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maximum: 16
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+
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tx-fifo-resize:
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description: Determines if the TX fifos can be dynamically resized depending
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on the number of IN endpoints used and if bursting is supported. This
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may help improve bandwidth on platforms with higher system latencies, as
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increased fifo space allows for the controller to prefetch data into its
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internal memory.
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type: boolean
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+
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tx-fifo-max-num:
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description: Specifies the max number of packets the txfifo resizing logic
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can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
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higher the number, the more fifo space the txfifo resizing logic will
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allocate for that endpoint.
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$ref: /schemas/types.yaml#/definitions/uint8
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minimum: 3
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+
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snps,incr-burst-type-adjustment:
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description:
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Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
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burst type enable and INCRx type. A single value means INCRX burst mode
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enabled. If more than one value specified, undefined length INCR burst
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type will be enabled with burst lengths utilized up to the maximum
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of the values passed in this property.
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$ref: /schemas/types.yaml#/definitions/uint32-array
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minItems: 1
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+
maxItems: 8
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uniqueItems: true
375
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items:
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enum: [1, 4, 8, 16, 32, 64, 128, 256]
377
+
378
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num-hc-interrupters:
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maximum: 8
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default: 1
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+
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port:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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This port is used with the 'usb-role-switch' property to connect the
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dwc3 to type C connector.
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+
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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description:
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Those ports should be used with any connector to the data bus of this
392
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controller using the OF graph bindings specified if the "usb-role-switch"
393
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property is used.
394
+
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: High Speed (HS) data bus.
399
+
400
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: Super Speed (SS) data bus.
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+
404
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wakeup-source:
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$ref: /schemas/types.yaml#/definitions/flag
406
+
description:
407
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Enable USB remote wakeup.
408
+
409
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required:
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- compatible
411
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- reg
412
+
413
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additionalProperties: true
414
+
...
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+1
-390
Documentation/devicetree/bindings/usb/snps,dwc3.yaml
+1
-390
Documentation/devicetree/bindings/usb/snps,dwc3.yaml
···
15
15
compatible string.
16
16
17
17
allOf:
18
-
- $ref: usb-drd.yaml#
19
-
- if:
20
-
properties:
21
-
dr_mode:
22
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const: peripheral
23
-
24
-
required:
25
-
- dr_mode
26
-
then:
27
-
$ref: usb.yaml#
28
-
else:
29
-
$ref: usb-xhci.yaml#
18
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- $ref: snps,dwc3-common.yaml#
30
19
31
20
properties:
32
21
compatible:
···
59
70
60
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dma-coherent: true
61
72
62
-
extcon:
63
-
maxItems: 1
64
-
deprecated: true
65
-
66
73
iommus:
67
74
maxItems: 1
68
-
69
-
usb-phy:
70
-
minItems: 1
71
-
items:
72
-
- description: USB2/HS PHY
73
-
- description: USB3/SS PHY
74
-
75
-
phys:
76
-
minItems: 1
77
-
maxItems: 19
78
-
79
-
phy-names:
80
-
minItems: 1
81
-
maxItems: 19
82
-
oneOf:
83
-
- items:
84
-
enum: [ usb2-phy, usb3-phy ]
85
-
- items:
86
-
pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$"
87
75
88
76
power-domains:
89
77
description:
···
74
108
75
109
resets:
76
110
minItems: 1
77
-
78
-
snps,usb2-lpm-disable:
79
-
description: Indicate if we don't want to enable USB2 HW LPM for host
80
-
mode.
81
-
type: boolean
82
-
83
-
snps,usb3_lpm_capable:
84
-
description: Determines if platform is USB3 LPM capable
85
-
type: boolean
86
-
87
-
snps,usb2-gadget-lpm-disable:
88
-
description: Indicate if we don't want to enable USB2 HW LPM for gadget
89
-
mode.
90
-
type: boolean
91
-
92
-
snps,dis-start-transfer-quirk:
93
-
description:
94
-
When set, disable isoc START TRANSFER command failure SW work-around
95
-
for DWC_usb31 version 1.70a-ea06 and prior.
96
-
type: boolean
97
-
98
-
snps,disable_scramble_quirk:
99
-
description:
100
-
True when SW should disable data scrambling. Only really useful for FPGA
101
-
builds.
102
-
type: boolean
103
-
104
-
snps,has-lpm-erratum:
105
-
description: True when DWC3 was configured with LPM Erratum enabled
106
-
type: boolean
107
-
108
-
snps,lpm-nyet-threshold:
109
-
description: LPM NYET threshold
110
-
$ref: /schemas/types.yaml#/definitions/uint8
111
-
112
-
snps,u2exit_lfps_quirk:
113
-
description: Set if we want to enable u2exit lfps quirk
114
-
type: boolean
115
-
116
-
snps,u2ss_inp3_quirk:
117
-
description: Set if we enable P3 OK for U2/SS Inactive quirk
118
-
type: boolean
119
-
120
-
snps,req_p1p2p3_quirk:
121
-
description:
122
-
When set, the core will always request for P1/P2/P3 transition sequence.
123
-
type: boolean
124
-
125
-
snps,del_p1p2p3_quirk:
126
-
description:
127
-
When set core will delay P1/P2/P3 until a certain amount of 8B10B errors
128
-
occur.
129
-
type: boolean
130
-
131
-
snps,del_phy_power_chg_quirk:
132
-
description: When set core will delay PHY power change from P0 to P1/P2/P3.
133
-
type: boolean
134
-
135
-
snps,lfps_filter_quirk:
136
-
description: When set core will filter LFPS reception.
137
-
type: boolean
138
-
139
-
snps,rx_detect_poll_quirk:
140
-
description:
141
-
when set core will disable a 400us delay to start Polling LFPS after
142
-
RX.Detect.
143
-
type: boolean
144
-
145
-
snps,tx_de_emphasis_quirk:
146
-
description: When set core will set Tx de-emphasis value
147
-
type: boolean
148
-
149
-
snps,tx_de_emphasis:
150
-
description:
151
-
The value driven to the PHY is controlled by the LTSSM during USB3
152
-
Compliance mode.
153
-
$ref: /schemas/types.yaml#/definitions/uint8
154
-
enum:
155
-
- 0 # -6dB de-emphasis
156
-
- 1 # -3.5dB de-emphasis
157
-
- 2 # No de-emphasis
158
-
159
-
snps,dis_u3_susphy_quirk:
160
-
description: When set core will disable USB3 suspend phy
161
-
type: boolean
162
-
163
-
snps,dis_u2_susphy_quirk:
164
-
description: When set core will disable USB2 suspend phy
165
-
type: boolean
166
-
167
-
snps,dis_enblslpm_quirk:
168
-
description:
169
-
When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal
170
-
to the PHY.
171
-
type: boolean
172
-
173
-
snps,dis-u1-entry-quirk:
174
-
description: Set if link entering into U1 needs to be disabled
175
-
type: boolean
176
-
177
-
snps,dis-u2-entry-quirk:
178
-
description: Set if link entering into U2 needs to be disabled
179
-
type: boolean
180
-
181
-
snps,dis_rxdet_inp3_quirk:
182
-
description:
183
-
When set core will disable receiver detection in PHY P3 power state.
184
-
type: boolean
185
-
186
-
snps,dis-u2-freeclk-exists-quirk:
187
-
description:
188
-
When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2
189
-
PHY doesn't provide a free-running PHY clock.
190
-
type: boolean
191
-
192
-
snps,dis-del-phy-power-chg-quirk:
193
-
description:
194
-
When set core will change PHY power from P0 to P1/P2/P3 without delay.
195
-
type: boolean
196
-
197
-
snps,dis-tx-ipgap-linecheck-quirk:
198
-
description: When set, disable u2mac linestate check during HS transmit
199
-
type: boolean
200
-
201
-
snps,parkmode-disable-ss-quirk:
202
-
description:
203
-
When set, all SuperSpeed bus instances in park mode are disabled.
204
-
type: boolean
205
-
206
-
snps,parkmode-disable-hs-quirk:
207
-
description:
208
-
When set, all HighSpeed bus instances in park mode are disabled.
209
-
type: boolean
210
-
211
-
snps,dis_metastability_quirk:
212
-
description:
213
-
When set, disable metastability workaround. CAUTION! Use only if you are
214
-
absolutely sure of it.
215
-
type: boolean
216
-
217
-
snps,dis-split-quirk:
218
-
description:
219
-
When set, change the way URBs are handled by the driver. Needed to
220
-
avoid -EPROTO errors with usbhid on some devices (Hikey 970).
221
-
type: boolean
222
-
223
-
snps,gfladj-refclk-lpm-sel-quirk:
224
-
description:
225
-
When set, run the SOF/ITP counter based on ref_clk.
226
-
type: boolean
227
-
228
-
snps,resume-hs-terminations:
229
-
description:
230
-
Fix the issue of HS terminations CRC error on resume by enabling this
231
-
quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end
232
-
of resume. This option is to support certain legacy ULPI PHYs.
233
-
type: boolean
234
-
235
-
snps,ulpi-ext-vbus-drv:
236
-
description:
237
-
Some ULPI USB PHY does not support internal VBUS supply, and driving
238
-
the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL
239
-
bit. When set, the xhci host will configure the USB2 PHY drives VBUS
240
-
with an external supply.
241
-
type: boolean
242
-
243
-
snps,is-utmi-l1-suspend:
244
-
description:
245
-
True when DWC3 asserts output signal utmi_l1_suspend_n, false when
246
-
asserts utmi_sleep_n.
247
-
type: boolean
248
-
249
-
snps,hird-threshold:
250
-
description: HIRD threshold
251
-
$ref: /schemas/types.yaml#/definitions/uint8
252
-
253
-
snps,hsphy_interface:
254
-
description:
255
-
High-Speed PHY interface selection between UTMI+ and ULPI when the
256
-
DWC_USB3_HSPHY_INTERFACE has value 3.
257
-
$ref: /schemas/types.yaml#/definitions/string
258
-
enum: [utmi, ulpi]
259
-
260
-
snps,quirk-frame-length-adjustment:
261
-
description:
262
-
Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame
263
-
length adjustment when the fladj_30mhz_sdbnd signal is invalid or
264
-
incorrect.
265
-
$ref: /schemas/types.yaml#/definitions/uint32
266
-
minimum: 0
267
-
maximum: 0x3f
268
-
269
-
snps,ref-clock-period-ns:
270
-
description:
271
-
Value for REFCLKPER field of GUCTL register for reference clock period in
272
-
nanoseconds, when the hardware set default does not match the actual
273
-
clock.
274
-
275
-
This binding is deprecated. Instead, provide an appropriate reference clock.
276
-
minimum: 8
277
-
maximum: 62
278
-
deprecated: true
279
-
280
-
snps,rx-thr-num-pkt:
281
-
description:
282
-
USB RX packet threshold count. In host mode, this field specifies
283
-
the space that must be available in the RX FIFO before the core can
284
-
start the corresponding USB RX transaction (burst).
285
-
In device mode, this field specifies the space that must be
286
-
available in the RX FIFO before the core can send ERDY for a
287
-
flow-controlled endpoint. It is only used for SuperSpeed.
288
-
The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
289
-
USB 3.0 Controller Databook)
290
-
$ref: /schemas/types.yaml#/definitions/uint8
291
-
minimum: 1
292
-
maximum: 15
293
-
294
-
snps,rx-max-burst:
295
-
description:
296
-
Max USB RX burst size. In host mode, this field specifies the
297
-
Maximum Bulk IN burst the DWC_usb3 core can perform. When the system
298
-
bus is slower than the USB, RX FIFO can overrun during a long burst.
299
-
You can program a smaller value to this field to limit the RX burst
300
-
size that the core can perform. It only applies to SS Bulk,
301
-
Isochronous, and Interrupt IN endpoints in the host mode.
302
-
In device mode, this field specifies the NUMP value that is sent in
303
-
ERDY for an OUT endpoint.
304
-
The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
305
-
USB 3.0 Controller Databook)
306
-
$ref: /schemas/types.yaml#/definitions/uint8
307
-
minimum: 1
308
-
maximum: 16
309
-
310
-
snps,tx-thr-num-pkt:
311
-
description:
312
-
USB TX packet threshold count. This field specifies the number of
313
-
packets that must be in the TXFIFO before the core can start
314
-
transmission for the corresponding USB transaction (burst).
315
-
This count is valid in both host and device modes. It is only used
316
-
for SuperSpeed operation.
317
-
Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller
318
-
Databook)
319
-
$ref: /schemas/types.yaml#/definitions/uint8
320
-
minimum: 1
321
-
maximum: 15
322
-
323
-
snps,tx-max-burst:
324
-
description:
325
-
Max USB TX burst size. When the system bus is slower than the USB,
326
-
TX FIFO can underrun during a long burst. Program a smaller value
327
-
to this field to limit the TX burst size that the core can execute.
328
-
In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt
329
-
OUT endpoints. This value is not used in device mode.
330
-
Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller
331
-
Databook)
332
-
$ref: /schemas/types.yaml#/definitions/uint8
333
-
minimum: 1
334
-
maximum: 16
335
-
336
-
snps,rx-thr-num-pkt-prd:
337
-
description:
338
-
Periodic ESS RX packet threshold count (host mode only). Set this and
339
-
snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
340
-
programming guide section 1.2.4) to enable periodic ESS RX threshold.
341
-
$ref: /schemas/types.yaml#/definitions/uint8
342
-
minimum: 1
343
-
maximum: 16
344
-
345
-
snps,rx-max-burst-prd:
346
-
description:
347
-
Max periodic ESS RX burst size (host mode only). Set this and
348
-
snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
349
-
programming guide section 1.2.4) to enable periodic ESS RX threshold.
350
-
$ref: /schemas/types.yaml#/definitions/uint8
351
-
minimum: 1
352
-
maximum: 16
353
-
354
-
snps,tx-thr-num-pkt-prd:
355
-
description:
356
-
Periodic ESS TX packet threshold count (host mode only). Set this and
357
-
snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31
358
-
programming guide section 1.2.3) to enable periodic ESS TX threshold.
359
-
$ref: /schemas/types.yaml#/definitions/uint8
360
-
minimum: 1
361
-
maximum: 16
362
-
363
-
snps,tx-max-burst-prd:
364
-
description:
365
-
Max periodic ESS TX burst size (host mode only). Set this and
366
-
snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31
367
-
programming guide section 1.2.3) to enable periodic ESS TX threshold.
368
-
$ref: /schemas/types.yaml#/definitions/uint8
369
-
minimum: 1
370
-
maximum: 16
371
-
372
-
tx-fifo-resize:
373
-
description: Determines if the TX fifos can be dynamically resized depending
374
-
on the number of IN endpoints used and if bursting is supported. This
375
-
may help improve bandwidth on platforms with higher system latencies, as
376
-
increased fifo space allows for the controller to prefetch data into its
377
-
internal memory.
378
-
type: boolean
379
-
380
-
tx-fifo-max-num:
381
-
description: Specifies the max number of packets the txfifo resizing logic
382
-
can account for when higher endpoint bursting is used. (bMaxBurst > 6) The
383
-
higher the number, the more fifo space the txfifo resizing logic will
384
-
allocate for that endpoint.
385
-
$ref: /schemas/types.yaml#/definitions/uint8
386
-
minimum: 3
387
-
388
-
snps,incr-burst-type-adjustment:
389
-
description:
390
-
Value for INCR burst type of GSBUSCFG0 register, undefined length INCR
391
-
burst type enable and INCRx type. A single value means INCRX burst mode
392
-
enabled. If more than one value specified, undefined length INCR burst
393
-
type will be enabled with burst lengths utilized up to the maximum
394
-
of the values passed in this property.
395
-
$ref: /schemas/types.yaml#/definitions/uint32-array
396
-
minItems: 1
397
-
maxItems: 8
398
-
uniqueItems: true
399
-
items:
400
-
enum: [1, 4, 8, 16, 32, 64, 128, 256]
401
-
402
-
num-hc-interrupters:
403
-
maximum: 8
404
-
default: 1
405
-
406
-
port:
407
-
$ref: /schemas/graph.yaml#/properties/port
408
-
description:
409
-
This port is used with the 'usb-role-switch' property to connect the
410
-
dwc3 to type C connector.
411
-
412
-
ports:
413
-
$ref: /schemas/graph.yaml#/properties/ports
414
-
description:
415
-
Those ports should be used with any connector to the data bus of this
416
-
controller using the OF graph bindings specified if the "usb-role-switch"
417
-
property is used.
418
-
419
-
properties:
420
-
port@0:
421
-
$ref: /schemas/graph.yaml#/properties/port
422
-
description: High Speed (HS) data bus.
423
-
424
-
port@1:
425
-
$ref: /schemas/graph.yaml#/properties/port
426
-
description: Super Speed (SS) data bus.
427
-
428
-
wakeup-source:
429
-
$ref: /schemas/types.yaml#/definitions/flag
430
-
description:
431
-
Enable USB remote wakeup.
432
111
433
112
unevaluatedProperties: false
434
113