Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-intel-next-2022-07-06' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Suspend fixes for Display (Jose)
- Properly block D3Cold for now (Anshuman)
- Eliminate PIPECONF RMWs from .color_commit()(Ville)
- Display info clean-up (Ville)
- Fix error code (Dan)
- Fix possible refcount leak on DP MST (Hangyu)
- Other general display clean-ups (Jani, Tom)
- Add bios debug logs (Jani)
- PCH type clean-up (Ville)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YsZNJUVh0iHOtORz@intel.com
+192
-192
+6
-2
drivers/gpu/drm/i915/display/intel_bios.c
+6
-2
drivers/gpu/drm/i915/display/intel_bios.c
···
2670
2670
2671
2671
sanitize_device_type(devdata, port);
2672
2672
2673
-
print_ddi_port(devdata, port);
2674
-
2675
2673
if (intel_bios_encoder_supports_dvi(devdata))
2676
2674
sanitize_ddc_pin(devdata, port);
2677
2675
···
2687
2689
static void parse_ddi_ports(struct drm_i915_private *i915)
2688
2690
{
2689
2691
struct intel_bios_encoder_data *devdata;
2692
+
enum port port;
2690
2693
2691
2694
if (!has_ddi_port_info(i915))
2692
2695
return;
2693
2696
2694
2697
list_for_each_entry(devdata, &i915->vbt.display_devices, node)
2695
2698
parse_ddi_port(devdata);
2699
+
2700
+
for_each_port(port) {
2701
+
if (i915->vbt.ports[port])
2702
+
print_ddi_port(i915->vbt.ports[port], port);
2703
+
}
2696
2704
}
2697
2705
2698
2706
static void
+19
-30
drivers/gpu/drm/i915/display/intel_color.c
+19
-30
drivers/gpu/drm/i915/display/intel_color.c
···
505
505
506
506
static void i9xx_color_commit_arm(const struct intel_crtc_state *crtc_state)
507
507
{
508
-
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
509
-
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
510
-
enum pipe pipe = crtc->pipe;
511
-
u32 val;
512
-
513
-
val = intel_de_read(dev_priv, PIPECONF(pipe));
514
-
val &= ~PIPECONF_GAMMA_MODE_MASK_I9XX;
515
-
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
516
-
intel_de_write(dev_priv, PIPECONF(pipe), val);
508
+
/* update PIPECONF GAMMA_MODE */
509
+
i9xx_set_pipeconf(crtc_state);
517
510
}
518
511
519
512
static void ilk_color_commit_arm(const struct intel_crtc_state *crtc_state)
520
513
{
521
514
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
522
515
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
523
-
enum pipe pipe = crtc->pipe;
524
-
u32 val;
525
516
526
-
val = intel_de_read(dev_priv, PIPECONF(pipe));
527
-
val &= ~PIPECONF_GAMMA_MODE_MASK_ILK;
528
-
val |= PIPECONF_GAMMA_MODE(crtc_state->gamma_mode);
529
-
intel_de_write(dev_priv, PIPECONF(pipe), val);
517
+
/* update PIPECONF GAMMA_MODE */
518
+
ilk_set_pipeconf(crtc_state);
530
519
531
-
intel_de_write_fw(dev_priv, PIPE_CSC_MODE(pipe),
520
+
intel_de_write_fw(dev_priv, PIPE_CSC_MODE(crtc->pipe),
532
521
crtc_state->csc_mode);
533
522
}
534
523
···
841
852
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
842
853
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
843
854
enum pipe pipe = crtc->pipe;
844
-
int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
855
+
int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
845
856
const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
846
857
847
858
/*
···
883
894
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
884
895
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
885
896
enum pipe pipe = crtc->pipe;
886
-
int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
897
+
int i, lut_size = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
887
898
888
899
/*
889
900
* When setting the auto-increment bit, the hardware seems to
···
1335
1346
return -EINVAL;
1336
1347
}
1337
1348
1338
-
degamma_length = INTEL_INFO(dev_priv)->color.degamma_lut_size;
1339
-
gamma_length = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1340
-
degamma_tests = INTEL_INFO(dev_priv)->color.degamma_lut_tests;
1341
-
gamma_tests = INTEL_INFO(dev_priv)->color.gamma_lut_tests;
1349
+
degamma_length = INTEL_INFO(dev_priv)->display.color.degamma_lut_size;
1350
+
gamma_length = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
1351
+
degamma_tests = INTEL_INFO(dev_priv)->display.color.degamma_lut_tests;
1352
+
gamma_tests = INTEL_INFO(dev_priv)->display.color.gamma_lut_tests;
1342
1353
1343
1354
if (check_lut_size(degamma_lut, degamma_length) ||
1344
1355
check_lut_size(gamma_lut, gamma_length))
···
1874
1885
static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
1875
1886
{
1876
1887
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1877
-
int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1888
+
int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
1878
1889
enum pipe pipe = crtc->pipe;
1879
1890
struct drm_property_blob *blob;
1880
1891
struct drm_color_lut *lut;
···
1917
1928
static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
1918
1929
{
1919
1930
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1920
-
int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1931
+
int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
1921
1932
enum pipe pipe = crtc->pipe;
1922
1933
struct drm_property_blob *blob;
1923
1934
struct drm_color_lut *lut;
···
1978
1989
static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
1979
1990
{
1980
1991
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1981
-
int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
1992
+
int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
1982
1993
enum pipe pipe = crtc->pipe;
1983
1994
struct drm_property_blob *blob;
1984
1995
struct drm_color_lut *lut;
···
2029
2040
{
2030
2041
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2031
2042
int i, hw_lut_size = ivb_lut_10_size(prec_index);
2032
-
int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
2043
+
int lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
2033
2044
enum pipe pipe = crtc->pipe;
2034
2045
struct drm_property_blob *blob;
2035
2046
struct drm_color_lut *lut;
···
2082
2093
icl_read_lut_multi_segment(struct intel_crtc *crtc)
2083
2094
{
2084
2095
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2085
-
int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
2096
+
int i, lut_size = INTEL_INFO(dev_priv)->display.color.gamma_lut_size;
2086
2097
enum pipe pipe = crtc->pipe;
2087
2098
struct drm_property_blob *blob;
2088
2099
struct drm_color_lut *lut;
···
2219
2230
void intel_color_init(struct intel_crtc *crtc)
2220
2231
{
2221
2232
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2222
-
bool has_ctm = INTEL_INFO(dev_priv)->color.degamma_lut_size != 0;
2233
+
bool has_ctm = INTEL_INFO(dev_priv)->display.color.degamma_lut_size != 0;
2223
2234
2224
2235
drm_mode_crtc_set_gamma_size(&crtc->base, 256);
2225
2236
···
2250
2261
}
2251
2262
2252
2263
drm_crtc_enable_color_mgmt(&crtc->base,
2253
-
INTEL_INFO(dev_priv)->color.degamma_lut_size,
2264
+
INTEL_INFO(dev_priv)->display.color.degamma_lut_size,
2254
2265
has_ctm,
2255
-
INTEL_INFO(dev_priv)->color.gamma_lut_size);
2266
+
INTEL_INFO(dev_priv)->display.color.gamma_lut_size);
2256
2267
}
+1
-1
drivers/gpu/drm/i915/display/intel_ddi.c
+1
-1
drivers/gpu/drm/i915/display/intel_ddi.c
+22
-8
drivers/gpu/drm/i915/display/intel_display.c
+22
-8
drivers/gpu/drm/i915/display/intel_display.c
···
126
126
127
127
static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
128
128
static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
129
-
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
130
-
static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
131
129
static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
132
130
static void bdw_set_pipemisc(const struct intel_crtc_state *crtc_state);
133
131
static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state);
···
3013
3015
intel_bigjoiner_adjust_pipe_src(pipe_config);
3014
3016
}
3015
3017
3016
-
static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
3018
+
void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
3017
3019
{
3018
3020
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3019
3021
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3020
3022
u32 pipeconf = 0;
3021
3023
3022
-
/* we keep both pipes enabled on 830 */
3023
-
if (IS_I830(dev_priv))
3024
+
/*
3025
+
* - We keep both pipes enabled on 830
3026
+
* - During modeset the pipe is still disabled and must remain so
3027
+
* - During fastset the pipe is already enabled and must remain so
3028
+
*/
3029
+
if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
3024
3030
pipeconf |= PIPECONF_ENABLE;
3025
3031
3026
3032
if (crtc_state->double_wide)
···
3337
3335
return ret;
3338
3336
}
3339
3337
3340
-
static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3338
+
void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3341
3339
{
3342
3340
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3343
3341
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3344
3342
enum pipe pipe = crtc->pipe;
3345
-
u32 val;
3343
+
u32 val = 0;
3346
3344
3347
-
val = 0;
3345
+
/*
3346
+
* - During modeset the pipe is still disabled and must remain so
3347
+
* - During fastset the pipe is already enabled and must remain so
3348
+
*/
3349
+
if (!intel_crtc_needs_modeset(crtc_state))
3350
+
val |= PIPECONF_ENABLE;
3348
3351
3349
3352
switch (crtc_state->pipe_bpp) {
3350
3353
default:
···
3407
3400
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3408
3401
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3409
3402
u32 val = 0;
3403
+
3404
+
/*
3405
+
* - During modeset the pipe is still disabled and must remain so
3406
+
* - During fastset the pipe is already enabled and must remain so
3407
+
*/
3408
+
if (!intel_crtc_needs_modeset(crtc_state))
3409
+
val |= PIPECONF_ENABLE;
3410
3410
3411
3411
if (IS_HASWELL(dev_priv) && crtc_state->dither)
3412
3412
val |= PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP;
+3
-1
drivers/gpu/drm/i915/display/intel_display.h
+3
-1
drivers/gpu/drm/i915/display/intel_display.h
···
193
193
194
194
#define for_each_dbuf_slice(__dev_priv, __slice) \
195
195
for ((__slice) = DBUF_S1; (__slice) < I915_MAX_DBUF_SLICES; (__slice)++) \
196
-
for_each_if(INTEL_INFO(__dev_priv)->dbuf.slice_mask & BIT(__slice))
196
+
for_each_if(INTEL_INFO(__dev_priv)->display.dbuf.slice_mask & BIT(__slice))
197
197
198
198
#define for_each_dbuf_slice_in_mask(__dev_priv, __slice, __mask) \
199
199
for_each_dbuf_slice((__dev_priv), (__slice)) \
···
567
567
void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state);
568
568
569
569
void intel_plane_destroy(struct drm_plane *plane);
570
+
void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);
571
+
void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);
570
572
void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state);
571
573
void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state);
572
574
void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe);
+2
-2
drivers/gpu/drm/i915/display/intel_display_power.c
+2
-2
drivers/gpu/drm/i915/display/intel_display_power.c
···
1038
1038
u8 req_slices)
1039
1039
{
1040
1040
struct i915_power_domains *power_domains = &dev_priv->power_domains;
1041
-
u8 slice_mask = INTEL_INFO(dev_priv)->dbuf.slice_mask;
1041
+
u8 slice_mask = INTEL_INFO(dev_priv)->display.dbuf.slice_mask;
1042
1042
enum dbuf_slice slice;
1043
1043
1044
1044
drm_WARN(&dev_priv->drm, req_slices & ~slice_mask,
···
1608
1608
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
1609
1609
1610
1610
/* Wa_14011294188:ehl,jsl,tgl,rkl,adl-s */
1611
-
if (INTEL_PCH_TYPE(dev_priv) >= PCH_JSP &&
1611
+
if (INTEL_PCH_TYPE(dev_priv) >= PCH_TGP &&
1612
1612
INTEL_PCH_TYPE(dev_priv) < PCH_DG1)
1613
1613
intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0,
1614
1614
PCH_DPMGUNIT_CLOCK_GATE_DISABLE);
+1
drivers/gpu/drm/i915/display/intel_dp_mst.c
+1
drivers/gpu/drm/i915/display/intel_dp_mst.c
+1
-1
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+1
-1
drivers/gpu/drm/i915/display/intel_dpll_mgr.c
···
3184
3184
struct icl_port_dpll *port_dpll =
3185
3185
&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3186
3186
struct skl_wrpll_params pll_params = {};
3187
-
bool ret;
3187
+
int ret;
3188
3188
3189
3189
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
3190
3190
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+1
-1
drivers/gpu/drm/i915/display/intel_hdmi.c
+1
-1
drivers/gpu/drm/i915/display/intel_hdmi.c
···
2852
2852
ddc_pin = rkl_port_to_ddc_pin(dev_priv, port);
2853
2853
else if (DISPLAY_VER(dev_priv) == 9 && HAS_PCH_TGP(dev_priv))
2854
2854
ddc_pin = gen9bc_tgp_port_to_ddc_pin(dev_priv, port);
2855
-
else if (HAS_PCH_MCC(dev_priv))
2855
+
else if (IS_JSL_EHL(dev_priv) && HAS_PCH_TGP(dev_priv))
2856
2856
ddc_pin = mcc_port_to_ddc_pin(dev_priv, port);
2857
2857
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
2858
2858
ddc_pin = icl_port_to_ddc_pin(dev_priv, port);
+4
-4
drivers/gpu/drm/i915/display/intel_psr.c
+4
-4
drivers/gpu/drm/i915/display/intel_psr.c
···
555
555
/*
556
556
* TODO: 7 lines of IO_BUFFER_WAKE and FAST_WAKE are default
557
557
* values from BSpec. In order to setting an optimal power
558
-
* consumption, lower than 4k resoluition mode needs to decrese
558
+
* consumption, lower than 4k resolution mode needs to decrease
559
559
* IO_BUFFER_WAKE and FAST_WAKE. And higher than 4K resolution
560
560
* mode needs to increase IO_BUFFER_WAKE and FAST_WAKE.
561
561
*/
···
959
959
int psr_setup_time;
960
960
961
961
/*
962
-
* Current PSR panels dont work reliably with VRR enabled
962
+
* Current PSR panels don't work reliably with VRR enabled
963
963
* So if VRR is enabled, do not enable PSR.
964
964
*/
965
965
if (crtc_state->vrr.enable)
···
1664
1664
*
1665
1665
* Plane scaling and rotation is not supported by selective fetch and both
1666
1666
* properties can change without a modeset, so need to be check at every
1667
-
* atomic commmit.
1667
+
* atomic commit.
1668
1668
*/
1669
1669
static bool psr2_sel_fetch_plane_state_supported(const struct intel_plane_state *plane_state)
1670
1670
{
···
2203
2203
}
2204
2204
2205
2205
/**
2206
-
* intel_psr_invalidate - Invalidade PSR
2206
+
* intel_psr_invalidate - Invalidate PSR
2207
2207
* @dev_priv: i915 device
2208
2208
* @frontbuffer_bits: frontbuffer plane tracking bits
2209
2209
* @origin: which operation caused the invalidate
+20
-24
drivers/gpu/drm/i915/i915_driver.c
+20
-24
drivers/gpu/drm/i915/i915_driver.c
···
549
549
static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
550
550
{
551
551
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
552
+
struct pci_dev *root_pdev;
552
553
int ret;
553
554
554
555
if (i915_inject_probe_failure(dev_priv))
···
661
660
662
661
intel_bw_init_hw(dev_priv);
663
662
663
+
/*
664
+
* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
665
+
* This should be totally removed when we handle the pci states properly
666
+
* on runtime PM and on s2idle cases.
667
+
*/
668
+
root_pdev = pcie_find_root_port(pdev);
669
+
if (root_pdev)
670
+
pci_d3cold_disable(root_pdev);
671
+
664
672
return 0;
665
673
666
674
err_msi:
···
693
683
static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
694
684
{
695
685
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
686
+
struct pci_dev *root_pdev;
696
687
697
688
i915_perf_fini(dev_priv);
698
689
699
690
if (pdev->msi_enabled)
700
691
pci_disable_msi(pdev);
692
+
693
+
root_pdev = pcie_find_root_port(pdev);
694
+
if (root_pdev)
695
+
pci_d3cold_enable(root_pdev);
701
696
}
702
697
703
698
/**
···
847
832
*/
848
833
int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
849
834
{
850
-
const struct intel_device_info *match_info =
851
-
(struct intel_device_info *)ent->driver_data;
852
835
struct drm_i915_private *i915;
853
836
int ret;
854
837
···
855
842
return PTR_ERR(i915);
856
843
857
844
/* Disable nuclear pageflip by default on pre-ILK */
858
-
if (!i915->params.nuclear_pageflip && match_info->graphics.ver < 5)
845
+
if (!i915->params.nuclear_pageflip && DISPLAY_VER(i915) < 5)
859
846
i915->drm.driver_features &= ~DRIVER_ATOMIC;
860
847
861
848
ret = pci_enable_device(pdev);
···
1083
1070
intel_runtime_pm_disable(&i915->runtime_pm);
1084
1071
intel_power_domains_disable(i915);
1085
1072
1086
-
i915_gem_suspend(i915);
1087
-
1088
1073
if (HAS_DISPLAY(i915)) {
1089
1074
drm_kms_helper_poll_disable(&i915->drm);
1090
1075
···
1098
1087
intel_shutdown_encoders(i915);
1099
1088
1100
1089
intel_dmc_ucode_suspend(i915);
1090
+
1091
+
i915_gem_suspend(i915);
1101
1092
1102
1093
/*
1103
1094
* The only requirement is to reboot with display DC states disabled,
···
1184
1171
1185
1172
enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1186
1173
1174
+
i915_gem_drain_freed_objects(dev_priv);
1175
+
1187
1176
return 0;
1188
1177
}
1189
1178
···
1226
1211
1227
1212
goto out;
1228
1213
}
1229
-
1230
-
/*
1231
-
* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1232
-
* This should be totally removed when we handle the pci states properly
1233
-
* on runtime PM and on s2idle cases.
1234
-
*/
1235
-
if (suspend_to_idle(dev_priv))
1236
-
pci_d3cold_disable(pdev);
1237
1214
1238
1215
pci_disable_device(pdev);
1239
1216
/*
···
1390
1383
return -EIO;
1391
1384
1392
1385
pci_set_master(pdev);
1393
-
1394
-
pci_d3cold_enable(pdev);
1395
1386
1396
1387
disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1397
1388
···
1580
1575
{
1581
1576
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1582
1577
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1583
-
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1584
1578
int ret;
1585
1579
1586
1580
if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
···
1625
1621
drm_err(&dev_priv->drm,
1626
1622
"Unclaimed access detected prior to suspending\n");
1627
1623
1628
-
/*
1629
-
* FIXME: Temporary hammer to avoid freezing the machine on our DGFX
1630
-
* This should be totally removed when we handle the pci states properly
1631
-
* on runtime PM and on s2idle cases.
1632
-
*/
1633
-
pci_d3cold_disable(pdev);
1634
1624
rpm->suspended = true;
1635
1625
1636
1626
/*
···
1663
1665
{
1664
1666
struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1665
1667
struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1666
-
struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1667
1668
int ret;
1668
1669
1669
1670
if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
···
1675
1678
1676
1679
intel_opregion_notify_adapter(dev_priv, PCI_D0);
1677
1680
rpm->suspended = false;
1678
-
pci_d3cold_enable(pdev);
1679
1681
if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1680
1682
drm_dbg(&dev_priv->drm,
1681
1683
"Unclaimed access during suspend, bios?\n");
+54
-58
drivers/gpu/drm/i915/i915_pci.c
+54
-58
drivers/gpu/drm/i915/i915_pci.c
···
38
38
.display.ver = (x)
39
39
40
40
#define I845_PIPE_OFFSETS \
41
-
.pipe_offsets = { \
41
+
.display.pipe_offsets = { \
42
42
[TRANSCODER_A] = PIPE_A_OFFSET, \
43
43
}, \
44
-
.trans_offsets = { \
44
+
.display.trans_offsets = { \
45
45
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
46
46
}
47
47
48
48
#define I9XX_PIPE_OFFSETS \
49
-
.pipe_offsets = { \
49
+
.display.pipe_offsets = { \
50
50
[TRANSCODER_A] = PIPE_A_OFFSET, \
51
51
[TRANSCODER_B] = PIPE_B_OFFSET, \
52
52
}, \
53
-
.trans_offsets = { \
53
+
.display.trans_offsets = { \
54
54
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
55
55
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
56
56
}
57
57
58
58
#define IVB_PIPE_OFFSETS \
59
-
.pipe_offsets = { \
59
+
.display.pipe_offsets = { \
60
60
[TRANSCODER_A] = PIPE_A_OFFSET, \
61
61
[TRANSCODER_B] = PIPE_B_OFFSET, \
62
62
[TRANSCODER_C] = PIPE_C_OFFSET, \
63
63
}, \
64
-
.trans_offsets = { \
64
+
.display.trans_offsets = { \
65
65
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
66
66
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
67
67
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
68
68
}
69
69
70
70
#define HSW_PIPE_OFFSETS \
71
-
.pipe_offsets = { \
71
+
.display.pipe_offsets = { \
72
72
[TRANSCODER_A] = PIPE_A_OFFSET, \
73
73
[TRANSCODER_B] = PIPE_B_OFFSET, \
74
74
[TRANSCODER_C] = PIPE_C_OFFSET, \
75
75
[TRANSCODER_EDP] = PIPE_EDP_OFFSET, \
76
76
}, \
77
-
.trans_offsets = { \
77
+
.display.trans_offsets = { \
78
78
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
79
79
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
80
80
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
···
82
82
}
83
83
84
84
#define CHV_PIPE_OFFSETS \
85
-
.pipe_offsets = { \
85
+
.display.pipe_offsets = { \
86
86
[TRANSCODER_A] = PIPE_A_OFFSET, \
87
87
[TRANSCODER_B] = PIPE_B_OFFSET, \
88
88
[TRANSCODER_C] = CHV_PIPE_C_OFFSET, \
89
89
}, \
90
-
.trans_offsets = { \
90
+
.display.trans_offsets = { \
91
91
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
92
92
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
93
93
[TRANSCODER_C] = CHV_TRANSCODER_C_OFFSET, \
94
94
}
95
95
96
96
#define I845_CURSOR_OFFSETS \
97
-
.cursor_offsets = { \
97
+
.display.cursor_offsets = { \
98
98
[PIPE_A] = CURSOR_A_OFFSET, \
99
99
}
100
100
101
101
#define I9XX_CURSOR_OFFSETS \
102
-
.cursor_offsets = { \
102
+
.display.cursor_offsets = { \
103
103
[PIPE_A] = CURSOR_A_OFFSET, \
104
104
[PIPE_B] = CURSOR_B_OFFSET, \
105
105
}
106
106
107
107
#define CHV_CURSOR_OFFSETS \
108
-
.cursor_offsets = { \
108
+
.display.cursor_offsets = { \
109
109
[PIPE_A] = CURSOR_A_OFFSET, \
110
110
[PIPE_B] = CURSOR_B_OFFSET, \
111
111
[PIPE_C] = CHV_CURSOR_C_OFFSET, \
112
112
}
113
113
114
114
#define IVB_CURSOR_OFFSETS \
115
-
.cursor_offsets = { \
115
+
.display.cursor_offsets = { \
116
116
[PIPE_A] = CURSOR_A_OFFSET, \
117
117
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
118
118
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
119
119
}
120
120
121
121
#define TGL_CURSOR_OFFSETS \
122
-
.cursor_offsets = { \
122
+
.display.cursor_offsets = { \
123
123
[PIPE_A] = CURSOR_A_OFFSET, \
124
124
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
125
125
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
···
127
127
}
128
128
129
129
#define I9XX_COLORS \
130
-
.color = { .gamma_lut_size = 256 }
130
+
.display.color = { .gamma_lut_size = 256 }
131
131
#define I965_COLORS \
132
-
.color = { .gamma_lut_size = 129, \
132
+
.display.color = { .gamma_lut_size = 129, \
133
133
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
134
134
}
135
135
#define ILK_COLORS \
136
-
.color = { .gamma_lut_size = 1024 }
136
+
.display.color = { .gamma_lut_size = 1024 }
137
137
#define IVB_COLORS \
138
-
.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
138
+
.display.color = { .degamma_lut_size = 1024, .gamma_lut_size = 1024 }
139
139
#define CHV_COLORS \
140
-
.color = { .degamma_lut_size = 65, .gamma_lut_size = 257, \
141
-
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
142
-
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
140
+
.display.color = { \
141
+
.degamma_lut_size = 65, .gamma_lut_size = 257, \
142
+
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143
+
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
143
144
}
144
145
#define GLK_COLORS \
145
-
.color = { .degamma_lut_size = 33, .gamma_lut_size = 1024, \
146
-
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
147
-
DRM_COLOR_LUT_EQUAL_CHANNELS, \
146
+
.display.color = { \
147
+
.degamma_lut_size = 33, .gamma_lut_size = 1024, \
148
+
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
149
+
DRM_COLOR_LUT_EQUAL_CHANNELS, \
148
150
}
149
151
#define ICL_COLORS \
150
-
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145, \
151
-
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
152
-
DRM_COLOR_LUT_EQUAL_CHANNELS, \
153
-
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
152
+
.display.color = { \
153
+
.degamma_lut_size = 33, .gamma_lut_size = 262145, \
154
+
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
155
+
DRM_COLOR_LUT_EQUAL_CHANNELS, \
156
+
.gamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING, \
154
157
}
155
158
156
159
/* Keep in gen based order, and chronological order within a gen */
···
539
536
.has_snoop = true,
540
537
.has_coherent_ggtt = false,
541
538
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0),
542
-
.display_mmio_offset = VLV_DISPLAY_BASE,
539
+
.display.mmio_offset = VLV_DISPLAY_BASE,
543
540
I9XX_PIPE_OFFSETS,
544
541
I9XX_CURSOR_OFFSETS,
545
542
I965_COLORS,
···
637
634
.has_reset_engine = 1,
638
635
.has_snoop = true,
639
636
.has_coherent_ggtt = false,
640
-
.display_mmio_offset = VLV_DISPLAY_BASE,
637
+
.display.mmio_offset = VLV_DISPLAY_BASE,
641
638
CHV_PIPE_OFFSETS,
642
639
CHV_CURSOR_OFFSETS,
643
640
CHV_COLORS,
···
659
656
.display.has_ipc = 1, \
660
657
.display.has_psr = 1, \
661
658
.display.has_psr_hw_tracking = 1, \
662
-
.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
663
-
.dbuf.slice_mask = BIT(DBUF_S1)
659
+
.display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
660
+
.display.dbuf.slice_mask = BIT(DBUF_S1)
664
661
665
662
#define SKL_PLATFORM \
666
663
GEN9_FEATURES, \
···
695
692
#define GEN9_LP_FEATURES \
696
693
GEN(9), \
697
694
.is_lp = 1, \
698
-
.dbuf.slice_mask = BIT(DBUF_S1), \
695
+
.display.dbuf.slice_mask = BIT(DBUF_S1), \
699
696
.display.has_hotplug = 1, \
700
697
.platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
701
698
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
···
733
730
static const struct intel_device_info bxt_info = {
734
731
GEN9_LP_FEATURES,
735
732
PLATFORM(INTEL_BROXTON),
736
-
.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
733
+
.display.dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
737
734
};
738
735
739
736
static const struct intel_device_info glk_info = {
740
737
GEN9_LP_FEATURES,
741
738
PLATFORM(INTEL_GEMINILAKE),
742
739
.display.ver = 10,
743
-
.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
740
+
.display.dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
744
741
GLK_COLORS,
745
742
};
746
743
···
812
809
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
813
810
BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
814
811
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
815
-
.pipe_offsets = { \
812
+
.display.pipe_offsets = { \
816
813
[TRANSCODER_A] = PIPE_A_OFFSET, \
817
814
[TRANSCODER_B] = PIPE_B_OFFSET, \
818
815
[TRANSCODER_C] = PIPE_C_OFFSET, \
···
820
817
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
821
818
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
822
819
}, \
823
-
.trans_offsets = { \
820
+
.display.trans_offsets = { \
824
821
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
825
822
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
826
823
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
···
830
827
}, \
831
828
GEN(11), \
832
829
ICL_COLORS, \
833
-
.dbuf.size = 2048, \
834
-
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
830
+
.display.dbuf.size = 2048, \
831
+
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2), \
835
832
.display.has_dsc = 1, \
836
833
.has_coherent_ggtt = false, \
837
834
.has_logical_ring_elsq = 1
···
865
862
.display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
866
863
BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
867
864
BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
868
-
.pipe_offsets = { \
865
+
.display.pipe_offsets = { \
869
866
[TRANSCODER_A] = PIPE_A_OFFSET, \
870
867
[TRANSCODER_B] = PIPE_B_OFFSET, \
871
868
[TRANSCODER_C] = PIPE_C_OFFSET, \
···
873
870
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
874
871
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
875
872
}, \
876
-
.trans_offsets = { \
873
+
.display.trans_offsets = { \
877
874
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
878
875
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
879
876
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
···
940
937
.dma_mask_size = 39,
941
938
};
942
939
943
-
#define XE_LPD_CURSOR_OFFSETS \
944
-
.cursor_offsets = { \
945
-
[PIPE_A] = CURSOR_A_OFFSET, \
946
-
[PIPE_B] = IVB_CURSOR_B_OFFSET, \
947
-
[PIPE_C] = IVB_CURSOR_C_OFFSET, \
948
-
[PIPE_D] = TGL_CURSOR_D_OFFSET, \
949
-
}
950
-
951
940
#define XE_LPD_FEATURES \
952
941
.display.abox_mask = GENMASK(1, 0), \
953
-
.color = { .degamma_lut_size = 128, .gamma_lut_size = 1024, \
954
-
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
955
-
DRM_COLOR_LUT_EQUAL_CHANNELS, \
942
+
.display.color = { \
943
+
.degamma_lut_size = 128, .gamma_lut_size = 1024, \
944
+
.degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
945
+
DRM_COLOR_LUT_EQUAL_CHANNELS, \
956
946
}, \
957
-
.dbuf.size = 4096, \
958
-
.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
947
+
.display.dbuf.size = 4096, \
948
+
.display.dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
959
949
BIT(DBUF_S4), \
960
950
.display.has_ddi = 1, \
961
951
.display.has_dmc = 1, \
···
963
967
.display.has_psr = 1, \
964
968
.display.ver = 13, \
965
969
.display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
966
-
.pipe_offsets = { \
970
+
.display.pipe_offsets = { \
967
971
[TRANSCODER_A] = PIPE_A_OFFSET, \
968
972
[TRANSCODER_B] = PIPE_B_OFFSET, \
969
973
[TRANSCODER_C] = PIPE_C_OFFSET, \
···
971
975
[TRANSCODER_DSI_0] = PIPE_DSI0_OFFSET, \
972
976
[TRANSCODER_DSI_1] = PIPE_DSI1_OFFSET, \
973
977
}, \
974
-
.trans_offsets = { \
978
+
.display.trans_offsets = { \
975
979
[TRANSCODER_A] = TRANSCODER_A_OFFSET, \
976
980
[TRANSCODER_B] = TRANSCODER_B_OFFSET, \
977
981
[TRANSCODER_C] = TRANSCODER_C_OFFSET, \
···
979
983
[TRANSCODER_DSI_0] = TRANSCODER_DSI0_OFFSET, \
980
984
[TRANSCODER_DSI_1] = TRANSCODER_DSI1_OFFSET, \
981
985
}, \
982
-
XE_LPD_CURSOR_OFFSETS
986
+
TGL_CURSOR_OFFSETS
983
987
984
988
static const struct intel_device_info adl_p_info = {
985
989
GEN12_FEATURES,
+23
-24
drivers/gpu/drm/i915/i915_reg.h
+23
-24
drivers/gpu/drm/i915/i915_reg.h
···
115
115
* #define GEN8_BAR _MMIO(0xb888)
116
116
*/
117
117
118
-
#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display_mmio_offset)
118
+
#define DISPLAY_MMIO_BASE(dev_priv) (INTEL_INFO(dev_priv)->display.mmio_offset)
119
119
120
120
/*
121
121
* Given the first two numbers __a and __b of arbitrarily many evenly spaced
···
161
161
* Device info offset array based helpers for groups of registers with unevenly
162
162
* spaced base offsets.
163
163
*/
164
-
#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
165
-
INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
166
-
DISPLAY_MMIO_BASE(dev_priv))
167
-
#define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
168
-
INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
169
-
DISPLAY_MMIO_BASE(dev_priv))
170
-
#define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
171
-
#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
172
-
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
173
-
DISPLAY_MMIO_BASE(dev_priv))
164
+
#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
165
+
INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
166
+
DISPLAY_MMIO_BASE(dev_priv) + (reg))
167
+
#define _MMIO_TRANS2(tran, reg) _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
168
+
INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
169
+
DISPLAY_MMIO_BASE(dev_priv) + (reg))
170
+
#define _MMIO_CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
171
+
INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
172
+
DISPLAY_MMIO_BASE(dev_priv) + (reg))
174
173
175
174
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
176
175
#define _MASKED_FIELD(mask, value) ({ \
···
2170
2171
*/
2171
2172
#define _SRD_CTL_A 0x60800
2172
2173
#define _SRD_CTL_EDP 0x6f800
2173
-
#define EDP_PSR_CTL(tran) _MMIO(_TRANS2(tran, _SRD_CTL_A))
2174
+
#define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A)
2174
2175
#define EDP_PSR_ENABLE (1 << 31)
2175
2176
#define BDW_PSR_SINGLE_FRAME (1 << 30)
2176
2177
#define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK (1 << 29) /* SW can't modify */
···
2216
2217
2217
2218
#define _SRD_AUX_DATA_A 0x60814
2218
2219
#define _SRD_AUX_DATA_EDP 0x6f814
2219
-
#define EDP_PSR_AUX_DATA(tran, i) _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
2220
+
#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
2220
2221
2221
2222
#define _SRD_STATUS_A 0x60840
2222
2223
#define _SRD_STATUS_EDP 0x6f840
2223
-
#define EDP_PSR_STATUS(tran) _MMIO(_TRANS2(tran, _SRD_STATUS_A))
2224
+
#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A)
2224
2225
#define EDP_PSR_STATUS_STATE_MASK (7 << 29)
2225
2226
#define EDP_PSR_STATUS_STATE_SHIFT 29
2226
2227
#define EDP_PSR_STATUS_STATE_IDLE (0 << 29)
···
2247
2248
2248
2249
#define _SRD_PERF_CNT_A 0x60844
2249
2250
#define _SRD_PERF_CNT_EDP 0x6f844
2250
-
#define EDP_PSR_PERF_CNT(tran) _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
2251
+
#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
2251
2252
#define EDP_PSR_PERF_CNT_MASK 0xffffff
2252
2253
2253
2254
/* PSR_MASK on SKL+ */
2254
2255
#define _SRD_DEBUG_A 0x60860
2255
2256
#define _SRD_DEBUG_EDP 0x6f860
2256
-
#define EDP_PSR_DEBUG(tran) _MMIO(_TRANS2(tran, _SRD_DEBUG_A))
2257
+
#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A)
2257
2258
#define EDP_PSR_DEBUG_MASK_MAX_SLEEP (1 << 28)
2258
2259
#define EDP_PSR_DEBUG_MASK_LPSP (1 << 27)
2259
2260
#define EDP_PSR_DEBUG_MASK_MEMUP (1 << 26)
···
2328
2329
2329
2330
#define _PSR2_SU_STATUS_A 0x60914
2330
2331
#define _PSR2_SU_STATUS_EDP 0x6f914
2331
-
#define _PSR2_SU_STATUS(tran, index) _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
2332
+
#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
2332
2333
#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3))
2333
2334
#define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10)
2334
2335
#define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame))
···
4327
4328
#define _CURBBASE_IVB 0x71084
4328
4329
#define _CURBPOS_IVB 0x71088
4329
4330
4330
-
#define CURCNTR(pipe) _CURSOR2(pipe, _CURACNTR)
4331
-
#define CURBASE(pipe) _CURSOR2(pipe, _CURABASE)
4332
-
#define CURPOS(pipe) _CURSOR2(pipe, _CURAPOS)
4333
-
#define CURSIZE(pipe) _CURSOR2(pipe, _CURASIZE)
4334
-
#define CUR_FBC_CTL(pipe) _CURSOR2(pipe, _CUR_FBC_CTL_A)
4335
-
#define CURSURFLIVE(pipe) _CURSOR2(pipe, _CURASURFLIVE)
4331
+
#define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR)
4332
+
#define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE)
4333
+
#define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS)
4334
+
#define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE)
4335
+
#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A)
4336
+
#define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE)
4336
4337
4337
4338
#define CURSOR_A_OFFSET 0x70080
4338
4339
#define CURSOR_B_OFFSET 0x700c0
···
4407
4408
#define DSPLINOFF(plane) DSPADDR(plane)
4408
4409
#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET)
4409
4410
#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE)
4410
-
#define DSPGAMC(plane, i) _MMIO(_PIPE2(plane, _DSPAGAMC) + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
4411
+
#define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
4411
4412
4412
4413
/* CHV pipe B blender and primary plane */
4413
4414
#define _CHV_BLEND_A 0x60a00
+20
-19
drivers/gpu/drm/i915/intel_device_info.h
+20
-19
drivers/gpu/drm/i915/intel_device_info.h
···
214
214
215
215
u32 memory_regions; /* regions supported by the HW */
216
216
217
-
u32 display_mmio_offset;
218
-
219
217
u8 gt; /* GT number, 0 if undefined */
220
218
221
219
#define DEFINE_FLAG(name) u8 name:1
···
229
231
u8 fbc_mask;
230
232
u8 abox_mask;
231
233
234
+
struct {
235
+
u16 size; /* in blocks */
236
+
u8 slice_mask;
237
+
} dbuf;
238
+
232
239
#define DEFINE_FLAG(name) u8 name:1
233
240
DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
234
241
#undef DEFINE_FLAG
242
+
243
+
/* Global register offset for the display engine */
244
+
u32 mmio_offset;
245
+
246
+
/* Register offsets for the various display pipes and transcoders */
247
+
u32 pipe_offsets[I915_MAX_TRANSCODERS];
248
+
u32 trans_offsets[I915_MAX_TRANSCODERS];
249
+
u32 cursor_offsets[I915_MAX_PIPES];
250
+
251
+
struct {
252
+
u32 degamma_lut_size;
253
+
u32 gamma_lut_size;
254
+
u32 degamma_lut_tests;
255
+
u32 gamma_lut_tests;
256
+
} color;
235
257
} display;
236
-
237
-
struct {
238
-
u16 size; /* in blocks */
239
-
u8 slice_mask;
240
-
} dbuf;
241
-
242
-
/* Register offsets for the various display pipes and transcoders */
243
-
int pipe_offsets[I915_MAX_TRANSCODERS];
244
-
int trans_offsets[I915_MAX_TRANSCODERS];
245
-
int cursor_offsets[I915_MAX_PIPES];
246
-
247
-
struct color_luts {
248
-
u32 degamma_lut_size;
249
-
u32 gamma_lut_size;
250
-
u32 degamma_lut_tests;
251
-
u32 gamma_lut_tests;
252
-
} color;
253
258
};
254
259
255
260
struct intel_runtime_info {
+9
-7
drivers/gpu/drm/i915/intel_pch.c
+9
-7
drivers/gpu/drm/i915/intel_pch.c
···
25
25
drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n");
26
26
drm_WARN_ON(&dev_priv->drm,
27
27
GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
28
-
/* PantherPoint is CPT compatible */
28
+
/* PPT is CPT compatible */
29
29
return PCH_CPT;
30
30
case INTEL_PCH_LPT_DEVICE_ID_TYPE:
31
31
drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n");
···
47
47
!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
48
48
drm_WARN_ON(&dev_priv->drm,
49
49
IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
50
-
/* WildcatPoint is LPT compatible */
50
+
/* WPT is LPT compatible */
51
51
return PCH_LPT;
52
52
case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
53
53
drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n");
···
55
55
!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
56
56
drm_WARN_ON(&dev_priv->drm,
57
57
!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
58
-
/* WildcatPoint is LPT compatible */
58
+
/* WPT is LPT compatible */
59
59
return PCH_LPT;
60
60
case INTEL_PCH_SPT_DEVICE_ID_TYPE:
61
61
drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n");
···
99
99
!IS_COFFEELAKE(dev_priv) &&
100
100
!IS_COMETLAKE(dev_priv) &&
101
101
!IS_ROCKETLAKE(dev_priv));
102
-
/* CometPoint is CNP Compatible */
102
+
/* CMP is CNP compatible */
103
103
return PCH_CNP;
104
104
case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
105
105
drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n");
106
106
drm_WARN_ON(&dev_priv->drm,
107
107
!IS_COFFEELAKE(dev_priv) &&
108
108
!IS_COMETLAKE(dev_priv));
109
-
/* Comet Lake V PCH is based on KBP, which is SPT compatible */
109
+
/* CMP-V is based on KBP, which is SPT compatible */
110
110
return PCH_SPT;
111
111
case INTEL_PCH_ICP_DEVICE_ID_TYPE:
112
112
case INTEL_PCH_ICP2_DEVICE_ID_TYPE:
···
116
116
case INTEL_PCH_MCC_DEVICE_ID_TYPE:
117
117
drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
118
118
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
119
-
return PCH_MCC;
119
+
/* MCC is TGP compatible */
120
+
return PCH_TGP;
120
121
case INTEL_PCH_TGP_DEVICE_ID_TYPE:
121
122
case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
122
123
drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
···
128
127
case INTEL_PCH_JSP_DEVICE_ID_TYPE:
129
128
drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
130
129
drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
131
-
return PCH_JSP;
130
+
/* JSP is ICP compatible */
131
+
return PCH_ICP;
132
132
case INTEL_PCH_ADP_DEVICE_ID_TYPE:
133
133
case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
134
134
case INTEL_PCH_ADP3_DEVICE_ID_TYPE:
+2
-6
drivers/gpu/drm/i915/intel_pch.h
+2
-6
drivers/gpu/drm/i915/intel_pch.h
···
22
22
PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */
23
23
PCH_SPT, /* Sunrisepoint/Kaby Lake PCH */
24
24
PCH_CNP, /* Cannon/Comet Lake PCH */
25
-
PCH_ICP, /* Ice Lake PCH */
26
-
PCH_JSP, /* Jasper Lake PCH */
27
-
PCH_MCC, /* Mule Creek Canyon PCH */
28
-
PCH_TGP, /* Tiger Lake PCH */
25
+
PCH_ICP, /* Ice Lake/Jasper Lake PCH */
26
+
PCH_TGP, /* Tiger Lake/Mule Creek Canyon PCH */
29
27
PCH_ADP, /* Alder Lake PCH */
30
28
31
29
/* Fake PCHs, functionality handled on the same PCI dev */
···
66
68
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
67
69
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
68
70
#define HAS_PCH_DG1(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
69
-
#define HAS_PCH_JSP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_JSP)
70
-
#define HAS_PCH_MCC(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MCC)
71
71
#define HAS_PCH_TGP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
72
72
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
73
73
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
+4
-4
drivers/gpu/drm/i915/intel_pm.c
+4
-4
drivers/gpu/drm/i915/intel_pm.c
···
4101
4101
4102
4102
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)
4103
4103
{
4104
-
return INTEL_INFO(dev_priv)->dbuf.size /
4105
-
hweight8(INTEL_INFO(dev_priv)->dbuf.slice_mask);
4104
+
return INTEL_INFO(dev_priv)->display.dbuf.size /
4105
+
hweight8(INTEL_INFO(dev_priv)->display.dbuf.slice_mask);
4106
4106
}
4107
4107
4108
4108
static void
···
4121
4121
ddb->end = fls(slice_mask) * slice_size;
4122
4122
4123
4123
WARN_ON(ddb->start >= ddb->end);
4124
-
WARN_ON(ddb->end > INTEL_INFO(dev_priv)->dbuf.size);
4124
+
WARN_ON(ddb->end > INTEL_INFO(dev_priv)->display.dbuf.size);
4125
4125
}
4126
4126
4127
4127
static unsigned int mbus_ddb_offset(struct drm_i915_private *i915, u8 slice_mask)
···
6096
6096
"Enabled dbuf slices 0x%x -> 0x%x (total dbuf slices 0x%x), mbus joined? %s->%s\n",
6097
6097
old_dbuf_state->enabled_slices,
6098
6098
new_dbuf_state->enabled_slices,
6099
-
INTEL_INFO(dev_priv)->dbuf.slice_mask,
6099
+
INTEL_INFO(dev_priv)->display.dbuf.slice_mask,
6100
6100
str_yes_no(old_dbuf_state->joined_mbus),
6101
6101
str_yes_no(new_dbuf_state->joined_mbus));
6102
6102
}