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Merge tag 'samsung-dt64-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt

Samsung DTS ARM64 changes for v6.4

1. Exynos850: add headers with AUD, G3D and HSI clock controller clock
IDs. Add G3D (GPU) clock controller node.
2. Exynos5433: fixes for dtbs_check: move MIPI phy to PMU node.
3. Drop old MSHC aliases (while adding proper mmc-ddr-1_8v which was
selected by the driver based on the MSHC alias) and add generic MMC
aliases in each board. The aliases match known numbering in
the schematics.

* tag 'samsung-dt64-6.4' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: add mmc aliases
arm64: dts: exynos: drop mshc aliases
arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
arm64: dts: exynos: move MIPI phy to PMU node in Exynos5433
dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D

Link: https://lore.kernel.org/r/20230405080438.156805-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Arnd Bergmann 6dcb6ff6 837be1cc

+69 -17
+19
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
··· 37 37 - samsung,exynos850-cmu-cmgp 38 38 - samsung,exynos850-cmu-core 39 39 - samsung,exynos850-cmu-dpu 40 + - samsung,exynos850-cmu-g3d 40 41 - samsung,exynos850-cmu-hsi 41 42 - samsung,exynos850-cmu-is 42 43 - samsung,exynos850-cmu-mfcmscl ··· 169 168 items: 170 169 - const: oscclk 171 170 - const: dout_dpu 171 + 172 + - if: 173 + properties: 174 + compatible: 175 + contains: 176 + const: samsung,exynos850-cmu-g3d 177 + 178 + then: 179 + properties: 180 + clocks: 181 + items: 182 + - description: External reference clock (26 MHz) 183 + - description: G3D clock (from CMU_TOP) 184 + 185 + clock-names: 186 + items: 187 + - const: oscclk 188 + - const: dout_g3d_switch 172 189 173 190 - if: 174 191 properties:
+3 -2
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi
··· 21 21 gsc0 = &gsc_0; 22 22 gsc1 = &gsc_1; 23 23 gsc2 = &gsc_2; 24 + mmc0 = &mshc_0; 25 + mmc2 = &mshc_2; 24 26 pinctrl0 = &pinctrl_alive; 25 27 pinctrl1 = &pinctrl_aud; 26 28 pinctrl2 = &pinctrl_cpif; ··· 42 40 spi2 = &spi_2; 43 41 spi3 = &spi_3; 44 42 spi4 = &spi_4; 45 - mshc0 = &mshc_0; 46 - mshc2 = &mshc_2; 47 43 }; 48 44 49 45 chosen { ··· 952 952 953 953 &mshc_0 { 954 954 status = "okay"; 955 + mmc-ddr-1_8v; 955 956 mmc-hs200-1_8v; 956 957 mmc-hs400-1_8v; 957 958 cap-mmc-highspeed;
+9 -10
arch/arm64/boot/dts/exynos/exynos5433.dtsi
··· 911 911 }; 912 912 913 913 pmu_system_controller: system-controller@105c0000 { 914 - compatible = "samsung,exynos5433-pmu", "syscon"; 914 + compatible = "samsung,exynos5433-pmu", "simple-mfd", "syscon"; 915 915 reg = <0x105c0000 0x5008>; 916 916 #clock-cells = <1>; 917 917 clock-names = "clkout16"; 918 918 clocks = <&xxti>; 919 + 920 + mipi_phy: mipi-phy { 921 + compatible = "samsung,exynos5433-mipi-video-phy"; 922 + #phy-cells = <1>; 923 + samsung,cam0-sysreg = <&syscon_cam0>; 924 + samsung,cam1-sysreg = <&syscon_cam1>; 925 + samsung,disp-sysreg = <&syscon_disp>; 926 + }; 919 927 920 928 reboot: syscon-reboot { 921 929 compatible = "syscon-reboot"; ··· 942 934 <0x11004000 0x2000>, 943 935 <0x11006000 0x2000>; 944 936 interrupts = <GIC_PPI 9 0xf04>; 945 - }; 946 - 947 - mipi_phy: video-phy { 948 - compatible = "samsung,exynos5433-mipi-video-phy"; 949 - #phy-cells = <1>; 950 - samsung,pmu-syscon = <&pmu_system_controller>; 951 - samsung,cam0-sysreg = <&syscon_cam0>; 952 - samsung,cam1-sysreg = <&syscon_cam1>; 953 - samsung,disp-sysreg = <&syscon_disp>; 954 937 }; 955 938 956 939 decon: decon@13800000 {
+3 -2
arch/arm64/boot/dts/exynos/exynos7-espresso.dts
··· 17 17 compatible = "samsung,exynos7-espresso", "samsung,exynos7"; 18 18 19 19 aliases { 20 + mmc0 = &mmc_0; 21 + mmc2 = &mmc_2; 20 22 serial0 = &serial_2; 21 - mshc0 = &mmc_0; 22 - mshc2 = &mmc_2; 23 23 }; 24 24 25 25 chosen { ··· 362 362 &mmc_0 { 363 363 status = "okay"; 364 364 cap-mmc-highspeed; 365 + mmc-ddr-1_8v; 365 366 mmc-hs200-1_8v; 366 367 non-removable; 367 368 card-detect-delay = <200>;
+1
arch/arm64/boot/dts/exynos/exynos7885-jackpotlte.dts
··· 18 18 chassis-type = "handset"; 19 19 20 20 aliases { 21 + mmc0 = &mmc_0; 21 22 serial0 = &serial_0; 22 23 serial1 = &serial_1; 23 24 serial2 = &serial_2;
+9
arch/arm64/boot/dts/exynos/exynos850.dtsi
··· 245 245 "dout_peri_uart", "dout_peri_ip"; 246 246 }; 247 247 248 + cmu_g3d: clock-controller@11400000 { 249 + compatible = "samsung,exynos850-cmu-g3d"; 250 + reg = <0x11400000 0x8000>; 251 + #clock-cells = <1>; 252 + 253 + clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; 254 + clock-names = "oscclk", "dout_g3d_switch"; 255 + }; 256 + 248 257 cmu_apm: clock-controller@11800000 { 249 258 compatible = "samsung,exynos850-cmu-apm"; 250 259 reg = <0x11800000 0x8000>;
+25 -3
include/dt-bindings/clock/exynos850.h
··· 85 85 #define CLK_DOUT_MFCMSCL_M2M 73 86 86 #define CLK_DOUT_MFCMSCL_MCSC 74 87 87 #define CLK_DOUT_MFCMSCL_JPEG 75 88 - #define TOP_NR_CLK 76 88 + #define CLK_MOUT_G3D_SWITCH 76 89 + #define CLK_GOUT_G3D_SWITCH 77 90 + #define CLK_DOUT_G3D_SWITCH 78 91 + #define TOP_NR_CLK 79 89 92 90 93 /* CMU_APM */ 91 94 #define CLK_RCO_I3C_PMIC 1 ··· 178 175 #define IOCLK_AUDIOCDCLK5 58 179 176 #define IOCLK_AUDIOCDCLK6 59 180 177 #define TICK_USB 60 181 - #define AUD_NR_CLK 61 178 + #define CLK_GOUT_AUD_CMU_AUD_PCLK 61 179 + #define AUD_NR_CLK 62 182 180 183 181 /* CMU_CMGP */ 184 182 #define CLK_RCO_CMGP 1 ··· 199 195 #define CLK_GOUT_SYSREG_CMGP_PCLK 15 200 196 #define CMGP_NR_CLK 16 201 197 198 + /* CMU_G3D */ 199 + #define CLK_FOUT_G3D_PLL 1 200 + #define CLK_MOUT_G3D_PLL 2 201 + #define CLK_MOUT_G3D_SWITCH_USER 3 202 + #define CLK_MOUT_G3D_BUSD 4 203 + #define CLK_DOUT_G3D_BUSP 5 204 + #define CLK_GOUT_G3D_CMU_G3D_PCLK 6 205 + #define CLK_GOUT_G3D_GPU_CLK 7 206 + #define CLK_GOUT_G3D_TZPC_PCLK 8 207 + #define CLK_GOUT_G3D_GRAY2BIN_CLK 9 208 + #define CLK_GOUT_G3D_BUSD_CLK 10 209 + #define CLK_GOUT_G3D_BUSP_CLK 11 210 + #define CLK_GOUT_G3D_SYSREG_PCLK 12 211 + #define G3D_NR_CLK 13 212 + 202 213 /* CMU_HSI */ 203 214 #define CLK_MOUT_HSI_BUS_USER 1 204 215 #define CLK_MOUT_HSI_MMC_CARD_USER 2 ··· 228 209 #define CLK_GOUT_MMC_CARD_ACLK 11 229 210 #define CLK_GOUT_MMC_CARD_SDCLKIN 12 230 211 #define CLK_GOUT_SYSREG_HSI_PCLK 13 231 - #define HSI_NR_CLK 14 212 + #define CLK_GOUT_HSI_PPMU_ACLK 14 213 + #define CLK_GOUT_HSI_PPMU_PCLK 15 214 + #define CLK_GOUT_HSI_CMU_HSI_PCLK 16 215 + #define HSI_NR_CLK 17 232 216 233 217 /* CMU_IS */ 234 218 #define CLK_MOUT_IS_BUS_USER 1