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linux
spi: rzv2h-rspi: Fix max_speed_hz and clock configuration issues
Prabhakar <prabhakar.csengg@gmail.com> says:
This patch series addresses three issues in the RZV2H RSPI driver:
1. The max_speed_hz field was advertising a prohibited bit rate, which
could lead to incorrect behavior when userspace applications attempt
to set the SPI clock speed.
2. The clock configuration logic allowed for an invalid combination of
SPR=0 and BRDV=0, which is not supported by the hardware.
3. Simplified the clock rate search function as min/max speed parameters
are not needed.
Note, patches apply on top of next-20260409.
+25
-27
+25
-27
drivers/spi/spi-rzv2h-rspi.c
+25
-27
drivers/spi/spi-rzv2h-rspi.c
···
50
50
51
51
/* Register SPBR */
52
52
#define RSPI_SPBR_SPR_MIN 0
53
-
#define RSPI_SPBR_SPR_PCLK_MIN 1
54
53
#define RSPI_SPBR_SPR_MAX 255
55
54
56
55
/* Register SPCMD */
···
76
77
77
78
#define RSPI_RESET_NUM 2
78
79
80
+
#define RSPI_MAX_SPEED_HZ 50000000
81
+
79
82
struct rzv2h_rspi_best_clock {
80
83
struct clk *clk;
81
84
unsigned long clk_rate;
···
88
87
};
89
88
90
89
struct rzv2h_rspi_info {
91
-
void (*find_tclk_rate)(struct clk *clk, u32 hz, u8 spr_min, u8 spr_max,
90
+
void (*find_tclk_rate)(struct clk *clk, u32 hz,
92
91
struct rzv2h_rspi_best_clock *best_clk);
93
-
void (*find_pclk_rate)(struct clk *clk, u32 hz, u8 spr_low, u8 spr_high,
92
+
void (*find_pclk_rate)(struct clk *clk, u32 hz,
94
93
struct rzv2h_rspi_best_clock *best_clk);
95
94
const char *tclk_name;
96
95
unsigned int fifo_size;
···
413
412
}
414
413
415
414
static void rzv2h_rspi_find_rate_variable(struct clk *clk, u32 hz,
416
-
u8 spr_min, u8 spr_max,
417
415
struct rzv2h_rspi_best_clock *best)
418
416
{
419
417
long clk_rate, clk_min_rate, clk_max_rate;
···
463
463
* minimum SPR that is in the valid range.
464
464
*/
465
465
min_rate_spr = DIV_ROUND_CLOSEST(clk_min_rate, rate_div) - 1;
466
-
if (min_rate_spr > spr_max)
466
+
if (min_rate_spr > RSPI_SPBR_SPR_MAX)
467
467
continue;
468
468
469
469
/*
···
473
473
* maximum SPR that is in the valid range.
474
474
*/
475
475
max_rate_spr = DIV_ROUND_CLOSEST(clk_max_rate, rate_div) - 1;
476
-
if (max_rate_spr < spr_min)
476
+
if (max_rate_spr < RSPI_SPBR_SPR_MIN)
477
477
break;
478
478
479
-
if (min_rate_spr < spr_min)
480
-
min_rate_spr = spr_min;
479
+
if (min_rate_spr < RSPI_SPBR_SPR_MIN)
480
+
min_rate_spr = RSPI_SPBR_SPR_MIN;
481
481
482
-
if (max_rate_spr > spr_max)
483
-
max_rate_spr = spr_max;
482
+
if (max_rate_spr > RSPI_SPBR_SPR_MAX)
483
+
max_rate_spr = RSPI_SPBR_SPR_MAX;
484
484
485
485
for (spr = min_rate_spr; spr <= max_rate_spr; spr++) {
486
486
clk_rate = (spr + 1) * rate_div;
···
511
511
}
512
512
513
513
static void rzv2h_rspi_find_rate_fixed(struct clk *clk, u32 hz,
514
-
u8 spr_min, u8 spr_max,
515
514
struct rzv2h_rspi_best_clock *best)
516
515
{
517
516
unsigned long clk_rate;
···
532
533
for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
533
534
spr = DIV_ROUND_UP(clk_rate, hz * (1 << (brdv + 1)));
534
535
spr--;
535
-
if (spr >= spr_min && spr <= spr_max)
536
+
/*
537
+
* Skip SPR=0 and BRDV=0 as it is not a valid combination:
538
+
* - On RZ/G3E, RZ/G3L, RZ/V2H(P) and RZ/V2N, RSPI_n_TCLK is
539
+
* fixed at 200MHz and SPR=0 and BRDV=0 results in the maximum
540
+
* bit rate of 100Mbps which is prohibited.
541
+
* - On RZ/T2H and RZ/N2H, when PCLK (125MHz) is used as
542
+
* the clock source, SPR=0 and BRDV=0 is explicitly listed
543
+
* as unsupported in the hardware manual (Table 36.7).
544
+
*/
545
+
if (!spr && !brdv)
546
+
continue;
547
+
if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
536
548
goto clock_found;
537
549
}
538
550
···
573
563
};
574
564
int ret;
575
565
576
-
rspi->info->find_tclk_rate(rspi->tclk, hz, RSPI_SPBR_SPR_MIN,
577
-
RSPI_SPBR_SPR_MAX, &best_clock);
566
+
rspi->info->find_tclk_rate(rspi->tclk, hz, &best_clock);
578
567
579
-
/*
580
-
* T2H and N2H can also use PCLK as a source, which is 125MHz, but not
581
-
* when both SPR and BRDV are 0.
582
-
*/
583
568
if (best_clock.error && rspi->info->find_pclk_rate)
584
-
rspi->info->find_pclk_rate(rspi->pclk, hz, RSPI_SPBR_SPR_PCLK_MIN,
585
-
RSPI_SPBR_SPR_MAX, &best_clock);
569
+
rspi->info->find_pclk_rate(rspi->pclk, hz, &best_clock);
586
570
587
571
if (!best_clock.clk_rate)
588
572
return -EINVAL;
···
775
771
RSPI_SPBR_SPR_MAX,
776
772
RSPI_SPCMD_BRDV_MAX);
777
773
778
-
tclk_rate = clk_round_rate(rspi->tclk, ULONG_MAX);
779
-
if (tclk_rate < 0)
780
-
return tclk_rate;
781
-
782
-
controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
783
-
RSPI_SPBR_SPR_MIN,
784
-
RSPI_SPCMD_BRDV_MIN);
774
+
controller->max_speed_hz = RSPI_MAX_SPEED_HZ;
785
775
786
776
controller->dma_tx = devm_dma_request_chan(dev, "tx");
787
777
if (IS_ERR(controller->dma_tx)) {