tjh.dev / kernel
Linux kernel mirror (for testing) git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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Merge tag 'drm-fixes-2025-05-03' of https://gitlab.freedesktop.org/drm/kernel

Pull drm fixes from Dave Airlie:
"Weekly drm fixes, amdgpu and xe as usual, the new adp driver has a
bunch of vblank fixes, then a bunch of small fixes across the board.

Seems about the right level for this time in the release cycle.

ttm:
- docs warning fix

kunit
- fix leak in shmem tests

fdinfo:
- driver unbind race fix

amdgpu:
- Fix possible UAF in HDCP
- XGMI dma-buf fix
- NBIO 7.11 fix
- VCN 5.0.1 fix

xe:
- EU stall locking fix and disabling on VF
- Documentation fix kernel version supporting hwmon entries
- SVM fixes on error handling

i915:
- Fix build for CONFIG_DRM_I915_PXP=n

nouveau:
- fix race condition in fence handling

ivpu:
- interrupt handling fix
- D0i2 test mode fix

adp:
- vblank fixes

mipi-dbi:
- timing fix"

* tag 'drm-fixes-2025-05-03' of https://gitlab.freedesktop.org/drm/kernel: (23 commits)
drm/gpusvm: set has_dma_mapping inside mapping loop
drm/xe/hwmon: Fix kernel version documentation for temperature
drm/xe/eustall: Do not support EU stall on SRIOV VF
drm/xe/eustall: Resolve a possible circular locking dependency
drm/amdgpu: Add DPG pause for VCN v5.0.1
drm/amdgpu: Fix offset for HDP remap in nbio v7.11
drm/amdgpu: Fail DMABUF map of XGMI-accessible memory
drm/amd/display: Fix slab-use-after-free in hdcp
drm/mipi-dbi: Fix blanking for non-16 bit formats
drm/tests: shmem: Fix memleak
drm/xe/guc: Fix capture of steering registers
drm/xe/svm: fix dereferencing error pointer in drm_gpusvm_range_alloc()
drm: Select DRM_KMS_HELPER from DRM_DEBUG_DP_MST_TOPOLOGY_REFS
drm: adp: Remove pointless irq_lock spin lock
drm: adp: Enable vblank interrupts in crtc's .atomic_enable
drm: adp: Handle drm_crtc_vblank_get() errors
drm: adp: Use spin_lock_irqsave for drm device event_lock
drm/fdinfo: Protect against driver unbind
drm/ttm: fix the warning for hit_low and evict_low
accel/ivpu: Fix the D0i2 disable test mode
...

Linus Torvalds 6de6674c 00b827f0

+146 -42
+2 -2
Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon
··· 111 111 112 112 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp2_input 113 113 Date: March 2025 114 - KernelVersion: 6.14 114 + KernelVersion: 6.15 115 115 Contact: intel-xe@lists.freedesktop.org 116 116 Description: RO. Package temperature in millidegree Celsius. 117 117 ··· 119 119 120 120 What: /sys/bus/pci/drivers/xe/.../hwmon/hwmon<i>/temp3_input 121 121 Date: March 2025 122 - KernelVersion: 6.14 122 + KernelVersion: 6.15 123 123 Contact: intel-xe@lists.freedesktop.org 124 124 Description: RO. VRAM temperature in millidegree Celsius. 125 125
+2 -2
drivers/accel/ivpu/ivpu_fw.c
··· 544 544 boot_params->d0i3_entry_vpu_ts); 545 545 ivpu_dbg(vdev, FW_BOOT, "boot_params.system_time_us = %llu\n", 546 546 boot_params->system_time_us); 547 - ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = %u\n", 547 + ivpu_dbg(vdev, FW_BOOT, "boot_params.power_profile = 0x%x\n", 548 548 boot_params->power_profile); 549 549 } 550 550 ··· 646 646 boot_params->d0i3_residency_time_us = 0; 647 647 boot_params->d0i3_entry_vpu_ts = 0; 648 648 if (IVPU_WA(disable_d0i2)) 649 - boot_params->power_profile = 1; 649 + boot_params->power_profile |= BIT(1); 650 650 651 651 boot_params->system_time_us = ktime_to_us(ktime_get_real()); 652 652 wmb(); /* Flush WC buffers after writing bootparams */
+1 -1
drivers/accel/ivpu/ivpu_hw_btrs.h
··· 14 14 #define PLL_PROFILING_FREQ_DEFAULT 38400000 15 15 #define PLL_PROFILING_FREQ_HIGH 400000000 16 16 17 - #define DCT_DEFAULT_ACTIVE_PERCENT 15u 17 + #define DCT_DEFAULT_ACTIVE_PERCENT 30u 18 18 #define DCT_PERIOD_US 35300u 19 19 20 20 int ivpu_hw_btrs_info_init(struct ivpu_device *vdev);
+10 -8
drivers/accel/ivpu/ivpu_pm.c
··· 428 428 active_us = (DCT_PERIOD_US * active_percent) / 100; 429 429 inactive_us = DCT_PERIOD_US - active_us; 430 430 431 + vdev->pm->dct_active_percent = active_percent; 432 + 433 + ivpu_dbg(vdev, PM, "DCT requested %u%% (D0: %uus, D0i2: %uus)\n", 434 + active_percent, active_us, inactive_us); 435 + 431 436 ret = ivpu_jsm_dct_enable(vdev, active_us, inactive_us); 432 437 if (ret) { 433 438 ivpu_err_ratelimited(vdev, "Failed to enable DCT: %d\n", ret); 434 439 return ret; 435 440 } 436 441 437 - vdev->pm->dct_active_percent = active_percent; 438 - 439 - ivpu_dbg(vdev, PM, "DCT set to %u%% (D0: %uus, D0i2: %uus)\n", 440 - active_percent, active_us, inactive_us); 441 442 return 0; 442 443 } 443 444 ··· 446 445 { 447 446 int ret; 448 447 448 + vdev->pm->dct_active_percent = 0; 449 + 450 + ivpu_dbg(vdev, PM, "DCT requested to be disabled\n"); 451 + 449 452 ret = ivpu_jsm_dct_disable(vdev); 450 453 if (ret) { 451 454 ivpu_err_ratelimited(vdev, "Failed to disable DCT: %d\n", ret); 452 455 return ret; 453 456 } 454 457 455 - vdev->pm->dct_active_percent = 0; 456 - 457 - ivpu_dbg(vdev, PM, "DCT disabled\n"); 458 458 return 0; 459 459 } 460 460 ··· 468 466 if (ivpu_hw_btrs_dct_get_request(vdev, &enable)) 469 467 return; 470 468 471 - if (vdev->pm->dct_active_percent) 469 + if (enable) 472 470 ret = ivpu_pm_dct_enable(vdev, DCT_DEFAULT_ACTIVE_PERCENT); 473 471 else 474 472 ret = ivpu_pm_dct_disable(vdev);
+1 -1
drivers/gpu/drm/Kconfig
··· 188 188 bool "Enable refcount backtrace history in the DP MST helpers" 189 189 depends on STACKTRACE_SUPPORT 190 190 select STACKDEPOT 191 - depends on DRM_KMS_HELPER 191 + select DRM_KMS_HELPER 192 192 depends on DEBUG_KERNEL 193 193 depends on EXPERT 194 194 help
+14 -13
drivers/gpu/drm/adp/adp_drv.c
··· 121 121 dma_addr_t mask_iova; 122 122 int be_irq; 123 123 int fe_irq; 124 - spinlock_t irq_lock; 125 124 struct drm_pending_vblank_event *event; 126 125 }; 127 126 ··· 287 288 writel(BIT(0), adp->be + ADBE_BLEND_EN3); 288 289 writel(BIT(0), adp->be + ADBE_BLEND_BYPASS); 289 290 writel(BIT(0), adp->be + ADBE_BLEND_EN4); 291 + drm_crtc_vblank_on(crtc); 290 292 } 291 293 292 294 static void adp_crtc_atomic_disable(struct drm_crtc *crtc, ··· 310 310 struct drm_atomic_state *state) 311 311 { 312 312 u32 frame_num = 1; 313 + unsigned long flags; 313 314 struct adp_drv_private *adp = crtc_to_adp(crtc); 314 315 struct drm_crtc_state *new_state = drm_atomic_get_new_crtc_state(state, crtc); 315 316 u64 new_size = ALIGN(new_state->mode.hdisplay * ··· 331 330 } 332 331 writel(ADBE_FIFO_SYNC | frame_num, adp->be + ADBE_FIFO); 333 332 //FIXME: use adbe flush interrupt 334 - spin_lock_irq(&crtc->dev->event_lock); 335 333 if (crtc->state->event) { 336 - drm_crtc_vblank_get(crtc); 337 - adp->event = crtc->state->event; 334 + struct drm_pending_vblank_event *event = crtc->state->event; 335 + 336 + crtc->state->event = NULL; 337 + spin_lock_irqsave(&crtc->dev->event_lock, flags); 338 + 339 + if (drm_crtc_vblank_get(crtc) != 0) 340 + drm_crtc_send_vblank_event(crtc, event); 341 + else 342 + adp->event = event; 343 + 344 + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 338 345 } 339 - crtc->state->event = NULL; 340 - spin_unlock_irq(&crtc->dev->event_lock); 341 346 } 342 347 343 348 static const struct drm_crtc_funcs adp_crtc_funcs = { ··· 489 482 u32 int_status; 490 483 u32 int_ctl; 491 484 492 - spin_lock(&adp->irq_lock); 493 - 494 485 int_status = readl(adp->fe + ADP_INT_STATUS); 495 486 if (int_status & ADP_INT_STATUS_VBLANK) { 496 487 drm_crtc_handle_vblank(&adp->crtc); ··· 506 501 507 502 writel(int_status, adp->fe + ADP_INT_STATUS); 508 503 509 - spin_unlock(&adp->irq_lock); 510 504 511 505 return IRQ_HANDLED; 512 506 } ··· 516 512 struct adp_drv_private *adp = to_adp(drm); 517 513 int err; 518 514 519 - adp_disable_vblank(adp); 520 - writel(ADP_CTRL_FIFO_ON | ADP_CTRL_VBLANK_ON, adp->fe + ADP_CTRL); 515 + writel(ADP_CTRL_FIFO_ON, adp->fe + ADP_CTRL); 521 516 522 517 adp->next_bridge = drmm_of_get_bridge(&adp->drm, dev->of_node, 0, 0); 523 518 if (IS_ERR(adp->next_bridge)) { ··· 569 566 adp = devm_drm_dev_alloc(&pdev->dev, &adp_driver, struct adp_drv_private, drm); 570 567 if (IS_ERR(adp)) 571 568 return PTR_ERR(adp); 572 - 573 - spin_lock_init(&adp->irq_lock); 574 569 575 570 dev_set_drvdata(&pdev->dev, &adp->drm); 576 571
+5
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
··· 199 199 break; 200 200 201 201 case TTM_PL_VRAM: 202 + /* XGMI-accessible memory should never be DMA-mapped */ 203 + if (WARN_ON(amdgpu_dmabuf_is_xgmi_accessible( 204 + dma_buf_attach_adev(attach), bo))) 205 + return ERR_PTR(-EINVAL); 206 + 202 207 r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0, 203 208 bo->tbo.base.size, attach->dev, 204 209 dir, &sgt);
+1 -1
drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c
··· 360 360 *flags |= AMD_CG_SUPPORT_BIF_LS; 361 361 } 362 362 363 - #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE) 363 + #define MMIO_REG_HOLE_OFFSET 0x44000 364 364 365 365 static void nbio_v7_11_set_reg_remap(struct amdgpu_device *adev) 366 366 {
+54
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_1.c
··· 503 503 } 504 504 505 505 /** 506 + * vcn_v5_0_1_pause_dpg_mode - VCN pause with dpg mode 507 + * 508 + * @vinst: VCN instance 509 + * @new_state: pause state 510 + * 511 + * Pause dpg mode for VCN block 512 + */ 513 + static int vcn_v5_0_1_pause_dpg_mode(struct amdgpu_vcn_inst *vinst, 514 + struct dpg_pause_state *new_state) 515 + { 516 + struct amdgpu_device *adev = vinst->adev; 517 + uint32_t reg_data = 0; 518 + int vcn_inst; 519 + 520 + vcn_inst = GET_INST(VCN, vinst->inst); 521 + 522 + /* pause/unpause if state is changed */ 523 + if (vinst->pause_state.fw_based != new_state->fw_based) { 524 + DRM_DEV_DEBUG(adev->dev, "dpg pause state changed %d -> %d %s\n", 525 + vinst->pause_state.fw_based, new_state->fw_based, 526 + new_state->fw_based ? "VCN_DPG_STATE__PAUSE" : "VCN_DPG_STATE__UNPAUSE"); 527 + reg_data = RREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE) & 528 + (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 529 + 530 + if (new_state->fw_based == VCN_DPG_STATE__PAUSE) { 531 + /* pause DPG */ 532 + reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 533 + WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 534 + 535 + /* wait for ACK */ 536 + SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, 537 + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK, 538 + UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK); 539 + } else { 540 + /* unpause DPG, no need to wait */ 541 + reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK; 542 + WREG32_SOC15(VCN, vcn_inst, regUVD_DPG_PAUSE, reg_data); 543 + } 544 + vinst->pause_state.fw_based = new_state->fw_based; 545 + } 546 + 547 + return 0; 548 + } 549 + 550 + 551 + /** 506 552 * vcn_v5_0_1_start_dpg_mode - VCN start with dpg mode 507 553 * 508 554 * @vinst: VCN instance ··· 564 518 volatile struct amdgpu_vcn5_fw_shared *fw_shared = 565 519 adev->vcn.inst[inst_idx].fw_shared.cpu_addr; 566 520 struct amdgpu_ring *ring; 521 + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__PAUSE}; 567 522 int vcn_inst; 568 523 uint32_t tmp; 569 524 ··· 628 581 629 582 if (indirect) 630 583 amdgpu_vcn_psp_update_sram(adev, inst_idx, AMDGPU_UCODE_ID_VCN0_RAM); 584 + 585 + /* Pause dpg */ 586 + vcn_v5_0_1_pause_dpg_mode(vinst, &state); 631 587 632 588 ring = &adev->vcn.inst[inst_idx].ring_enc[0]; 633 589 ··· 825 775 int inst_idx = vinst->inst; 826 776 uint32_t tmp; 827 777 int vcn_inst; 778 + struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE}; 828 779 829 780 vcn_inst = GET_INST(VCN, inst_idx); 781 + 782 + /* Unpause dpg */ 783 + vcn_v5_0_1_pause_dpg_mode(vinst, &state); 830 784 831 785 /* Wait for power status to be 1 */ 832 786 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1,
+16 -3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c
··· 173 173 unsigned int conn_index = aconnector->base.index; 174 174 175 175 guard(mutex)(&hdcp_w->mutex); 176 + drm_connector_get(&aconnector->base); 177 + if (hdcp_w->aconnector[conn_index]) 178 + drm_connector_put(&hdcp_w->aconnector[conn_index]->base); 176 179 hdcp_w->aconnector[conn_index] = aconnector; 177 180 178 181 memset(&link_adjust, 0, sizeof(link_adjust)); ··· 223 220 unsigned int conn_index = aconnector->base.index; 224 221 225 222 guard(mutex)(&hdcp_w->mutex); 226 - hdcp_w->aconnector[conn_index] = aconnector; 227 223 228 224 /* the removal of display will invoke auth reset -> hdcp destroy and 229 225 * we'd expect the Content Protection (CP) property changed back to ··· 238 236 } 239 237 240 238 mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); 241 - 239 + if (hdcp_w->aconnector[conn_index]) { 240 + drm_connector_put(&hdcp_w->aconnector[conn_index]->base); 241 + hdcp_w->aconnector[conn_index] = NULL; 242 + } 242 243 process_output(hdcp_w); 243 244 } 244 245 ··· 259 254 for (conn_index = 0; conn_index < AMDGPU_DM_MAX_DISPLAY_INDEX; conn_index++) { 260 255 hdcp_w->encryption_status[conn_index] = 261 256 MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; 257 + if (hdcp_w->aconnector[conn_index]) { 258 + drm_connector_put(&hdcp_w->aconnector[conn_index]->base); 259 + hdcp_w->aconnector[conn_index] = NULL; 260 + } 262 261 } 263 262 264 263 process_output(hdcp_w); ··· 497 488 struct hdcp_workqueue *hdcp_work = handle; 498 489 struct amdgpu_dm_connector *aconnector = config->dm_stream_ctx; 499 490 int link_index = aconnector->dc_link->link_index; 491 + unsigned int conn_index = aconnector->base.index; 500 492 struct mod_hdcp_display *display = &hdcp_work[link_index].display; 501 493 struct mod_hdcp_link *link = &hdcp_work[link_index].link; 502 494 struct hdcp_workqueue *hdcp_w = &hdcp_work[link_index]; ··· 554 544 guard(mutex)(&hdcp_w->mutex); 555 545 556 546 mod_hdcp_add_display(&hdcp_w->hdcp, link, display, &hdcp_w->output); 557 - 547 + drm_connector_get(&aconnector->base); 548 + if (hdcp_w->aconnector[conn_index]) 549 + drm_connector_put(&hdcp_w->aconnector[conn_index]->base); 550 + hdcp_w->aconnector[conn_index] = aconnector; 558 551 process_output(hdcp_w); 559 552 } 560 553
+6
drivers/gpu/drm/drm_file.c
··· 964 964 struct drm_file *file = f->private_data; 965 965 struct drm_device *dev = file->minor->dev; 966 966 struct drm_printer p = drm_seq_file_printer(m); 967 + int idx; 968 + 969 + if (!drm_dev_enter(dev, &idx)) 970 + return; 967 971 968 972 drm_printf(&p, "drm-driver:\t%s\n", dev->driver->name); 969 973 drm_printf(&p, "drm-client-id:\t%llu\n", file->client_id); ··· 987 983 988 984 if (dev->driver->show_fdinfo) 989 985 dev->driver->show_fdinfo(&p, file); 986 + 987 + drm_dev_exit(idx); 990 988 } 991 989 EXPORT_SYMBOL(drm_show_fdinfo); 992 990
+1 -1
drivers/gpu/drm/drm_gpusvm.c
··· 1469 1469 } 1470 1470 i += 1 << order; 1471 1471 num_dma_mapped = i; 1472 + range->flags.has_dma_mapping = true; 1472 1473 } 1473 1474 1474 - range->flags.has_dma_mapping = true; 1475 1475 if (zdd) { 1476 1476 range->flags.has_devmem_pages = true; 1477 1477 range->dpagemap = dpagemap;
+5 -1
drivers/gpu/drm/drm_mipi_dbi.c
··· 404 404 u16 height = drm->mode_config.min_height; 405 405 u16 width = drm->mode_config.min_width; 406 406 struct mipi_dbi *dbi = &dbidev->dbi; 407 - size_t len = width * height * 2; 407 + const struct drm_format_info *dst_format; 408 + size_t len; 408 409 int idx; 409 410 410 411 if (!drm_dev_enter(drm, &idx)) 411 412 return; 413 + 414 + dst_format = drm_format_info(dbidev->pixel_format); 415 + len = drm_format_info_min_pitch(dst_format, 0, width) * height; 412 416 413 417 memset(dbidev->tx_buf, 0, len); 414 418
+6 -2
drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
··· 23 23 24 24 int intel_pxp_gsccs_create_session(struct intel_pxp *pxp, int arb_session_id); 25 25 void intel_pxp_gsccs_end_arb_fw_session(struct intel_pxp *pxp, u32 arb_session_id); 26 + bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp); 26 27 27 28 #else 28 29 static inline void intel_pxp_gsccs_fini(struct intel_pxp *pxp) ··· 35 34 return 0; 36 35 } 37 36 38 - #endif 37 + static inline bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp) 38 + { 39 + return false; 40 + } 39 41 40 - bool intel_pxp_gsccs_is_ready_for_sessions(struct intel_pxp *pxp); 42 + #endif 41 43 42 44 #endif /*__INTEL_PXP_GSCCS_H__ */
+1 -1
drivers/gpu/drm/nouveau/nouveau_fence.c
··· 90 90 while (!list_empty(&fctx->pending)) { 91 91 fence = list_entry(fctx->pending.next, typeof(*fence), head); 92 92 93 - if (error) 93 + if (error && !dma_fence_is_signaled_locked(&fence->base)) 94 94 dma_fence_set_error(&fence->base, error); 95 95 96 96 if (nouveau_fence_signal(fence))
+3
drivers/gpu/drm/tests/drm_gem_shmem_test.c
··· 216 216 KUNIT_ASSERT_NOT_ERR_OR_NULL(test, sgt); 217 217 KUNIT_EXPECT_NULL(test, shmem->sgt); 218 218 219 + ret = kunit_add_action_or_reset(test, kfree_wrapper, sgt); 220 + KUNIT_ASSERT_EQ(test, ret, 0); 221 + 219 222 ret = kunit_add_action_or_reset(test, sg_free_table_wrapper, sgt); 220 223 KUNIT_ASSERT_EQ(test, ret, 0); 221 224
+2 -1
drivers/gpu/drm/ttm/ttm_bo.c
··· 1093 1093 struct ttm_lru_walk walk; 1094 1094 /** @gfp_flags: The gfp flags to use for ttm_tt_swapout() */ 1095 1095 gfp_t gfp_flags; 1096 - 1096 + /** @hit_low: Whether we should attempt to swap BO's with low watermark threshold */ 1097 + /** @evict_low: If we cannot swap a bo when @try_low is false (first pass) */ 1097 1098 bool hit_low, evict_low; 1098 1099 }; 1099 1100
+12 -2
drivers/gpu/drm/xe/xe_eu_stall.c
··· 52 52 53 53 struct xe_gt *gt; 54 54 struct xe_bo *bo; 55 + /* Lock to protect data buffer pointers */ 56 + struct mutex xecore_buf_lock; 55 57 struct per_xecore_buf *xecore_buf; 56 58 struct { 57 59 bool reported_to_user; ··· 209 207 { 210 208 struct xe_device *xe = gt_to_xe(gt); 211 209 int ret; 210 + 211 + if (!xe_eu_stall_supported_on_platform(xe)) 212 + return 0; 212 213 213 214 gt->eu_stall = kzalloc(sizeof(*gt->eu_stall), GFP_KERNEL); 214 215 if (!gt->eu_stall) { ··· 383 378 u16 group, instance; 384 379 unsigned int xecore; 385 380 386 - mutex_lock(&gt->eu_stall->stream_lock); 381 + mutex_lock(&stream->xecore_buf_lock); 387 382 for_each_dss_steering(xecore, gt, group, instance) { 388 383 xecore_buf = &stream->xecore_buf[xecore]; 389 384 read_ptr = xecore_buf->read; ··· 401 396 set_bit(xecore, stream->data_drop.mask); 402 397 xecore_buf->write = write_ptr; 403 398 } 404 - mutex_unlock(&gt->eu_stall->stream_lock); 399 + mutex_unlock(&stream->xecore_buf_lock); 405 400 406 401 return min_data_present; 407 402 } ··· 516 511 unsigned int xecore; 517 512 int ret = 0; 518 513 514 + mutex_lock(&stream->xecore_buf_lock); 519 515 if (bitmap_weight(stream->data_drop.mask, XE_MAX_DSS_FUSE_BITS)) { 520 516 if (!stream->data_drop.reported_to_user) { 521 517 stream->data_drop.reported_to_user = true; 522 518 xe_gt_dbg(gt, "EU stall data dropped in XeCores: %*pb\n", 523 519 XE_MAX_DSS_FUSE_BITS, stream->data_drop.mask); 520 + mutex_unlock(&stream->xecore_buf_lock); 524 521 return -EIO; 525 522 } 526 523 stream->data_drop.reported_to_user = false; ··· 534 527 if (ret || count == total_size) 535 528 break; 536 529 } 530 + mutex_unlock(&stream->xecore_buf_lock); 537 531 return total_size ?: (ret ?: -EAGAIN); 538 532 } 539 533 ··· 591 583 { 592 584 struct xe_gt *gt = stream->gt; 593 585 586 + mutex_destroy(&stream->xecore_buf_lock); 594 587 gt->eu_stall->stream = NULL; 595 588 kfree(stream); 596 589 } ··· 727 718 } 728 719 729 720 init_waitqueue_head(&stream->poll_wq); 721 + mutex_init(&stream->xecore_buf_lock); 730 722 INIT_DELAYED_WORK(&stream->buf_poll_work, eu_stall_data_buf_poll_work_fn); 731 723 stream->per_xecore_buf_size = per_xecore_buf_size; 732 724 stream->sampling_rate_mult = props->sampling_rate_mult;
+2 -1
drivers/gpu/drm/xe/xe_eu_stall.h
··· 7 7 #define __XE_EU_STALL_H__ 8 8 9 9 #include "xe_gt_types.h" 10 + #include "xe_sriov.h" 10 11 11 12 size_t xe_eu_stall_get_per_xecore_buf_size(void); 12 13 size_t xe_eu_stall_data_record_size(struct xe_device *xe); ··· 20 19 21 20 static inline bool xe_eu_stall_supported_on_platform(struct xe_device *xe) 22 21 { 23 - return xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20; 22 + return !IS_SRIOV_VF(xe) && (xe->info.platform == XE_PVC || GRAPHICS_VER(xe) >= 20); 24 23 } 25 24 #endif
+1 -1
drivers/gpu/drm/xe/xe_guc_capture.c
··· 359 359 360 360 ext->reg = XE_REG(extlist->reg.__reg.addr); 361 361 ext->flags = FIELD_PREP(GUC_REGSET_STEERING_NEEDED, 1); 362 - ext->flags = FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); 362 + ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_GROUP, slice_id); 363 363 ext->flags |= FIELD_PREP(GUC_REGSET_STEERING_INSTANCE, subslice_id); 364 364 ext->regname = extlist->name; 365 365 }
+1 -1
drivers/gpu/drm/xe/xe_svm.c
··· 79 79 80 80 range = kzalloc(sizeof(*range), GFP_KERNEL); 81 81 if (!range) 82 - return ERR_PTR(-ENOMEM); 82 + return NULL; 83 83 84 84 INIT_LIST_HEAD(&range->garbage_collector_link); 85 85 xe_vm_get(gpusvm_to_vm(gpusvm));