Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2025-08-23-1' of https://gitlab.freedesktop.org/drm/kernel
Pull drm fixes from Dave Airlie:
"Weekly drm fixes. Looks like things did indeed get busier after rc2,
nothing seems too major, but stuff scattered all over the place,
amdgpu, xe, i915, hibmc, rust support code, and other small fixes.
rust:
- drm device memory layout and safety fixes
tests:
- Endianness fixes
gpuvm:
- docs warning fix
panic:
- fix division on 32-bit arm
i915:
- TypeC DP display Fixes
- Silence rpm wakeref asserts on GEN11_GU_MISC_IIR access
- Relocate compression repacking WA for JSL/EHL
xe:
- xe_vm_create fixes
- fix vm bind ioctl double free
amdgpu:
- Replay fixes
- SMU14 fix
- Null check DC fixes
- DCE6 DC fixes
- Misc DC fixes
bridge:
- analogix_dp: devm_drm_bridge_alloc() error handling fix
habanalabs:
- Memory deallocation fix
hibmc:
- modesetting black screen fixes
- fix UAF on irq
- fix leak on i2c failure path
nouveau:
- memory leak fixes
- typos
rockchip:
- Kconfig fix
- register caching fix"
* tag 'drm-fixes-2025-08-23-1' of https://gitlab.freedesktop.org/drm/kernel: (49 commits)
drm/xe: Fix vm_bind_ioctl double free bug
drm/xe: Move ASID allocation and user PT BO tracking into xe_vm_create
drm/xe: Assign ioctl xe file handler to vm in xe_vm_create
drm/i915/gt: Relocate compression repacking WA for JSL/EHL
drm/i915: silence rpm wakeref asserts on GEN11_GU_MISC_IIR access
drm/amd/display: Fix DP audio DTO1 clock source on DCE 6.
drm/amd/display: Fix fractional fb divider in set_pixel_clock_v3
drm/amd/display: Don't print errors for nonexistent connectors
drm/amd/display: Don't warn when missing DCE encoder caps
drm/amd/display: Fill display clock and vblank time in dce110_fill_display_configs
drm/amd/display: Find first CRTC and its line time in dce110_fill_display_configs
drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
drm/amd/display: Don't overclock DCE 6 by 15%
drm/amd/display: Add null pointer check in mod_hdcp_hdcp1_create_session()
drm/amd/display: Fix Xorg desktop unresponsive on Replay panel
drm/amd/display: Avoid a NULL pointer dereference
drm/amdgpu/swm14: Update power limit logic
drm/amd/display: Revert Add HPO encoder support to Replay
drm/i915/icl+/tc: Convert AUX powered WARN to a debug message
drm/i915/lnl+/tc: Use the cached max lane count value
...
+382
-239
+13
-1
MAINTAINERS
+13
-1
MAINTAINERS
···
8426
8426
F: drivers/gpu/drm/scheduler/
8427
8427
F: include/drm/gpu_scheduler.h
8428
8428
8429
+
DRM GPUVM
8430
+
M: Danilo Krummrich <dakr@kernel.org>
8431
+
R: Matthew Brost <matthew.brost@intel.com>
8432
+
R: Thomas Hellström <thomas.hellstrom@linux.intel.com>
8433
+
R: Alice Ryhl <aliceryhl@google.com>
8434
+
L: dri-devel@lists.freedesktop.org
8435
+
S: Supported
8436
+
T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
8437
+
F: drivers/gpu/drm/drm_gpuvm.c
8438
+
F: include/drm/drm_gpuvm.h
8439
+
8429
8440
DRM LOG
8430
8441
M: Jocelyn Falempe <jfalempe@redhat.com>
8431
8442
M: Javier Martinez Canillas <javierm@redhat.com>
···
10666
10655
F: block/partitions/efi.*
10667
10656
10668
10657
HABANALABS PCI DRIVER
10669
-
M: Yaron Avizrat <yaron.avizrat@intel.com>
10658
+
M: Koby Elbaz <koby.elbaz@intel.com>
10659
+
M: Konstantin Sinyuk <konstantin.sinyuk@intel.com>
10670
10660
L: dri-devel@lists.freedesktop.org
10671
10661
S: Supported
10672
10662
C: irc://irc.oftc.net/dri-devel
+1
-1
drivers/accel/habanalabs/gaudi2/gaudi2.c
+1
-1
drivers/accel/habanalabs/gaudi2/gaudi2.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+2
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
···
317
317
*/
318
318
if (!vm->is_compute_context || !vm->process_info)
319
319
return 0;
320
-
if (!drm_gem_is_imported(obj) || !dma_buf_is_dynamic(obj->dma_buf))
320
+
if (!drm_gem_is_imported(obj) ||
321
+
!dma_buf_is_dynamic(obj->import_attach->dmabuf))
321
322
return 0;
322
323
mutex_lock_nested(&vm->process_info->lock, 1);
323
324
if (!WARN_ON(!vm->process_info->eviction_fence)) {
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+1
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
1283
1283
struct drm_gem_object *obj = &bo->tbo.base;
1284
1284
1285
1285
if (drm_gem_is_imported(obj) && bo_va->is_xgmi) {
1286
-
struct dma_buf *dma_buf = obj->dma_buf;
1286
+
struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1287
1287
struct drm_gem_object *gobj = dma_buf->priv;
1288
1288
struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1289
1289
+3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+3
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
7792
7792
struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn);
7793
7793
int ret;
7794
7794
7795
+
if (WARN_ON(unlikely(!old_con_state || !new_con_state)))
7796
+
return -EINVAL;
7797
+
7795
7798
trace_amdgpu_dm_connector_atomic_check(new_con_state);
7796
7799
7797
7800
if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) {
+19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+19
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
···
299
299
irq_type = amdgpu_display_crtc_idx_to_irq_type(adev, acrtc->crtc_id);
300
300
301
301
if (enable) {
302
+
struct dc *dc = adev->dm.dc;
303
+
struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
304
+
struct psr_settings *psr = &acrtc_state->stream->link->psr_settings;
305
+
struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
306
+
bool sr_supported = (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED) ||
307
+
pr->config.replay_supported;
308
+
309
+
/*
310
+
* IPS & self-refresh feature can cause vblank counter resets between
311
+
* vblank disable and enable.
312
+
* It may cause system stuck due to waiting for the vblank counter.
313
+
* Call this function to estimate missed vblanks by using timestamps and
314
+
* update the vblank counter in DRM.
315
+
*/
316
+
if (dc->caps.ips_support &&
317
+
dc->config.disable_ips != DMUB_IPS_DISABLE_ALL &&
318
+
sr_supported && vblank->config.disable_immediate)
319
+
drm_crtc_vblank_restore(crtc);
320
+
302
321
/* vblank irq on -> Only need vupdate irq in vrr mode */
303
322
if (amdgpu_dm_crtc_vrr_active(acrtc_state))
304
323
rc = amdgpu_dm_crtc_set_vupdate_irq(crtc, true);
+1
-4
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+1
-4
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
···
174
174
return object_id;
175
175
}
176
176
177
-
if (tbl->ucNumberOfObjects <= i) {
178
-
dm_error("Can't find connector id %d in connector table of size %d.\n",
179
-
i, tbl->ucNumberOfObjects);
177
+
if (tbl->ucNumberOfObjects <= i)
180
178
return object_id;
181
-
}
182
179
183
180
id = le16_to_cpu(tbl->asObjects[i].usObjectID);
184
181
object_id = object_id_from_bios_object_id(id);
+1
-1
drivers/gpu/drm/amd/display/dc/bios/command_table.c
+1
-1
drivers/gpu/drm/amd/display/dc/bios/command_table.c
···
993
993
allocation.sPCLKInput.usFbDiv =
994
994
cpu_to_le16((uint16_t)bp_params->feedback_divider);
995
995
allocation.sPCLKInput.ucFracFbDiv =
996
-
(uint8_t)bp_params->fractional_feedback_divider;
996
+
(uint8_t)(bp_params->fractional_feedback_divider / 100000);
997
997
allocation.sPCLKInput.ucPostDiv =
998
998
(uint8_t)bp_params->pixel_clock_post_divider;
999
999
+5
-9
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+5
-9
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
···
72
72
/* ClocksStateLow */
73
73
{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
74
74
/* ClocksStateNominal */
75
-
{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
75
+
{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
76
76
/* ClocksStatePerformance */
77
-
{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
77
+
{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
78
78
79
79
int dentist_get_divider_from_did(int did)
80
80
{
···
391
391
{
392
392
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
393
393
394
-
pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
395
-
396
394
dce110_fill_display_configs(context, pp_display_cfg);
397
395
398
396
if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
···
403
405
{
404
406
struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
405
407
struct dm_pp_power_level_change_request level_change_req;
406
-
int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
407
-
408
-
/*TODO: W/A for dal3 linux, investigate why this works */
409
-
if (!clk_mgr_dce->dfs_bypass_active)
410
-
patched_disp_clk = patched_disp_clk * 115 / 100;
408
+
const int max_disp_clk =
409
+
clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
410
+
int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
411
411
412
412
level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
413
413
/* get max clock state from PPLIB */
+23
-17
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+23
-17
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
···
120
120
const struct dc_state *context,
121
121
struct dm_pp_display_configuration *pp_display_cfg)
122
122
{
123
+
struct dc *dc = context->clk_mgr->ctx->dc;
123
124
int j;
124
125
int num_cfgs = 0;
126
+
127
+
pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
128
+
pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
129
+
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
130
+
pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
125
131
126
132
for (j = 0; j < context->stream_count; j++) {
127
133
int k;
···
170
164
cfg->v_refresh /= stream->timing.h_total;
171
165
cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2)
172
166
/ stream->timing.v_total;
167
+
168
+
/* Find first CRTC index and calculate its line time.
169
+
* This is necessary for DPM on SI GPUs.
170
+
*/
171
+
if (cfg->pipe_idx < pp_display_cfg->crtc_index) {
172
+
const struct dc_crtc_timing *timing =
173
+
&context->streams[0]->timing;
174
+
175
+
pp_display_cfg->crtc_index = cfg->pipe_idx;
176
+
pp_display_cfg->line_time_in_us =
177
+
timing->h_total * 10000 / timing->pix_clk_100hz;
178
+
}
179
+
}
180
+
181
+
if (!num_cfgs) {
182
+
pp_display_cfg->crtc_index = 0;
183
+
pp_display_cfg->line_time_in_us = 0;
173
184
}
174
185
175
186
pp_display_cfg->display_count = num_cfgs;
···
246
223
pp_display_cfg->min_engine_clock_deep_sleep_khz
247
224
= context->bw_ctx.bw.dce.sclk_deep_sleep_khz;
248
225
249
-
pp_display_cfg->avail_mclk_switch_time_us =
250
-
dce110_get_min_vblank_time_us(context);
251
-
/* TODO: dce11.2*/
252
-
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
253
-
254
-
pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
255
-
256
226
dce110_fill_display_configs(context, pp_display_cfg);
257
-
258
-
/* TODO: is this still applicable?*/
259
-
if (pp_display_cfg->display_count == 1) {
260
-
const struct dc_crtc_timing *timing =
261
-
&context->streams[0]->timing;
262
-
263
-
pp_display_cfg->crtc_index =
264
-
pp_display_cfg->disp_configs[0].pipe_idx;
265
-
pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz;
266
-
}
267
227
268
228
if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0)
269
229
dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg);
+9
-22
drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
+9
-22
drivers/gpu/drm/amd/display/dc/clk_mgr/dce60/dce60_clk_mgr.c
···
83
83
static int dce60_get_dp_ref_freq_khz(struct clk_mgr *clk_mgr_base)
84
84
{
85
85
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
86
-
int dprefclk_wdivider;
87
-
int dp_ref_clk_khz;
88
-
int target_div;
86
+
struct dc_context *ctx = clk_mgr_base->ctx;
87
+
int dp_ref_clk_khz = 0;
89
88
90
-
/* DCE6 has no DPREFCLK_CNTL to read DP Reference Clock source */
91
-
92
-
/* Read the mmDENTIST_DISPCLK_CNTL to get the currently
93
-
* programmed DID DENTIST_DPREFCLK_WDIVIDER*/
94
-
REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DPREFCLK_WDIVIDER, &dprefclk_wdivider);
95
-
96
-
/* Convert DENTIST_DPREFCLK_WDIVIDERto actual divider*/
97
-
target_div = dentist_get_divider_from_did(dprefclk_wdivider);
98
-
99
-
/* Calculate the current DFS clock, in kHz.*/
100
-
dp_ref_clk_khz = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR
101
-
* clk_mgr->base.dentist_vco_freq_khz) / target_div;
89
+
if (ASIC_REV_IS_TAHITI_P(ctx->asic_id.hw_internal_rev))
90
+
dp_ref_clk_khz = ctx->dc_bios->fw_info.default_display_engine_pll_frequency;
91
+
else
92
+
dp_ref_clk_khz = clk_mgr_base->clks.dispclk_khz;
102
93
103
94
return dce_adjust_dp_ref_freq_for_ss(clk_mgr, dp_ref_clk_khz);
104
95
}
···
99
108
struct dc_state *context)
100
109
{
101
110
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
102
-
103
-
pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
104
111
105
112
dce110_fill_display_configs(context, pp_display_cfg);
106
113
···
112
123
{
113
124
struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
114
125
struct dm_pp_power_level_change_request level_change_req;
115
-
int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
116
-
117
-
/*TODO: W/A for dal3 linux, investigate why this works */
118
-
if (!clk_mgr_dce->dfs_bypass_active)
119
-
patched_disp_clk = patched_disp_clk * 115 / 100;
126
+
const int max_disp_clk =
127
+
clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
128
+
int patched_disp_clk = MIN(max_disp_clk, context->bw_ctx.bw.dce.dispclk_khz);
120
129
121
130
level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context);
122
131
/* get max clock state from PPLIB */
+14
-1
drivers/gpu/drm/amd/display/dc/core/dc.c
+14
-1
drivers/gpu/drm/amd/display/dc/core/dc.c
···
217
217
connectors_num,
218
218
num_virtual_links);
219
219
220
-
// condition loop on link_count to allow skipping invalid indices
220
+
/* When getting the number of connectors, the VBIOS reports the number of valid indices,
221
+
* but it doesn't say which indices are valid, and not every index has an actual connector.
222
+
* So, if we don't find a connector on an index, that is not an error.
223
+
*
224
+
* - There is no guarantee that the first N indices will be valid
225
+
* - VBIOS may report a higher amount of valid indices than there are actual connectors
226
+
* - Some VBIOS have valid configurations for more connectors than there actually are
227
+
* on the card. This may be because the manufacturer used the same VBIOS for different
228
+
* variants of the same card.
229
+
*/
221
230
for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
231
+
struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);
222
232
struct link_init_data link_init_params = {0};
223
233
struct dc_link *link;
234
+
235
+
if (connector_id.id == CONNECTOR_ID_UNKNOWN)
236
+
continue;
224
237
225
238
DC_LOG_DC("BIOS object table - printing link object info for connector number: %d, link_index: %d", i, dc->link_count);
226
239
+4
-4
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
+4
-4
drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c
···
896
896
enc110->base.id, &bp_cap_info);
897
897
898
898
/* Override features with DCE-specific values */
899
-
if (BP_RESULT_OK == result) {
899
+
if (result == BP_RESULT_OK) {
900
900
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
901
901
bp_cap_info.DP_HBR2_EN;
902
902
enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
903
903
bp_cap_info.DP_HBR3_EN;
904
904
enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
905
-
} else {
905
+
} else if (result != BP_RESULT_NORECORD) {
906
906
DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
907
907
__func__,
908
908
result);
···
1798
1798
enc110->base.id, &bp_cap_info);
1799
1799
1800
1800
/* Override features with DCE-specific values */
1801
-
if (BP_RESULT_OK == result) {
1801
+
if (result == BP_RESULT_OK) {
1802
1802
enc110->base.features.flags.bits.IS_HBR2_CAPABLE =
1803
1803
bp_cap_info.DP_HBR2_EN;
1804
1804
enc110->base.features.flags.bits.IS_HBR3_CAPABLE =
1805
1805
bp_cap_info.DP_HBR3_EN;
1806
1806
enc110->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
1807
-
} else {
1807
+
} else if (result != BP_RESULT_NORECORD) {
1808
1808
DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
1809
1809
__func__,
1810
1810
result);
+3
-40
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+3
-40
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
···
4
4
5
5
#include "dc.h"
6
6
#include "dc_dmub_srv.h"
7
-
#include "dc_dp_types.h"
8
7
#include "dmub/dmub_srv.h"
9
8
#include "core_types.h"
10
9
#include "dmub_replay.h"
···
43
44
/*
44
45
* Enable/Disable Replay.
45
46
*/
46
-
static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst,
47
-
struct dc_link *link)
47
+
static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst)
48
48
{
49
49
union dmub_rb_cmd cmd;
50
50
struct dc_context *dc = dmub->ctx;
51
51
uint32_t retry_count;
52
52
enum replay_state state = REPLAY_STATE_0;
53
-
struct pipe_ctx *pipe_ctx = NULL;
54
-
struct resource_context *res_ctx = &link->ctx->dc->current_state->res_ctx;
55
-
uint8_t i;
56
53
57
54
memset(&cmd, 0, sizeof(cmd));
58
55
cmd.replay_enable.header.type = DMUB_CMD__REPLAY;
59
56
cmd.replay_enable.data.panel_inst = panel_inst;
60
57
61
58
cmd.replay_enable.header.sub_type = DMUB_CMD__REPLAY_ENABLE;
62
-
if (enable) {
59
+
if (enable)
63
60
cmd.replay_enable.data.enable = REPLAY_ENABLE;
64
-
// hpo stream/link encoder assignments are not static, need to update everytime we try to enable replay
65
-
if (link->cur_link_settings.link_rate >= LINK_RATE_UHBR10) {
66
-
for (i = 0; i < MAX_PIPES; i++) {
67
-
if (res_ctx &&
68
-
res_ctx->pipe_ctx[i].stream &&
69
-
res_ctx->pipe_ctx[i].stream->link &&
70
-
res_ctx->pipe_ctx[i].stream->link == link &&
71
-
res_ctx->pipe_ctx[i].stream->link->connector_signal == SIGNAL_TYPE_EDP) {
72
-
pipe_ctx = &res_ctx->pipe_ctx[i];
73
-
//TODO: refactor for multi edp support
74
-
break;
75
-
}
76
-
}
77
-
78
-
if (!pipe_ctx)
79
-
return;
80
-
81
-
cmd.replay_enable.data.hpo_stream_enc_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
82
-
cmd.replay_enable.data.hpo_link_enc_inst = pipe_ctx->link_res.hpo_dp_link_enc->inst;
83
-
}
84
-
} else
61
+
else
85
62
cmd.replay_enable.data.enable = REPLAY_DISABLE;
86
63
87
64
cmd.replay_enable.header.payload_bytes = sizeof(struct dmub_rb_cmd_replay_enable_data);
···
149
174
copy_settings_data->digbe_inst = replay_context->digbe_inst;
150
175
copy_settings_data->digfe_inst = replay_context->digfe_inst;
151
176
152
-
if (link->cur_link_settings.link_rate >= LINK_RATE_UHBR10) {
153
-
if (pipe_ctx->stream_res.hpo_dp_stream_enc)
154
-
copy_settings_data->hpo_stream_enc_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;
155
-
else
156
-
copy_settings_data->hpo_stream_enc_inst = 0;
157
-
if (pipe_ctx->link_res.hpo_dp_link_enc)
158
-
copy_settings_data->hpo_link_enc_inst = pipe_ctx->link_res.hpo_dp_link_enc->inst;
159
-
else
160
-
copy_settings_data->hpo_link_enc_inst = 0;
161
-
}
162
-
163
177
if (pipe_ctx->plane_res.dpp)
164
178
copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
165
179
else
···
211
247
pCmd->header.type = DMUB_CMD__REPLAY;
212
248
pCmd->header.sub_type = DMUB_CMD__REPLAY_SET_COASTING_VTOTAL;
213
249
pCmd->header.payload_bytes = sizeof(struct dmub_cmd_replay_set_coasting_vtotal_data);
214
-
pCmd->replay_set_coasting_vtotal_data.panel_inst = panel_inst;
215
250
pCmd->replay_set_coasting_vtotal_data.coasting_vtotal = (coasting_vtotal & 0xFFFF);
216
251
pCmd->replay_set_coasting_vtotal_data.coasting_vtotal_high = (coasting_vtotal & 0xFFFF0000) >> 16;
217
252
+1
-1
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
+1
-1
drivers/gpu/drm/amd/display/dc/dce/dmub_replay.h
···
19
19
void (*replay_get_state)(struct dmub_replay *dmub, enum replay_state *state,
20
20
uint8_t panel_inst);
21
21
void (*replay_enable)(struct dmub_replay *dmub, bool enable, bool wait,
22
-
uint8_t panel_inst, struct dc_link *link);
22
+
uint8_t panel_inst);
23
23
bool (*replay_copy_settings)(struct dmub_replay *dmub, struct dc_link *link,
24
24
struct replay_context *replay_context, uint8_t panel_inst);
25
25
void (*replay_set_power_opt)(struct dmub_replay *dmub, unsigned int power_opt,
+1
-1
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+1
-1
drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
···
944
944
// TODO: Handle mux change case if force_static is set
945
945
// If force_static is set, just change the replay_allow_active state directly
946
946
if (replay != NULL && link->replay_settings.replay_feature_enabled)
947
-
replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst, link);
947
+
replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst);
948
948
link->replay_settings.replay_allow_active = *allow_active;
949
949
}
950
950
-20
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
-20
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
···
4048
4048
*/
4049
4049
uint8_t digbe_inst;
4050
4050
/**
4051
-
* @hpo_stream_enc_inst: HPO stream encoder instance
4052
-
*/
4053
-
uint8_t hpo_stream_enc_inst;
4054
-
/**
4055
-
* @hpo_link_enc_inst: HPO link encoder instance
4056
-
*/
4057
-
uint8_t hpo_link_enc_inst;
4058
-
/**
4059
4051
* AUX HW instance.
4060
4052
*/
4061
4053
uint8_t aux_inst;
···
4151
4159
* This does not support HDMI/DP2 for now.
4152
4160
*/
4153
4161
uint8_t phy_rate;
4154
-
/**
4155
-
* @hpo_stream_enc_inst: HPO stream encoder instance
4156
-
*/
4157
-
uint8_t hpo_stream_enc_inst;
4158
-
/**
4159
-
* @hpo_link_enc_inst: HPO link encoder instance
4160
-
*/
4161
-
uint8_t hpo_link_enc_inst;
4162
-
/**
4163
-
* @pad: Align structure to 4 byte boundary.
4164
-
*/
4165
-
uint8_t pad[2];
4166
4162
};
4167
4163
4168
4164
/**
+3
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+3
drivers/gpu/drm/amd/display/modules/hdcp/hdcp_psp.c
+25
-5
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
+25
-5
drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c
···
1697
1697
uint32_t *min_power_limit)
1698
1698
{
1699
1699
struct smu_table_context *table_context = &smu->smu_table;
1700
+
struct smu_14_0_2_powerplay_table *powerplay_table =
1701
+
table_context->power_play_table;
1700
1702
PPTable_t *pptable = table_context->driver_pptable;
1701
1703
CustomSkuTable_t *skutable = &pptable->CustomSkuTable;
1702
-
uint32_t power_limit;
1704
+
uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
1703
1705
uint32_t msg_limit = pptable->SkuTable.MsgLimits.Power[PPT_THROTTLER_PPT0][POWER_SOURCE_AC];
1704
1706
1705
1707
if (smu_v14_0_get_current_power_limit(smu, &power_limit))
···
1714
1712
if (default_power_limit)
1715
1713
*default_power_limit = power_limit;
1716
1714
1717
-
if (max_power_limit)
1718
-
*max_power_limit = msg_limit;
1715
+
if (powerplay_table) {
1716
+
if (smu->od_enabled &&
1717
+
smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
1718
+
od_percent_upper = pptable->SkuTable.OverDriveLimitsBasicMax.Ppt;
1719
+
od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt;
1720
+
} else if (smu_v14_0_2_is_od_feature_supported(smu, PP_OD_FEATURE_PPT_BIT)) {
1721
+
od_percent_upper = 0;
1722
+
od_percent_lower = pptable->SkuTable.OverDriveLimitsBasicMin.Ppt;
1723
+
}
1724
+
}
1719
1725
1720
-
if (min_power_limit)
1721
-
*min_power_limit = 0;
1726
+
dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
1727
+
od_percent_upper, od_percent_lower, power_limit);
1728
+
1729
+
if (max_power_limit) {
1730
+
*max_power_limit = msg_limit * (100 + od_percent_upper);
1731
+
*max_power_limit /= 100;
1732
+
}
1733
+
1734
+
if (min_power_limit) {
1735
+
*min_power_limit = power_limit * (100 + od_percent_lower);
1736
+
*min_power_limit /= 100;
1737
+
}
1722
1738
1723
1739
return 0;
1724
1740
}
+2
-2
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+2
-2
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
···
1474
1474
1475
1475
dp = devm_drm_bridge_alloc(dev, struct analogix_dp_device, bridge,
1476
1476
&analogix_dp_bridge_funcs);
1477
-
if (!dp)
1478
-
return ERR_PTR(-ENOMEM);
1477
+
if (IS_ERR(dp))
1478
+
return ERR_CAST(dp);
1479
1479
1480
1480
dp->dev = &pdev->dev;
1481
1481
dp->dpms_mode = DRM_MODE_DPMS_OFF;
+2
drivers/gpu/drm/drm_gpuvm.c
+2
drivers/gpu/drm/drm_gpuvm.c
+21
-1
drivers/gpu/drm/drm_panic_qr.rs
+21
-1
drivers/gpu/drm/drm_panic_qr.rs
···
381
381
len: usize,
382
382
}
383
383
384
+
// On arm32 architecture, dividing an `u64` by a constant will generate a call
385
+
// to `__aeabi_uldivmod` which is not present in the kernel.
386
+
// So use the multiply by inverse method for this architecture.
387
+
fn div10(val: u64) -> u64 {
388
+
if cfg!(target_arch = "arm") {
389
+
let val_h = val >> 32;
390
+
let val_l = val & 0xFFFFFFFF;
391
+
let b_h: u64 = 0x66666666;
392
+
let b_l: u64 = 0x66666667;
393
+
394
+
let tmp1 = val_h * b_l + ((val_l * b_l) >> 32);
395
+
let tmp2 = val_l * b_h + (tmp1 & 0xffffffff);
396
+
let tmp3 = val_h * b_h + (tmp1 >> 32) + (tmp2 >> 32);
397
+
398
+
tmp3 >> 2
399
+
} else {
400
+
val / 10
401
+
}
402
+
}
403
+
384
404
impl DecFifo {
385
405
fn push(&mut self, data: u64, len: usize) {
386
406
let mut chunk = data;
···
409
389
}
410
390
for i in 0..len {
411
391
self.decimals[i] = (chunk % 10) as u8;
412
-
chunk /= 10;
392
+
chunk = div10(chunk);
413
393
}
414
394
self.len += len;
415
395
}
+12
-2
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
+12
-2
drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c
···
325
325
return hibmc_dp_link_reduce_rate(dp);
326
326
}
327
327
328
+
static void hibmc_dp_update_caps(struct hibmc_dp_dev *dp)
329
+
{
330
+
dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE];
331
+
if (dp->link.cap.link_rate > DP_LINK_BW_8_1 || !dp->link.cap.link_rate)
332
+
dp->link.cap.link_rate = DP_LINK_BW_8_1;
333
+
334
+
dp->link.cap.lanes = dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
335
+
if (dp->link.cap.lanes > HIBMC_DP_LANE_NUM_MAX)
336
+
dp->link.cap.lanes = HIBMC_DP_LANE_NUM_MAX;
337
+
}
338
+
328
339
int hibmc_dp_link_training(struct hibmc_dp_dev *dp)
329
340
{
330
341
struct hibmc_dp_link *link = &dp->link;
···
345
334
if (ret)
346
335
drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret);
347
336
348
-
dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE];
349
-
dp->link.cap.lanes = 0x2;
337
+
hibmc_dp_update_caps(dp);
350
338
351
339
ret = hibmc_dp_get_serdes_rate_cfg(dp);
352
340
if (ret < 0)
+13
-9
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
+13
-9
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c
···
32
32
33
33
DEFINE_DRM_GEM_FOPS(hibmc_fops);
34
34
35
-
static const char *g_irqs_names_map[HIBMC_MAX_VECTORS] = { "vblank", "hpd" };
35
+
static const char *g_irqs_names_map[HIBMC_MAX_VECTORS] = { "hibmc-vblank", "hibmc-hpd" };
36
36
37
37
static irqreturn_t hibmc_interrupt(int irq, void *arg)
38
38
{
···
115
115
static int hibmc_kms_init(struct hibmc_drm_private *priv)
116
116
{
117
117
struct drm_device *dev = &priv->dev;
118
+
struct drm_encoder *encoder;
119
+
u32 clone_mask = 0;
118
120
int ret;
119
121
120
122
ret = drmm_mode_config_init(dev);
···
155
153
drm_err(dev, "failed to init vdac: %d\n", ret);
156
154
return ret;
157
155
}
156
+
157
+
drm_for_each_encoder(encoder, dev)
158
+
clone_mask |= drm_encoder_mask(encoder);
159
+
160
+
drm_for_each_encoder(encoder, dev)
161
+
encoder->possible_clones = clone_mask;
158
162
159
163
return 0;
160
164
}
···
285
277
static int hibmc_msi_init(struct drm_device *dev)
286
278
{
287
279
struct pci_dev *pdev = to_pci_dev(dev->dev);
288
-
char name[32] = {0};
289
280
int valid_irq_num;
290
281
int irq;
291
282
int ret;
···
299
292
valid_irq_num = ret;
300
293
301
294
for (int i = 0; i < valid_irq_num; i++) {
302
-
snprintf(name, ARRAY_SIZE(name) - 1, "%s-%s-%s",
303
-
dev->driver->name, pci_name(pdev), g_irqs_names_map[i]);
304
-
305
295
irq = pci_irq_vector(pdev, i);
306
296
307
297
if (i)
···
306
302
ret = devm_request_threaded_irq(&pdev->dev, irq,
307
303
hibmc_dp_interrupt,
308
304
hibmc_dp_hpd_isr,
309
-
IRQF_SHARED, name, dev);
305
+
IRQF_SHARED, g_irqs_names_map[i], dev);
310
306
else
311
307
ret = devm_request_irq(&pdev->dev, irq, hibmc_interrupt,
312
-
IRQF_SHARED, name, dev);
308
+
IRQF_SHARED, g_irqs_names_map[i], dev);
313
309
if (ret) {
314
310
drm_err(dev, "install irq failed: %d\n", ret);
315
311
return ret;
···
327
323
328
324
ret = hibmc_hw_init(priv);
329
325
if (ret)
330
-
goto err;
326
+
return ret;
331
327
332
328
ret = drmm_vram_helper_init(dev, pci_resource_start(pdev, 0),
333
329
pci_resource_len(pdev, 0));
334
330
if (ret) {
335
331
drm_err(dev, "Error initializing VRAM MM; %d\n", ret);
336
-
goto err;
332
+
return ret;
337
333
}
338
334
339
335
ret = hibmc_kms_init(priv);
+1
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h
+1
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h
+5
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c
+5
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_i2c.c
+8
-3
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
+8
-3
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c
···
53
53
{
54
54
struct hibmc_vdac *vdac = to_hibmc_vdac(connector);
55
55
56
-
i2c_del_adapter(&vdac->adapter);
56
+
hibmc_ddc_del(vdac);
57
57
drm_connector_cleanup(connector);
58
58
}
59
59
···
110
110
ret = drmm_encoder_init(dev, encoder, NULL, DRM_MODE_ENCODER_DAC, NULL);
111
111
if (ret) {
112
112
drm_err(dev, "failed to init encoder: %d\n", ret);
113
-
return ret;
113
+
goto err;
114
114
}
115
115
116
116
drm_encoder_helper_add(encoder, &hibmc_encoder_helper_funcs);
···
121
121
&vdac->adapter);
122
122
if (ret) {
123
123
drm_err(dev, "failed to init connector: %d\n", ret);
124
-
return ret;
124
+
goto err;
125
125
}
126
126
127
127
drm_connector_helper_add(connector, &hibmc_connector_helper_funcs);
···
131
131
connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
132
132
133
133
return 0;
134
+
135
+
err:
136
+
hibmc_ddc_del(vdac);
137
+
138
+
return ret;
134
139
}
+4
drivers/gpu/drm/i915/display/intel_display_irq.c
+4
drivers/gpu/drm/i915/display/intel_display_irq.c
···
1506
1506
if (!(master_ctl & GEN11_GU_MISC_IRQ))
1507
1507
return 0;
1508
1508
1509
+
intel_display_rpm_assert_block(display);
1510
+
1509
1511
iir = intel_de_read(display, GEN11_GU_MISC_IIR);
1510
1512
if (likely(iir))
1511
1513
intel_de_write(display, GEN11_GU_MISC_IIR, iir);
1514
+
1515
+
intel_display_rpm_assert_unblock(display);
1512
1516
1513
1517
return iir;
1514
1518
}
+75
-18
drivers/gpu/drm/i915/display/intel_tc.c
+75
-18
drivers/gpu/drm/i915/display/intel_tc.c
···
23
23
#include "intel_modeset_lock.h"
24
24
#include "intel_tc.h"
25
25
26
+
#define DP_PIN_ASSIGNMENT_NONE 0x0
26
27
#define DP_PIN_ASSIGNMENT_C 0x3
27
28
#define DP_PIN_ASSIGNMENT_D 0x4
28
29
#define DP_PIN_ASSIGNMENT_E 0x5
···
67
66
enum tc_port_mode init_mode;
68
67
enum phy_fia phy_fia;
69
68
u8 phy_fia_idx;
69
+
u8 max_lane_count;
70
70
};
71
71
72
72
static enum intel_display_power_domain
···
309
307
REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
310
308
311
309
switch (pin_assignment) {
310
+
case DP_PIN_ASSIGNMENT_NONE:
311
+
return 0;
312
312
default:
313
313
MISSING_CASE(pin_assignment);
314
314
fallthrough;
···
369
365
}
370
366
}
371
367
372
-
int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
368
+
static int get_max_lane_count(struct intel_tc_port *tc)
373
369
{
374
-
struct intel_display *display = to_intel_display(dig_port);
375
-
struct intel_tc_port *tc = to_tc_port(dig_port);
370
+
struct intel_display *display = to_intel_display(tc->dig_port);
371
+
struct intel_digital_port *dig_port = tc->dig_port;
376
372
377
-
if (!intel_encoder_is_tc(&dig_port->base) || tc->mode != TC_PORT_DP_ALT)
373
+
if (tc->mode != TC_PORT_DP_ALT)
378
374
return 4;
379
375
380
376
assert_tc_cold_blocked(tc);
···
386
382
return mtl_tc_port_get_max_lane_count(dig_port);
387
383
388
384
return intel_tc_port_get_max_lane_count(dig_port);
385
+
}
386
+
387
+
static void read_pin_configuration(struct intel_tc_port *tc)
388
+
{
389
+
tc->max_lane_count = get_max_lane_count(tc);
390
+
}
391
+
392
+
int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
393
+
{
394
+
struct intel_display *display = to_intel_display(dig_port);
395
+
struct intel_tc_port *tc = to_tc_port(dig_port);
396
+
397
+
if (!intel_encoder_is_tc(&dig_port->base))
398
+
return 4;
399
+
400
+
if (DISPLAY_VER(display) < 20)
401
+
return get_max_lane_count(tc);
402
+
403
+
return tc->max_lane_count;
389
404
}
390
405
391
406
void intel_tc_port_set_fia_lane_count(struct intel_digital_port *dig_port,
···
619
596
tc_cold_wref = __tc_cold_block(tc, &domain);
620
597
621
598
tc->mode = tc_phy_get_current_mode(tc);
622
-
if (tc->mode != TC_PORT_DISCONNECTED)
599
+
if (tc->mode != TC_PORT_DISCONNECTED) {
623
600
tc->lock_wakeref = tc_cold_block(tc);
601
+
602
+
read_pin_configuration(tc);
603
+
}
624
604
625
605
__tc_cold_unblock(tc, domain, tc_cold_wref);
626
606
}
···
682
656
683
657
tc->lock_wakeref = tc_cold_block(tc);
684
658
685
-
if (tc->mode == TC_PORT_TBT_ALT)
659
+
if (tc->mode == TC_PORT_TBT_ALT) {
660
+
read_pin_configuration(tc);
661
+
686
662
return true;
663
+
}
687
664
688
665
if ((!tc_phy_is_ready(tc) ||
689
666
!icl_tc_phy_take_ownership(tc, true)) &&
···
697
668
goto out_unblock_tc_cold;
698
669
}
699
670
671
+
read_pin_configuration(tc);
700
672
701
673
if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
702
674
goto out_release_phy;
···
888
858
port_wakeref = intel_display_power_get(display, port_power_domain);
889
859
890
860
tc->mode = tc_phy_get_current_mode(tc);
891
-
if (tc->mode != TC_PORT_DISCONNECTED)
861
+
if (tc->mode != TC_PORT_DISCONNECTED) {
892
862
tc->lock_wakeref = tc_cold_block(tc);
863
+
864
+
read_pin_configuration(tc);
865
+
}
893
866
894
867
intel_display_power_put(display, port_power_domain, port_wakeref);
895
868
}
···
906
873
907
874
if (tc->mode == TC_PORT_TBT_ALT) {
908
875
tc->lock_wakeref = tc_cold_block(tc);
876
+
877
+
read_pin_configuration(tc);
878
+
909
879
return true;
910
880
}
911
881
···
929
893
}
930
894
931
895
tc->lock_wakeref = tc_cold_block(tc);
896
+
897
+
read_pin_configuration(tc);
932
898
933
899
if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
934
900
goto out_unblock_tc_cold;
···
1162
1124
tc_cold_wref = __tc_cold_block(tc, &domain);
1163
1125
1164
1126
tc->mode = tc_phy_get_current_mode(tc);
1165
-
if (tc->mode != TC_PORT_DISCONNECTED)
1127
+
if (tc->mode != TC_PORT_DISCONNECTED) {
1166
1128
tc->lock_wakeref = tc_cold_block(tc);
1129
+
1130
+
read_pin_configuration(tc);
1131
+
/*
1132
+
* Set a valid lane count value for a DP-alt sink which got
1133
+
* disconnected. The driver can only disable the output on this PHY.
1134
+
*/
1135
+
if (tc->max_lane_count == 0)
1136
+
tc->max_lane_count = 4;
1137
+
}
1167
1138
1168
1139
drm_WARN_ON(display->drm,
1169
1140
(tc->mode == TC_PORT_DP_ALT || tc->mode == TC_PORT_LEGACY) &&
···
1185
1138
{
1186
1139
tc->lock_wakeref = tc_cold_block(tc);
1187
1140
1188
-
if (tc->mode == TC_PORT_TBT_ALT)
1141
+
if (tc->mode == TC_PORT_TBT_ALT) {
1142
+
read_pin_configuration(tc);
1143
+
1189
1144
return true;
1145
+
}
1190
1146
1191
1147
if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
1192
1148
goto out_unblock_tccold;
1193
1149
1194
1150
xelpdp_tc_phy_take_ownership(tc, true);
1151
+
1152
+
read_pin_configuration(tc);
1195
1153
1196
1154
if (!tc_phy_verify_legacy_or_dp_alt_mode(tc, required_lanes))
1197
1155
goto out_release_phy;
···
1278
1226
tc->phy_ops->get_hw_state(tc);
1279
1227
}
1280
1228
1281
-
static bool tc_phy_is_ready_and_owned(struct intel_tc_port *tc,
1282
-
bool phy_is_ready, bool phy_is_owned)
1229
+
/* Is the PHY owned by display i.e. is it in legacy or DP-alt mode? */
1230
+
static bool tc_phy_owned_by_display(struct intel_tc_port *tc,
1231
+
bool phy_is_ready, bool phy_is_owned)
1283
1232
{
1284
1233
struct intel_display *display = to_intel_display(tc->dig_port);
1285
1234
1286
-
drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready);
1235
+
if (DISPLAY_VER(display) < 20) {
1236
+
drm_WARN_ON(display->drm, phy_is_owned && !phy_is_ready);
1287
1237
1288
-
return phy_is_ready && phy_is_owned;
1238
+
return phy_is_ready && phy_is_owned;
1239
+
} else {
1240
+
return phy_is_owned;
1241
+
}
1289
1242
}
1290
1243
1291
1244
static bool tc_phy_is_connected(struct intel_tc_port *tc,
···
1301
1244
bool phy_is_owned = tc_phy_is_owned(tc);
1302
1245
bool is_connected;
1303
1246
1304
-
if (tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned))
1247
+
if (tc_phy_owned_by_display(tc, phy_is_ready, phy_is_owned))
1305
1248
is_connected = port_pll_type == ICL_PORT_DPLL_MG_PHY;
1306
1249
else
1307
1250
is_connected = port_pll_type == ICL_PORT_DPLL_DEFAULT;
···
1409
1352
phy_is_ready = tc_phy_is_ready(tc);
1410
1353
phy_is_owned = tc_phy_is_owned(tc);
1411
1354
1412
-
if (!tc_phy_is_ready_and_owned(tc, phy_is_ready, phy_is_owned)) {
1355
+
if (!tc_phy_owned_by_display(tc, phy_is_ready, phy_is_owned)) {
1413
1356
mode = get_tc_mode_in_phy_not_owned_state(tc, live_mode);
1414
1357
} else {
1415
1358
drm_WARN_ON(display->drm, live_mode == TC_PORT_TBT_ALT);
···
1498
1441
intel_display_power_flush_work(display);
1499
1442
if (!intel_tc_cold_requires_aux_pw(dig_port)) {
1500
1443
enum intel_display_power_domain aux_domain;
1501
-
bool aux_powered;
1502
1444
1503
1445
aux_domain = intel_aux_power_domain(dig_port);
1504
-
aux_powered = intel_display_power_is_enabled(display, aux_domain);
1505
-
drm_WARN_ON(display->drm, aux_powered);
1446
+
if (intel_display_power_is_enabled(display, aux_domain))
1447
+
drm_dbg_kms(display->drm, "Port %s: AUX unexpectedly powered\n",
1448
+
tc->port_name);
1506
1449
}
1507
1450
1508
1451
tc_phy_disconnect(tc);
+11
-9
drivers/gpu/drm/i915/gt/intel_workarounds.c
+11
-9
drivers/gpu/drm/i915/gt/intel_workarounds.c
···
634
634
static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
635
635
struct i915_wa_list *wal)
636
636
{
637
+
struct drm_i915_private *i915 = engine->i915;
638
+
637
639
/* Wa_1406697149 (WaDisableBankHangMode:icl) */
638
640
wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
639
641
···
671
669
672
670
/* Wa_1406306137:icl,ehl */
673
671
wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, GEN11_DIS_PICK_2ND_EU);
672
+
673
+
if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {
674
+
/*
675
+
* Disable Repacking for Compression (masked R/W access)
676
+
* before rendering compressed surfaces for display.
677
+
*/
678
+
wa_masked_en(wal, CACHE_MODE_0_GEN7,
679
+
DISABLE_REPACKING_FOR_COMPRESSION);
680
+
}
674
681
}
675
682
676
683
/*
···
2315
2304
RING_PSMI_CTL(RENDER_RING_BASE),
2316
2305
GEN12_WAIT_FOR_EVENT_POWER_DOWN_DISABLE |
2317
2306
GEN8_RC_SEMA_IDLE_MSG_DISABLE);
2318
-
}
2319
-
2320
-
if (IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) {
2321
-
/*
2322
-
* "Disable Repacking for Compression (masked R/W access)
2323
-
* before rendering compressed surfaces for display."
2324
-
*/
2325
-
wa_masked_en(wal, CACHE_MODE_0_GEN7,
2326
-
DISABLE_REPACKING_FOR_COMPRESSION);
2327
2307
}
2328
2308
2329
2309
if (GRAPHICS_VER(i915) == 11) {
+3
-3
drivers/gpu/drm/nouveau/nouveau_exec.c
+3
-3
drivers/gpu/drm/nouveau/nouveau_exec.c
···
60
60
* virtual address in the GPU's VA space there is no guarantee that the actual
61
61
* mappings are created in the GPU's MMU. If the given memory is swapped out
62
62
* at the time the bind operation is executed the kernel will stash the mapping
63
-
* details into it's internal alloctor and create the actual MMU mappings once
63
+
* details into it's internal allocator and create the actual MMU mappings once
64
64
* the memory is swapped back in. While this is transparent for userspace, it is
65
65
* guaranteed that all the backing memory is swapped back in and all the memory
66
66
* mappings, as requested by userspace previously, are actually mapped once the
67
67
* DRM_NOUVEAU_EXEC ioctl is called to submit an exec job.
68
68
*
69
69
* A VM_BIND job can be executed either synchronously or asynchronously. If
70
-
* exectued asynchronously, userspace may provide a list of syncobjs this job
70
+
* executed asynchronously, userspace may provide a list of syncobjs this job
71
71
* will wait for and/or a list of syncobj the kernel will signal once the
72
72
* VM_BIND job finished execution. If executed synchronously the ioctl will
73
73
* block until the bind job is finished. For synchronous jobs the kernel will
···
82
82
* Since VM_BIND jobs update the GPU's VA space on job submit, EXEC jobs do have
83
83
* an up to date view of the VA space. However, the actual mappings might still
84
84
* be pending. Hence, EXEC jobs require to have the particular fences - of
85
-
* the corresponding VM_BIND jobs they depent on - attached to them.
85
+
* the corresponding VM_BIND jobs they depend on - attached to them.
86
86
*/
87
87
88
88
static int
+2
-1
drivers/gpu/drm/nouveau/nvif/vmm.c
+2
-1
drivers/gpu/drm/nouveau/nvif/vmm.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/rpc.c
···
325
325
326
326
rpc = r535_gsp_msgq_peek(gsp, sizeof(*rpc), info.retries);
327
327
if (IS_ERR_OR_NULL(rpc)) {
328
-
kfree(buf);
328
+
kvfree(buf);
329
329
return rpc;
330
330
}
331
331
···
334
334
335
335
rpc = r535_gsp_msgq_recv_one_elem(gsp, &info);
336
336
if (IS_ERR_OR_NULL(rpc)) {
337
-
kfree(buf);
337
+
kvfree(buf);
338
338
return rpc;
339
339
}
340
340
+2
-1
drivers/gpu/drm/nova/file.rs
+2
-1
drivers/gpu/drm/nova/file.rs
+1
drivers/gpu/drm/rockchip/Kconfig
+1
drivers/gpu/drm/rockchip/Kconfig
+5
-4
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+5
-4
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
···
2579
2579
}
2580
2580
2581
2581
/*
2582
-
* The window registers are only updated when config done is written.
2583
-
* Until that they read back the old value. As we read-modify-write
2584
-
* these registers mark them as non-volatile. This makes sure we read
2585
-
* the new values from the regmap register cache.
2582
+
* The window and video port registers are only updated when config
2583
+
* done is written. Until that they read back the old value. As we
2584
+
* read-modify-write these registers mark them as non-volatile. This
2585
+
* makes sure we read the new values from the regmap register cache.
2586
2586
*/
2587
2587
static const struct regmap_range vop2_nonvolatile_range[] = {
2588
+
regmap_reg_range(RK3568_VP0_CTRL_BASE, RK3588_VP3_CTRL_BASE + 255),
2588
2589
regmap_reg_range(0x1000, 0x23ff),
2589
2590
};
2590
2591
+2
-1
drivers/gpu/drm/tests/drm_format_helper_test.c
+2
-1
drivers/gpu/drm/tests/drm_format_helper_test.c
···
1033
1033
NULL : &result->dst_pitch;
1034
1034
1035
1035
drm_fb_xrgb8888_to_xrgb2101010(&dst, dst_pitch, &src, &fb, ¶ms->clip, &fmtcnv_state);
1036
-
buf = le32buf_to_cpu(test, buf, dst_size / sizeof(u32));
1036
+
buf = le32buf_to_cpu(test, (__force const __le32 *)buf, dst_size / sizeof(u32));
1037
1037
KUNIT_EXPECT_MEMEQ(test, buf, result->expected, dst_size);
1038
1038
1039
1039
buf = dst.vaddr; /* restore original value of buf */
1040
1040
memset(buf, 0, dst_size);
1041
1041
1042
1042
drm_fb_xrgb8888_to_xrgb2101010(&dst, dst_pitch, &src, &fb, ¶ms->clip, &fmtcnv_state);
1043
+
buf = le32buf_to_cpu(test, (__force const __le32 *)buf, dst_size / sizeof(u32));
1043
1044
KUNIT_EXPECT_MEMEQ(test, buf, result->expected, dst_size);
1044
1045
}
1045
1046
+1
-1
drivers/gpu/drm/xe/xe_migrate.c
+1
-1
drivers/gpu/drm/xe/xe_migrate.c
+1
-1
drivers/gpu/drm/xe/xe_pxp_submit.c
+1
-1
drivers/gpu/drm/xe/xe_pxp_submit.c
+23
-25
drivers/gpu/drm/xe/xe_vm.c
+23
-25
drivers/gpu/drm/xe/xe_vm.c
···
1640
1640
}
1641
1641
}
1642
1642
1643
-
struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags)
1643
+
struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef)
1644
1644
{
1645
1645
struct drm_gem_object *vm_resv_obj;
1646
1646
struct xe_vm *vm;
···
1661
1661
vm->xe = xe;
1662
1662
1663
1663
vm->size = 1ull << xe->info.va_bits;
1664
-
1665
1664
vm->flags = flags;
1666
1665
1666
+
if (xef)
1667
+
vm->xef = xe_file_get(xef);
1667
1668
/**
1668
1669
* GSC VMs are kernel-owned, only used for PXP ops and can sometimes be
1669
1670
* manipulated under the PXP mutex. However, the PXP mutex can be taken
···
1795
1794
if (number_tiles > 1)
1796
1795
vm->composite_fence_ctx = dma_fence_context_alloc(1);
1797
1796
1797
+
if (xef && xe->info.has_asid) {
1798
+
u32 asid;
1799
+
1800
+
down_write(&xe->usm.lock);
1801
+
err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, vm,
1802
+
XA_LIMIT(1, XE_MAX_ASID - 1),
1803
+
&xe->usm.next_asid, GFP_KERNEL);
1804
+
up_write(&xe->usm.lock);
1805
+
if (err < 0)
1806
+
goto err_unlock_close;
1807
+
1808
+
vm->usm.asid = asid;
1809
+
}
1810
+
1798
1811
trace_xe_vm_create(vm);
1799
1812
1800
1813
return vm;
···
1829
1814
for_each_tile(tile, xe, id)
1830
1815
xe_range_fence_tree_fini(&vm->rftree[id]);
1831
1816
ttm_lru_bulk_move_fini(&xe->ttm, &vm->lru_bulk_move);
1817
+
if (vm->xef)
1818
+
xe_file_put(vm->xef);
1832
1819
kfree(vm);
1833
1820
if (flags & XE_VM_FLAG_LR_MODE)
1834
1821
xe_pm_runtime_put(xe);
···
2076
2059
struct xe_device *xe = to_xe_device(dev);
2077
2060
struct xe_file *xef = to_xe_file(file);
2078
2061
struct drm_xe_vm_create *args = data;
2079
-
struct xe_tile *tile;
2080
2062
struct xe_vm *vm;
2081
-
u32 id, asid;
2063
+
u32 id;
2082
2064
int err;
2083
2065
u32 flags = 0;
2084
2066
···
2113
2097
if (args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE)
2114
2098
flags |= XE_VM_FLAG_FAULT_MODE;
2115
2099
2116
-
vm = xe_vm_create(xe, flags);
2100
+
vm = xe_vm_create(xe, flags, xef);
2117
2101
if (IS_ERR(vm))
2118
2102
return PTR_ERR(vm);
2119
-
2120
-
if (xe->info.has_asid) {
2121
-
down_write(&xe->usm.lock);
2122
-
err = xa_alloc_cyclic(&xe->usm.asid_to_vm, &asid, vm,
2123
-
XA_LIMIT(1, XE_MAX_ASID - 1),
2124
-
&xe->usm.next_asid, GFP_KERNEL);
2125
-
up_write(&xe->usm.lock);
2126
-
if (err < 0)
2127
-
goto err_close_and_put;
2128
-
2129
-
vm->usm.asid = asid;
2130
-
}
2131
-
2132
-
vm->xef = xe_file_get(xef);
2133
-
2134
-
/* Record BO memory for VM pagetable created against client */
2135
-
for_each_tile(tile, xe, id)
2136
-
if (vm->pt_root[id])
2137
-
xe_drm_client_add_bo(vm->xef->client, vm->pt_root[id]->bo);
2138
2103
2139
2104
#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_MEM)
2140
2105
/* Warning: Security issue - never enable by default */
···
3418
3421
free_bind_ops:
3419
3422
if (args->num_binds > 1)
3420
3423
kvfree(*bind_ops);
3424
+
*bind_ops = NULL;
3421
3425
return err;
3422
3426
}
3423
3427
···
3525
3527
struct xe_exec_queue *q = NULL;
3526
3528
u32 num_syncs, num_ufence = 0;
3527
3529
struct xe_sync_entry *syncs = NULL;
3528
-
struct drm_xe_vm_bind_op *bind_ops;
3530
+
struct drm_xe_vm_bind_op *bind_ops = NULL;
3529
3531
struct xe_vma_ops vops;
3530
3532
struct dma_fence *fence;
3531
3533
int err;
+1
-1
drivers/gpu/drm/xe/xe_vm.h
+1
-1
drivers/gpu/drm/xe/xe_vm.h
···
26
26
struct xe_svm_range;
27
27
struct drm_exec;
28
28
29
-
struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags);
29
+
struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags, struct xe_file *xef);
30
30
31
31
struct xe_vm *xe_vm_lookup(struct xe_file *xef, u32 id);
32
32
int xe_vma_cmp_vma_cb(const void *key, const struct rb_node *node);
+1
-6
include/linux/iosys-map.h
+1
-6
include/linux/iosys-map.h
+18
-12
rust/kernel/alloc/allocator.rs
+18
-12
rust/kernel/alloc/allocator.rs
···
43
43
/// For more details see [self].
44
44
pub struct KVmalloc;
45
45
46
-
/// Returns a proper size to alloc a new object aligned to `new_layout`'s alignment.
47
-
fn aligned_size(new_layout: Layout) -> usize {
48
-
// Customized layouts from `Layout::from_size_align()` can have size < align, so pad first.
49
-
let layout = new_layout.pad_to_align();
50
-
51
-
// Note that `layout.size()` (after padding) is guaranteed to be a multiple of `layout.align()`
52
-
// which together with the slab guarantees means the `krealloc` will return a properly aligned
53
-
// object (see comments in `kmalloc()` for more information).
54
-
layout.size()
55
-
}
56
-
57
46
/// # Invariants
58
47
///
59
48
/// One of the following: `krealloc`, `vrealloc`, `kvrealloc`.
···
77
88
old_layout: Layout,
78
89
flags: Flags,
79
90
) -> Result<NonNull<[u8]>, AllocError> {
80
-
let size = aligned_size(layout);
91
+
let size = layout.size();
81
92
let ptr = match ptr {
82
93
Some(ptr) => {
83
94
if old_layout.size() == 0 {
···
112
123
}
113
124
}
114
125
126
+
impl Kmalloc {
127
+
/// Returns a [`Layout`] that makes [`Kmalloc`] fulfill the requested size and alignment of
128
+
/// `layout`.
129
+
pub fn aligned_layout(layout: Layout) -> Layout {
130
+
// Note that `layout.size()` (after padding) is guaranteed to be a multiple of
131
+
// `layout.align()` which together with the slab guarantees means that `Kmalloc` will return
132
+
// a properly aligned object (see comments in `kmalloc()` for more information).
133
+
layout.pad_to_align()
134
+
}
135
+
}
136
+
115
137
// SAFETY: `realloc` delegates to `ReallocFunc::call`, which guarantees that
116
138
// - memory remains valid until it is explicitly freed,
117
139
// - passing a pointer to a valid memory allocation is OK,
···
135
135
old_layout: Layout,
136
136
flags: Flags,
137
137
) -> Result<NonNull<[u8]>, AllocError> {
138
+
let layout = Kmalloc::aligned_layout(layout);
139
+
138
140
// SAFETY: `ReallocFunc::call` has the same safety requirements as `Allocator::realloc`.
139
141
unsafe { ReallocFunc::KREALLOC.call(ptr, layout, old_layout, flags) }
140
142
}
···
178
176
old_layout: Layout,
179
177
flags: Flags,
180
178
) -> Result<NonNull<[u8]>, AllocError> {
179
+
// `KVmalloc` may use the `Kmalloc` backend, hence we have to enforce a `Kmalloc`
180
+
// compatible layout.
181
+
let layout = Kmalloc::aligned_layout(layout);
182
+
181
183
// TODO: Support alignments larger than PAGE_SIZE.
182
184
if layout.align() > bindings::PAGE_SIZE {
183
185
pr_warn!("KVmalloc does not support alignments larger than PAGE_SIZE yet.\n");
+11
rust/kernel/alloc/allocator_test.rs
+11
rust/kernel/alloc/allocator_test.rs
···
22
22
pub type Vmalloc = Kmalloc;
23
23
pub type KVmalloc = Kmalloc;
24
24
25
+
impl Cmalloc {
26
+
/// Returns a [`Layout`] that makes [`Kmalloc`] fulfill the requested size and alignment of
27
+
/// `layout`.
28
+
pub fn aligned_layout(layout: Layout) -> Layout {
29
+
// Note that `layout.size()` (after padding) is guaranteed to be a multiple of
30
+
// `layout.align()` which together with the slab guarantees means that `Kmalloc` will return
31
+
// a properly aligned object (see comments in `kmalloc()` for more information).
32
+
layout.pad_to_align()
33
+
}
34
+
}
35
+
25
36
extern "C" {
26
37
#[link_name = "aligned_alloc"]
27
38
fn libc_aligned_alloc(align: usize, size: usize) -> *mut crate::ffi::c_void;
+25
-7
rust/kernel/drm/device.rs
+25
-7
rust/kernel/drm/device.rs
···
5
5
//! C header: [`include/linux/drm/drm_device.h`](srctree/include/linux/drm/drm_device.h)
6
6
7
7
use crate::{
8
+
alloc::allocator::Kmalloc,
8
9
bindings, device, drm,
9
10
drm::driver::AllocImpl,
10
11
error::from_err_ptr,
···
13
12
prelude::*,
14
13
types::{ARef, AlwaysRefCounted, Opaque},
15
14
};
16
-
use core::{mem, ops::Deref, ptr, ptr::NonNull};
15
+
use core::{alloc::Layout, mem, ops::Deref, ptr, ptr::NonNull};
17
16
18
17
#[cfg(CONFIG_DRM_LEGACY)]
19
18
macro_rules! drm_legacy_fields {
···
54
53
///
55
54
/// `self.dev` is a valid instance of a `struct device`.
56
55
#[repr(C)]
57
-
#[pin_data]
58
56
pub struct Device<T: drm::Driver> {
59
57
dev: Opaque<bindings::drm_device>,
60
-
#[pin]
61
58
data: T::Data,
62
59
}
63
60
···
95
96
96
97
/// Create a new `drm::Device` for a `drm::Driver`.
97
98
pub fn new(dev: &device::Device, data: impl PinInit<T::Data, Error>) -> Result<ARef<Self>> {
99
+
// `__drm_dev_alloc` uses `kmalloc()` to allocate memory, hence ensure a `kmalloc()`
100
+
// compatible `Layout`.
101
+
let layout = Kmalloc::aligned_layout(Layout::new::<Self>());
102
+
98
103
// SAFETY:
99
104
// - `VTABLE`, as a `const` is pinned to the read-only section of the compilation,
100
105
// - `dev` is valid by its type invarants,
···
106
103
bindings::__drm_dev_alloc(
107
104
dev.as_raw(),
108
105
&Self::VTABLE,
109
-
mem::size_of::<Self>(),
106
+
layout.size(),
110
107
mem::offset_of!(Self, dev),
111
108
)
112
109
}
···
120
117
// - `raw_data` is a valid pointer to uninitialized memory.
121
118
// - `raw_data` will not move until it is dropped.
122
119
unsafe { data.__pinned_init(raw_data) }.inspect_err(|_| {
123
-
// SAFETY: `__drm_dev_alloc()` was successful, hence `raw_drm` must be valid and the
120
+
// SAFETY: `raw_drm` is a valid pointer to `Self`, given that `__drm_dev_alloc` was
121
+
// successful.
122
+
let drm_dev = unsafe { Self::into_drm_device(raw_drm) };
123
+
124
+
// SAFETY: `__drm_dev_alloc()` was successful, hence `drm_dev` must be valid and the
124
125
// refcount must be non-zero.
125
-
unsafe { bindings::drm_dev_put(ptr::addr_of_mut!((*raw_drm.as_ptr()).dev).cast()) };
126
+
unsafe { bindings::drm_dev_put(drm_dev) };
126
127
})?;
127
128
128
129
// SAFETY: The reference count is one, and now we take ownership of that reference as a
···
145
138
// SAFETY: By the safety requirements of this function `ptr` is a valid pointer to a
146
139
// `struct drm_device` embedded in `Self`.
147
140
unsafe { crate::container_of!(Opaque::cast_from(ptr), Self, dev) }.cast_mut()
141
+
}
142
+
143
+
/// # Safety
144
+
///
145
+
/// `ptr` must be a valid pointer to `Self`.
146
+
unsafe fn into_drm_device(ptr: NonNull<Self>) -> *mut bindings::drm_device {
147
+
// SAFETY: By the safety requirements of this function, `ptr` is a valid pointer to `Self`.
148
+
unsafe { &raw mut (*ptr.as_ptr()).dev }.cast()
148
149
}
149
150
150
151
/// Not intended to be called externally, except via declare_drm_ioctls!()
···
204
189
}
205
190
206
191
unsafe fn dec_ref(obj: NonNull<Self>) {
192
+
// SAFETY: `obj` is a valid pointer to `Self`.
193
+
let drm_dev = unsafe { Self::into_drm_device(obj) };
194
+
207
195
// SAFETY: The safety requirements guarantee that the refcount is non-zero.
208
-
unsafe { bindings::drm_dev_put(obj.cast().as_ptr()) };
196
+
unsafe { bindings::drm_dev_put(drm_dev) };
209
197
}
210
198
}
211
199