Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'net-stmmac-mdio-cleanups'
Russell King says:
====================
net: stmmac: mdio cleanups
Clean up the stmmac MDIO code:
- provide an address register formatter to avoid repeated code
- provide a common function to wait for the busy bit to clear
- pre-compute the CR field (mdio clock divider)
- move address formatter into read/write functions
- combine the read/write functions into a common accessor function
- move runtime PM handling into common accessor function
- rename register constants to better reflect manufacturer names
- move stmmac_clk_csr_set() into stmmac_mdio
- make stmmac_clk_csr_set() return the CR field value and remove
priv->clk_csr
- clean up if() range tests in stmmac_clk_csr_set()
- use STMMAC_CSR_xxx definitions in initialisers
For Qualcomm QCS9100 Ride R3 board with the AQR115C PHY:
Tested-by: Mohd Ayaan Anwar <quic_mohdayaa@quicinc.com>
====================
Link: https://patch.msgid.link/aLmBwsMdW__XBv7g@shell.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+206
-234
+3
-2
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+3
-2
drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
···
563
563
564
564
static void common_default_data(struct plat_stmmacenet_data *plat)
565
565
{
566
-
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
566
+
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
567
+
plat->clk_csr = STMMAC_CSR_20_35M;
567
568
plat->has_gmac = 1;
568
569
plat->force_sf_dma_mode = 1;
569
570
···
611
610
612
611
plat->pdev = pdev;
613
612
plat->phy_addr = -1;
614
-
plat->clk_csr = 5;
613
+
plat->clk_csr = STMMAC_CSR_250_300M;
615
614
plat->has_gmac = 0;
616
615
plat->has_gmac4 = 1;
617
616
plat->force_sf_dma_mode = 0;
+2
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
+2
-1
drivers/net/ethernet/stmicro/stmmac/dwmac-loongson.c
···
90
90
/* Get bus_id, this can be overwritten later */
91
91
plat->bus_id = pci_dev_id(pdev);
92
92
93
-
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
93
+
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
94
+
plat->clk_csr = STMMAC_CSR_20_35M;
94
95
plat->has_gmac = 1;
95
96
plat->force_sf_dma_mode = 1;
96
97
+1
-1
drivers/net/ethernet/stmicro/stmmac/stmmac.h
+1
-1
drivers/net/ethernet/stmicro/stmmac/stmmac.h
-82
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-82
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
···
314
314
stmmac_service_event_schedule(priv);
315
315
}
316
316
317
-
/**
318
-
* stmmac_clk_csr_set - dynamically set the MDC clock
319
-
* @priv: driver private structure
320
-
* Description: this is to dynamically set the MDC clock according to the csr
321
-
* clock input.
322
-
* Note:
323
-
* If a specific clk_csr value is passed from the platform
324
-
* this means that the CSR Clock Range selection cannot be
325
-
* changed at run-time and it is fixed (as reported in the driver
326
-
* documentation). Viceversa the driver will try to set the MDC
327
-
* clock dynamically according to the actual clock input.
328
-
*/
329
-
static void stmmac_clk_csr_set(struct stmmac_priv *priv)
330
-
{
331
-
unsigned long clk_rate;
332
-
333
-
clk_rate = clk_get_rate(priv->plat->stmmac_clk);
334
-
335
-
/* Platform provided default clk_csr would be assumed valid
336
-
* for all other cases except for the below mentioned ones.
337
-
* For values higher than the IEEE 802.3 specified frequency
338
-
* we can not estimate the proper divider as it is not known
339
-
* the frequency of clk_csr_i. So we do not change the default
340
-
* divider.
341
-
*/
342
-
if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) {
343
-
if (clk_rate < CSR_F_35M)
344
-
priv->clk_csr = STMMAC_CSR_20_35M;
345
-
else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M))
346
-
priv->clk_csr = STMMAC_CSR_35_60M;
347
-
else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M))
348
-
priv->clk_csr = STMMAC_CSR_60_100M;
349
-
else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M))
350
-
priv->clk_csr = STMMAC_CSR_100_150M;
351
-
else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M))
352
-
priv->clk_csr = STMMAC_CSR_150_250M;
353
-
else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M))
354
-
priv->clk_csr = STMMAC_CSR_250_300M;
355
-
else if ((clk_rate >= CSR_F_300M) && (clk_rate < CSR_F_500M))
356
-
priv->clk_csr = STMMAC_CSR_300_500M;
357
-
else if ((clk_rate >= CSR_F_500M) && (clk_rate < CSR_F_800M))
358
-
priv->clk_csr = STMMAC_CSR_500_800M;
359
-
}
360
-
361
-
if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
362
-
if (clk_rate > 160000000)
363
-
priv->clk_csr = 0x03;
364
-
else if (clk_rate > 80000000)
365
-
priv->clk_csr = 0x02;
366
-
else if (clk_rate > 40000000)
367
-
priv->clk_csr = 0x01;
368
-
else
369
-
priv->clk_csr = 0;
370
-
}
371
-
372
-
if (priv->plat->has_xgmac) {
373
-
if (clk_rate > 400000000)
374
-
priv->clk_csr = 0x5;
375
-
else if (clk_rate > 350000000)
376
-
priv->clk_csr = 0x4;
377
-
else if (clk_rate > 300000000)
378
-
priv->clk_csr = 0x3;
379
-
else if (clk_rate > 250000000)
380
-
priv->clk_csr = 0x2;
381
-
else if (clk_rate > 150000000)
382
-
priv->clk_csr = 0x1;
383
-
else
384
-
priv->clk_csr = 0x0;
385
-
}
386
-
}
387
-
388
317
static void print_pkt(unsigned char *buf, int len)
389
318
{
390
319
pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf);
···
7646
7717
mutex_init(&priv->lock);
7647
7718
7648
7719
stmmac_fpe_init(priv);
7649
-
7650
-
/* If a specific clk_csr value is passed from the platform
7651
-
* this means that the CSR Clock Range selection cannot be
7652
-
* changed at run-time and it is fixed. Viceversa the driver'll try to
7653
-
* set the MDC clock dynamically according to the csr actual
7654
-
* clock input.
7655
-
*/
7656
-
if (priv->plat->clk_csr >= 0)
7657
-
priv->clk_csr = priv->plat->clk_csr;
7658
-
else
7659
-
stmmac_clk_csr_set(priv);
7660
7720
7661
7721
stmmac_check_pcs_mode(priv);
7662
7722
+197
-146
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+197
-146
drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
···
23
23
#include "dwxgmac2.h"
24
24
#include "stmmac.h"
25
25
26
-
#define MII_BUSY 0x00000001
27
-
#define MII_WRITE 0x00000002
28
-
#define MII_DATA_MASK GENMASK(15, 0)
26
+
#define MII_ADDR_GBUSY BIT(0)
27
+
#define MII_ADDR_GWRITE BIT(1)
28
+
#define MII_DATA_GD_MASK GENMASK(15, 0)
29
29
30
30
/* GMAC4 defines */
31
31
#define MII_GMAC4_GOC_SHIFT 2
···
44
44
#define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0)
45
45
#define MII_XGMAC_PA_SHIFT 16
46
46
#define MII_XGMAC_DA_SHIFT 21
47
+
48
+
static int stmmac_mdio_wait(void __iomem *reg, u32 mask)
49
+
{
50
+
u32 v;
51
+
52
+
if (readl_poll_timeout(reg, v, !(v & mask), 100, 10000))
53
+
return -EBUSY;
54
+
55
+
return 0;
56
+
}
47
57
48
58
static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr,
49
59
int devad, int phyreg, u32 *hw_addr)
···
93
83
{
94
84
unsigned int mii_address = priv->hw->mii.addr;
95
85
unsigned int mii_data = priv->hw->mii.data;
96
-
u32 tmp;
97
86
int ret;
98
87
99
88
ret = pm_runtime_resume_and_get(priv->device);
···
100
91
return ret;
101
92
102
93
/* Wait until any existing MII operation is complete */
103
-
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
104
-
!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
105
-
ret = -EBUSY;
94
+
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
95
+
if (ret)
106
96
goto err_disable_clks;
107
-
}
108
97
109
-
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
110
-
& priv->hw->mii.clk_csr_mask;
111
-
value |= MII_XGMAC_READ;
98
+
value |= priv->gmii_address_bus_config | MII_XGMAC_READ;
112
99
113
100
/* Wait until any existing MII operation is complete */
114
-
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
115
-
!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
116
-
ret = -EBUSY;
101
+
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
102
+
if (ret)
117
103
goto err_disable_clks;
118
-
}
119
104
120
105
/* Set the MII address register to read */
121
106
writel(addr, priv->ioaddr + mii_address);
122
107
writel(value, priv->ioaddr + mii_data);
123
108
124
109
/* Wait until any existing MII operation is complete */
125
-
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
126
-
!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
127
-
ret = -EBUSY;
110
+
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
111
+
if (ret)
128
112
goto err_disable_clks;
129
-
}
130
113
131
114
/* Read the data from the MII data register */
132
115
ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0);
···
161
160
{
162
161
unsigned int mii_address = priv->hw->mii.addr;
163
162
unsigned int mii_data = priv->hw->mii.data;
164
-
u32 tmp;
165
163
int ret;
166
164
167
165
ret = pm_runtime_resume_and_get(priv->device);
···
168
168
return ret;
169
169
170
170
/* Wait until any existing MII operation is complete */
171
-
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
172
-
!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
173
-
ret = -EBUSY;
171
+
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
172
+
if (ret)
174
173
goto err_disable_clks;
175
-
}
176
174
177
-
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
178
-
& priv->hw->mii.clk_csr_mask;
179
-
value |= phydata;
180
-
value |= MII_XGMAC_WRITE;
175
+
value |= priv->gmii_address_bus_config | phydata | MII_XGMAC_WRITE;
181
176
182
177
/* Wait until any existing MII operation is complete */
183
-
if (readl_poll_timeout(priv->ioaddr + mii_data, tmp,
184
-
!(tmp & MII_XGMAC_BUSY), 100, 10000)) {
185
-
ret = -EBUSY;
178
+
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
179
+
if (ret)
186
180
goto err_disable_clks;
187
-
}
188
181
189
182
/* Set the MII address register to write */
190
183
writel(addr, priv->ioaddr + mii_address);
191
184
writel(value, priv->ioaddr + mii_data);
192
185
193
186
/* Wait until any existing MII operation is complete */
194
-
ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp,
195
-
!(tmp & MII_XGMAC_BUSY), 100, 10000);
187
+
ret = stmmac_mdio_wait(priv->ioaddr + mii_data, MII_XGMAC_BUSY);
196
188
197
189
err_disable_clks:
198
190
pm_runtime_put(priv->device);
···
221
229
phydata);
222
230
}
223
231
224
-
static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value)
232
+
/**
233
+
* stmmac_mdio_format_addr() - format the address register
234
+
* @priv: struct stmmac_priv pointer
235
+
* @pa: 5-bit MDIO package address
236
+
* @gr: 5-bit MDIO register address (C22) or MDIO device address (C45)
237
+
*
238
+
* Return: formatted address register
239
+
*/
240
+
static u32 stmmac_mdio_format_addr(struct stmmac_priv *priv,
241
+
unsigned int pa, unsigned int gr)
225
242
{
226
-
unsigned int mii_address = priv->hw->mii.addr;
227
-
unsigned int mii_data = priv->hw->mii.data;
228
-
u32 v;
243
+
const struct mii_regs *mii_regs = &priv->hw->mii;
229
244
230
-
if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
231
-
100, 10000))
232
-
return -EBUSY;
245
+
return ((pa << mii_regs->addr_shift) & mii_regs->addr_mask) |
246
+
((gr << mii_regs->reg_shift) & mii_regs->reg_mask) |
247
+
priv->gmii_address_bus_config |
248
+
MII_ADDR_GBUSY;
249
+
}
233
250
234
-
writel(data, priv->ioaddr + mii_data);
235
-
writel(value, priv->ioaddr + mii_address);
251
+
static int stmmac_mdio_access(struct stmmac_priv *priv, unsigned int pa,
252
+
unsigned int gr, u32 cmd, u32 data, bool read)
253
+
{
254
+
void __iomem *mii_address = priv->ioaddr + priv->hw->mii.addr;
255
+
void __iomem *mii_data = priv->ioaddr + priv->hw->mii.data;
256
+
u32 addr;
257
+
int ret;
236
258
237
-
if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
238
-
100, 10000))
239
-
return -EBUSY;
259
+
ret = pm_runtime_resume_and_get(priv->device);
260
+
if (ret < 0)
261
+
return ret;
240
262
241
-
/* Read the data from the MII data register */
242
-
return readl(priv->ioaddr + mii_data) & MII_DATA_MASK;
263
+
ret = stmmac_mdio_wait(mii_address, MII_ADDR_GBUSY);
264
+
if (ret)
265
+
goto out;
266
+
267
+
addr = stmmac_mdio_format_addr(priv, pa, gr) | cmd;
268
+
269
+
writel(data, mii_data);
270
+
writel(addr, mii_address);
271
+
272
+
ret = stmmac_mdio_wait(mii_address, MII_ADDR_GBUSY);
273
+
if (ret)
274
+
goto out;
275
+
276
+
/* Read the data from the MII data register if in read mode */
277
+
ret = read ? readl(mii_data) & MII_DATA_GD_MASK : 0;
278
+
279
+
out:
280
+
pm_runtime_put(priv->device);
281
+
282
+
return ret;
283
+
}
284
+
285
+
static int stmmac_mdio_read(struct stmmac_priv *priv, unsigned int pa,
286
+
unsigned int gr, u32 cmd, int data)
287
+
{
288
+
return stmmac_mdio_access(priv, pa, gr, cmd, data, true);
289
+
}
290
+
291
+
static int stmmac_mdio_write(struct stmmac_priv *priv, unsigned int pa,
292
+
unsigned int gr, u32 cmd, int data)
293
+
{
294
+
return stmmac_mdio_access(priv, pa, gr, cmd, data, false);
243
295
}
244
296
245
297
/**
···
299
263
static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg)
300
264
{
301
265
struct stmmac_priv *priv = netdev_priv(bus->priv);
302
-
u32 value = MII_BUSY;
303
-
int data = 0;
266
+
u32 cmd;
304
267
305
-
data = pm_runtime_resume_and_get(priv->device);
306
-
if (data < 0)
307
-
return data;
308
-
309
-
value |= (phyaddr << priv->hw->mii.addr_shift)
310
-
& priv->hw->mii.addr_mask;
311
-
value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
312
-
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
313
-
& priv->hw->mii.clk_csr_mask;
314
268
if (priv->plat->has_gmac4)
315
-
value |= MII_GMAC4_READ;
269
+
cmd = MII_GMAC4_READ;
270
+
else
271
+
cmd = 0;
316
272
317
-
data = stmmac_mdio_read(priv, data, value);
318
-
319
-
pm_runtime_put(priv->device);
320
-
321
-
return data;
273
+
return stmmac_mdio_read(priv, phyaddr, phyreg, cmd, 0);
322
274
}
323
275
324
276
/**
···
324
300
int phyreg)
325
301
{
326
302
struct stmmac_priv *priv = netdev_priv(bus->priv);
327
-
u32 value = MII_BUSY;
328
-
int data = 0;
303
+
int data = phyreg << MII_GMAC4_REG_ADDR_SHIFT;
304
+
u32 cmd = MII_GMAC4_READ | MII_GMAC4_C45E;
329
305
330
-
data = pm_runtime_resume_and_get(priv->device);
331
-
if (data < 0)
332
-
return data;
333
-
334
-
value |= (phyaddr << priv->hw->mii.addr_shift)
335
-
& priv->hw->mii.addr_mask;
336
-
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
337
-
& priv->hw->mii.clk_csr_mask;
338
-
value |= MII_GMAC4_READ;
339
-
value |= MII_GMAC4_C45E;
340
-
value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
341
-
342
-
data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
343
-
344
-
data = stmmac_mdio_read(priv, data, value);
345
-
346
-
pm_runtime_put(priv->device);
347
-
348
-
return data;
349
-
}
350
-
351
-
static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value)
352
-
{
353
-
unsigned int mii_address = priv->hw->mii.addr;
354
-
unsigned int mii_data = priv->hw->mii.data;
355
-
u32 v;
356
-
357
-
/* Wait until any existing MII operation is complete */
358
-
if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY),
359
-
100, 10000))
360
-
return -EBUSY;
361
-
362
-
/* Set the MII address register to write */
363
-
writel(data, priv->ioaddr + mii_data);
364
-
writel(value, priv->ioaddr + mii_address);
365
-
366
-
/* Wait until any existing MII operation is complete */
367
-
return readl_poll_timeout(priv->ioaddr + mii_address, v,
368
-
!(v & MII_BUSY), 100, 10000);
306
+
return stmmac_mdio_read(priv, phyaddr, devad, cmd, data);
369
307
}
370
308
371
309
/**
···
342
356
u16 phydata)
343
357
{
344
358
struct stmmac_priv *priv = netdev_priv(bus->priv);
345
-
int ret, data = phydata;
346
-
u32 value = MII_BUSY;
359
+
u32 cmd;
347
360
348
-
ret = pm_runtime_resume_and_get(priv->device);
349
-
if (ret < 0)
350
-
return ret;
351
-
352
-
value |= (phyaddr << priv->hw->mii.addr_shift)
353
-
& priv->hw->mii.addr_mask;
354
-
value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
355
-
356
-
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
357
-
& priv->hw->mii.clk_csr_mask;
358
361
if (priv->plat->has_gmac4)
359
-
value |= MII_GMAC4_WRITE;
362
+
cmd = MII_GMAC4_WRITE;
360
363
else
361
-
value |= MII_WRITE;
364
+
cmd = MII_ADDR_GWRITE;
362
365
363
-
ret = stmmac_mdio_write(priv, data, value);
364
-
365
-
pm_runtime_put(priv->device);
366
-
367
-
return ret;
366
+
return stmmac_mdio_write(priv, phyaddr, phyreg, cmd, phydata);
368
367
}
369
368
370
369
/**
···
365
394
int devad, int phyreg, u16 phydata)
366
395
{
367
396
struct stmmac_priv *priv = netdev_priv(bus->priv);
368
-
int ret, data = phydata;
369
-
u32 value = MII_BUSY;
370
-
371
-
ret = pm_runtime_resume_and_get(priv->device);
372
-
if (ret < 0)
373
-
return ret;
374
-
375
-
value |= (phyaddr << priv->hw->mii.addr_shift)
376
-
& priv->hw->mii.addr_mask;
377
-
378
-
value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift)
379
-
& priv->hw->mii.clk_csr_mask;
380
-
381
-
value |= MII_GMAC4_WRITE;
382
-
value |= MII_GMAC4_C45E;
383
-
value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask;
397
+
u32 cmd = MII_GMAC4_WRITE | MII_GMAC4_C45E;
398
+
int data = phydata;
384
399
385
400
data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT;
386
401
387
-
ret = stmmac_mdio_write(priv, data, value);
388
-
389
-
pm_runtime_put(priv->device);
390
-
391
-
return ret;
402
+
return stmmac_mdio_write(priv, phyaddr, devad, cmd, data);
392
403
}
393
404
394
405
/**
···
474
521
}
475
522
476
523
/**
524
+
* stmmac_clk_csr_set - dynamically set the MDC clock
525
+
* @priv: driver private structure
526
+
* Description: this is to dynamically set the MDC clock according to the csr
527
+
* clock input.
528
+
* Return: MII register CR field value
529
+
* Note:
530
+
* If a specific clk_csr value is passed from the platform
531
+
* this means that the CSR Clock Range selection cannot be
532
+
* changed at run-time and it is fixed (as reported in the driver
533
+
* documentation). Viceversa the driver will try to set the MDC
534
+
* clock dynamically according to the actual clock input.
535
+
*/
536
+
static u32 stmmac_clk_csr_set(struct stmmac_priv *priv)
537
+
{
538
+
unsigned long clk_rate;
539
+
u32 value = ~0;
540
+
541
+
clk_rate = clk_get_rate(priv->plat->stmmac_clk);
542
+
543
+
/* Platform provided default clk_csr would be assumed valid
544
+
* for all other cases except for the below mentioned ones.
545
+
* For values higher than the IEEE 802.3 specified frequency
546
+
* we can not estimate the proper divider as it is not known
547
+
* the frequency of clk_csr_i. So we do not change the default
548
+
* divider.
549
+
*/
550
+
if (clk_rate < CSR_F_35M)
551
+
value = STMMAC_CSR_20_35M;
552
+
else if (clk_rate < CSR_F_60M)
553
+
value = STMMAC_CSR_35_60M;
554
+
else if (clk_rate < CSR_F_100M)
555
+
value = STMMAC_CSR_60_100M;
556
+
else if (clk_rate < CSR_F_150M)
557
+
value = STMMAC_CSR_100_150M;
558
+
else if (clk_rate < CSR_F_250M)
559
+
value = STMMAC_CSR_150_250M;
560
+
else if (clk_rate <= CSR_F_300M)
561
+
value = STMMAC_CSR_250_300M;
562
+
else if (clk_rate < CSR_F_500M)
563
+
value = STMMAC_CSR_300_500M;
564
+
else if (clk_rate < CSR_F_800M)
565
+
value = STMMAC_CSR_500_800M;
566
+
567
+
if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) {
568
+
if (clk_rate > 160000000)
569
+
value = 0x03;
570
+
else if (clk_rate > 80000000)
571
+
value = 0x02;
572
+
else if (clk_rate > 40000000)
573
+
value = 0x01;
574
+
else
575
+
value = 0;
576
+
}
577
+
578
+
if (priv->plat->has_xgmac) {
579
+
if (clk_rate > 400000000)
580
+
value = 0x5;
581
+
else if (clk_rate > 350000000)
582
+
value = 0x4;
583
+
else if (clk_rate > 300000000)
584
+
value = 0x3;
585
+
else if (clk_rate > 250000000)
586
+
value = 0x2;
587
+
else if (clk_rate > 150000000)
588
+
value = 0x1;
589
+
else
590
+
value = 0x0;
591
+
}
592
+
593
+
return value;
594
+
}
595
+
596
+
static void stmmac_mdio_bus_config(struct stmmac_priv *priv)
597
+
{
598
+
u32 value;
599
+
600
+
/* If a specific clk_csr value is passed from the platform, this means
601
+
* that the CSR Clock Range value should not be computed from the CSR
602
+
* clock.
603
+
*/
604
+
if (priv->plat->clk_csr >= 0)
605
+
value = priv->plat->clk_csr;
606
+
else
607
+
value = stmmac_clk_csr_set(priv);
608
+
609
+
value <<= priv->hw->mii.clk_csr_shift;
610
+
611
+
if (value & ~priv->hw->mii.clk_csr_mask)
612
+
dev_warn(priv->device,
613
+
"clk_csr value out of range (0x%08x exceeds mask 0x%08x), truncating\n",
614
+
value, priv->hw->mii.clk_csr_mask);
615
+
616
+
priv->gmii_address_bus_config = value & priv->hw->mii.clk_csr_mask;
617
+
}
618
+
619
+
/**
477
620
* stmmac_mdio_register
478
621
* @ndev: net device structure
479
622
* Description: it registers the MII bus
···
588
539
589
540
if (!mdio_bus_data)
590
541
return 0;
542
+
543
+
stmmac_mdio_bus_config(priv);
591
544
592
545
new_bus = mdiobus_alloc();
593
546
if (!new_bus)
+3
-2
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
+3
-2
drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
···
21
21
22
22
static void common_default_data(struct plat_stmmacenet_data *plat)
23
23
{
24
-
plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
24
+
/* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
25
+
plat->clk_csr = STMMAC_CSR_20_35M;
25
26
plat->has_gmac = 1;
26
27
plat->force_sf_dma_mode = 1;
27
28
···
75
74
{
76
75
int i;
77
76
78
-
plat->clk_csr = 5;
77
+
plat->clk_csr = STMMAC_CSR_250_300M;
79
78
plat->has_gmac4 = 1;
80
79
plat->force_sf_dma_mode = 1;
81
80
plat->flags |= STMMAC_FLAG_TSO_EN;