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net: phy: vitesse: add inband caps and configuration

Add support for VSC8662 reporting its inband capabilities, and also
hook to configure the PHY's inband mode.

This fixes a regression in the macb driver caused by commit
1338cfef1ff1 ("net: macb: fix SGMII with inband aneg disabled")

Cc: stable+noautosel@kernel.org # neither this nor commit under fixes should be backported
Reported-by: Conor Dooley <conor@kernel.org>
Link: https://lore.kernel.org/r/20260304-nebulizer-rounding-40fbc81a2ba1@spud
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fixes: 1338cfef1ff1b958 ("net: macb: fix SGMII with inband aneg disabled")
Link: https://patch.msgid.link/E1w082O-0000000ChNc-1wDz@rmk-PC.armlinux.org.uk
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Russell King (Oracle) and committed by
Jakub Kicinski 6e263aad 7c52f407

+41
+41
drivers/net/phy/vitesse.c
··· 62 62 /* Vitesse Extended Page Access Register */ 63 63 #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f 64 64 65 + /* Vitesse VSC8662 extended control register */ 66 + #define VSC8662_EXT_CON1 0x17 67 + #define VSC8662_EXT_CON_MAC_AN BIT(13) 68 + 69 + #define VSC8662_MAC_AN 0x1b 70 + #define VSC8662_MAC_AN_BYPASS BIT(13) 71 + 65 72 /* Vitesse VSC73XX Extended Control Register */ 66 73 #define MII_VSC73XX_PHY_CTRL_EXT3 0x14 67 74 ··· 145 138 err = vsc824x_add_skew(phydev); 146 139 147 140 return err; 141 + } 142 + 143 + static unsigned int vsc8662_inband_caps(struct phy_device *phydev, 144 + phy_interface_t interface) 145 + { 146 + if (interface == PHY_INTERFACE_MODE_SGMII) 147 + return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE | 148 + LINK_INBAND_BYPASS; 149 + 150 + return 0; 151 + } 152 + 153 + static int vsc8662_config_inband(struct phy_device *phydev, unsigned int modes) 154 + { 155 + u16 mask, set; 156 + int ret; 157 + 158 + mask = VSC8662_MAC_AN_BYPASS; 159 + set = modes & LINK_INBAND_BYPASS ? mask : 0; 160 + ret = phy_modify(phydev, VSC8662_MAC_AN, mask, set); 161 + if (ret < 0) 162 + return ret; 163 + 164 + mask = VSC8662_EXT_CON_MAC_AN; 165 + set = modes & (LINK_INBAND_ENABLE | LINK_INBAND_BYPASS) ? mask : 0; 166 + 167 + ret = phy_modify_changed(phydev, VSC8662_EXT_CON1, mask, set); 168 + if (ret <= 0) 169 + return ret; 170 + 171 + /* We need to soft-reset the PHY when changing VSC8662_EXT_CON_MAC_AN */ 172 + return genphy_soft_reset(phydev); 148 173 } 149 174 150 175 #define VSC73XX_EXT_PAGE_ACCESS 0x1f ··· 688 649 .phy_id_mask = 0x000ffff0, 689 650 /* PHY_GBIT_FEATURES */ 690 651 .config_init = &vsc824x_config_init, 652 + .inband_caps = vsc8662_inband_caps, 653 + .config_inband = vsc8662_config_inband, 691 654 .config_aneg = &vsc82x4_config_aneg, 692 655 .config_intr = &vsc82xx_config_intr, 693 656 .handle_interrupt = &vsc82xx_handle_interrupt,