Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-imx-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux into clk-imx
Pull i.MX clock driver updates from Abel Vesa:
- Add optional ENET reference pad clock inputs for i.MX6Q/UL
- Fix debug output in PLL14xx driver to use unsigned format specifier
- Add 333.333 MHz and 477.4 MHz support to fracn-gppll for display use cases
- Fix device node reference leaks in i.MX6 driver
- Fix device node reference leak in of_assigned_ldb_sels()
- Fix ACM clock flags on i.MX8 to prevent SAI sysclk failures
- Move VF610_CLK_END define into the driver
- Add VF610 Ethernet switch clock support
- Correct CSI PHY parent clock selection on i.MX8MQ
* tag 'clk-imx-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux:
clk: imx8mq: Correct the CSI PHY sels
clk: vf610: Add support for the Ethernet switch clocks
dt-bindings: clock: vf610: Add definitions for MTIP L2 switch
dt-bindings: clock: vf610: Drop VF610_CLK_END define
clk: vf610: Move VF610_CLK_END define to clk-vf610 driver
clk: imx: imx8-acm: fix flags for acm clocks
clk: imx: imx6q: Fix device node reference leak in of_assigned_ldb_sels()
clk: imx: imx6q: Fix device node reference leak in pll6_bypassed()
clk: imx: fracn-gppll: Add 477.4MHz support
clk: imx: fracn-gppll: Add 333.333333 MHz support
clk: imx: pll14xx: Use unsigned format specifier
dt-bindings: clock: imx6q[ul]-clock: add optional clock enet[1]_ref_pad
+45
-8
+4
Documentation/devicetree/bindings/clock/imx6q-clock.yaml
+4
Documentation/devicetree/bindings/clock/imx6q-clock.yaml
···
29
29
const: 1
30
30
31
31
clocks:
32
+
minItems: 5
32
33
items:
33
34
- description: 24m osc
34
35
- description: 32k osc
35
36
- description: ckih1 clock input
36
37
- description: anaclk1 clock input
37
38
- description: anaclk2 clock input
39
+
- description: clock input from enet ref pad
38
40
39
41
clock-names:
42
+
minItems: 5
40
43
items:
41
44
- const: osc
42
45
- const: ckil
43
46
- const: ckih1
44
47
- const: anaclk1
45
48
- const: anaclk2
49
+
- const: enet_ref_pad
46
50
47
51
fsl,pmic-stby-poweroff:
48
52
$ref: /schemas/types.yaml#/definitions/flag
+4
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
+4
Documentation/devicetree/bindings/clock/imx6ul-clock.yaml
···
29
29
const: 1
30
30
31
31
clocks:
32
+
minItems: 4
32
33
items:
33
34
- description: 32k osc
34
35
- description: 24m osc
35
36
- description: ipp_di0 clock input
36
37
- description: ipp_di1 clock input
38
+
- description: clock input from enet1 ref pad
37
39
38
40
clock-names:
41
+
minItems: 4
39
42
items:
40
43
- const: ckil
41
44
- const: osc
42
45
- const: ipp_di0
43
46
- const: ipp_di1
47
+
- const: enet1_ref_pad
44
48
45
49
required:
46
50
- compatible
+2
drivers/clk/imx/clk-fracn-gppll.c
+2
drivers/clk/imx/clk-fracn-gppll.c
···
85
85
PLL_FRACN_GP(519750000U, 173, 25, 100, 1, 8),
86
86
PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8),
87
87
PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6),
88
+
PLL_FRACN_GP(477400000U, 119, 35, 100, 0, 6),
88
89
PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9),
89
90
PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12),
90
91
PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10),
92
+
PLL_FRACN_GP(333333333U, 125, 0, 1, 1, 9),
91
93
PLL_FRACN_GP(332600000U, 138, 584, 1000, 0, 10),
92
94
PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12),
93
95
PLL_FRACN_GP(241900000U, 201, 584, 1000, 0, 20),
+11
-1
drivers/clk/imx/clk-imx6q.c
+11
-1
drivers/clk/imx/clk-imx6q.c
···
188
188
}
189
189
if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
190
190
pr_err("ccm: parent clock %d not in ccm\n", index);
191
+
of_node_put(clkspec.np);
191
192
return;
192
193
}
193
194
parent = clkspec.args[0];
195
+
of_node_put(clkspec.np);
194
196
195
197
rc = of_parse_phandle_with_args(node, "assigned-clocks",
196
198
"#clock-cells", index, &clkspec);
···
200
198
return;
201
199
if (clkspec.np != node || clkspec.args[0] >= IMX6QDL_CLK_END) {
202
200
pr_err("ccm: child clock %d not in ccm\n", index);
201
+
of_node_put(clkspec.np);
203
202
return;
204
203
}
205
204
child = clkspec.args[0];
205
+
of_node_put(clkspec.np);
206
206
207
207
if (child != IMX6QDL_CLK_LDB_DI0_SEL &&
208
208
child != IMX6QDL_CLK_LDB_DI1_SEL)
···
242
238
return false;
243
239
244
240
if (clkspec.np == node &&
245
-
clkspec.args[0] == IMX6QDL_PLL6_BYPASS)
241
+
clkspec.args[0] == IMX6QDL_PLL6_BYPASS) {
242
+
of_node_put(clkspec.np);
246
243
break;
244
+
}
245
+
of_node_put(clkspec.np);
247
246
}
248
247
249
248
/* PLL6 bypass is not part of the assigned clock list */
···
255
248
256
249
ret = of_parse_phandle_with_args(node, "assigned-clock-parents",
257
250
"#clock-cells", index, &clkspec);
251
+
252
+
if (!ret)
253
+
of_node_put(clkspec.np);
258
254
259
255
if (clkspec.args[0] != IMX6QDL_CLK_PLL6)
260
256
return true;
+2
-1
drivers/clk/imx/clk-imx8-acm.c
+2
-1
drivers/clk/imx/clk-imx8-acm.c
···
371
371
for (i = 0; i < priv->soc_data->num_sels; i++) {
372
372
hws[sels[i].clkid] = devm_clk_hw_register_mux_parent_data_table(dev,
373
373
sels[i].name, sels[i].parents,
374
-
sels[i].num_parents, 0,
374
+
sels[i].num_parents,
375
+
CLK_SET_RATE_NO_REPARENT,
375
376
base + sels[i].reg,
376
377
sels[i].shift, sels[i].width,
377
378
0, NULL, NULL);
+2
-2
drivers/clk/imx/clk-imx8mq.c
+2
-2
drivers/clk/imx/clk-imx8mq.c
···
237
237
static const char * const imx8mq_csi1_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
238
238
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
239
239
240
-
static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
240
+
static const char * const imx8mq_csi1_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
241
241
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
242
242
243
243
static const char * const imx8mq_csi1_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
···
246
246
static const char * const imx8mq_csi2_core_sels[] = {"osc_25m", "sys1_pll_266m", "sys2_pll_250m", "sys1_pll_800m",
247
247
"sys2_pll_1000m", "sys3_pll_out", "audio_pll2_out", "video_pll1_out", };
248
248
249
-
static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_125m", "sys2_pll_100m", "sys1_pll_800m",
249
+
static const char * const imx8mq_csi2_phy_sels[] = {"osc_25m", "sys2_pll_333m", "sys2_pll_100m", "sys1_pll_800m",
250
250
"sys2_pll_1000m", "clk_ext2", "audio_pll2_out", "video_pll1_out", };
251
251
252
252
static const char * const imx8mq_csi2_esc_sels[] = {"osc_25m", "sys2_pll_100m", "sys1_pll_80m", "sys1_pll_800m",
+3
-3
drivers/clk/imx/clk-pll14xx.c
+3
-3
drivers/clk/imx/clk-pll14xx.c
···
151
151
/* First try if we can get the desired rate from one of the static entries */
152
152
tt = imx_get_pll_settings(pll, rate);
153
153
if (tt) {
154
-
pr_debug("%s: in=%ld, want=%ld, Using PLL setting from table\n",
154
+
pr_debug("%s: in=%lu, want=%lu, Using PLL setting from table\n",
155
155
clk_hw_get_name(&pll->hw), prate, rate);
156
156
t->rate = tt->rate;
157
157
t->mdiv = tt->mdiv;
···
173
173
174
174
if (rate >= rate_min && rate <= rate_max) {
175
175
kdiv = pll1443x_calc_kdiv(mdiv, pdiv, sdiv, rate, prate);
176
-
pr_debug("%s: in=%ld, want=%ld Only adjust kdiv %ld -> %d\n",
176
+
pr_debug("%s: in=%lu, want=%lu Only adjust kdiv %ld -> %d\n",
177
177
clk_hw_get_name(&pll->hw), prate, rate,
178
178
FIELD_GET(KDIV_MASK, pll_div_ctl1), kdiv);
179
179
fout = pll14xx_calc_rate(pll, mdiv, pdiv, sdiv, kdiv, prate);
···
211
211
}
212
212
}
213
213
found:
214
-
pr_debug("%s: in=%ld, want=%ld got=%d (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
214
+
pr_debug("%s: in=%lu, want=%lu got=%u (pdiv=%d sdiv=%d mdiv=%d kdiv=%d)\n",
215
215
clk_hw_get_name(&pll->hw), prate, rate, t->rate, t->pdiv, t->sdiv,
216
216
t->mdiv, t->kdiv);
217
217
}
+12
drivers/clk/imx/clk-vf610.c
+12
drivers/clk/imx/clk-vf610.c
···
11
11
12
12
#include "clk.h"
13
13
14
+
/*
15
+
* The VF610_CLK_END corresponds to ones defined in
16
+
* include/dt-bindings/clock/vf610-clock.h
17
+
* It shall be the value of the last defined clock +1
18
+
*/
19
+
#define VF610_CLK_END 196
20
+
14
21
#define CCM_CCR (ccm_base + 0x00)
15
22
#define CCM_CSR (ccm_base + 0x04)
16
23
#define CCM_CCSR (ccm_base + 0x08)
···
320
313
clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
321
314
clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
322
315
clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
316
+
clk[VF610_CLK_ESW] = imx_clk_gate2("esw", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(8));
317
+
clk[VF610_CLK_ESW_MAC_TAB0] = imx_clk_gate2("esw_tab0", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(12));
318
+
clk[VF610_CLK_ESW_MAC_TAB1] = imx_clk_gate2("esw_tab1", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(13));
319
+
clk[VF610_CLK_ESW_MAC_TAB2] = imx_clk_gate2("esw_tab2", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(14));
320
+
clk[VF610_CLK_ESW_MAC_TAB3] = imx_clk_gate2("esw_tab3", "ipg_bus", CCM_CCGR10, CCM_CCGRx_CGn(15));
323
321
324
322
clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
325
323
+5
-1
include/dt-bindings/clock/vf610-clock.h
+5
-1
include/dt-bindings/clock/vf610-clock.h
···
197
197
#define VF610_CLK_TCON1 188
198
198
#define VF610_CLK_CAAM 189
199
199
#define VF610_CLK_CRC 190
200
-
#define VF610_CLK_END 191
200
+
#define VF610_CLK_ESW 191
201
+
#define VF610_CLK_ESW_MAC_TAB0 192
202
+
#define VF610_CLK_ESW_MAC_TAB1 193
203
+
#define VF610_CLK_ESW_MAC_TAB2 194
204
+
#define VF610_CLK_ESW_MAC_TAB3 195
201
205
202
206
#endif /* __DT_BINDINGS_CLOCK_VF610_H */