Merge tag 'mips_6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

+2 -1

arch/mips/bcm47xx/prom.c

··· 35 35 #include <asm/bootinfo.h> 36 36 #include <bcm47xx.h> 37 37 #include <bcm47xx_board.h> 38 + #include "bcm47xx_private.h" 38 39 39 40 static char bcm47xx_system_type[20] = "Broadcom BCM47XX"; 40 41 ··· 124 123 /* Stripped version of tlb_init, with the call to build_tlb_refill_handler 125 124 * dropped. Calling it at this stage causes a hang. 126 125 */ 127 - void early_tlb_init(void) 126 + static void early_tlb_init(void) 128 127 { 129 128 write_c0_pagemask(PM_DEFAULT_MASK); 130 129 write_c0_wired(0);

+244 -196

arch/mips/boot/dts/ralink/mt7621.dtsi

··· 5 5 #include <dt-bindings/reset/mt7621-reset.h> 6 6 7 7 / { 8 + compatible = "mediatek,mt7621-soc"; 9 + 8 10 #address-cells = <1>; 9 11 #size-cells = <1>; 10 - compatible = "mediatek,mt7621-soc"; 11 12 12 13 cpus { 13 14 #address-cells = <1>; 14 15 #size-cells = <0>; 15 16 16 17 cpu@0 { 17 - device_type = "cpu"; 18 18 compatible = "mips,mips1004Kc"; 19 19 reg = <0>; 20 + device_type = "cpu"; 20 21 }; 21 22 22 23 cpu@1 { 23 - device_type = "cpu"; 24 24 compatible = "mips,mips1004Kc"; 25 25 reg = <1>; 26 + device_type = "cpu"; 26 27 }; 27 28 }; 28 29 29 30 cpuintc: cpuintc { 31 + compatible = "mti,cpu-interrupt-controller"; 32 + 30 33 #address-cells = <0>; 31 34 #interrupt-cells = <1>; 35 + 32 36 interrupt-controller; 33 - compatible = "mti,cpu-interrupt-controller"; 34 37 }; 35 38 36 39 mmc_fixed_3v3: regulator-3v3 { 37 40 compatible = "regulator-fixed"; 38 - regulator-name = "mmc_power"; 39 - regulator-min-microvolt = <3300000>; 40 - regulator-max-microvolt = <3300000>; 41 + 41 42 enable-active-high; 43 + 42 44 regulator-always-on; 45 + regulator-max-microvolt = <3300000>; 46 + regulator-min-microvolt = <3300000>; 47 + regulator-name = "mmc_power"; 43 48 }; 44 49 45 50 mmc_fixed_1v8_io: regulator-1v8 { 46 51 compatible = "regulator-fixed"; 47 - regulator-name = "mmc_io"; 48 - regulator-min-microvolt = <1800000>; 49 - regulator-max-microvolt = <1800000>; 52 + 50 53 enable-active-high; 54 + 51 55 regulator-always-on; 56 + regulator-max-microvolt = <1800000>; 57 + regulator-min-microvolt = <1800000>; 58 + regulator-name = "mmc_io"; 59 + }; 60 + 61 + pinctrl: pinctrl { 62 + compatible = "ralink,mt7621-pinctrl"; 63 + 64 + i2c_pins: i2c0-pins { 65 + pinmux { 66 + groups = "i2c"; 67 + function = "i2c"; 68 + }; 69 + }; 70 + 71 + mdio_pins: mdio0-pins { 72 + pinmux { 73 + groups = "mdio"; 74 + function = "mdio"; 75 + }; 76 + }; 77 + 78 + nand_pins: nand0-pins { 79 + sdhci-pinmux { 80 + groups = "sdhci"; 81 + function = "nand2"; 82 + }; 83 + 84 + spi-pinmux { 85 + groups = "spi"; 86 + function = "nand1"; 87 + }; 88 + }; 89 + 90 + pcie_pins: pcie0-pins { 91 + pinmux { 92 + groups = "pcie"; 93 + function = "gpio"; 94 + }; 95 + }; 96 + 97 + rgmii1_pins: rgmii1-pins { 98 + pinmux { 99 + groups = "rgmii1"; 100 + function = "rgmii1"; 101 + }; 102 + }; 103 + 104 + rgmii2_pins: rgmii2-pins { 105 + pinmux { 106 + groups = "rgmii2"; 107 + function = "rgmii2"; 108 + }; 109 + }; 110 + 111 + sdhci_pins: sdhci0-pins { 112 + pinmux { 113 + groups = "sdhci"; 114 + function = "sdhci"; 115 + }; 116 + }; 117 + 118 + spi_pins: spi0-pins { 119 + pinmux { 120 + groups = "spi"; 121 + function = "spi"; 122 + }; 123 + }; 124 + 125 + uart1_pins: uart1-pins { 126 + pinmux { 127 + groups = "uart1"; 128 + function = "uart1"; 129 + }; 130 + }; 131 + 132 + uart2_pins: uart2-pins { 133 + pinmux { 134 + groups = "uart2"; 135 + function = "uart2"; 136 + }; 137 + }; 138 + 139 + uart3_pins: uart3-pins { 140 + pinmux { 141 + groups = "uart3"; 142 + function = "uart3"; 143 + }; 144 + }; 52 145 }; 53 146 54 147 palmbus: palmbus@1e000000 { ··· 155 62 sysc: syscon@0 { 156 63 compatible = "mediatek,mt7621-sysc", "syscon"; 157 64 reg = <0x0 0x100>; 65 + 158 66 #clock-cells = <1>; 159 67 #reset-cells = <1>; 160 - ralink,memctl = <&memc>; 68 + 161 69 clock-output-names = "xtal", "cpu", "bus", 162 70 "50m", "125m", "150m", 163 71 "250m", "270m"; 72 + 73 + ralink,memctl = <&memc>; 164 74 }; 165 75 166 76 wdt: watchdog@100 { ··· 173 77 }; 174 78 175 79 gpio: gpio@600 { 80 + compatible = "mediatek,mt7621-gpio"; 81 + reg = <0x600 0x100>; 82 + 176 83 #gpio-cells = <2>; 177 84 #interrupt-cells = <2>; 178 - compatible = "mediatek,mt7621-gpio"; 85 + 179 86 gpio-controller; 180 87 gpio-ranges = <&pinctrl 0 0 95>; 88 + 181 89 interrupt-controller; 182 - reg = <0x600 0x100>; 183 90 interrupt-parent = <&gic>; 184 91 interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 185 92 }; ··· 191 92 compatible = "mediatek,mt7621-i2c"; 192 93 reg = <0x900 0x100>; 193 94 194 - clocks = <&sysc MT7621_CLK_I2C>; 195 - clock-names = "i2c"; 196 - resets = <&sysc MT7621_RST_I2C>; 197 - reset-names = "i2c"; 198 - 199 95 #address-cells = <1>; 200 96 #size-cells = <0>; 201 97 202 - status = "disabled"; 98 + clocks = <&sysc MT7621_CLK_I2C>; 99 + clock-names = "i2c"; 203 100 204 101 pinctrl-names = "default"; 205 102 pinctrl-0 = <&i2c_pins>; 103 + 104 + resets = <&sysc MT7621_RST_I2C>; 105 + reset-names = "i2c"; 106 + 107 + status = "disabled"; 206 108 }; 207 109 208 110 memc: memory-controller@5000 { ··· 270 170 }; 271 171 272 172 spi0: spi@b00 { 273 - status = "disabled"; 274 - 275 173 compatible = "ralink,mt7621-spi"; 276 174 reg = <0xb00 0x100>; 277 - 278 - clocks = <&sysc MT7621_CLK_SPI>; 279 - clock-names = "spi"; 280 - 281 - resets = <&sysc MT7621_RST_SPI>; 282 - reset-names = "spi"; 283 175 284 176 #address-cells = <1>; 285 177 #size-cells = <0>; 286 178 179 + clock-names = "spi"; 180 + clocks = <&sysc MT7621_CLK_SPI>; 181 + 287 182 pinctrl-names = "default"; 288 183 pinctrl-0 = <&spi_pins>; 289 - }; 290 - }; 291 184 292 - pinctrl: pinctrl { 293 - compatible = "ralink,mt7621-pinctrl"; 185 + reset-names = "spi"; 186 + resets = <&sysc MT7621_RST_SPI>; 294 187 295 - i2c_pins: i2c0-pins { 296 - pinmux { 297 - groups = "i2c"; 298 - function = "i2c"; 299 - }; 300 - }; 301 - 302 - spi_pins: spi0-pins { 303 - pinmux { 304 - groups = "spi"; 305 - function = "spi"; 306 - }; 307 - }; 308 - 309 - uart1_pins: uart1-pins { 310 - pinmux { 311 - groups = "uart1"; 312 - function = "uart1"; 313 - }; 314 - }; 315 - 316 - uart2_pins: uart2-pins { 317 - pinmux { 318 - groups = "uart2"; 319 - function = "uart2"; 320 - }; 321 - }; 322 - 323 - uart3_pins: uart3-pins { 324 - pinmux { 325 - groups = "uart3"; 326 - function = "uart3"; 327 - }; 328 - }; 329 - 330 - rgmii1_pins: rgmii1-pins { 331 - pinmux { 332 - groups = "rgmii1"; 333 - function = "rgmii1"; 334 - }; 335 - }; 336 - 337 - rgmii2_pins: rgmii2-pins { 338 - pinmux { 339 - groups = "rgmii2"; 340 - function = "rgmii2"; 341 - }; 342 - }; 343 - 344 - mdio_pins: mdio0-pins { 345 - pinmux { 346 - groups = "mdio"; 347 - function = "mdio"; 348 - }; 349 - }; 350 - 351 - pcie_pins: pcie0-pins { 352 - pinmux { 353 - groups = "pcie"; 354 - function = "gpio"; 355 - }; 356 - }; 357 - 358 - nand_pins: nand0-pins { 359 - spi-pinmux { 360 - groups = "spi"; 361 - function = "nand1"; 362 - }; 363 - 364 - sdhci-pinmux { 365 - groups = "sdhci"; 366 - function = "nand2"; 367 - }; 368 - }; 369 - 370 - sdhci_pins: sdhci0-pins { 371 - pinmux { 372 - groups = "sdhci"; 373 - function = "sdhci"; 374 - }; 188 + status = "disabled"; 375 189 }; 376 190 }; 377 191 378 192 mmc: mmc@1e130000 { 379 - status = "disabled"; 380 - 381 193 compatible = "mediatek,mt7620-mmc"; 382 194 reg = <0x1e130000 0x4000>; 383 195 384 196 bus-width = <4>; 385 - max-frequency = <48000000>; 386 - cap-sd-highspeed; 387 - cap-mmc-highspeed; 388 - vmmc-supply = <&mmc_fixed_3v3>; 389 - vqmmc-supply = <&mmc_fixed_1v8_io>; 390 - disable-wp; 391 197 392 - pinctrl-names = "default", "state_uhs"; 393 - pinctrl-0 = <&sdhci_pins>; 394 - pinctrl-1 = <&sdhci_pins>; 198 + cap-mmc-highspeed; 199 + cap-sd-highspeed; 395 200 396 201 clocks = <&sysc MT7621_CLK_SHXC>, 397 202 <&sysc MT7621_CLK_50M>; 398 203 clock-names = "source", "hclk"; 399 204 205 + disable-wp; 206 + 400 207 interrupt-parent = <&gic>; 401 208 interrupts = <GIC_SHARED 20 IRQ_TYPE_LEVEL_HIGH>; 209 + 210 + max-frequency = <48000000>; 211 + 212 + pinctrl-names = "default", "state_uhs"; 213 + pinctrl-0 = <&sdhci_pins>; 214 + pinctrl-1 = <&sdhci_pins>; 215 + 216 + vmmc-supply = <&mmc_fixed_3v3>; 217 + vqmmc-supply = <&mmc_fixed_1v8_io>; 218 + 219 + status = "disabled"; 402 220 }; 403 221 404 222 usb: usb@1e1c0000 { ··· 339 321 compatible = "mti,gic"; 340 322 reg = <0x1fbc0000 0x2000>; 341 323 342 - interrupt-controller; 343 324 #interrupt-cells = <3>; 325 + interrupt-controller; 344 326 345 327 mti,reserved-cpu-vectors = <7>; 346 328 347 329 timer { 348 330 compatible = "mti,gic-timer"; 349 - interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 350 331 clocks = <&sysc MT7621_CLK_CPU>; 332 + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>; 351 333 }; 352 334 }; 353 335 ··· 365 347 compatible = "mediatek,mt7621-eth"; 366 348 reg = <0x1e100000 0x10000>; 367 349 368 - clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; 369 - clock-names = "fe", "ethif"; 370 - 371 350 #address-cells = <1>; 372 351 #size-cells = <0>; 373 352 374 - resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; 375 - reset-names = "fe", "eth"; 353 + clock-names = "fe", "ethif"; 354 + clocks = <&sysc MT7621_CLK_FE>, <&sysc MT7621_CLK_ETH>; 376 355 377 356 interrupt-parent = <&gic>; 378 357 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; 379 358 380 - mediatek,ethsys = <&sysc>; 381 - 382 359 pinctrl-names = "default"; 383 360 pinctrl-0 = <&mdio_pins>, <&rgmii1_pins>, <&rgmii2_pins>; 384 361 385 - gmac0: mac@0 { 386 - compatible = "mediatek,eth-mac"; 387 - reg = <0>; 388 - phy-mode = "trgmii"; 362 + reset-names = "fe", "eth"; 363 + resets = <&sysc MT7621_RST_FE>, <&sysc MT7621_RST_ETH>; 389 364 390 - fixed-link { 391 - speed = <1000>; 392 - full-duplex; 393 - pause; 394 - }; 395 - }; 396 - 397 - gmac1: mac@1 { 398 - compatible = "mediatek,eth-mac"; 399 - reg = <1>; 400 - phy-mode = "rgmii"; 401 - 402 - fixed-link { 403 - speed = <1000>; 404 - full-duplex; 405 - pause; 406 - }; 407 - }; 365 + mediatek,ethsys = <&sysc>; 408 366 409 367 mdio: mdio-bus { 410 368 #address-cells = <1>; ··· 389 395 switch0: switch@1f { 390 396 compatible = "mediatek,mt7621"; 391 397 reg = <0x1f>; 392 - mediatek,mcm; 393 - resets = <&sysc MT7621_RST_MCM>; 394 - reset-names = "mcm"; 395 - interrupt-controller; 398 + 396 399 #interrupt-cells = <1>; 400 + interrupt-controller; 397 401 interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>; 402 + 403 + reset-names = "mcm"; 404 + resets = <&sysc MT7621_RST_MCM>; 405 + 406 + mediatek,mcm; 398 407 399 408 ports { 400 409 #address-cells = <1>; 401 410 #size-cells = <0>; 402 411 403 412 port@0 { 404 - status = "disabled"; 405 413 reg = <0>; 406 414 label = "swp0"; 415 + status = "disabled"; 407 416 }; 408 417 409 418 port@1 { 410 - status = "disabled"; 411 419 reg = <1>; 412 420 label = "swp1"; 421 + status = "disabled"; 413 422 }; 414 423 415 424 port@2 { 416 - status = "disabled"; 417 425 reg = <2>; 418 426 label = "swp2"; 427 + status = "disabled"; 419 428 }; 420 429 421 430 port@3 { 422 - status = "disabled"; 423 431 reg = <3>; 424 432 label = "swp3"; 433 + status = "disabled"; 425 434 }; 426 435 427 436 port@4 { 428 - status = "disabled"; 429 437 reg = <4>; 430 438 label = "swp4"; 439 + status = "disabled"; 431 440 }; 432 441 433 442 port@5 { 434 443 reg = <5>; 444 + 435 445 ethernet = <&gmac1>; 436 446 phy-mode = "rgmii"; 437 447 438 448 fixed-link { 439 - speed = <1000>; 440 449 full-duplex; 441 450 pause; 451 + speed = <1000>; 442 452 }; 443 453 }; 444 454 445 455 port@6 { 446 456 reg = <6>; 457 + 447 458 ethernet = <&gmac0>; 448 459 phy-mode = "trgmii"; 449 460 450 461 fixed-link { 451 - speed = <1000>; 452 462 full-duplex; 453 463 pause; 464 + speed = <1000>; 454 465 }; 455 466 }; 456 467 }; 457 468 }; 458 469 }; 470 + 471 + gmac0: mac@0 { 472 + compatible = "mediatek,eth-mac"; 473 + reg = <0>; 474 + 475 + phy-mode = "trgmii"; 476 + 477 + fixed-link { 478 + full-duplex; 479 + pause; 480 + speed = <1000>; 481 + }; 482 + }; 483 + 484 + gmac1: mac@1 { 485 + compatible = "mediatek,eth-mac"; 486 + reg = <1>; 487 + 488 + phy-mode = "rgmii"; 489 + 490 + fixed-link { 491 + full-duplex; 492 + pause; 493 + speed = <1000>; 494 + }; 495 + }; 496 + 459 497 }; 460 498 461 499 pcie: pcie@1e140000 { ··· 496 470 <0x1e142000 0x100>, /* pcie port 0 RC control registers */ 497 471 <0x1e143000 0x100>, /* pcie port 1 RC control registers */ 498 472 <0x1e144000 0x100>; /* pcie port 2 RC control registers */ 473 + ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ 474 + <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ 475 + 499 476 #address-cells = <3>; 477 + #interrupt-cells = <1>; 500 478 #size-cells = <2>; 479 + 480 + device_type = "pci"; 481 + 482 + interrupt-map-mask = <0xf800 0 0 0>; 483 + interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, 484 + <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 485 + <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 501 486 502 487 pinctrl-names = "default"; 503 488 pinctrl-0 = <&pcie_pins>; 504 489 505 - device_type = "pci"; 506 - 507 - ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */ 508 - <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */ 509 - 510 - #interrupt-cells = <1>; 511 - interrupt-map-mask = <0xF800 0 0 0>; 512 - interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>, 513 - <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>, 514 - <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 490 + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; 515 491 516 492 status = "disabled"; 517 493 518 - reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>; 519 - 520 494 pcie@0,0 { 521 495 reg = <0x0000 0 0 0 0>; 496 + ranges; 497 + 522 498 #address-cells = <3>; 523 - #size-cells = <2>; 524 - device_type = "pci"; 525 499 #interrupt-cells = <1>; 500 + #size-cells = <2>; 501 + 502 + clocks = <&sysc MT7621_CLK_PCIE0>; 503 + 504 + device_type = "pci"; 505 + 526 506 interrupt-map-mask = <0 0 0 0>; 527 507 interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>; 528 - resets = <&sysc MT7621_RST_PCIE0>; 529 - clocks = <&sysc MT7621_CLK_PCIE0>; 530 - phys = <&pcie0_phy 1>; 508 + 531 509 phy-names = "pcie-phy0"; 532 - ranges; 510 + phys = <&pcie0_phy 1>; 511 + 512 + resets = <&sysc MT7621_RST_PCIE0>; 533 513 }; 534 514 535 515 pcie@1,0 { 536 516 reg = <0x0800 0 0 0 0>; 517 + ranges; 518 + 537 519 #address-cells = <3>; 538 - #size-cells = <2>; 539 - device_type = "pci"; 540 520 #interrupt-cells = <1>; 521 + #size-cells = <2>; 522 + 523 + clocks = <&sysc MT7621_CLK_PCIE1>; 524 + 525 + device_type = "pci"; 526 + 541 527 interrupt-map-mask = <0 0 0 0>; 542 528 interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>; 543 - resets = <&sysc MT7621_RST_PCIE1>; 544 - clocks = <&sysc MT7621_CLK_PCIE1>; 545 - phys = <&pcie0_phy 1>; 529 + 546 530 phy-names = "pcie-phy1"; 547 - ranges; 531 + phys = <&pcie0_phy 1>; 532 + 533 + resets = <&sysc MT7621_RST_PCIE1>; 548 534 }; 549 535 550 536 pcie@2,0 { 551 537 reg = <0x1000 0 0 0 0>; 538 + ranges; 539 + 552 540 #address-cells = <3>; 553 - #size-cells = <2>; 554 - device_type = "pci"; 555 541 #interrupt-cells = <1>; 542 + #size-cells = <2>; 543 + 544 + clocks = <&sysc MT7621_CLK_PCIE2>; 545 + 546 + device_type = "pci"; 547 + 556 548 interrupt-map-mask = <0 0 0 0>; 557 549 interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>; 558 - resets = <&sysc MT7621_RST_PCIE2>; 559 - clocks = <&sysc MT7621_CLK_PCIE2>; 560 - phys = <&pcie2_phy 0>; 550 + 561 551 phy-names = "pcie-phy2"; 562 - ranges; 552 + phys = <&pcie2_phy 0>; 553 + 554 + resets = <&sysc MT7621_RST_PCIE2>; 563 555 }; 564 556 }; 565 557 566 558 pcie0_phy: pcie-phy@1e149000 { 567 559 compatible = "mediatek,mt7621-pci-phy"; 568 560 reg = <0x1e149000 0x0700>; 569 - clocks = <&sysc MT7621_CLK_XTAL>; 561 + 570 562 #phy-cells = <1>; 563 + 564 + clocks = <&sysc MT7621_CLK_XTAL>; 571 565 }; 572 566 573 567 pcie2_phy: pcie-phy@1e14a000 { 574 568 compatible = "mediatek,mt7621-pci-phy"; 575 569 reg = <0x1e14a000 0x0700>; 576 - clocks = <&sysc MT7621_CLK_XTAL>; 570 + 577 571 #phy-cells = <1>; 572 + 573 + clocks = <&sysc MT7621_CLK_XTAL>; 578 574 }; 579 575 };

+3

arch/mips/include/asm/asm.h

··· 37 37 #define CFI_SECTIONS 38 38 #endif 39 39 40 + #ifdef __ASSEMBLY__ 40 41 /* 41 42 * LEAF - declare leaf routine 42 43 */ ··· 122 121 #else 123 122 #define ASM_PRINT(string) 124 123 #endif 124 + 125 + #endif /* __ASSEMBLY__ */ 125 126 126 127 /* 127 128 * Stack alignment

+6

arch/mips/include/asm/setup.h

··· 2 2 #ifndef _MIPS_SETUP_H 3 3 #define _MIPS_SETUP_H 4 4 5 + #include <linux/init.h> 5 6 #include <linux/types.h> 6 7 #include <uapi/asm/setup.h> 7 8 ··· 29 28 extern void per_cpu_trap_init(bool); 30 29 extern void cpu_cache_init(void); 31 30 extern void tlb_init(void); 31 + 32 + #ifdef CONFIG_RELOCATABLE 33 + extern void * __init relocate_kernel(void); 34 + extern int plat_post_relocation(long); 35 + #endif 32 36 33 37 #endif /* __SETUP_H */

+11 -8

arch/mips/include/asm/stackframe.h

··· 308 308 jal octeon_mult_restore 309 309 #endif 310 310 #ifdef CONFIG_CPU_HAS_SMARTMIPS 311 - LONG_L $24, PT_ACX(sp) 312 - mtlhx $24 313 - LONG_L $24, PT_HI(sp) 314 - mtlhx $24 311 + LONG_L $14, PT_ACX(sp) 315 312 LONG_L $24, PT_LO(sp) 316 - mtlhx $24 313 + LONG_L $15, PT_HI(sp) 317 314 #elif !defined(CONFIG_CPU_MIPSR6) 318 315 LONG_L $24, PT_LO(sp) 319 - mtlo $24 320 - LONG_L $24, PT_HI(sp) 321 - mthi $24 316 + LONG_L $15, PT_HI(sp) 322 317 #endif 323 318 #ifdef CONFIG_32BIT 324 319 cfi_ld $8, PT_R8, \docfi ··· 322 327 cfi_ld $10, PT_R10, \docfi 323 328 cfi_ld $11, PT_R11, \docfi 324 329 cfi_ld $12, PT_R12, \docfi 330 + #ifdef CONFIG_CPU_HAS_SMARTMIPS 331 + mtlhx $14 332 + mtlhx $15 333 + mtlhx $24 334 + #elif !defined(CONFIG_CPU_MIPSR6) 335 + mtlo $24 336 + mthi $15 337 + #endif 325 338 cfi_ld $13, PT_R13, \docfi 326 339 cfi_ld $14, PT_R14, \docfi 327 340 cfi_ld $15, PT_R15, \docfi

+6

arch/mips/pci/pcie-octeon.c

··· 230 230 { 231 231 union cvmx_pcie_address pcie_addr; 232 232 union cvmx_pciercx_cfg006 pciercx_cfg006; 233 + union cvmx_pciercx_cfg032 pciercx_cfg032; 233 234 234 235 pciercx_cfg006.u32 = 235 236 cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port)); 236 237 if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0)) 238 + return 0; 239 + 240 + pciercx_cfg032.u32 = 241 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port)); 242 + if ((pciercx_cfg032.s.dlla == 0) || (pciercx_cfg032.s.lt == 1)) 237 243 return 0; 238 244 239 245 pcie_addr.u64 = 0;

+1 -1

arch/mips/rb532/gpio.c

··· 197 197 } 198 198 EXPORT_SYMBOL(rb532_gpio_set_func); 199 199 200 - int __init rb532_gpio_init(void) 200 + static int __init rb532_gpio_init(void) 201 201 { 202 202 struct resource *r; 203 203

+1 -1

arch/mips/rb532/prom.c

··· 46 46 return simple_strtoul(num, 0, 10); 47 47 } 48 48 49 - void __init prom_setup_cmdline(void) 49 + static void __init prom_setup_cmdline(void) 50 50 { 51 51 static char cmd_line[COMMAND_LINE_SIZE] __initdata; 52 52 char *cp, *board;

+5 -10

arch/mips/sgi-ip27/ip27-irq.c

··· 277 277 { 278 278 struct irq_domain *domain; 279 279 struct fwnode_handle *fn; 280 - int i; 281 280 282 281 mips_cpu_irq_init(); 283 282 ··· 285 286 * Mark these as reserved right away so they won't be used accidentally 286 287 * later. 287 288 */ 288 - for (i = 0; i <= CPU_CALL_B_IRQ; i++) 289 - set_bit(i, hub_irq_map); 290 - 291 - for (i = NI_BRDCAST_ERR_A; i <= MSC_PANIC_INTR; i++) 292 - set_bit(i, hub_irq_map); 289 + bitmap_set(hub_irq_map, 0, CPU_CALL_B_IRQ + 1); 290 + bitmap_set(hub_irq_map, NI_BRDCAST_ERR_A, MSC_PANIC_INTR - NI_BRDCAST_ERR_A + 1); 293 291 294 292 fn = irq_domain_alloc_named_fwnode("HUB"); 295 - WARN_ON(fn == NULL); 296 - if (!fn) 293 + if (WARN_ON(fn == NULL)) 297 294 return; 295 + 298 296 domain = irq_domain_create_linear(fn, IP27_HUB_IRQ_COUNT, 299 297 &hub_domain_ops, NULL); 300 - WARN_ON(domain == NULL); 301 - if (!domain) 298 + if (WARN_ON(domain == NULL)) 302 299 return; 303 300 304 301 irq_set_default_host(domain);

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