Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk fixes from Stephen Boyd:
"One more round of updates for problems seen this -rc series. Drivers
fixes are:
- Amlogic Meson audio divider fix and CPU clk critical marking
- Qualcomm multimedia GDSC marked as 'always on' to keep display
working
- Aspeed fixes for critical clks, resets causing clks to stay
disabled, and an incorrect HPLL frequency calculation
- Marvell Armada 3700 cpu clks would undervolt when switching from
low frequencies to high frequencies because the voltage didn't
stabilize in time so now we switch to an intermediate frequency
Plus we have a core framework thinko that messed up the debugfs flag
printing logic to make it not very useful"
* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
clk: aspeed: Support HPLL strapping on ast2400
clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz
clk: aspeed: Mark bclk (PCIe) and dclk (VGA) as critical
clk/mmcc-msm8996: Make mmagic_bimc_gdsc ALWAYS_ON
clk: aspeed: Treat a gate in reset as disabled
clk: Really show symbolic clock flags in debugfs
clk: qcom: gcc-msm8996: Disable halt check on UFS tx clock
clk: meson: audio-divider is one based
clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL
+87
-18
+44
-15
drivers/clk/clk-aspeed.c
+44
-15
drivers/clk/clk-aspeed.c
···
24
24
#define ASPEED_MPLL_PARAM 0x20
25
25
#define ASPEED_HPLL_PARAM 0x24
26
26
#define AST2500_HPLL_BYPASS_EN BIT(20)
27
-
#define AST2400_HPLL_STRAPPED BIT(18)
27
+
#define AST2400_HPLL_PROGRAMMED BIT(18)
28
28
#define AST2400_HPLL_BYPASS_EN BIT(17)
29
29
#define ASPEED_MISC_CTRL 0x2c
30
30
#define UART_DIV13_EN BIT(12)
···
91
91
[ASPEED_CLK_GATE_GCLK] = { 1, 7, "gclk-gate", NULL, 0 }, /* 2D engine */
92
92
[ASPEED_CLK_GATE_MCLK] = { 2, -1, "mclk-gate", "mpll", CLK_IS_CRITICAL }, /* SDRAM */
93
93
[ASPEED_CLK_GATE_VCLK] = { 3, 6, "vclk-gate", NULL, 0 }, /* Video Capture */
94
-
[ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", 0 }, /* PCIe/PCI */
95
-
[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, 0 }, /* DAC */
94
+
[ASPEED_CLK_GATE_BCLK] = { 4, 8, "bclk-gate", "bclk", CLK_IS_CRITICAL }, /* PCIe/PCI */
95
+
[ASPEED_CLK_GATE_DCLK] = { 5, -1, "dclk-gate", NULL, CLK_IS_CRITICAL }, /* DAC */
96
96
[ASPEED_CLK_GATE_REFCLK] = { 6, -1, "refclk-gate", "clkin", CLK_IS_CRITICAL },
97
97
[ASPEED_CLK_GATE_USBPORT2CLK] = { 7, 3, "usb-port2-gate", NULL, 0 }, /* USB2.0 Host port 2 */
98
98
[ASPEED_CLK_GATE_LCLK] = { 8, 5, "lclk-gate", NULL, 0 }, /* LPC */
···
212
212
{
213
213
struct aspeed_clk_gate *gate = to_aspeed_clk_gate(hw);
214
214
u32 clk = BIT(gate->clock_idx);
215
+
u32 rst = BIT(gate->reset_idx);
215
216
u32 enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
216
217
u32 reg;
218
+
219
+
/*
220
+
* If the IP is in reset, treat the clock as not enabled,
221
+
* this happens with some clocks such as the USB one when
222
+
* coming from cold reset. Without this, aspeed_clk_enable()
223
+
* will fail to lift the reset.
224
+
*/
225
+
if (gate->reset_idx >= 0) {
226
+
regmap_read(gate->map, ASPEED_RESET_CTRL, ®);
227
+
if (reg & rst)
228
+
return 0;
229
+
}
217
230
218
231
regmap_read(gate->map, ASPEED_CLK_STOP_CTRL, ®);
219
232
···
578
565
static void __init aspeed_ast2400_cc(struct regmap *map)
579
566
{
580
567
struct clk_hw *hw;
581
-
u32 val, freq, div;
568
+
u32 val, div, clkin, hpll;
569
+
const u16 hpll_rates[][4] = {
570
+
{384, 360, 336, 408},
571
+
{400, 375, 350, 425},
572
+
};
573
+
int rate;
582
574
583
575
/*
584
576
* CLKIN is the crystal oscillator, 24, 48 or 25MHz selected by
585
577
* strapping
586
578
*/
587
579
regmap_read(map, ASPEED_STRAP, &val);
588
-
if (val & CLKIN_25MHZ_EN)
589
-
freq = 25000000;
590
-
else if (val & AST2400_CLK_SOURCE_SEL)
591
-
freq = 48000000;
592
-
else
593
-
freq = 24000000;
594
-
hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, freq);
595
-
pr_debug("clkin @%u MHz\n", freq / 1000000);
580
+
rate = (val >> 8) & 3;
581
+
if (val & CLKIN_25MHZ_EN) {
582
+
clkin = 25000000;
583
+
hpll = hpll_rates[1][rate];
584
+
} else if (val & AST2400_CLK_SOURCE_SEL) {
585
+
clkin = 48000000;
586
+
hpll = hpll_rates[0][rate];
587
+
} else {
588
+
clkin = 24000000;
589
+
hpll = hpll_rates[0][rate];
590
+
}
591
+
hw = clk_hw_register_fixed_rate(NULL, "clkin", NULL, 0, clkin);
592
+
pr_debug("clkin @%u MHz\n", clkin / 1000000);
596
593
597
594
/*
598
595
* High-speed PLL clock derived from the crystal. This the CPU clock,
599
-
* and we assume that it is enabled
596
+
* and we assume that it is enabled. It can be configured through the
597
+
* HPLL_PARAM register, or set to a specified frequency by strapping.
600
598
*/
601
599
regmap_read(map, ASPEED_HPLL_PARAM, &val);
602
-
WARN(val & AST2400_HPLL_STRAPPED, "hpll is strapped not configured");
603
-
aspeed_clk_data->hws[ASPEED_CLK_HPLL] = aspeed_ast2400_calc_pll("hpll", val);
600
+
if (val & AST2400_HPLL_PROGRAMMED)
601
+
hw = aspeed_ast2400_calc_pll("hpll", val);
602
+
else
603
+
hw = clk_hw_register_fixed_rate(NULL, "hpll", "clkin", 0,
604
+
hpll * 1000000);
605
+
606
+
aspeed_clk_data->hws[ASPEED_CLK_HPLL] = hw;
604
607
605
608
/*
606
609
* Strap bits 11:10 define the CPU/AHB clock frequency ratio (aka HCLK)
+1
-2
drivers/clk/clk.c
+1
-2
drivers/clk/clk.c
···
24
24
#include <linux/pm_runtime.h>
25
25
#include <linux/sched.h>
26
26
#include <linux/clkdev.h>
27
-
#include <linux/stringify.h>
28
27
29
28
#include "clk.h"
30
29
···
2558
2559
unsigned long flag;
2559
2560
const char *name;
2560
2561
} clk_flags[] = {
2561
-
#define ENTRY(f) { f, __stringify(f) }
2562
+
#define ENTRY(f) { f, #f }
2562
2563
ENTRY(CLK_SET_RATE_GATE),
2563
2564
ENTRY(CLK_SET_PARENT_GATE),
2564
2565
ENTRY(CLK_SET_RATE_PARENT),
+1
-1
drivers/clk/meson/clk-audio-divider.c
+1
-1
drivers/clk/meson/clk-audio-divider.c
+1
drivers/clk/meson/gxbb.c
+1
drivers/clk/meson/gxbb.c
+38
drivers/clk/mvebu/armada-37xx-periph.c
+38
drivers/clk/mvebu/armada-37xx-periph.c
···
35
35
#define CLK_SEL 0x10
36
36
#define CLK_DIS 0x14
37
37
38
+
#define ARMADA_37XX_DVFS_LOAD_1 1
38
39
#define LOAD_LEVEL_NR 4
39
40
40
41
#define ARMADA_37XX_NB_L0L1 0x18
···
508
507
return -EINVAL;
509
508
}
510
509
510
+
/*
511
+
* Switching the CPU from the L2 or L3 frequencies (300 and 200 Mhz
512
+
* respectively) to L0 frequency (1.2 Ghz) requires a significant
513
+
* amount of time to let VDD stabilize to the appropriate
514
+
* voltage. This amount of time is large enough that it cannot be
515
+
* covered by the hardware countdown register. Due to this, the CPU
516
+
* might start operating at L0 before the voltage is stabilized,
517
+
* leading to CPU stalls.
518
+
*
519
+
* To work around this problem, we prevent switching directly from the
520
+
* L2/L3 frequencies to the L0 frequency, and instead switch to the L1
521
+
* frequency in-between. The sequence therefore becomes:
522
+
* 1. First switch from L2/L3(200/300MHz) to L1(600MHZ)
523
+
* 2. Sleep 20ms for stabling VDD voltage
524
+
* 3. Then switch from L1(600MHZ) to L0(1200Mhz).
525
+
*/
526
+
static void clk_pm_cpu_set_rate_wa(unsigned long rate, struct regmap *base)
527
+
{
528
+
unsigned int cur_level;
529
+
530
+
if (rate != 1200 * 1000 * 1000)
531
+
return;
532
+
533
+
regmap_read(base, ARMADA_37XX_NB_CPU_LOAD, &cur_level);
534
+
cur_level &= ARMADA_37XX_NB_CPU_LOAD_MASK;
535
+
if (cur_level <= ARMADA_37XX_DVFS_LOAD_1)
536
+
return;
537
+
538
+
regmap_update_bits(base, ARMADA_37XX_NB_CPU_LOAD,
539
+
ARMADA_37XX_NB_CPU_LOAD_MASK,
540
+
ARMADA_37XX_DVFS_LOAD_1);
541
+
msleep(20);
542
+
}
543
+
511
544
static int clk_pm_cpu_set_rate(struct clk_hw *hw, unsigned long rate,
512
545
unsigned long parent_rate)
513
546
{
···
572
537
*/
573
538
reg = ARMADA_37XX_NB_CPU_LOAD;
574
539
mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
540
+
541
+
clk_pm_cpu_set_rate_wa(rate, base);
542
+
575
543
regmap_update_bits(base, reg, mask, load_level);
576
544
577
545
return rate;
+1
drivers/clk/qcom/gcc-msm8996.c
+1
drivers/clk/qcom/gcc-msm8996.c