Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
Merge branch 'net-dsa-lantiq_gswip-prepare-for-supporting-new-features'
Daniel Golle says:
====================
net: dsa: lantiq_gswip: prepare for supporting new features
Prepare for supporting the newer standalone MaxLinear GSW1xx switch
family by refactoring the existing lantiq_gswip driver.
This is the first of a total of 3 series and doesn't yet introduce
any functional changes, but rather just makes the driver more
flexible, so new hardware and features can be supported in future.
This series has been preceded by an RFC series which covers everything
needed to support the MaxLinear GSW1xx family of switches. Andrew Lunn
had suggested to start with the 8 patches now submitted as they prepare
but don't yet introduce any functional changes.
Everything has been compile and runtime tested on AVM Fritz!Box 7490
(GSWIP version 2.1, VR9 v1.2)
Link: https://lore.kernel.org/aKDhFCNwjDDwRKsI@pidgin.makrotopia.org
====================
Link: https://patch.msgid.link/cover.1755878232.git.daniel@makrotopia.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+375
-320
+101
-313
drivers/net/dsa/lantiq_gswip.c
+101
-313
drivers/net/dsa/lantiq_gswip.c
···
25
25
* between all LAN ports by default.
26
26
*/
27
27
28
-
#include <linux/clk.h>
28
+
#include "lantiq_gswip.h"
29
+
#include "lantiq_pce.h"
30
+
29
31
#include <linux/delay.h>
30
32
#include <linux/etherdevice.h>
31
33
#include <linux/firmware.h>
···
41
39
#include <linux/of_platform.h>
42
40
#include <linux/phy.h>
43
41
#include <linux/phylink.h>
44
-
#include <linux/platform_device.h>
45
-
#include <linux/regmap.h>
46
-
#include <linux/reset.h>
47
-
#include <net/dsa.h>
48
42
#include <dt-bindings/mips/lantiq_rcu_gphy.h>
49
-
50
-
#include "lantiq_pce.h"
51
-
52
-
/* GSWIP MDIO Registers */
53
-
#define GSWIP_MDIO_GLOB 0x00
54
-
#define GSWIP_MDIO_GLOB_ENABLE BIT(15)
55
-
#define GSWIP_MDIO_CTRL 0x08
56
-
#define GSWIP_MDIO_CTRL_BUSY BIT(12)
57
-
#define GSWIP_MDIO_CTRL_RD BIT(11)
58
-
#define GSWIP_MDIO_CTRL_WR BIT(10)
59
-
#define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
60
-
#define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
61
-
#define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
62
-
#define GSWIP_MDIO_READ 0x09
63
-
#define GSWIP_MDIO_WRITE 0x0A
64
-
#define GSWIP_MDIO_MDC_CFG0 0x0B
65
-
#define GSWIP_MDIO_MDC_CFG1 0x0C
66
-
#define GSWIP_MDIO_PHYp(p) (0x15 - (p))
67
-
#define GSWIP_MDIO_PHY_LINK_MASK 0x6000
68
-
#define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
69
-
#define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
70
-
#define GSWIP_MDIO_PHY_LINK_UP 0x2000
71
-
#define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
72
-
#define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
73
-
#define GSWIP_MDIO_PHY_SPEED_M10 0x0000
74
-
#define GSWIP_MDIO_PHY_SPEED_M100 0x0800
75
-
#define GSWIP_MDIO_PHY_SPEED_G1 0x1000
76
-
#define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
77
-
#define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
78
-
#define GSWIP_MDIO_PHY_FDUP_EN 0x0200
79
-
#define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
80
-
#define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
81
-
#define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
82
-
#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
83
-
#define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
84
-
#define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
85
-
#define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
86
-
#define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
87
-
#define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
88
-
#define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
89
-
#define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
90
-
GSWIP_MDIO_PHY_FCONRX_MASK | \
91
-
GSWIP_MDIO_PHY_FCONTX_MASK | \
92
-
GSWIP_MDIO_PHY_LINK_MASK | \
93
-
GSWIP_MDIO_PHY_SPEED_MASK | \
94
-
GSWIP_MDIO_PHY_FDUP_MASK)
95
-
96
-
/* GSWIP MII Registers */
97
-
#define GSWIP_MII_CFGp(p) (0x2 * (p))
98
-
#define GSWIP_MII_CFG_RESET BIT(15)
99
-
#define GSWIP_MII_CFG_EN BIT(14)
100
-
#define GSWIP_MII_CFG_ISOLATE BIT(13)
101
-
#define GSWIP_MII_CFG_LDCLKDIS BIT(12)
102
-
#define GSWIP_MII_CFG_RGMII_IBS BIT(8)
103
-
#define GSWIP_MII_CFG_RMII_CLK BIT(7)
104
-
#define GSWIP_MII_CFG_MODE_MIIP 0x0
105
-
#define GSWIP_MII_CFG_MODE_MIIM 0x1
106
-
#define GSWIP_MII_CFG_MODE_RMIIP 0x2
107
-
#define GSWIP_MII_CFG_MODE_RMIIM 0x3
108
-
#define GSWIP_MII_CFG_MODE_RGMII 0x4
109
-
#define GSWIP_MII_CFG_MODE_GMII 0x9
110
-
#define GSWIP_MII_CFG_MODE_MASK 0xf
111
-
#define GSWIP_MII_CFG_RATE_M2P5 0x00
112
-
#define GSWIP_MII_CFG_RATE_M25 0x10
113
-
#define GSWIP_MII_CFG_RATE_M125 0x20
114
-
#define GSWIP_MII_CFG_RATE_M50 0x30
115
-
#define GSWIP_MII_CFG_RATE_AUTO 0x40
116
-
#define GSWIP_MII_CFG_RATE_MASK 0x70
117
-
#define GSWIP_MII_PCDU0 0x01
118
-
#define GSWIP_MII_PCDU1 0x03
119
-
#define GSWIP_MII_PCDU5 0x05
120
-
#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
121
-
#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
122
-
123
-
/* GSWIP Core Registers */
124
-
#define GSWIP_SWRES 0x000
125
-
#define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
126
-
#define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
127
-
#define GSWIP_VERSION 0x013
128
-
#define GSWIP_VERSION_REV_SHIFT 0
129
-
#define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
130
-
#define GSWIP_VERSION_MOD_SHIFT 8
131
-
#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
132
-
#define GSWIP_VERSION_2_0 0x100
133
-
#define GSWIP_VERSION_2_1 0x021
134
-
#define GSWIP_VERSION_2_2 0x122
135
-
#define GSWIP_VERSION_2_2_ETC 0x022
136
-
137
-
#define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
138
-
#define GSWIP_BM_RAM_ADDR 0x044
139
-
#define GSWIP_BM_RAM_CTRL 0x045
140
-
#define GSWIP_BM_RAM_CTRL_BAS BIT(15)
141
-
#define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
142
-
#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
143
-
#define GSWIP_BM_QUEUE_GCTRL 0x04A
144
-
#define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
145
-
/* buffer management Port Configuration Register */
146
-
#define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
147
-
#define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
148
-
#define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
149
-
/* buffer management Port Control Register */
150
-
#define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
151
-
#define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
152
-
#define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
153
-
154
-
/* PCE */
155
-
#define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
156
-
#define GSWIP_PCE_TBL_MASK 0x448
157
-
#define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
158
-
#define GSWIP_PCE_TBL_ADDR 0x44E
159
-
#define GSWIP_PCE_TBL_CTRL 0x44F
160
-
#define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
161
-
#define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
162
-
#define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
163
-
#define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
164
-
#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
165
-
#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
166
-
#define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
167
-
#define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
168
-
#define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
169
-
#define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
170
-
#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
171
-
#define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
172
-
#define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
173
-
#define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
174
-
#define GSWIP_PCE_GCTRL_0 0x456
175
-
#define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
176
-
#define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
177
-
#define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
178
-
#define GSWIP_PCE_GCTRL_1 0x457
179
-
#define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
180
-
#define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
181
-
#define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
182
-
#define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
183
-
#define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
184
-
#define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
185
-
#define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
186
-
#define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
187
-
#define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
188
-
#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
189
-
#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
190
-
#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
191
-
#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
192
-
#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
193
-
#define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
194
-
#define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
195
-
#define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
196
-
#define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
197
-
#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
198
-
199
-
#define GSWIP_MAC_FLEN 0x8C5
200
-
#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
201
-
#define GSWIP_MAC_CTRL_0_PADEN BIT(8)
202
-
#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
203
-
#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
204
-
#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
205
-
#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
206
-
#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
207
-
#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
208
-
#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
209
-
#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
210
-
#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
211
-
#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
212
-
#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
213
-
#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
214
-
#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
215
-
#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
216
-
#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
217
-
#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
218
-
#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */
219
-
#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
220
-
221
-
/* Ethernet Switch Fetch DMA Port Control Register */
222
-
#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
223
-
#define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
224
-
#define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
225
-
#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
226
-
#define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
227
-
#define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
228
-
#define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
229
-
#define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
230
-
#define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
231
-
232
-
/* Ethernet Switch Store DMA Port Control Register */
233
-
#define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
234
-
#define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
235
-
#define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
236
-
#define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */
237
-
238
-
#define GSWIP_TABLE_ACTIVE_VLAN 0x01
239
-
#define GSWIP_TABLE_VLAN_MAPPING 0x02
240
-
#define GSWIP_TABLE_MAC_BRIDGE 0x0b
241
-
#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */
242
-
#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */
243
-
#define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */
244
-
245
-
#define XRX200_GPHY_FW_ALIGN (16 * 1024)
246
-
247
-
/* Maximum packet size supported by the switch. In theory this should be 10240,
248
-
* but long packets currently cause lock-ups with an MTU of over 2526. Medium
249
-
* packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
250
-
* over 2526), hence an MTU value of 2400 seems safe. This issue only affects
251
-
* packet reception. This is probably caused by the PPA engine, which is on the
252
-
* RX part of the device. Packet transmission works properly up to 10240.
253
-
*/
254
-
#define GSWIP_MAX_PACKET_LENGTH 2400
255
-
256
-
struct gswip_hw_info {
257
-
int max_ports;
258
-
int cpu_port;
259
-
const struct dsa_switch_ops *ops;
260
-
};
261
43
262
44
struct xway_gphy_match_data {
263
45
char *fe_firmware_name;
264
46
char *ge_firmware_name;
265
-
};
266
-
267
-
struct gswip_gphy_fw {
268
-
struct clk *clk_gate;
269
-
struct reset_control *reset;
270
-
u32 fw_addr_offset;
271
-
char *fw_name;
272
-
};
273
-
274
-
struct gswip_vlan {
275
-
struct net_device *bridge;
276
-
u16 vid;
277
-
u8 fid;
278
-
};
279
-
280
-
struct gswip_priv {
281
-
__iomem void *gswip;
282
-
__iomem void *mdio;
283
-
__iomem void *mii;
284
-
const struct gswip_hw_info *hw_info;
285
-
const struct xway_gphy_match_data *gphy_fw_name_cfg;
286
-
struct dsa_switch *ds;
287
-
struct device *dev;
288
-
struct regmap *rcu_regmap;
289
-
struct gswip_vlan vlans[64];
290
-
int num_gphy_fw;
291
-
struct gswip_gphy_fw *gphy_fw;
292
-
u32 port_vlan_filter;
293
-
struct mutex pce_table_lock;
294
47
};
295
48
296
49
struct gswip_pce_table_entry {
···
183
426
static void gswip_mii_mask_cfg(struct gswip_priv *priv, u32 clear, u32 set,
184
427
int port)
185
428
{
186
-
/* There's no MII_CFG register for the CPU port */
187
-
if (!dsa_is_cpu_port(priv->ds, port))
188
-
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
429
+
/* MII_CFG register only exists for MII ports */
430
+
if (!(priv->hw_info->mii_ports & BIT(port)))
431
+
return;
432
+
433
+
gswip_mii_mask(priv, clear, set, GSWIP_MII_CFGp(port));
189
434
}
190
435
191
436
static void gswip_mii_mask_pcdu(struct gswip_priv *priv, u32 clear, u32 set,
192
437
int port)
193
438
{
439
+
/* MII_PCDU register only exists for MII ports */
440
+
if (!(priv->hw_info->mii_ports & BIT(port)))
441
+
return;
442
+
194
443
switch (port) {
195
444
case 0:
196
445
gswip_mii_mask(priv, clear, set, GSWIP_MII_PCDU0);
···
417
654
{
418
655
struct gswip_pce_table_entry vlan_active = {0,};
419
656
struct gswip_pce_table_entry vlan_mapping = {0,};
420
-
unsigned int cpu_port = priv->hw_info->cpu_port;
421
657
int err;
422
658
423
659
vlan_active.index = port + 1;
···
436
674
vlan_mapping.index = port + 1;
437
675
vlan_mapping.table = GSWIP_TABLE_VLAN_MAPPING;
438
676
vlan_mapping.val[0] = 0 /* vid */;
439
-
vlan_mapping.val[1] = BIT(port) | BIT(cpu_port);
677
+
vlan_mapping.val[1] = BIT(port) | dsa_cpu_ports(priv->ds);
440
678
vlan_mapping.val[2] = 0;
441
679
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
442
680
if (err) {
···
500
738
GSWIP_PCE_TBL_CTRL_OPMOD_ADWR, GSWIP_PCE_TBL_CTRL);
501
739
gswip_switch_w(priv, 0, GSWIP_PCE_TBL_MASK);
502
740
503
-
for (i = 0; i < ARRAY_SIZE(gswip_pce_microcode); i++) {
741
+
for (i = 0; i < priv->hw_info->pce_microcode_size; i++) {
504
742
gswip_switch_w(priv, i, GSWIP_PCE_TBL_ADDR);
505
-
gswip_switch_w(priv, gswip_pce_microcode[i].val_0,
743
+
gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_0,
506
744
GSWIP_PCE_TBL_VAL(0));
507
-
gswip_switch_w(priv, gswip_pce_microcode[i].val_1,
745
+
gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_1,
508
746
GSWIP_PCE_TBL_VAL(1));
509
-
gswip_switch_w(priv, gswip_pce_microcode[i].val_2,
747
+
gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_2,
510
748
GSWIP_PCE_TBL_VAL(2));
511
-
gswip_switch_w(priv, gswip_pce_microcode[i].val_3,
749
+
gswip_switch_w(priv, (*priv->hw_info->pce_microcode)[i].val_3,
512
750
GSWIP_PCE_TBL_VAL(3));
513
751
514
752
/* start the table access: */
···
566
804
567
805
static int gswip_setup(struct dsa_switch *ds)
568
806
{
807
+
unsigned int cpu_ports = dsa_cpu_ports(ds);
569
808
struct gswip_priv *priv = ds->priv;
570
-
unsigned int cpu_port = priv->hw_info->cpu_port;
571
-
int i;
572
-
int err;
809
+
struct dsa_port *cpu_dp;
810
+
int err, i;
573
811
574
812
gswip_switch_w(priv, GSWIP_SWRES_R0, GSWIP_SWRES);
575
813
usleep_range(5000, 10000);
···
591
829
}
592
830
593
831
/* Default unknown Broadcast/Multicast/Unicast port maps */
594
-
gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP1);
595
-
gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP2);
596
-
gswip_switch_w(priv, BIT(cpu_port), GSWIP_PCE_PMAP3);
832
+
gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP1);
833
+
gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP2);
834
+
gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP3);
597
835
598
836
/* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
599
837
* interoperability problem with this auto polling mechanism because
···
622
860
GSWIP_MII_CFG_EN | GSWIP_MII_CFG_ISOLATE,
623
861
0, i);
624
862
625
-
/* enable special tag insertion on cpu port */
626
-
gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
627
-
GSWIP_FDMA_PCTRLp(cpu_port));
863
+
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
864
+
/* enable special tag insertion on cpu port */
865
+
gswip_switch_mask(priv, 0, GSWIP_FDMA_PCTRL_STEN,
866
+
GSWIP_FDMA_PCTRLp(cpu_dp->index));
628
867
629
-
/* accept special tag in ingress direction */
630
-
gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
631
-
GSWIP_PCE_PCTRL_0p(cpu_port));
868
+
/* accept special tag in ingress direction */
869
+
gswip_switch_mask(priv, 0, GSWIP_PCE_PCTRL_0_INGRESS,
870
+
GSWIP_PCE_PCTRL_0p(cpu_dp->index));
871
+
}
632
872
633
873
gswip_switch_mask(priv, 0, GSWIP_BM_QUEUE_GCTRL_GL_MOD,
634
874
GSWIP_BM_QUEUE_GCTRL);
···
659
895
int port,
660
896
enum dsa_tag_protocol mp)
661
897
{
662
-
return DSA_TAG_PROTO_GSWIP;
898
+
struct gswip_priv *priv = ds->priv;
899
+
900
+
return priv->hw_info->tag_protocol;
663
901
}
664
902
665
903
static int gswip_vlan_active_create(struct gswip_priv *priv,
···
728
962
{
729
963
struct gswip_pce_table_entry vlan_mapping = {0,};
730
964
unsigned int max_ports = priv->hw_info->max_ports;
731
-
unsigned int cpu_port = priv->hw_info->cpu_port;
732
965
bool active_vlan_created = false;
733
966
int idx = -1;
734
967
int i;
···
767
1002
}
768
1003
769
1004
/* Update the VLAN mapping entry and write it to the switch */
770
-
vlan_mapping.val[1] |= BIT(cpu_port);
1005
+
vlan_mapping.val[1] |= dsa_cpu_ports(priv->ds);
771
1006
vlan_mapping.val[1] |= BIT(port);
772
1007
err = gswip_pce_table_entry_write(priv, &vlan_mapping);
773
1008
if (err) {
···
789
1024
{
790
1025
struct gswip_pce_table_entry vlan_mapping = {0,};
791
1026
unsigned int max_ports = priv->hw_info->max_ports;
792
-
unsigned int cpu_port = priv->hw_info->cpu_port;
1027
+
unsigned int cpu_ports = dsa_cpu_ports(priv->ds);
793
1028
bool active_vlan_created = false;
794
1029
int idx = -1;
795
1030
int fid = -1;
···
836
1071
837
1072
vlan_mapping.val[0] = vid;
838
1073
/* Update the VLAN mapping entry and write it to the switch */
839
-
vlan_mapping.val[1] |= BIT(cpu_port);
840
-
vlan_mapping.val[2] |= BIT(cpu_port);
1074
+
vlan_mapping.val[1] |= cpu_ports;
1075
+
vlan_mapping.val[2] |= cpu_ports;
841
1076
vlan_mapping.val[1] |= BIT(port);
842
1077
if (untagged)
843
1078
vlan_mapping.val[2] &= ~BIT(port);
···
864
1099
{
865
1100
struct gswip_pce_table_entry vlan_mapping = {0,};
866
1101
unsigned int max_ports = priv->hw_info->max_ports;
867
-
unsigned int cpu_port = priv->hw_info->cpu_port;
868
1102
int idx = -1;
869
1103
int i;
870
1104
int err;
···
899
1135
}
900
1136
901
1137
/* In case all ports are removed from the bridge, remove the VLAN */
902
-
if ((vlan_mapping.val[1] & ~BIT(cpu_port)) == 0) {
1138
+
if (!(vlan_mapping.val[1] & ~dsa_cpu_ports(priv->ds))) {
903
1139
err = gswip_vlan_active_remove(priv, idx);
904
1140
if (err) {
905
1141
dev_err(priv->dev, "failed to write active VLAN: %d\n",
···
1318
1554
MAC_10 | MAC_100 | MAC_1000;
1319
1555
}
1320
1556
1557
+
static void gswip_phylink_get_caps(struct dsa_switch *ds, int port,
1558
+
struct phylink_config *config)
1559
+
{
1560
+
struct gswip_priv *priv = ds->priv;
1561
+
1562
+
priv->hw_info->phylink_get_caps(ds, port, config);
1563
+
}
1564
+
1321
1565
static void gswip_port_set_link(struct gswip_priv *priv, int port, bool link)
1322
1566
{
1323
1567
u32 mdio_phy;
···
1598
1826
.mac_link_up = gswip_phylink_mac_link_up,
1599
1827
};
1600
1828
1601
-
static const struct dsa_switch_ops gswip_xrx200_switch_ops = {
1829
+
static const struct dsa_switch_ops gswip_switch_ops = {
1602
1830
.get_tag_protocol = gswip_get_tag_protocol,
1603
1831
.setup = gswip_setup,
1604
1832
.port_enable = gswip_port_enable,
···
1615
1843
.port_fdb_dump = gswip_port_fdb_dump,
1616
1844
.port_change_mtu = gswip_port_change_mtu,
1617
1845
.port_max_mtu = gswip_port_max_mtu,
1618
-
.phylink_get_caps = gswip_xrx200_phylink_get_caps,
1619
-
.get_strings = gswip_get_strings,
1620
-
.get_ethtool_stats = gswip_get_ethtool_stats,
1621
-
.get_sset_count = gswip_get_sset_count,
1622
-
};
1623
-
1624
-
static const struct dsa_switch_ops gswip_xrx300_switch_ops = {
1625
-
.get_tag_protocol = gswip_get_tag_protocol,
1626
-
.setup = gswip_setup,
1627
-
.port_enable = gswip_port_enable,
1628
-
.port_disable = gswip_port_disable,
1629
-
.port_bridge_join = gswip_port_bridge_join,
1630
-
.port_bridge_leave = gswip_port_bridge_leave,
1631
-
.port_fast_age = gswip_port_fast_age,
1632
-
.port_vlan_filtering = gswip_port_vlan_filtering,
1633
-
.port_vlan_add = gswip_port_vlan_add,
1634
-
.port_vlan_del = gswip_port_vlan_del,
1635
-
.port_stp_state_set = gswip_port_stp_state_set,
1636
-
.port_fdb_add = gswip_port_fdb_add,
1637
-
.port_fdb_del = gswip_port_fdb_del,
1638
-
.port_fdb_dump = gswip_port_fdb_dump,
1639
-
.port_change_mtu = gswip_port_change_mtu,
1640
-
.port_max_mtu = gswip_port_max_mtu,
1641
-
.phylink_get_caps = gswip_xrx300_phylink_get_caps,
1846
+
.phylink_get_caps = gswip_phylink_get_caps,
1642
1847
.get_strings = gswip_get_strings,
1643
1848
.get_ethtool_stats = gswip_get_ethtool_stats,
1644
1849
.get_sset_count = gswip_get_sset_count,
···
1841
2092
return err;
1842
2093
}
1843
2094
2095
+
static int gswip_validate_cpu_port(struct dsa_switch *ds)
2096
+
{
2097
+
struct gswip_priv *priv = ds->priv;
2098
+
struct dsa_port *cpu_dp;
2099
+
int cpu_port = -1;
2100
+
2101
+
dsa_switch_for_each_cpu_port(cpu_dp, ds) {
2102
+
if (cpu_port != -1)
2103
+
return dev_err_probe(ds->dev, -EINVAL,
2104
+
"only a single CPU port is supported\n");
2105
+
2106
+
cpu_port = cpu_dp->index;
2107
+
}
2108
+
2109
+
if (cpu_port == -1)
2110
+
return dev_err_probe(ds->dev, -EINVAL, "no CPU port defined\n");
2111
+
2112
+
if (BIT(cpu_port) & ~priv->hw_info->allowed_cpu_ports)
2113
+
return dev_err_probe(ds->dev, -EINVAL,
2114
+
"unsupported CPU port defined\n");
2115
+
2116
+
return 0;
2117
+
}
2118
+
1844
2119
static int gswip_probe(struct platform_device *pdev)
1845
2120
{
1846
2121
struct device_node *np, *gphy_fw_np;
···
1901
2128
priv->ds->dev = dev;
1902
2129
priv->ds->num_ports = priv->hw_info->max_ports;
1903
2130
priv->ds->priv = priv;
1904
-
priv->ds->ops = priv->hw_info->ops;
2131
+
priv->ds->ops = &gswip_switch_ops;
1905
2132
priv->ds->phylink_mac_ops = &gswip_phylink_mac_ops;
1906
2133
priv->dev = dev;
1907
2134
mutex_init(&priv->pce_table_lock);
1908
2135
version = gswip_switch_r(priv, GSWIP_VERSION);
2136
+
2137
+
/* The hardware has the 'major/minor' version bytes in the wrong order
2138
+
* preventing numerical comparisons. Construct a 16-bit unsigned integer
2139
+
* having the REV field as most significant byte and the MOD field as
2140
+
* least significant byte. This is effectively swapping the two bytes of
2141
+
* the version variable, but other than using swab16 it doesn't affect
2142
+
* the source variable.
2143
+
*/
2144
+
priv->version = GSWIP_VERSION_REV(version) << 8 |
2145
+
GSWIP_VERSION_MOD(version);
1909
2146
1910
2147
np = dev->of_node;
1911
2148
switch (version) {
···
1957
2174
dev_err_probe(dev, err, "dsa switch registration failed\n");
1958
2175
goto gphy_fw_remove;
1959
2176
}
1960
-
if (!dsa_is_cpu_port(priv->ds, priv->hw_info->cpu_port)) {
1961
-
err = dev_err_probe(dev, -EINVAL,
1962
-
"wrong CPU port defined, HW only supports port: %i\n",
1963
-
priv->hw_info->cpu_port);
2177
+
2178
+
err = gswip_validate_cpu_port(priv->ds);
2179
+
if (err)
1964
2180
goto disable_switch;
1965
-
}
1966
2181
1967
2182
platform_set_drvdata(pdev, priv);
1968
2183
1969
2184
dev_info(dev, "probed GSWIP version %lx mod %lx\n",
1970
-
(version & GSWIP_VERSION_REV_MASK) >> GSWIP_VERSION_REV_SHIFT,
1971
-
(version & GSWIP_VERSION_MOD_MASK) >> GSWIP_VERSION_MOD_SHIFT);
2185
+
GSWIP_VERSION_REV(version), GSWIP_VERSION_MOD(version));
1972
2186
return 0;
1973
2187
1974
2188
disable_switch:
···
2008
2228
2009
2229
static const struct gswip_hw_info gswip_xrx200 = {
2010
2230
.max_ports = 7,
2011
-
.cpu_port = 6,
2012
-
.ops = &gswip_xrx200_switch_ops,
2231
+
.allowed_cpu_ports = BIT(6),
2232
+
.mii_ports = BIT(0) | BIT(1) | BIT(5),
2233
+
.phylink_get_caps = gswip_xrx200_phylink_get_caps,
2234
+
.pce_microcode = &gswip_pce_microcode,
2235
+
.pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode),
2236
+
.tag_protocol = DSA_TAG_PROTO_GSWIP,
2013
2237
};
2014
2238
2015
2239
static const struct gswip_hw_info gswip_xrx300 = {
2016
2240
.max_ports = 7,
2017
-
.cpu_port = 6,
2018
-
.ops = &gswip_xrx300_switch_ops,
2241
+
.allowed_cpu_ports = BIT(6),
2242
+
.mii_ports = BIT(0) | BIT(5),
2243
+
.phylink_get_caps = gswip_xrx300_phylink_get_caps,
2244
+
.pce_microcode = &gswip_pce_microcode,
2245
+
.pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode),
2246
+
.tag_protocol = DSA_TAG_PROTO_GSWIP,
2019
2247
};
2020
2248
2021
2249
static const struct of_device_id gswip_of_match[] = {
+272
drivers/net/dsa/lantiq_gswip.h
+272
drivers/net/dsa/lantiq_gswip.h
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
#ifndef __LANTIQ_GSWIP_H
3
+
#define __LANTIQ_GSWIP_H
4
+
5
+
#include <linux/clk.h>
6
+
#include <linux/mutex.h>
7
+
#include <linux/platform_device.h>
8
+
#include <linux/regmap.h>
9
+
#include <linux/reset.h>
10
+
#include <linux/swab.h>
11
+
#include <net/dsa.h>
12
+
13
+
/* GSWIP MDIO Registers */
14
+
#define GSWIP_MDIO_GLOB 0x00
15
+
#define GSWIP_MDIO_GLOB_ENABLE BIT(15)
16
+
#define GSWIP_MDIO_CTRL 0x08
17
+
#define GSWIP_MDIO_CTRL_BUSY BIT(12)
18
+
#define GSWIP_MDIO_CTRL_RD BIT(11)
19
+
#define GSWIP_MDIO_CTRL_WR BIT(10)
20
+
#define GSWIP_MDIO_CTRL_PHYAD_MASK 0x1f
21
+
#define GSWIP_MDIO_CTRL_PHYAD_SHIFT 5
22
+
#define GSWIP_MDIO_CTRL_REGAD_MASK 0x1f
23
+
#define GSWIP_MDIO_READ 0x09
24
+
#define GSWIP_MDIO_WRITE 0x0A
25
+
#define GSWIP_MDIO_MDC_CFG0 0x0B
26
+
#define GSWIP_MDIO_MDC_CFG1 0x0C
27
+
#define GSWIP_MDIO_PHYp(p) (0x15 - (p))
28
+
#define GSWIP_MDIO_PHY_LINK_MASK 0x6000
29
+
#define GSWIP_MDIO_PHY_LINK_AUTO 0x0000
30
+
#define GSWIP_MDIO_PHY_LINK_DOWN 0x4000
31
+
#define GSWIP_MDIO_PHY_LINK_UP 0x2000
32
+
#define GSWIP_MDIO_PHY_SPEED_MASK 0x1800
33
+
#define GSWIP_MDIO_PHY_SPEED_AUTO 0x1800
34
+
#define GSWIP_MDIO_PHY_SPEED_M10 0x0000
35
+
#define GSWIP_MDIO_PHY_SPEED_M100 0x0800
36
+
#define GSWIP_MDIO_PHY_SPEED_G1 0x1000
37
+
#define GSWIP_MDIO_PHY_FDUP_MASK 0x0600
38
+
#define GSWIP_MDIO_PHY_FDUP_AUTO 0x0000
39
+
#define GSWIP_MDIO_PHY_FDUP_EN 0x0200
40
+
#define GSWIP_MDIO_PHY_FDUP_DIS 0x0600
41
+
#define GSWIP_MDIO_PHY_FCONTX_MASK 0x0180
42
+
#define GSWIP_MDIO_PHY_FCONTX_AUTO 0x0000
43
+
#define GSWIP_MDIO_PHY_FCONTX_EN 0x0100
44
+
#define GSWIP_MDIO_PHY_FCONTX_DIS 0x0180
45
+
#define GSWIP_MDIO_PHY_FCONRX_MASK 0x0060
46
+
#define GSWIP_MDIO_PHY_FCONRX_AUTO 0x0000
47
+
#define GSWIP_MDIO_PHY_FCONRX_EN 0x0020
48
+
#define GSWIP_MDIO_PHY_FCONRX_DIS 0x0060
49
+
#define GSWIP_MDIO_PHY_ADDR_MASK 0x001f
50
+
#define GSWIP_MDIO_PHY_MASK (GSWIP_MDIO_PHY_ADDR_MASK | \
51
+
GSWIP_MDIO_PHY_FCONRX_MASK | \
52
+
GSWIP_MDIO_PHY_FCONTX_MASK | \
53
+
GSWIP_MDIO_PHY_LINK_MASK | \
54
+
GSWIP_MDIO_PHY_SPEED_MASK | \
55
+
GSWIP_MDIO_PHY_FDUP_MASK)
56
+
57
+
/* GSWIP MII Registers */
58
+
#define GSWIP_MII_CFGp(p) (0x2 * (p))
59
+
#define GSWIP_MII_CFG_RESET BIT(15)
60
+
#define GSWIP_MII_CFG_EN BIT(14)
61
+
#define GSWIP_MII_CFG_ISOLATE BIT(13)
62
+
#define GSWIP_MII_CFG_LDCLKDIS BIT(12)
63
+
#define GSWIP_MII_CFG_RGMII_IBS BIT(8)
64
+
#define GSWIP_MII_CFG_RMII_CLK BIT(7)
65
+
#define GSWIP_MII_CFG_MODE_MIIP 0x0
66
+
#define GSWIP_MII_CFG_MODE_MIIM 0x1
67
+
#define GSWIP_MII_CFG_MODE_RMIIP 0x2
68
+
#define GSWIP_MII_CFG_MODE_RMIIM 0x3
69
+
#define GSWIP_MII_CFG_MODE_RGMII 0x4
70
+
#define GSWIP_MII_CFG_MODE_GMII 0x9
71
+
#define GSWIP_MII_CFG_MODE_MASK 0xf
72
+
#define GSWIP_MII_CFG_RATE_M2P5 0x00
73
+
#define GSWIP_MII_CFG_RATE_M25 0x10
74
+
#define GSWIP_MII_CFG_RATE_M125 0x20
75
+
#define GSWIP_MII_CFG_RATE_M50 0x30
76
+
#define GSWIP_MII_CFG_RATE_AUTO 0x40
77
+
#define GSWIP_MII_CFG_RATE_MASK 0x70
78
+
#define GSWIP_MII_PCDU0 0x01
79
+
#define GSWIP_MII_PCDU1 0x03
80
+
#define GSWIP_MII_PCDU5 0x05
81
+
#define GSWIP_MII_PCDU_TXDLY_MASK GENMASK(2, 0)
82
+
#define GSWIP_MII_PCDU_RXDLY_MASK GENMASK(9, 7)
83
+
84
+
/* GSWIP Core Registers */
85
+
#define GSWIP_SWRES 0x000
86
+
#define GSWIP_SWRES_R1 BIT(1) /* GSWIP Software reset */
87
+
#define GSWIP_SWRES_R0 BIT(0) /* GSWIP Hardware reset */
88
+
#define GSWIP_VERSION 0x013
89
+
#define GSWIP_VERSION_REV_MASK GENMASK(7, 0)
90
+
#define GSWIP_VERSION_MOD_MASK GENMASK(15, 8)
91
+
#define GSWIP_VERSION_REV(v) FIELD_GET(GSWIP_VERSION_REV_MASK, v)
92
+
#define GSWIP_VERSION_MOD(v) FIELD_GET(GSWIP_VERSION_MOD_MASK, v)
93
+
#define GSWIP_VERSION_2_0 0x100
94
+
#define GSWIP_VERSION_2_1 0x021
95
+
#define GSWIP_VERSION_2_2 0x122
96
+
#define GSWIP_VERSION_2_2_ETC 0x022
97
+
/* The hardware has the 'major/minor' version bytes in the wrong order
98
+
* preventing numerical comparisons. Swap the bytes of the 16-bit value
99
+
* to end up with REV being the most significant byte and MOD being the
100
+
* least significant byte, which then allows comparing it with the
101
+
* value stored in struct gswip_priv.
102
+
*/
103
+
#define GSWIP_VERSION_GE(priv, ver) ((priv)->version >= swab16(ver))
104
+
105
+
#define GSWIP_BM_RAM_VAL(x) (0x043 - (x))
106
+
#define GSWIP_BM_RAM_ADDR 0x044
107
+
#define GSWIP_BM_RAM_CTRL 0x045
108
+
#define GSWIP_BM_RAM_CTRL_BAS BIT(15)
109
+
#define GSWIP_BM_RAM_CTRL_OPMOD BIT(5)
110
+
#define GSWIP_BM_RAM_CTRL_ADDR_MASK GENMASK(4, 0)
111
+
#define GSWIP_BM_QUEUE_GCTRL 0x04A
112
+
#define GSWIP_BM_QUEUE_GCTRL_GL_MOD BIT(10)
113
+
/* buffer management Port Configuration Register */
114
+
#define GSWIP_BM_PCFGp(p) (0x080 + ((p) * 2))
115
+
#define GSWIP_BM_PCFG_CNTEN BIT(0) /* RMON Counter Enable */
116
+
#define GSWIP_BM_PCFG_IGCNT BIT(1) /* Ingres Special Tag RMON count */
117
+
/* buffer management Port Control Register */
118
+
#define GSWIP_BM_RMON_CTRLp(p) (0x81 + ((p) * 2))
119
+
#define GSWIP_BM_CTRL_RMON_RAM1_RES BIT(0) /* Software Reset for RMON RAM 1 */
120
+
#define GSWIP_BM_CTRL_RMON_RAM2_RES BIT(1) /* Software Reset for RMON RAM 2 */
121
+
122
+
/* PCE */
123
+
#define GSWIP_PCE_TBL_KEY(x) (0x447 - (x))
124
+
#define GSWIP_PCE_TBL_MASK 0x448
125
+
#define GSWIP_PCE_TBL_VAL(x) (0x44D - (x))
126
+
#define GSWIP_PCE_TBL_ADDR 0x44E
127
+
#define GSWIP_PCE_TBL_CTRL 0x44F
128
+
#define GSWIP_PCE_TBL_CTRL_BAS BIT(15)
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+
#define GSWIP_PCE_TBL_CTRL_TYPE BIT(13)
130
+
#define GSWIP_PCE_TBL_CTRL_VLD BIT(12)
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+
#define GSWIP_PCE_TBL_CTRL_KEYFORM BIT(11)
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+
#define GSWIP_PCE_TBL_CTRL_GMAP_MASK GENMASK(10, 7)
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+
#define GSWIP_PCE_TBL_CTRL_OPMOD_MASK GENMASK(6, 5)
134
+
#define GSWIP_PCE_TBL_CTRL_OPMOD_ADRD 0x00
135
+
#define GSWIP_PCE_TBL_CTRL_OPMOD_ADWR 0x20
136
+
#define GSWIP_PCE_TBL_CTRL_OPMOD_KSRD 0x40
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+
#define GSWIP_PCE_TBL_CTRL_OPMOD_KSWR 0x60
138
+
#define GSWIP_PCE_TBL_CTRL_ADDR_MASK GENMASK(4, 0)
139
+
#define GSWIP_PCE_PMAP1 0x453 /* Monitoring port map */
140
+
#define GSWIP_PCE_PMAP2 0x454 /* Default Multicast port map */
141
+
#define GSWIP_PCE_PMAP3 0x455 /* Default Unknown Unicast port map */
142
+
#define GSWIP_PCE_GCTRL_0 0x456
143
+
#define GSWIP_PCE_GCTRL_0_MTFL BIT(0) /* MAC Table Flushing */
144
+
#define GSWIP_PCE_GCTRL_0_MC_VALID BIT(3)
145
+
#define GSWIP_PCE_GCTRL_0_VLAN BIT(14) /* VLAN aware Switching */
146
+
#define GSWIP_PCE_GCTRL_1 0x457
147
+
#define GSWIP_PCE_GCTRL_1_MAC_GLOCK BIT(2) /* MAC Address table lock */
148
+
#define GSWIP_PCE_GCTRL_1_MAC_GLOCK_MOD BIT(3) /* Mac address table lock forwarding mode */
149
+
#define GSWIP_PCE_PCTRL_0p(p) (0x480 + ((p) * 0xA))
150
+
#define GSWIP_PCE_PCTRL_0_TVM BIT(5) /* Transparent VLAN mode */
151
+
#define GSWIP_PCE_PCTRL_0_VREP BIT(6) /* VLAN Replace Mode */
152
+
#define GSWIP_PCE_PCTRL_0_INGRESS BIT(11) /* Accept special tag in ingress */
153
+
#define GSWIP_PCE_PCTRL_0_PSTATE_LISTEN 0x0
154
+
#define GSWIP_PCE_PCTRL_0_PSTATE_RX 0x1
155
+
#define GSWIP_PCE_PCTRL_0_PSTATE_TX 0x2
156
+
#define GSWIP_PCE_PCTRL_0_PSTATE_LEARNING 0x3
157
+
#define GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING 0x7
158
+
#define GSWIP_PCE_PCTRL_0_PSTATE_MASK GENMASK(2, 0)
159
+
#define GSWIP_PCE_VCTRL(p) (0x485 + ((p) * 0xA))
160
+
#define GSWIP_PCE_VCTRL_UVR BIT(0) /* Unknown VLAN Rule */
161
+
#define GSWIP_PCE_VCTRL_VIMR BIT(3) /* VLAN Ingress Member violation rule */
162
+
#define GSWIP_PCE_VCTRL_VEMR BIT(4) /* VLAN Egress Member violation rule */
163
+
#define GSWIP_PCE_VCTRL_VSR BIT(5) /* VLAN Security */
164
+
#define GSWIP_PCE_VCTRL_VID0 BIT(6) /* Priority Tagged Rule */
165
+
#define GSWIP_PCE_DEFPVID(p) (0x486 + ((p) * 0xA))
166
+
167
+
#define GSWIP_MAC_FLEN 0x8C5
168
+
#define GSWIP_MAC_CTRL_0p(p) (0x903 + ((p) * 0xC))
169
+
#define GSWIP_MAC_CTRL_0_PADEN BIT(8)
170
+
#define GSWIP_MAC_CTRL_0_FCS_EN BIT(7)
171
+
#define GSWIP_MAC_CTRL_0_FCON_MASK 0x0070
172
+
#define GSWIP_MAC_CTRL_0_FCON_AUTO 0x0000
173
+
#define GSWIP_MAC_CTRL_0_FCON_RX 0x0010
174
+
#define GSWIP_MAC_CTRL_0_FCON_TX 0x0020
175
+
#define GSWIP_MAC_CTRL_0_FCON_RXTX 0x0030
176
+
#define GSWIP_MAC_CTRL_0_FCON_NONE 0x0040
177
+
#define GSWIP_MAC_CTRL_0_FDUP_MASK 0x000C
178
+
#define GSWIP_MAC_CTRL_0_FDUP_AUTO 0x0000
179
+
#define GSWIP_MAC_CTRL_0_FDUP_EN 0x0004
180
+
#define GSWIP_MAC_CTRL_0_FDUP_DIS 0x000C
181
+
#define GSWIP_MAC_CTRL_0_GMII_MASK 0x0003
182
+
#define GSWIP_MAC_CTRL_0_GMII_AUTO 0x0000
183
+
#define GSWIP_MAC_CTRL_0_GMII_MII 0x0001
184
+
#define GSWIP_MAC_CTRL_0_GMII_RGMII 0x0002
185
+
#define GSWIP_MAC_CTRL_2p(p) (0x905 + ((p) * 0xC))
186
+
#define GSWIP_MAC_CTRL_2_LCHKL BIT(2) /* Frame Length Check Long Enable */
187
+
#define GSWIP_MAC_CTRL_2_MLEN BIT(3) /* Maximum Untagged Frame Lnegth */
188
+
189
+
/* Ethernet Switch Fetch DMA Port Control Register */
190
+
#define GSWIP_FDMA_PCTRLp(p) (0xA80 + ((p) * 0x6))
191
+
#define GSWIP_FDMA_PCTRL_EN BIT(0) /* FDMA Port Enable */
192
+
#define GSWIP_FDMA_PCTRL_STEN BIT(1) /* Special Tag Insertion Enable */
193
+
#define GSWIP_FDMA_PCTRL_VLANMOD_MASK GENMASK(4, 3) /* VLAN Modification Control */
194
+
#define GSWIP_FDMA_PCTRL_VLANMOD_SHIFT 3 /* VLAN Modification Control */
195
+
#define GSWIP_FDMA_PCTRL_VLANMOD_DIS (0x0 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
196
+
#define GSWIP_FDMA_PCTRL_VLANMOD_PRIO (0x1 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
197
+
#define GSWIP_FDMA_PCTRL_VLANMOD_ID (0x2 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
198
+
#define GSWIP_FDMA_PCTRL_VLANMOD_BOTH (0x3 << GSWIP_FDMA_PCTRL_VLANMOD_SHIFT)
199
+
200
+
/* Ethernet Switch Store DMA Port Control Register */
201
+
#define GSWIP_SDMA_PCTRLp(p) (0xBC0 + ((p) * 0x6))
202
+
#define GSWIP_SDMA_PCTRL_EN BIT(0) /* SDMA Port Enable */
203
+
#define GSWIP_SDMA_PCTRL_FCEN BIT(1) /* Flow Control Enable */
204
+
#define GSWIP_SDMA_PCTRL_PAUFWD BIT(3) /* Pause Frame Forwarding */
205
+
206
+
#define GSWIP_TABLE_ACTIVE_VLAN 0x01
207
+
#define GSWIP_TABLE_VLAN_MAPPING 0x02
208
+
#define GSWIP_TABLE_MAC_BRIDGE 0x0b
209
+
#define GSWIP_TABLE_MAC_BRIDGE_KEY3_FID GENMASK(5, 0) /* Filtering identifier */
210
+
#define GSWIP_TABLE_MAC_BRIDGE_VAL0_PORT GENMASK(7, 4) /* Port on learned entries */
211
+
#define GSWIP_TABLE_MAC_BRIDGE_VAL1_STATIC BIT(0) /* Static, non-aging entry */
212
+
213
+
#define XRX200_GPHY_FW_ALIGN (16 * 1024)
214
+
215
+
/* Maximum packet size supported by the switch. In theory this should be 10240,
216
+
* but long packets currently cause lock-ups with an MTU of over 2526. Medium
217
+
* packets are sometimes dropped (e.g. TCP over 2477, UDP over 2516-2519, ICMP
218
+
* over 2526), hence an MTU value of 2400 seems safe. This issue only affects
219
+
* packet reception. This is probably caused by the PPA engine, which is on the
220
+
* RX part of the device. Packet transmission works properly up to 10240.
221
+
*/
222
+
#define GSWIP_MAX_PACKET_LENGTH 2400
223
+
224
+
struct gswip_pce_microcode {
225
+
u16 val_3;
226
+
u16 val_2;
227
+
u16 val_1;
228
+
u16 val_0;
229
+
};
230
+
231
+
struct gswip_hw_info {
232
+
int max_ports;
233
+
unsigned int allowed_cpu_ports;
234
+
unsigned int mii_ports;
235
+
const struct gswip_pce_microcode (*pce_microcode)[];
236
+
size_t pce_microcode_size;
237
+
enum dsa_tag_protocol tag_protocol;
238
+
void (*phylink_get_caps)(struct dsa_switch *ds, int port,
239
+
struct phylink_config *config);
240
+
};
241
+
242
+
struct gswip_gphy_fw {
243
+
struct clk *clk_gate;
244
+
struct reset_control *reset;
245
+
u32 fw_addr_offset;
246
+
char *fw_name;
247
+
};
248
+
249
+
struct gswip_vlan {
250
+
struct net_device *bridge;
251
+
u16 vid;
252
+
u8 fid;
253
+
};
254
+
255
+
struct gswip_priv {
256
+
__iomem void *gswip;
257
+
__iomem void *mdio;
258
+
__iomem void *mii;
259
+
const struct gswip_hw_info *hw_info;
260
+
const struct xway_gphy_match_data *gphy_fw_name_cfg;
261
+
struct dsa_switch *ds;
262
+
struct device *dev;
263
+
struct regmap *rcu_regmap;
264
+
struct gswip_vlan vlans[64];
265
+
int num_gphy_fw;
266
+
struct gswip_gphy_fw *gphy_fw;
267
+
u32 port_vlan_filter;
268
+
struct mutex pce_table_lock;
269
+
u16 version;
270
+
};
271
+
272
+
#endif /* __LANTIQ_GSWIP_H */
+2
-7
drivers/net/dsa/lantiq_pce.h
+2
-7
drivers/net/dsa/lantiq_pce.h
···
7
7
* Copyright (C) 2017 - 2018 Hauke Mehrtens <hauke@hauke-m.de>
8
8
*/
9
9
10
+
#include "lantiq_gswip.h"
11
+
10
12
enum {
11
13
OUT_MAC0 = 0,
12
14
OUT_MAC1,
···
74
72
FLAG_NN2,
75
73
FLAG_END,
76
74
FLAG_NO, /*13*/
77
-
};
78
-
79
-
struct gswip_pce_microcode {
80
-
u16 val_3;
81
-
u16 val_2;
82
-
u16 val_1;
83
-
u16 val_0;
84
75
};
85
76
86
77
#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \