Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Regression fixers for the big 3:
- nouveau: hdmi audio, dac load detect, s/r regressions fixed
- radeon: long standing system hang fixed, hdmi audio and rs780 fast
fb fixes
- intel: one old regression, a WARN removal, and a stop X dying fix
Otherwise one mgag200 fix, a couple of arm build fixes, and a core use
after free fix."
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/nv50/kms: use dac loadval from vbios, where it's available
drm/nv50/disp: force dac power state during load detect
drm/nv50-nv84/fifo: fix resume regression introduced by playlist race fix
drm/nv84/disp: Fix HDMI audio regression
drm/i915/sdvo: Use &intel_sdvo->ddc instead of intel_sdvo->i2c for DDC.
drm/radeon: don't allow audio on DCE6
drm/radeon: Use direct mapping for fast fb access on RS780/RS880 (v2)
radeon: Fix system hang issue when using KMS with older cards
drm/i915: no lvds quirk for hp t5740
drm/i915: Quirk the pipe A quirk in the modeset state checker
drm/i915: Fix spurious -EIO/SIGBUS on wedged gpus
drm/mgag200: Add missing write to index before accessing data register
drm/nouveau: use mdelay instead of large udelay constants
drm/tilcd: select BACKLIGHT_LCD_SUPPORT
drm: fix a use-after-free when GPU acceleration disabled
+188
-68
+5
-1
drivers/gpu/drm/drm_irq.c
+5
-1
drivers/gpu/drm/drm_irq.c
···
1054
1054
*/
1055
1055
void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
1056
1056
{
1057
-
/* vblank is not initialized (IRQ not installed ?) */
1057
+
/* vblank is not initialized (IRQ not installed ?), or has been freed */
1058
1058
if (!dev->num_crtcs)
1059
1059
return;
1060
1060
/*
···
1075
1075
void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
1076
1076
{
1077
1077
unsigned long irqflags;
1078
+
1079
+
/* vblank is not initialized (IRQ not installed ?), or has been freed */
1080
+
if (!dev->num_crtcs)
1081
+
return;
1078
1082
1079
1083
if (dev->vblank_inmodeset[crtc]) {
1080
1084
spin_lock_irqsave(&dev->vbl_lock, irqflags);
+2
-5
drivers/gpu/drm/i915/i915_gem.c
+2
-5
drivers/gpu/drm/i915/i915_gem.c
···
91
91
{
92
92
int ret;
93
93
94
-
#define EXIT_COND (!i915_reset_in_progress(error))
94
+
#define EXIT_COND (!i915_reset_in_progress(error) || \
95
+
i915_terminally_wedged(error))
95
96
if (EXIT_COND)
96
97
return 0;
97
-
98
-
/* GPU is already declared terminally dead, give up. */
99
-
if (i915_terminally_wedged(error))
100
-
return -EIO;
101
98
102
99
/*
103
100
* Only wait 10 seconds for the gpu reset to complete to avoid hanging
+5
drivers/gpu/drm/i915/intel_display.c
+5
drivers/gpu/drm/i915/intel_display.c
···
7937
7937
memset(&pipe_config, 0, sizeof(pipe_config));
7938
7938
active = dev_priv->display.get_pipe_config(crtc,
7939
7939
&pipe_config);
7940
+
7941
+
/* hw state is inconsistent with the pipe A quirk */
7942
+
if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
7943
+
active = crtc->active;
7944
+
7940
7945
WARN(crtc->active != active,
7941
7946
"crtc active state doesn't match with hw state "
7942
7947
"(expected %i, found %i)\n", crtc->active, active);
+2
-2
drivers/gpu/drm/i915/intel_lvds.c
+2
-2
drivers/gpu/drm/i915/intel_lvds.c
···
815
815
},
816
816
{
817
817
.callback = intel_no_lvds_dmi_callback,
818
-
.ident = "Hewlett-Packard HP t5740e Thin Client",
818
+
.ident = "Hewlett-Packard HP t5740",
819
819
.matches = {
820
820
DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
821
-
DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
821
+
DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
822
822
},
823
823
},
824
824
{
+1
-1
drivers/gpu/drm/i915/intel_sdvo.c
+1
-1
drivers/gpu/drm/i915/intel_sdvo.c
···
1776
1776
* Assume that the preferred modes are
1777
1777
* arranged in priority order.
1778
1778
*/
1779
-
intel_ddc_get_modes(connector, intel_sdvo->i2c);
1779
+
intel_ddc_get_modes(connector, &intel_sdvo->ddc);
1780
1780
if (list_empty(&connector->probed_modes) == false)
1781
1781
goto end;
1782
1782
+5
-4
drivers/gpu/drm/mgag200/mgag200_mode.c
+5
-4
drivers/gpu/drm/mgag200/mgag200_mode.c
···
1034
1034
else
1035
1035
hi_pri_lvl = 5;
1036
1036
1037
-
WREG8(0x1fde, 0x06);
1038
-
WREG8(0x1fdf, hi_pri_lvl);
1037
+
WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1038
+
WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
1039
1039
} else {
1040
+
WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
1040
1041
if (mdev->reg_1e24 >= 0x01)
1041
-
WREG8(0x1fdf, 0x03);
1042
+
WREG8(MGAREG_CRTCEXT_DATA, 0x03);
1042
1043
else
1043
-
WREG8(0x1fdf, 0x04);
1044
+
WREG8(MGAREG_CRTCEXT_DATA, 0x04);
1044
1045
}
1045
1046
}
1046
1047
return 0;
+6
-1
drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+6
-1
drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
···
50
50
{
51
51
const u32 doff = (or * 0x800);
52
52
int load = -EINVAL;
53
+
nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
54
+
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
53
55
nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
54
-
udelay(9500);
56
+
mdelay(9);
57
+
udelay(500);
55
58
nv_wr32(priv, 0x61a00c + doff, 0x80000000);
56
59
load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
57
60
nv_wr32(priv, 0x61a00c + doff, 0x00000000);
61
+
nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
62
+
nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
58
63
return load;
59
64
}
60
65
+4
drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
+4
drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
···
55
55
nv_wr32(priv, 0x616510 + hoff, 0x00000000);
56
56
nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
57
57
58
+
nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
59
+
nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
60
+
nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
61
+
58
62
/* ??? */
59
63
nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
60
64
nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
+10
-4
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+10
-4
drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
···
40
40
* FIFO channel objects
41
41
******************************************************************************/
42
42
43
-
void
44
-
nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
43
+
static void
44
+
nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
45
45
{
46
46
struct nouveau_bar *bar = nouveau_bar(priv);
47
47
struct nouveau_gpuobj *cur;
48
48
int i, p;
49
49
50
-
mutex_lock(&nv_subdev(priv)->mutex);
51
50
cur = priv->playlist[priv->cur_playlist];
52
51
priv->cur_playlist = !priv->cur_playlist;
53
52
···
60
61
nv_wr32(priv, 0x0032f4, cur->addr >> 12);
61
62
nv_wr32(priv, 0x0032ec, p);
62
63
nv_wr32(priv, 0x002500, 0x00000101);
64
+
}
65
+
66
+
void
67
+
nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
68
+
{
69
+
mutex_lock(&nv_subdev(priv)->mutex);
70
+
nv50_fifo_playlist_update_locked(priv);
63
71
mutex_unlock(&nv_subdev(priv)->mutex);
64
72
}
65
73
···
495
489
496
490
for (i = 0; i < 128; i++)
497
491
nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
498
-
nv50_fifo_playlist_update(priv);
492
+
nv50_fifo_playlist_update_locked(priv);
499
493
500
494
nv_wr32(priv, 0x003200, 0x00000001);
501
495
nv_wr32(priv, 0x003250, 0x00000001);
+1
-1
drivers/gpu/drm/nouveau/core/include/core/class.h
+1
-1
drivers/gpu/drm/nouveau/core/include/core/class.h
···
218
218
#define NV50_DISP_DAC_PWR_STATE 0x00000040
219
219
#define NV50_DISP_DAC_PWR_STATE_ON 0x00000000
220
220
#define NV50_DISP_DAC_PWR_STATE_OFF 0x00000040
221
-
#define NV50_DISP_DAC_LOAD 0x0002000c
221
+
#define NV50_DISP_DAC_LOAD 0x00020100
222
222
#define NV50_DISP_DAC_LOAD_VALUE 0x00000007
223
223
224
224
#define NV50_DISP_PIOR_MTHD 0x00030000
+3
-1
drivers/gpu/drm/nouveau/nv50_display.c
+3
-1
drivers/gpu/drm/nouveau/nv50_display.c
···
1554
1554
{
1555
1555
struct nv50_disp *disp = nv50_disp(encoder->dev);
1556
1556
int ret, or = nouveau_encoder(encoder)->or;
1557
-
u32 load = 0;
1557
+
u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
1558
+
if (load == 0)
1559
+
load = 340;
1558
1560
1559
1561
ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
1560
1562
if (ret || load != 7)
+8
-3
drivers/gpu/drm/radeon/atombios_encoders.c
+8
-3
drivers/gpu/drm/radeon/atombios_encoders.c
···
667
667
int
668
668
atombios_get_encoder_mode(struct drm_encoder *encoder)
669
669
{
670
+
struct drm_device *dev = encoder->dev;
671
+
struct radeon_device *rdev = dev->dev_private;
670
672
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
671
673
struct drm_connector *connector;
672
674
struct radeon_connector *radeon_connector;
···
695
693
case DRM_MODE_CONNECTOR_DVII:
696
694
case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
697
695
if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
698
-
radeon_audio)
696
+
radeon_audio &&
697
+
!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
699
698
return ATOM_ENCODER_MODE_HDMI;
700
699
else if (radeon_connector->use_digital)
701
700
return ATOM_ENCODER_MODE_DVI;
···
707
704
case DRM_MODE_CONNECTOR_HDMIA:
708
705
default:
709
706
if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
710
-
radeon_audio)
707
+
radeon_audio &&
708
+
!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
711
709
return ATOM_ENCODER_MODE_HDMI;
712
710
else
713
711
return ATOM_ENCODER_MODE_DVI;
···
722
718
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
723
719
return ATOM_ENCODER_MODE_DP;
724
720
else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
725
-
radeon_audio)
721
+
radeon_audio &&
722
+
!ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
726
723
return ATOM_ENCODER_MODE_HDMI;
727
724
else
728
725
return ATOM_ENCODER_MODE_DVI;
+6
-4
drivers/gpu/drm/radeon/evergreen.c
+6
-4
drivers/gpu/drm/radeon/evergreen.c
···
4754
4754
rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
4755
4755
4756
4756
/* Enable IRQ */
4757
+
if (!rdev->irq.installed) {
4758
+
r = radeon_irq_kms_init(rdev);
4759
+
if (r)
4760
+
return r;
4761
+
}
4762
+
4757
4763
r = r600_irq_init(rdev);
4758
4764
if (r) {
4759
4765
DRM_ERROR("radeon: IH init failed (%d).\n", r);
···
4926
4920
return r;
4927
4921
/* Memory manager */
4928
4922
r = radeon_bo_init(rdev);
4929
-
if (r)
4930
-
return r;
4931
-
4932
-
r = radeon_irq_kms_init(rdev);
4933
4923
if (r)
4934
4924
return r;
4935
4925
+6
-4
drivers/gpu/drm/radeon/ni.c
+6
-4
drivers/gpu/drm/radeon/ni.c
···
2025
2025
}
2026
2026
2027
2027
/* Enable IRQ */
2028
+
if (!rdev->irq.installed) {
2029
+
r = radeon_irq_kms_init(rdev);
2030
+
if (r)
2031
+
return r;
2032
+
}
2033
+
2028
2034
r = r600_irq_init(rdev);
2029
2035
if (r) {
2030
2036
DRM_ERROR("radeon: IH init failed (%d).\n", r);
···
2193
2187
return r;
2194
2188
/* Memory manager */
2195
2189
r = radeon_bo_init(rdev);
2196
-
if (r)
2197
-
return r;
2198
-
2199
-
r = radeon_irq_kms_init(rdev);
2200
2190
if (r)
2201
2191
return r;
2202
2192
+6
-3
drivers/gpu/drm/radeon/r100.c
+6
-3
drivers/gpu/drm/radeon/r100.c
···
3869
3869
}
3870
3870
3871
3871
/* Enable IRQ */
3872
+
if (!rdev->irq.installed) {
3873
+
r = radeon_irq_kms_init(rdev);
3874
+
if (r)
3875
+
return r;
3876
+
}
3877
+
3872
3878
r100_irq_set(rdev);
3873
3879
rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3874
3880
/* 1M ring buffer */
···
4028
4022
r100_mc_init(rdev);
4029
4023
/* Fence driver */
4030
4024
r = radeon_fence_driver_init(rdev);
4031
-
if (r)
4032
-
return r;
4033
-
r = radeon_irq_kms_init(rdev);
4034
4025
if (r)
4035
4026
return r;
4036
4027
/* Memory manager */
+6
-3
drivers/gpu/drm/radeon/r300.c
+6
-3
drivers/gpu/drm/radeon/r300.c
···
1382
1382
}
1383
1383
1384
1384
/* Enable IRQ */
1385
+
if (!rdev->irq.installed) {
1386
+
r = radeon_irq_kms_init(rdev);
1387
+
if (r)
1388
+
return r;
1389
+
}
1390
+
1385
1391
r100_irq_set(rdev);
1386
1392
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1387
1393
/* 1M ring buffer */
···
1520
1514
r300_mc_init(rdev);
1521
1515
/* Fence driver */
1522
1516
r = radeon_fence_driver_init(rdev);
1523
-
if (r)
1524
-
return r;
1525
-
r = radeon_irq_kms_init(rdev);
1526
1517
if (r)
1527
1518
return r;
1528
1519
/* Memory manager */
+6
-4
drivers/gpu/drm/radeon/r420.c
+6
-4
drivers/gpu/drm/radeon/r420.c
···
265
265
}
266
266
267
267
/* Enable IRQ */
268
+
if (!rdev->irq.installed) {
269
+
r = radeon_irq_kms_init(rdev);
270
+
if (r)
271
+
return r;
272
+
}
273
+
268
274
r100_irq_set(rdev);
269
275
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
270
276
/* 1M ring buffer */
···
414
408
r420_debugfs(rdev);
415
409
/* Fence driver */
416
410
r = radeon_fence_driver_init(rdev);
417
-
if (r) {
418
-
return r;
419
-
}
420
-
r = radeon_irq_kms_init(rdev);
421
411
if (r) {
422
412
return r;
423
413
}
+6
-3
drivers/gpu/drm/radeon/r520.c
+6
-3
drivers/gpu/drm/radeon/r520.c
···
194
194
}
195
195
196
196
/* Enable IRQ */
197
+
if (!rdev->irq.installed) {
198
+
r = radeon_irq_kms_init(rdev);
199
+
if (r)
200
+
return r;
201
+
}
202
+
197
203
rs600_irq_set(rdev);
198
204
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
199
205
/* 1M ring buffer */
···
301
295
rv515_debugfs(rdev);
302
296
/* Fence driver */
303
297
r = radeon_fence_driver_init(rdev);
304
-
if (r)
305
-
return r;
306
-
r = radeon_irq_kms_init(rdev);
307
298
if (r)
308
299
return r;
309
300
/* Memory manager */
+49
-4
drivers/gpu/drm/radeon/r600.c
+49
-4
drivers/gpu/drm/radeon/r600.c
···
1046
1046
return -1;
1047
1047
}
1048
1048
1049
+
uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
1050
+
{
1051
+
uint32_t r;
1052
+
1053
+
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
1054
+
r = RREG32(R_0028FC_MC_DATA);
1055
+
WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
1056
+
return r;
1057
+
}
1058
+
1059
+
void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1060
+
{
1061
+
WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
1062
+
S_0028F8_MC_IND_WR_EN(1));
1063
+
WREG32(R_0028FC_MC_DATA, v);
1064
+
WREG32(R_0028F8_MC_INDEX, 0x7F);
1065
+
}
1066
+
1049
1067
static void r600_mc_program(struct radeon_device *rdev)
1050
1068
{
1051
1069
struct rv515_mc_save save;
···
1199
1181
{
1200
1182
u32 tmp;
1201
1183
int chansize, numchan;
1184
+
uint32_t h_addr, l_addr;
1185
+
unsigned long long k8_addr;
1202
1186
1203
1187
/* Get VRAM informations */
1204
1188
rdev->mc.vram_is_ddr = true;
···
1241
1221
if (rdev->flags & RADEON_IS_IGP) {
1242
1222
rs690_pm_info(rdev);
1243
1223
rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1224
+
1225
+
if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
1226
+
/* Use K8 direct mapping for fast fb access. */
1227
+
rdev->fastfb_working = false;
1228
+
h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
1229
+
l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
1230
+
k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
1231
+
#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
1232
+
if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
1233
+
#endif
1234
+
{
1235
+
/* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
1236
+
* memory is present.
1237
+
*/
1238
+
if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
1239
+
DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
1240
+
(unsigned long long)rdev->mc.aper_base, k8_addr);
1241
+
rdev->mc.aper_base = (resource_size_t)k8_addr;
1242
+
rdev->fastfb_working = true;
1243
+
}
1244
+
}
1245
+
}
1244
1246
}
1247
+
1245
1248
radeon_update_bandwidth_info(rdev);
1246
1249
return 0;
1247
1250
}
···
3245
3202
}
3246
3203
3247
3204
/* Enable IRQ */
3205
+
if (!rdev->irq.installed) {
3206
+
r = radeon_irq_kms_init(rdev);
3207
+
if (r)
3208
+
return r;
3209
+
}
3210
+
3248
3211
r = r600_irq_init(rdev);
3249
3212
if (r) {
3250
3213
DRM_ERROR("radeon: IH init failed (%d).\n", r);
···
3402
3353
return r;
3403
3354
/* Memory manager */
3404
3355
r = radeon_bo_init(rdev);
3405
-
if (r)
3406
-
return r;
3407
-
3408
-
r = radeon_irq_kms_init(rdev);
3409
3356
if (r)
3410
3357
return r;
3411
3358
+8
drivers/gpu/drm/radeon/r600d.h
+8
drivers/gpu/drm/radeon/r600d.h
···
1342
1342
#define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */
1343
1343
#define PACKET3_SURFACE_BASE_UPDATE 0x73
1344
1344
1345
+
#define R_000011_K8_FB_LOCATION 0x11
1346
+
#define R_000012_MC_MISC_UMA_CNTL 0x12
1347
+
#define G_000012_K8_ADDR_EXT(x) (((x) >> 0) & 0xFF)
1348
+
#define R_0028F8_MC_INDEX 0x28F8
1349
+
#define S_0028F8_MC_IND_ADDR(x) (((x) & 0x1FF) << 0)
1350
+
#define C_0028F8_MC_IND_ADDR 0xFFFFFE00
1351
+
#define S_0028F8_MC_IND_WR_EN(x) (((x) & 0x1) << 9)
1352
+
#define R_0028FC_MC_DATA 0x28FC
1345
1353
1346
1354
#define R_008020_GRBM_SOFT_RESET 0x8020
1347
1355
#define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0)
+4
drivers/gpu/drm/radeon/radeon_asic.c
+4
drivers/gpu/drm/radeon/radeon_asic.c
···
122
122
rdev->mc_rreg = &rs600_mc_rreg;
123
123
rdev->mc_wreg = &rs600_mc_wreg;
124
124
}
125
+
if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126
+
rdev->mc_rreg = &rs780_mc_rreg;
127
+
rdev->mc_wreg = &rs780_mc_wreg;
128
+
}
125
129
if (rdev->family >= CHIP_R600) {
126
130
rdev->pciep_rreg = &r600_pciep_rreg;
127
131
rdev->pciep_wreg = &r600_pciep_wreg;
+2
drivers/gpu/drm/radeon/radeon_asic.h
+2
drivers/gpu/drm/radeon/radeon_asic.h
···
347
347
extern void r600_pm_misc(struct radeon_device *rdev);
348
348
extern void r600_pm_init_profile(struct radeon_device *rdev);
349
349
extern void rs780_pm_init_profile(struct radeon_device *rdev);
350
+
extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
351
+
extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
350
352
extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
351
353
extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
352
354
extern int r600_get_pcie_lanes(struct radeon_device *rdev);
+6
-3
drivers/gpu/drm/radeon/rs400.c
+6
-3
drivers/gpu/drm/radeon/rs400.c
···
417
417
}
418
418
419
419
/* Enable IRQ */
420
+
if (!rdev->irq.installed) {
421
+
r = radeon_irq_kms_init(rdev);
422
+
if (r)
423
+
return r;
424
+
}
425
+
420
426
r100_irq_set(rdev);
421
427
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
422
428
/* 1M ring buffer */
···
539
533
rs400_mc_init(rdev);
540
534
/* Fence driver */
541
535
r = radeon_fence_driver_init(rdev);
542
-
if (r)
543
-
return r;
544
-
r = radeon_irq_kms_init(rdev);
545
536
if (r)
546
537
return r;
547
538
/* Memory manager */
+6
-3
drivers/gpu/drm/radeon/rs600.c
+6
-3
drivers/gpu/drm/radeon/rs600.c
···
923
923
}
924
924
925
925
/* Enable IRQ */
926
+
if (!rdev->irq.installed) {
927
+
r = radeon_irq_kms_init(rdev);
928
+
if (r)
929
+
return r;
930
+
}
931
+
926
932
rs600_irq_set(rdev);
927
933
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
928
934
/* 1M ring buffer */
···
1051
1045
rs600_debugfs(rdev);
1052
1046
/* Fence driver */
1053
1047
r = radeon_fence_driver_init(rdev);
1054
-
if (r)
1055
-
return r;
1056
-
r = radeon_irq_kms_init(rdev);
1057
1048
if (r)
1058
1049
return r;
1059
1050
/* Memory manager */
+6
-3
drivers/gpu/drm/radeon/rs690.c
+6
-3
drivers/gpu/drm/radeon/rs690.c
···
651
651
}
652
652
653
653
/* Enable IRQ */
654
+
if (!rdev->irq.installed) {
655
+
r = radeon_irq_kms_init(rdev);
656
+
if (r)
657
+
return r;
658
+
}
659
+
654
660
rs600_irq_set(rdev);
655
661
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
656
662
/* 1M ring buffer */
···
780
774
rv515_debugfs(rdev);
781
775
/* Fence driver */
782
776
r = radeon_fence_driver_init(rdev);
783
-
if (r)
784
-
return r;
785
-
r = radeon_irq_kms_init(rdev);
786
777
if (r)
787
778
return r;
788
779
/* Memory manager */
+6
-3
drivers/gpu/drm/radeon/rv515.c
+6
-3
drivers/gpu/drm/radeon/rv515.c
···
532
532
}
533
533
534
534
/* Enable IRQ */
535
+
if (!rdev->irq.installed) {
536
+
r = radeon_irq_kms_init(rdev);
537
+
if (r)
538
+
return r;
539
+
}
540
+
535
541
rs600_irq_set(rdev);
536
542
rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
537
543
/* 1M ring buffer */
···
666
660
rv515_debugfs(rdev);
667
661
/* Fence driver */
668
662
r = radeon_fence_driver_init(rdev);
669
-
if (r)
670
-
return r;
671
-
r = radeon_irq_kms_init(rdev);
672
663
if (r)
673
664
return r;
674
665
/* Memory manager */
+6
-4
drivers/gpu/drm/radeon/rv770.c
+6
-4
drivers/gpu/drm/radeon/rv770.c
···
1887
1887
rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1888
1888
1889
1889
/* Enable IRQ */
1890
+
if (!rdev->irq.installed) {
1891
+
r = radeon_irq_kms_init(rdev);
1892
+
if (r)
1893
+
return r;
1894
+
}
1895
+
1890
1896
r = r600_irq_init(rdev);
1891
1897
if (r) {
1892
1898
DRM_ERROR("radeon: IH init failed (%d).\n", r);
···
2048
2042
return r;
2049
2043
/* Memory manager */
2050
2044
r = radeon_bo_init(rdev);
2051
-
if (r)
2052
-
return r;
2053
-
2054
-
r = radeon_irq_kms_init(rdev);
2055
2045
if (r)
2056
2046
return r;
2057
2047
+6
-4
drivers/gpu/drm/radeon/si.c
+6
-4
drivers/gpu/drm/radeon/si.c
···
5350
5350
}
5351
5351
5352
5352
/* Enable IRQ */
5353
+
if (!rdev->irq.installed) {
5354
+
r = radeon_irq_kms_init(rdev);
5355
+
if (r)
5356
+
return r;
5357
+
}
5358
+
5353
5359
r = si_irq_init(rdev);
5354
5360
if (r) {
5355
5361
DRM_ERROR("radeon: IH init failed (%d).\n", r);
···
5536
5530
return r;
5537
5531
/* Memory manager */
5538
5532
r = radeon_bo_init(rdev);
5539
-
if (r)
5540
-
return r;
5541
-
5542
-
r = radeon_irq_kms_init(rdev);
5543
5533
if (r)
5544
5534
return r;
5545
5535
+1
drivers/gpu/drm/tilcdc/Kconfig
+1
drivers/gpu/drm/tilcdc/Kconfig