Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
soundwire: qcom: prepare for v3.x
cleanup the register layout structs to prepare for adding new 3.x
controller support.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Tested-by: Alexey Klimov <alexey.klimov@linaro.org> # sm8550
Link: https://patch.msgid.link/20250912083225.228778-6-srinivas.kandagatla@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Srinivas Kandagatla
and committed by
Vinod Koul
6ed85ea1
9e53a66a
+56
-21
+56
-21
drivers/soundwire/qcom.c
+56
-21
drivers/soundwire/qcom.c
···
99
99
#define SWRM_MCP_SLV_STATUS 0x1090
100
100
#define SWRM_MCP_SLV_STATUS_MASK GENMASK(1, 0)
101
101
#define SWRM_MCP_SLV_STATUS_SZ 2
102
-
#define SWRM_DP_PORT_CTRL_BANK(n, m) (0x1124 + 0x100 * (n - 1) + 0x40 * m)
103
-
#define SWRM_DP_PORT_CTRL_2_BANK(n, m) (0x1128 + 0x100 * (n - 1) + 0x40 * m)
104
-
#define SWRM_DP_BLOCK_CTRL_1(n) (0x112C + 0x100 * (n - 1))
105
-
#define SWRM_DP_BLOCK_CTRL2_BANK(n, m) (0x1130 + 0x100 * (n - 1) + 0x40 * m)
106
-
#define SWRM_DP_PORT_HCTRL_BANK(n, m) (0x1134 + 0x100 * (n - 1) + 0x40 * m)
107
-
#define SWRM_DP_BLOCK_CTRL3_BANK(n, m) (0x1138 + 0x100 * (n - 1) + 0x40 * m)
108
-
#define SWRM_DP_SAMPLECTRL2_BANK(n, m) (0x113C + 0x100 * (n - 1) + 0x40 * m)
109
-
#define SWRM_DIN_DPn_PCM_PORT_CTRL(n) (0x1054 + 0x100 * (n - 1))
102
+
103
+
#define SWRM_DPn_PORT_CTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
104
+
#define SWRM_DPn_PORT_CTRL_2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
105
+
#define SWRM_DPn_BLOCK_CTRL_1(offset, n) (offset + 0x100 * (n - 1))
106
+
#define SWRM_DPn_BLOCK_CTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
107
+
#define SWRM_DPn_PORT_HCTRL_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
108
+
#define SWRM_DPn_BLOCK_CTRL3_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
109
+
#define SWRM_DPn_SAMPLECTRL2_BANK(offset, n, m) (offset + 0x100 * (n - 1) + 0x40 * m)
110
+
110
111
#define SWR_V1_3_MSTR_MAX_REG_ADDR 0x1740
111
112
#define SWR_V2_0_MSTR_MAX_REG_ADDR 0x50ac
112
113
···
172
171
SWRM_REG_CMD_FIFO_RD_CMD,
173
172
SWRM_REG_CMD_FIFO_STATUS,
174
173
SWRM_REG_CMD_FIFO_RD_FIFO_ADDR,
174
+
SWRM_OFFSET_DP_PORT_CTRL_BANK,
175
+
SWRM_OFFSET_DP_PORT_CTRL_2_BANK,
176
+
SWRM_OFFSET_DP_BLOCK_CTRL_1,
177
+
SWRM_OFFSET_DP_BLOCK_CTRL2_BANK,
178
+
SWRM_OFFSET_DP_PORT_HCTRL_BANK,
179
+
SWRM_OFFSET_DP_BLOCK_CTRL3_BANK,
180
+
SWRM_OFFSET_DP_SAMPLECTRL2_BANK,
175
181
};
176
182
177
183
struct qcom_swrm_ctrl {
···
238
230
[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V1_3_CMD_FIFO_RD_CMD,
239
231
[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V1_3_CMD_FIFO_STATUS,
240
232
[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V1_3_CMD_FIFO_RD_FIFO_ADDR,
233
+
[SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1124,
234
+
[SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1128,
235
+
[SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x112c,
236
+
[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1130,
237
+
[SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1134,
238
+
[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1138,
239
+
[SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x113c,
241
240
};
242
241
243
242
static const struct qcom_swrm_data swrm_v1_3_data = {
···
279
264
[SWRM_REG_CMD_FIFO_RD_CMD] = SWRM_V2_0_CMD_FIFO_RD_CMD,
280
265
[SWRM_REG_CMD_FIFO_STATUS] = SWRM_V2_0_CMD_FIFO_STATUS,
281
266
[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR] = SWRM_V2_0_CMD_FIFO_RD_FIFO_ADDR,
267
+
[SWRM_OFFSET_DP_PORT_CTRL_BANK] = 0x1124,
268
+
[SWRM_OFFSET_DP_PORT_CTRL_2_BANK] = 0x1128,
269
+
[SWRM_OFFSET_DP_BLOCK_CTRL_1] = 0x112c,
270
+
[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK] = 0x1130,
271
+
[SWRM_OFFSET_DP_PORT_HCTRL_BANK] = 0x1134,
272
+
[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK] = 0x1138,
273
+
[SWRM_OFFSET_DP_SAMPLECTRL2_BANK] = 0x113c,
282
274
};
283
275
284
276
static const struct qcom_swrm_data swrm_v2_0_data = {
···
986
964
unsigned int bank)
987
965
{
988
966
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
967
+
u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL_1];
989
968
990
-
return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
991
-
p_params->bps - 1);
992
-
969
+
return ctrl->reg_write(ctrl, SWRM_DPn_BLOCK_CTRL_1(offset, p_params->num),
970
+
p_params->bps - 1);
993
971
}
994
972
995
973
static int qcom_swrm_transport_params(struct sdw_bus *bus,
···
999
977
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1000
978
struct qcom_swrm_port_config *pcfg;
1001
979
u32 value;
1002
-
int reg = SWRM_DP_PORT_CTRL_BANK((params->port_num), bank);
980
+
int reg, offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
1003
981
int ret;
982
+
983
+
reg = SWRM_DPn_PORT_CTRL_BANK(offset, params->port_num, bank);
1004
984
1005
985
pcfg = &ctrl->pconfig[params->port_num];
1006
986
···
1015
991
goto err;
1016
992
1017
993
if (pcfg->si > 0xff) {
994
+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_SAMPLECTRL2_BANK];
1018
995
value = (pcfg->si >> 8) & 0xff;
1019
-
reg = SWRM_DP_SAMPLECTRL2_BANK(params->port_num, bank);
996
+
reg = SWRM_DPn_SAMPLECTRL2_BANK(offset, params->port_num, bank);
997
+
1020
998
ret = ctrl->reg_write(ctrl, reg, value);
1021
999
if (ret)
1022
1000
goto err;
1023
1001
}
1024
1002
1025
1003
if (pcfg->lane_control != SWR_INVALID_PARAM) {
1026
-
reg = SWRM_DP_PORT_CTRL_2_BANK(params->port_num, bank);
1004
+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_2_BANK];
1005
+
reg = SWRM_DPn_PORT_CTRL_2_BANK(offset, params->port_num, bank);
1006
+
1027
1007
value = pcfg->lane_control;
1028
1008
ret = ctrl->reg_write(ctrl, reg, value);
1029
1009
if (ret)
···
1035
1007
}
1036
1008
1037
1009
if (pcfg->blk_group_count != SWR_INVALID_PARAM) {
1038
-
reg = SWRM_DP_BLOCK_CTRL2_BANK(params->port_num, bank);
1010
+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL2_BANK];
1011
+
1012
+
reg = SWRM_DPn_BLOCK_CTRL2_BANK(offset, params->port_num, bank);
1013
+
1039
1014
value = pcfg->blk_group_count;
1040
1015
ret = ctrl->reg_write(ctrl, reg, value);
1041
1016
if (ret)
1042
1017
goto err;
1043
1018
}
1044
1019
1045
-
if (pcfg->hstart != SWR_INVALID_PARAM
1046
-
&& pcfg->hstop != SWR_INVALID_PARAM) {
1047
-
reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1020
+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_HCTRL_BANK];
1021
+
reg = SWRM_DPn_PORT_HCTRL_BANK(offset, params->port_num, bank);
1022
+
1023
+
if (pcfg->hstart != SWR_INVALID_PARAM && pcfg->hstop != SWR_INVALID_PARAM) {
1048
1024
value = (pcfg->hstop << 4) | pcfg->hstart;
1049
1025
ret = ctrl->reg_write(ctrl, reg, value);
1050
1026
} else {
1051
-
reg = SWRM_DP_PORT_HCTRL_BANK(params->port_num, bank);
1052
1027
value = (SWR_HSTOP_MAX_VAL << 4) | SWR_HSTART_MIN_VAL;
1053
1028
ret = ctrl->reg_write(ctrl, reg, value);
1054
1029
}
···
1060
1029
goto err;
1061
1030
1062
1031
if (pcfg->bp_mode != SWR_INVALID_PARAM) {
1063
-
reg = SWRM_DP_BLOCK_CTRL3_BANK(params->port_num, bank);
1032
+
offset = ctrl->reg_layout[SWRM_OFFSET_DP_BLOCK_CTRL3_BANK];
1033
+
reg = SWRM_DPn_BLOCK_CTRL3_BANK(offset, params->port_num, bank);
1064
1034
ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1065
1035
}
1066
1036
···
1073
1041
struct sdw_enable_ch *enable_ch,
1074
1042
unsigned int bank)
1075
1043
{
1076
-
u32 reg = SWRM_DP_PORT_CTRL_BANK(enable_ch->port_num, bank);
1044
+
u32 reg;
1077
1045
struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1078
1046
u32 val;
1047
+
u32 offset = ctrl->reg_layout[SWRM_OFFSET_DP_PORT_CTRL_BANK];
1048
+
1049
+
reg = SWRM_DPn_PORT_CTRL_BANK(offset, enable_ch->port_num, bank);
1079
1050
1080
1051
ctrl->reg_read(ctrl, reg, &val);
1081
1052