Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'drm-fixes-2019-02-22' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie:
"This contains a single i915 tiled display fix, and a set of
amdgpu/radeon fixes.
i915:
- tiled display fix
amdgpu/radeon:
- runtime PM fix
- bulk moves disable (fix is too large for 5.0)
- a set of display fixes that are all cc'ed stable so we didn't want
to leave them until -next"
* tag 'drm-fixes-2019-02-22' of git://anongit.freedesktop.org/drm/drm:
drm/amdgpu: disable bulk moves for now
drm/amd/display: set clocks to 0 on suspend on dce80
drm/amd/display: fix optimize_bandwidth func pointer for dce80
drm/amd/display: Fix negative cursor pos programming
drm/i915/fbdev: Actually configure untiled displays
drm/amd/display: Raise dispclk value for dce11
drm/amd/display: Fix MST reboot/poweroff sequence
drm/amdgpu: Update sdma golden setting for vega20
drm/amdgpu: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime
gpu: drm: radeon: Set DPM_FLAG_NEVER_SKIP when enabling PM-runtime
+47
-18
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+1
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+2
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
···
638
638
struct ttm_bo_global *glob = adev->mman.bdev.glob;
639
639
struct amdgpu_vm_bo_base *bo_base;
640
640
641
+
#if 0
641
642
if (vm->bulk_moveable) {
642
643
spin_lock(&glob->lru_lock);
643
644
ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
644
645
spin_unlock(&glob->lru_lock);
645
646
return;
646
647
}
648
+
#endif
647
649
648
650
memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
649
651
+2
-2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+2
-2
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
···
128
128
129
129
static const struct soc15_reg_golden golden_settings_sdma0_4_2[] =
130
130
{
131
-
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
131
+
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
132
132
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xffffffff, 0x3f000100),
133
133
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
134
134
SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
···
158
158
};
159
159
160
160
static const struct soc15_reg_golden golden_settings_sdma1_4_2[] = {
161
-
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
161
+
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CHICKEN_BITS, 0xfe931f07, 0x02831f07),
162
162
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_CLK_CTRL, 0xffffffff, 0x3f000100),
163
163
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG, 0x0000773f, 0x00004002),
164
164
SOC15_REG_GOLDEN_VALUE(SDMA1, 0, mmSDMA1_GB_ADDR_CONFIG_READ, 0x0000773f, 0x00004002),
+3
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+3
-2
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
···
786
786
struct amdgpu_display_manager *dm = &adev->dm;
787
787
int ret = 0;
788
788
789
+
WARN_ON(adev->dm.cached_state);
790
+
adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
791
+
789
792
s3_handle_mst(adev->ddev, true);
790
793
791
794
amdgpu_dm_irq_suspend(adev);
792
795
793
-
WARN_ON(adev->dm.cached_state);
794
-
adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
795
796
796
797
dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
797
798
+8
-3
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
+8
-3
drivers/gpu/drm/amd/display/dc/dce/dce_clk_mgr.c
···
662
662
{
663
663
struct dce_clk_mgr *clk_mgr_dce = TO_DCE_CLK_MGR(clk_mgr);
664
664
struct dm_pp_power_level_change_request level_change_req;
665
+
int patched_disp_clk = context->bw.dce.dispclk_khz;
666
+
667
+
/*TODO: W/A for dal3 linux, investigate why this works */
668
+
if (!clk_mgr_dce->dfs_bypass_active)
669
+
patched_disp_clk = patched_disp_clk * 115 / 100;
665
670
666
671
level_change_req.power_level = dce_get_required_clocks_state(clk_mgr, context);
667
672
/* get max clock state from PPLIB */
···
676
671
clk_mgr_dce->cur_min_clks_state = level_change_req.power_level;
677
672
}
678
673
679
-
if (should_set_clock(safe_to_lower, context->bw.dce.dispclk_khz, clk_mgr->clks.dispclk_khz)) {
680
-
context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, context->bw.dce.dispclk_khz);
681
-
clk_mgr->clks.dispclk_khz = context->bw.dce.dispclk_khz;
674
+
if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr->clks.dispclk_khz)) {
675
+
context->bw.dce.dispclk_khz = dce_set_clock(clk_mgr, patched_disp_clk);
676
+
clk_mgr->clks.dispclk_khz = patched_disp_clk;
682
677
}
683
678
dce11_pplib_apply_display_requirements(clk_mgr->ctx->dc, context);
684
679
}
+4
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+4
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
···
37
37
struct dc *dc,
38
38
struct dc_state *context);
39
39
40
+
void dce100_optimize_bandwidth(
41
+
struct dc *dc,
42
+
struct dc_state *context);
43
+
40
44
bool dce100_enable_display_power_gating(struct dc *dc, uint8_t controller_id,
41
45
struct dc_bios *dcb,
42
46
enum pipe_gating_control power_gating);
+1
-1
drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
+1
-1
drivers/gpu/drm/amd/display/dc/dce80/dce80_hw_sequencer.c
···
77
77
dc->hwss.enable_display_power_gating = dce100_enable_display_power_gating;
78
78
dc->hwss.pipe_control_lock = dce_pipe_control_lock;
79
79
dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
80
-
dc->hwss.optimize_bandwidth = dce100_prepare_bandwidth;
80
+
dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
81
81
}
82
82
+16
-3
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
+16
-3
drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c
···
790
790
struct dc *dc,
791
791
struct dc_state *context)
792
792
{
793
-
/* TODO implement when needed but for now hardcode max value*/
794
-
context->bw.dce.dispclk_khz = 681000;
795
-
context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
793
+
int i;
794
+
bool at_least_one_pipe = false;
795
+
796
+
for (i = 0; i < dc->res_pool->pipe_count; i++) {
797
+
if (context->res_ctx.pipe_ctx[i].stream)
798
+
at_least_one_pipe = true;
799
+
}
800
+
801
+
if (at_least_one_pipe) {
802
+
/* TODO implement when needed but for now hardcode max value*/
803
+
context->bw.dce.dispclk_khz = 681000;
804
+
context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
805
+
} else {
806
+
context->bw.dce.dispclk_khz = 0;
807
+
context->bw.dce.yclk_khz = 0;
808
+
}
796
809
797
810
return true;
798
811
}
+2
-2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+2
-2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
···
2658
2658
.mirror = pipe_ctx->plane_state->horizontal_mirror
2659
2659
};
2660
2660
2661
-
pos_cpy.x -= pipe_ctx->plane_state->dst_rect.x;
2662
-
pos_cpy.y -= pipe_ctx->plane_state->dst_rect.y;
2661
+
pos_cpy.x_hotspot += pipe_ctx->plane_state->dst_rect.x;
2662
+
pos_cpy.y_hotspot += pipe_ctx->plane_state->dst_rect.y;
2663
2663
2664
2664
if (pipe_ctx->plane_state->address.type
2665
2665
== PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
+7
-5
drivers/gpu/drm/i915/intel_fbdev.c
+7
-5
drivers/gpu/drm/i915/intel_fbdev.c
···
336
336
bool *enabled, int width, int height)
337
337
{
338
338
struct drm_i915_private *dev_priv = to_i915(fb_helper->dev);
339
-
unsigned long conn_configured, conn_seq, mask;
340
339
unsigned int count = min(fb_helper->connector_count, BITS_PER_LONG);
340
+
unsigned long conn_configured, conn_seq;
341
341
int i, j;
342
342
bool *save_enabled;
343
343
bool fallback = true, ret = true;
···
355
355
drm_modeset_backoff(&ctx);
356
356
357
357
memcpy(save_enabled, enabled, count);
358
-
mask = GENMASK(count - 1, 0);
358
+
conn_seq = GENMASK(count - 1, 0);
359
359
conn_configured = 0;
360
360
retry:
361
-
conn_seq = conn_configured;
362
361
for (i = 0; i < count; i++) {
363
362
struct drm_fb_helper_connector *fb_conn;
364
363
struct drm_connector *connector;
···
370
371
if (conn_configured & BIT(i))
371
372
continue;
372
373
373
-
if (conn_seq == 0 && !connector->has_tile)
374
+
/* First pass, only consider tiled connectors */
375
+
if (conn_seq == GENMASK(count - 1, 0) && !connector->has_tile)
374
376
continue;
375
377
376
378
if (connector->status == connector_status_connected)
···
475
475
conn_configured |= BIT(i);
476
476
}
477
477
478
-
if ((conn_configured & mask) != mask && conn_configured != conn_seq)
478
+
if (conn_configured != conn_seq) { /* repeat until no more are found */
479
+
conn_seq = conn_configured;
479
480
goto retry;
481
+
}
480
482
481
483
/*
482
484
* If the BIOS didn't enable everything it could, fall back to have the
+1
drivers/gpu/drm/radeon/radeon_kms.c
+1
drivers/gpu/drm/radeon/radeon_kms.c