drm/amd/display: PSR eDP p-state warning occurs intermittently after unplug DP

[Why]
with eDP + DP, each display use one pipe. after DP unplugged, eDP switch
from one pipe to two pipes -- pipe split. dpp1_cm_set_regamma_pwl will
be executed too. The duration from switch single pipe to dual pipes is a
little long which could let eDP enter PSR mode. upon two pipes for eDP
are setup, eDP PHY is disabled. front pipe is not really running to
fetch data from frame buffer. i.e., dchubp is not in normal working
status. execution of hubbub1_wm_change_req_wa may cause p-state warning.

[How]
disable eDP PSR before dc_commit_state. psr is disabled when execute
hubbub1_wm_change_req_wa.

Signed-off-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Roman Li <Roman.Li@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

authored by

hersen wu and committed by

Alex Deucher 5 years ago 6ee90e88 9804ecbb

+48 -6

3 changed files

expand all

drivers

gpu

drm

amd

display

amdgpu_dm

amdgpu_dm.c

core

dc.c

dc.h

+21 -6

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

··· 171 171 static bool amdgpu_dm_psr_enable(struct dc_stream_state *stream); 172 172 static bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream); 173 173 static bool amdgpu_dm_psr_disable(struct dc_stream_state *stream); 174 - 174 + static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm); 175 175 176 176 /* 177 177 * dm_vblank_get_counter ··· 7445 7445 struct drm_connector_state *old_con_state, *new_con_state; 7446 7446 struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; 7447 7447 int crtc_disable_count = 0; 7448 + bool mode_set_reset_required = false; 7448 7449 7449 7450 drm_atomic_helper_update_legacy_modeset_state(dev, state); 7450 7451 ··· 7522 7521 acrtc->enabled = true; 7523 7522 acrtc->hw_mode = new_crtc_state->mode; 7524 7523 crtc->hwmode = new_crtc_state->mode; 7524 + mode_set_reset_required = true; 7525 7525 } else if (modereset_required(new_crtc_state)) { 7526 7526 DRM_DEBUG_DRIVER("Atomic commit: RESET. crtc id %d:[%p]\n", acrtc->crtc_id, acrtc); 7527 7527 /* i.e. reset mode */ 7528 - if (dm_old_crtc_state->stream) { 7529 - if (dm_old_crtc_state->stream->link->psr_settings.psr_allow_active) 7530 - amdgpu_dm_psr_disable(dm_old_crtc_state->stream); 7531 - 7528 + if (dm_old_crtc_state->stream) 7532 7529 remove_stream(adev, acrtc, dm_old_crtc_state->stream); 7533 - } 7530 + mode_set_reset_required = true; 7534 7531 } 7535 7532 } /* for_each_crtc_in_state() */ 7536 7533 7537 7534 if (dc_state) { 7535 + /* if there mode set or reset, disable eDP PSR */ 7536 + if (mode_set_reset_required) 7537 + amdgpu_dm_psr_disable_all(dm); 7538 + 7538 7539 dm_enable_per_frame_crtc_master_sync(dc_state); 7539 7540 mutex_lock(&dm->dc_lock); 7540 7541 WARN_ON(!dc_commit_state(dm->dc, dc_state)); ··· 9055 9052 DRM_DEBUG_DRIVER("Disabling psr...\n"); 9056 9053 9057 9054 return dc_link_set_psr_allow_active(stream->link, false, true); 9055 + } 9056 + 9057 + /* 9058 + * amdgpu_dm_psr_disable() - disable psr f/w 9059 + * if psr is enabled on any stream 9060 + * 9061 + * Return: true if success 9062 + */ 9063 + static bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm) 9064 + { 9065 + DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n"); 9066 + return dc_set_psr_allow_active(dm->dc, false); 9058 9067 } 9059 9068 9060 9069 void amdgpu_dm_trigger_timing_sync(struct drm_device *dev)

+24

drivers/gpu/drm/amd/display/dc/core/dc.c

··· 2948 2948 dc->hwss.get_clock(dc, clock_type, clock_cfg); 2949 2949 } 2950 2950 2951 + /* enable/disable eDP PSR without specify stream for eDP */ 2952 + bool dc_set_psr_allow_active(struct dc *dc, bool enable) 2953 + { 2954 + int i; 2955 + 2956 + for (i = 0; i < dc->current_state->stream_count ; i++) { 2957 + struct dc_link *link; 2958 + struct dc_stream_state *stream = dc->current_state->streams[i]; 2959 + 2960 + link = stream->link; 2961 + if (!link) 2962 + continue; 2963 + 2964 + if (link->psr_settings.psr_feature_enabled) { 2965 + if (enable && !link->psr_settings.psr_allow_active) 2966 + return dc_link_set_psr_allow_active(link, true, false); 2967 + else if (!enable && link->psr_settings.psr_allow_active) 2968 + return dc_link_set_psr_allow_active(link, false, false); 2969 + } 2970 + } 2971 + 2972 + return true; 2973 + } 2974 + 2951 2975 #if defined(CONFIG_DRM_AMD_DC_DCN3_0) 2952 2976 2953 2977 void dc_allow_idle_optimizations(struct dc *dc, bool allow)

drivers/gpu/drm/amd/display/dc/dc.h

··· 1265 1265 void dc_lock_memory_clock_frequency(struct dc *dc); 1266 1266 1267 1267 #endif 1268 + 1269 + bool dc_set_psr_allow_active(struct dc *dc, bool enable); 1270 + 1268 1271 /******************************************************************************* 1269 1272 * DSC Interfaces 1270 1273 ******************************************************************************/

Configure Feed

Configure Feed