+31

Documentation/devicetree/bindings/mtd/nand-controller.yaml

reviewed

··· 55 55 $ref: /schemas/types.yaml#/definitions/string 56 56 enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die] 57 57 58 58 + nand-ecc-engine: 59 59 + allOf: 60 60 + - $ref: /schemas/types.yaml#/definitions/phandle 61 61 + description: | 62 62 + A phandle on the hardware ECC engine if any. There are 63 63 + basically three possibilities: 64 64 + 1/ The ECC engine is part of the NAND controller, in this 65 65 + case the phandle should reference the parent node. 66 66 + 2/ The ECC engine is part of the NAND part (on-die), in this 67 67 + case the phandle should reference the node itself. 68 68 + 3/ The ECC engine is external, in this case the phandle should 69 69 + reference the specific ECC engine node. 70 70 + 71 71 + nand-use-soft-ecc-engine: 72 72 + type: boolean 73 73 + description: Use a software ECC engine. 74 74 + 75 75 + nand-no-ecc-engine: 76 76 + type: boolean 77 77 + description: Do not use any ECC correction. 78 78 + 79 79 + nand-ecc-placement: 80 80 + allOf: 81 81 + - $ref: /schemas/types.yaml#/definitions/string 82 82 + - enum: [ oob, interleaved ] 83 83 + description: 84 84 + Location of the ECC bytes. This location is unknown by default 85 85 + but can be explicitly set to "oob", if all ECC bytes are 86 86 + known to be stored in the OOB area, or "interleaved" if ECC 87 87 + bytes will be interleaved with regular data in the main area. 88 88 + 58 89 nand-ecc-algo: 59 90 description: 60 91 Desired ECC algorithm.

+1 -1

arch/arm/mach-davinci/board-da830-evm.c

reviewed

··· 306 306 .core_chipsel = 1, 307 307 .parts = da830_evm_nand_partitions, 308 308 .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), 309 309 - .ecc_mode = NAND_ECC_HW, 309 309 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 310 310 .ecc_bits = 4, 311 311 .bbt_options = NAND_BBT_USE_FLASH, 312 312 .bbt_td = &da830_evm_nand_bbt_main_descr,

+1 -1

arch/arm/mach-davinci/board-da850-evm.c

reviewed

··· 239 239 .core_chipsel = 1, 240 240 .parts = da850_evm_nandflash_partition, 241 241 .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), 242 242 - .ecc_mode = NAND_ECC_HW, 242 242 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 243 243 .ecc_bits = 4, 244 244 .bbt_options = NAND_BBT_USE_FLASH, 245 245 .timing = &da850_evm_nandflash_timing,

+1 -1

arch/arm/mach-davinci/board-dm355-evm.c

reviewed

··· 82 82 .mask_chipsel = BIT(14), 83 83 .parts = davinci_nand_partitions, 84 84 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 85 85 - .ecc_mode = NAND_ECC_HW, 85 85 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 86 86 .bbt_options = NAND_BBT_USE_FLASH, 87 87 .ecc_bits = 4, 88 88 };

+2 -1

arch/arm/mach-davinci/board-dm355-leopard.c

reviewed

··· 76 76 .mask_chipsel = BIT(14), 77 77 .parts = davinci_nand_partitions, 78 78 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 79 79 - .ecc_mode = NAND_ECC_HW_SYNDROME, 79 79 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 80 80 + .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED, 80 81 .ecc_bits = 4, 81 82 .bbt_options = NAND_BBT_USE_FLASH, 82 83 };

+1 -1

arch/arm/mach-davinci/board-dm365-evm.c

reviewed

··· 146 146 .mask_chipsel = BIT(14), 147 147 .parts = davinci_nand_partitions, 148 148 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 149 149 - .ecc_mode = NAND_ECC_HW, 149 149 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 150 150 .bbt_options = NAND_BBT_USE_FLASH, 151 151 .ecc_bits = 4, 152 152 };

+1 -1

arch/arm/mach-davinci/board-dm644x-evm.c

reviewed

··· 162 162 .core_chipsel = 0, 163 163 .parts = davinci_evm_nandflash_partition, 164 164 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition), 165 165 - .ecc_mode = NAND_ECC_HW, 165 165 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 166 166 .ecc_bits = 1, 167 167 .bbt_options = NAND_BBT_USE_FLASH, 168 168 .timing = &davinci_evm_nandflash_timing,

+1 -1

arch/arm/mach-davinci/board-dm646x-evm.c

reviewed

··· 91 91 .mask_ale = 0x40000, 92 92 .parts = davinci_nand_partitions, 93 93 .nr_parts = ARRAY_SIZE(davinci_nand_partitions), 94 94 - .ecc_mode = NAND_ECC_HW, 94 94 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 95 95 .ecc_bits = 1, 96 96 .options = 0, 97 97 };

+1 -1

arch/arm/mach-davinci/board-mityomapl138.c

reviewed

··· 432 432 .core_chipsel = 1, 433 433 .parts = mityomapl138_nandflash_partition, 434 434 .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), 435 435 - .ecc_mode = NAND_ECC_HW, 435 435 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 436 436 .bbt_options = NAND_BBT_USE_FLASH, 437 437 .options = NAND_BUSWIDTH_16, 438 438 .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */

+1 -1

arch/arm/mach-davinci/board-neuros-osd2.c

reviewed

··· 90 90 .core_chipsel = 0, 91 91 .parts = davinci_ntosd2_nandflash_partition, 92 92 .nr_parts = ARRAY_SIZE(davinci_ntosd2_nandflash_partition), 93 93 - .ecc_mode = NAND_ECC_HW, 93 93 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 94 94 .ecc_bits = 1, 95 95 .bbt_options = NAND_BBT_USE_FLASH, 96 96 };

+1 -1

arch/arm/mach-davinci/board-omapl138-hawk.c

reviewed

··· 206 206 .core_chipsel = 1, 207 207 .parts = omapl138_hawk_nandflash_partition, 208 208 .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition), 209 209 - .ecc_mode = NAND_ECC_HW, 209 209 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 210 210 .ecc_bits = 4, 211 211 .bbt_options = NAND_BBT_USE_FLASH, 212 212 .options = NAND_BUSWIDTH_16,

+1 -1

arch/arm/mach-s3c24xx/common-smdk.c

reviewed

··· 191 191 .twrph1 = 20, 192 192 .nr_sets = ARRAY_SIZE(smdk_nand_sets), 193 193 .sets = smdk_nand_sets, 194 194 - .ecc_mode = NAND_ECC_SOFT, 194 194 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 195 195 }; 196 196 197 197 /* devices we initialise */

+1 -1

arch/arm/mach-s3c24xx/mach-anubis.c

reviewed

··· 218 218 .nr_sets = ARRAY_SIZE(anubis_nand_sets), 219 219 .sets = anubis_nand_sets, 220 220 .select_chip = anubis_nand_select, 221 221 - .ecc_mode = NAND_ECC_SOFT, 221 221 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 222 222 }; 223 223 224 224 /* IDE channels */

+1 -1

arch/arm/mach-s3c24xx/mach-at2440evb.c

reviewed

··· 109 109 .twrph1 = 40, 110 110 .nr_sets = ARRAY_SIZE(at2440evb_nand_sets), 111 111 .sets = at2440evb_nand_sets, 112 112 - .ecc_mode = NAND_ECC_SOFT, 112 112 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 113 113 }; 114 114 115 115 /* DM9000AEP 10/100 ethernet controller */

+1 -1

arch/arm/mach-s3c24xx/mach-bast.c

reviewed

··· 294 294 .nr_sets = ARRAY_SIZE(bast_nand_sets), 295 295 .sets = bast_nand_sets, 296 296 .select_chip = bast_nand_select, 297 297 - .ecc_mode = NAND_ECC_SOFT, 297 297 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 298 298 }; 299 299 300 300 /* DM9000 */

+1 -1

arch/arm/mach-s3c24xx/mach-gta02.c

reviewed

··· 417 417 .twrph1 = 15, 418 418 .nr_sets = ARRAY_SIZE(gta02_nand_sets), 419 419 .sets = gta02_nand_sets, 420 420 - .ecc_mode = NAND_ECC_SOFT, 420 420 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 421 421 }; 422 422 423 423

+1 -1

arch/arm/mach-s3c24xx/mach-jive.c

reviewed

··· 228 228 .twrph1 = 40, 229 229 .sets = jive_nand_sets, 230 230 .nr_sets = ARRAY_SIZE(jive_nand_sets), 231 231 - .ecc_mode = NAND_ECC_SOFT, 231 231 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 232 232 }; 233 233 234 234 static int __init jive_mtdset(char *options)

+1 -1

arch/arm/mach-s3c24xx/mach-mini2440.c

reviewed

··· 296 296 .nr_sets = ARRAY_SIZE(mini2440_nand_sets), 297 297 .sets = mini2440_nand_sets, 298 298 .ignore_unset_ecc = 1, 299 299 - .ecc_mode = NAND_ECC_HW, 299 299 + .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, 300 300 }; 301 301 302 302 /* DM9000AEP 10/100 ethernet controller */

+1 -1

arch/arm/mach-s3c24xx/mach-osiris.c

reviewed

··· 234 234 .nr_sets = ARRAY_SIZE(osiris_nand_sets), 235 235 .sets = osiris_nand_sets, 236 236 .select_chip = osiris_nand_select, 237 237 - .ecc_mode = NAND_ECC_SOFT, 237 237 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 238 238 }; 239 239 240 240 /* PCMCIA control and configuration */

+1 -1

arch/arm/mach-s3c24xx/mach-qt2410.c

reviewed

··· 287 287 .twrph1 = 20, 288 288 .nr_sets = ARRAY_SIZE(qt2410_nand_sets), 289 289 .sets = qt2410_nand_sets, 290 290 - .ecc_mode = NAND_ECC_SOFT, 290 290 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 291 291 }; 292 292 293 293 /* UDC */

+1 -1

arch/arm/mach-s3c24xx/mach-rx1950.c

reviewed

··· 620 620 .twrph1 = 15, 621 621 .nr_sets = ARRAY_SIZE(rx1950_nand_sets), 622 622 .sets = rx1950_nand_sets, 623 623 - .ecc_mode = NAND_ECC_SOFT, 623 623 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 624 624 }; 625 625 626 626 static struct s3c2410_udc_mach_info rx1950_udc_cfg __initdata = {

+1 -1

arch/arm/mach-s3c24xx/mach-rx3715.c

reviewed

··· 158 158 .twrph1 = 15, 159 159 .nr_sets = ARRAY_SIZE(rx3715_nand_sets), 160 160 .sets = rx3715_nand_sets, 161 161 - .ecc_mode = NAND_ECC_SOFT, 161 161 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 162 162 }; 163 163 164 164 static struct platform_device *rx3715_devices[] __initdata = {

+1 -1

arch/arm/mach-s3c24xx/mach-vstms.c

reviewed

··· 112 112 .twrph1 = 20, 113 113 .nr_sets = ARRAY_SIZE(vstms_nand_sets), 114 114 .sets = vstms_nand_sets, 115 115 - .ecc_mode = NAND_ECC_SOFT, 115 115 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 116 116 }; 117 117 118 118 static struct platform_device *vstms_devices[] __initdata = {

+1 -1

arch/arm/mach-s3c64xx/mach-hmt.c

reviewed

··· 199 199 .twrph1 = 40, 200 200 .nr_sets = ARRAY_SIZE(hmt_nand_sets), 201 201 .sets = hmt_nand_sets, 202 202 - .ecc_mode = NAND_ECC_SOFT, 202 202 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 203 203 }; 204 204 205 205 static struct gpio_led hmt_leds[] = {

+1 -1

arch/arm/mach-s3c64xx/mach-mini6410.c

reviewed

··· 136 136 .twrph1 = 40, 137 137 .nr_sets = ARRAY_SIZE(mini6410_nand_sets), 138 138 .sets = mini6410_nand_sets, 139 139 - .ecc_mode = NAND_ECC_SOFT, 139 139 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 140 140 }; 141 141 142 142 static struct s3c_fb_pd_win mini6410_lcd_type0_fb_win = {

+1 -1

arch/arm/mach-s3c64xx/mach-real6410.c

reviewed

··· 188 188 .twrph1 = 40, 189 189 .nr_sets = ARRAY_SIZE(real6410_nand_sets), 190 190 .sets = real6410_nand_sets, 191 191 - .ecc_mode = NAND_ECC_SOFT, 191 191 + .engine_type = NAND_ECC_ENGINE_TYPE_SOFT, 192 192 }; 193 193 194 194 static struct platform_device *real6410_devices[] __initdata = {

+1 -1

drivers/mtd/devices/Kconfig

reviewed

··· 91 91 92 92 config MTD_SPEAR_SMI 93 93 tristate "SPEAR MTD NOR Support through SMI controller" 94 94 - depends on PLAT_SPEAR 94 94 + depends on PLAT_SPEAR || COMPILE_TEST 95 95 default y 96 96 help 97 97 This enable SNOR support on SPEAR platforms using SMI controller

+8 -2

drivers/mtd/devices/lart.c

reviewed

··· 436 436 { 437 437 int gap = BUSWIDTH - (from & (BUSWIDTH - 1)); 438 438 439 439 - while (len && gap--) *buf++ = read8 (from++), len--; 439 439 + while (len && gap--) { 440 440 + *buf++ = read8 (from++); 441 441 + len--; 442 442 + } 440 443 } 441 444 442 445 /* now we read dwords until we reach a non-dword boundary */ ··· 521 518 i = n = 0; 522 519 523 520 while (gap--) tmp[i++] = 0xFF; 524 524 - while (len && i < BUSWIDTH) tmp[i++] = buf[n++], len--; 521 521 + while (len && i < BUSWIDTH) { 522 522 + tmp[i++] = buf[n++]; 523 523 + len--; 524 524 + } 525 525 while (i < BUSWIDTH) tmp[i++] = 0xFF; 526 526 527 527 if (!write_dword (aligned,*((__u32 *) tmp))) return (-EIO);

+2 -2

drivers/mtd/devices/spear_smi.c

reviewed

··· 793 793 struct device_node *np) 794 794 { 795 795 struct spear_smi_plat_data *pdata = dev_get_platdata(&pdev->dev); 796 796 - struct device_node *pp = NULL; 796 796 + struct device_node *pp; 797 797 const __be32 *addr; 798 798 u32 val; 799 799 int len; ··· 812 812 return -ENOMEM; 813 813 814 814 /* Fill structs for each subnode (flash device) */ 815 815 - while ((pp = of_get_next_child(np, pp))) { 815 815 + for_each_child_of_node(np, pp) { 816 816 pdata->np[i] = pp; 817 817 818 818 /* Read base-addr and size from DT */

+7

drivers/mtd/hyperbus/Kconfig

reviewed

··· 22 22 This is the driver for HyperBus controller on TI's AM65x and 23 23 other SoCs 24 24 25 25 + config RPCIF_HYPERBUS 26 26 + tristate "Renesas RPC-IF HyperBus driver" 27 27 + depends on RENESAS_RPCIF 28 28 + depends on MTD_CFI_BE_BYTE_SWAP 29 29 + help 30 30 + This option includes Renesas RPC-IF HyperBus support. 31 31 + 25 32 endif # MTD_HYPERBUS

+1

drivers/mtd/hyperbus/Makefile

reviewed

··· 2 2 3 3 obj-$(CONFIG_MTD_HYPERBUS) += hyperbus-core.o 4 4 obj-$(CONFIG_HBMC_AM654) += hbmc-am654.o 5 5 + obj-$(CONFIG_RPCIF_HYPERBUS) += rpc-if.o

+128 -16

drivers/mtd/hyperbus/hbmc-am654.c

reviewed

··· 3 3 // Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ 4 4 // Author: Vignesh Raghavendra <vigneshr@ti.com> 5 5 6 6 + #include <linux/completion.h> 7 7 + #include <linux/dma-direction.h> 8 8 + #include <linux/dma-mapping.h> 9 9 + #include <linux/dmaengine.h> 6 10 #include <linux/err.h> 7 11 #include <linux/kernel.h> 8 12 #include <linux/module.h> ··· 17 13 #include <linux/of.h> 18 14 #include <linux/of_address.h> 19 15 #include <linux/platform_device.h> 20 20 - #include <linux/pm_runtime.h> 16 16 + #include <linux/sched/task_stack.h> 21 17 #include <linux/types.h> 22 18 23 19 #define AM654_HBMC_CALIB_COUNT 25 20 20 + 21 21 + struct am654_hbmc_device_priv { 22 22 + struct completion rx_dma_complete; 23 23 + phys_addr_t device_base; 24 24 + struct hyperbus_ctlr *ctlr; 25 25 + struct dma_chan *rx_chan; 26 26 + }; 24 27 25 28 struct am654_hbmc_priv { 26 29 struct hyperbus_ctlr ctlr; ··· 63 52 return ret; 64 53 } 65 54 55 55 + static void am654_hbmc_dma_callback(void *param) 56 56 + { 57 57 + struct am654_hbmc_device_priv *priv = param; 58 58 + 59 59 + complete(&priv->rx_dma_complete); 60 60 + } 61 61 + 62 62 + static int am654_hbmc_dma_read(struct am654_hbmc_device_priv *priv, void *to, 63 63 + unsigned long from, ssize_t len) 64 64 + 65 65 + { 66 66 + enum dma_ctrl_flags flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; 67 67 + struct dma_chan *rx_chan = priv->rx_chan; 68 68 + struct dma_async_tx_descriptor *tx; 69 69 + dma_addr_t dma_dst, dma_src; 70 70 + dma_cookie_t cookie; 71 71 + int ret; 72 72 + 73 73 + if (!priv->rx_chan || !virt_addr_valid(to) || object_is_on_stack(to)) 74 74 + return -EINVAL; 75 75 + 76 76 + dma_dst = dma_map_single(rx_chan->device->dev, to, len, DMA_FROM_DEVICE); 77 77 + if (dma_mapping_error(rx_chan->device->dev, dma_dst)) { 78 78 + dev_dbg(priv->ctlr->dev, "DMA mapping failed\n"); 79 79 + return -EIO; 80 80 + } 81 81 + 82 82 + dma_src = priv->device_base + from; 83 83 + tx = dmaengine_prep_dma_memcpy(rx_chan, dma_dst, dma_src, len, flags); 84 84 + if (!tx) { 85 85 + dev_err(priv->ctlr->dev, "device_prep_dma_memcpy error\n"); 86 86 + ret = -EIO; 87 87 + goto unmap_dma; 88 88 + } 89 89 + 90 90 + reinit_completion(&priv->rx_dma_complete); 91 91 + tx->callback = am654_hbmc_dma_callback; 92 92 + tx->callback_param = priv; 93 93 + cookie = dmaengine_submit(tx); 94 94 + 95 95 + ret = dma_submit_error(cookie); 96 96 + if (ret) { 97 97 + dev_err(priv->ctlr->dev, "dma_submit_error %d\n", cookie); 98 98 + goto unmap_dma; 99 99 + } 100 100 + 101 101 + dma_async_issue_pending(rx_chan); 102 102 + if (!wait_for_completion_timeout(&priv->rx_dma_complete, msecs_to_jiffies(len + 1000))) { 103 103 + dmaengine_terminate_sync(rx_chan); 104 104 + dev_err(priv->ctlr->dev, "DMA wait_for_completion_timeout\n"); 105 105 + ret = -ETIMEDOUT; 106 106 + } 107 107 + 108 108 + unmap_dma: 109 109 + dma_unmap_single(rx_chan->device->dev, dma_dst, len, DMA_FROM_DEVICE); 110 110 + return ret; 111 111 + } 112 112 + 113 113 + static void am654_hbmc_read(struct hyperbus_device *hbdev, void *to, 114 114 + unsigned long from, ssize_t len) 115 115 + { 116 116 + struct am654_hbmc_device_priv *priv = hbdev->priv; 117 117 + 118 118 + if (len < SZ_1K || am654_hbmc_dma_read(priv, to, from, len)) 119 119 + memcpy_fromio(to, hbdev->map.virt + from, len); 120 120 + } 121 121 + 66 122 static const struct hyperbus_ops am654_hbmc_ops = { 67 123 .calibrate = am654_hbmc_calibrate, 124 124 + .copy_from = am654_hbmc_read, 68 125 }; 126 126 + 127 127 + static int am654_hbmc_request_mmap_dma(struct am654_hbmc_device_priv *priv) 128 128 + { 129 129 + struct dma_chan *rx_chan; 130 130 + dma_cap_mask_t mask; 131 131 + 132 132 + dma_cap_zero(mask); 133 133 + dma_cap_set(DMA_MEMCPY, mask); 134 134 + 135 135 + rx_chan = dma_request_chan_by_mask(&mask); 136 136 + if (IS_ERR(rx_chan)) { 137 137 + if (PTR_ERR(rx_chan) == -EPROBE_DEFER) 138 138 + return -EPROBE_DEFER; 139 139 + dev_dbg(priv->ctlr->dev, "No DMA channel available\n"); 140 140 + return 0; 141 141 + } 142 142 + priv->rx_chan = rx_chan; 143 143 + init_completion(&priv->rx_dma_complete); 144 144 + 145 145 + return 0; 146 146 + } 69 147 70 148 static int am654_hbmc_probe(struct platform_device *pdev) 71 149 { 72 150 struct device_node *np = pdev->dev.of_node; 151 151 + struct am654_hbmc_device_priv *dev_priv; 73 152 struct device *dev = &pdev->dev; 74 153 struct am654_hbmc_priv *priv; 75 154 struct resource res; ··· 171 70 172 71 platform_set_drvdata(pdev, priv); 173 72 174 174 - ret = of_address_to_resource(np, 0, &res); 73 73 + priv->hbdev.np = of_get_next_child(np, NULL); 74 74 + ret = of_address_to_resource(priv->hbdev.np, 0, &res); 175 75 if (ret) 176 76 return ret; 177 77 ··· 190 88 priv->mux_ctrl = control; 191 89 } 192 90 193 193 - pm_runtime_enable(dev); 194 194 - ret = pm_runtime_get_sync(dev); 195 195 - if (ret < 0) { 196 196 - pm_runtime_put_noidle(dev); 197 197 - goto disable_pm; 198 198 - } 199 199 - 200 91 priv->hbdev.map.size = resource_size(&res); 201 92 priv->hbdev.map.virt = devm_ioremap_resource(dev, &res); 202 93 if (IS_ERR(priv->hbdev.map.virt)) ··· 198 103 priv->ctlr.dev = dev; 199 104 priv->ctlr.ops = &am654_hbmc_ops; 200 105 priv->hbdev.ctlr = &priv->ctlr; 201 201 - priv->hbdev.np = of_get_next_child(dev->of_node, NULL); 106 106 + 107 107 + dev_priv = devm_kzalloc(dev, sizeof(*dev_priv), GFP_KERNEL); 108 108 + if (!dev_priv) { 109 109 + ret = -ENOMEM; 110 110 + goto disable_mux; 111 111 + } 112 112 + 113 113 + priv->hbdev.priv = dev_priv; 114 114 + dev_priv->device_base = res.start; 115 115 + dev_priv->ctlr = &priv->ctlr; 116 116 + 117 117 + ret = am654_hbmc_request_mmap_dma(dev_priv); 118 118 + if (ret) 119 119 + goto disable_mux; 120 120 + 202 121 ret = hyperbus_register_device(&priv->hbdev); 203 122 if (ret) { 204 123 dev_err(dev, "failed to register controller\n"); 205 205 - pm_runtime_put_sync(&pdev->dev); 206 206 - goto disable_pm; 124 124 + goto release_dma; 207 125 } 208 126 209 127 return 0; 210 210 - disable_pm: 211 211 - pm_runtime_disable(dev); 128 128 + release_dma: 129 129 + if (dev_priv->rx_chan) 130 130 + dma_release_channel(dev_priv->rx_chan); 131 131 + disable_mux: 212 132 if (priv->mux_ctrl) 213 133 mux_control_deselect(priv->mux_ctrl); 214 134 return ret; ··· 232 122 static int am654_hbmc_remove(struct platform_device *pdev) 233 123 { 234 124 struct am654_hbmc_priv *priv = platform_get_drvdata(pdev); 125 125 + struct am654_hbmc_device_priv *dev_priv = priv->hbdev.priv; 235 126 int ret; 236 127 237 128 ret = hyperbus_unregister_device(&priv->hbdev); 238 129 if (priv->mux_ctrl) 239 130 mux_control_deselect(priv->mux_ctrl); 240 240 - pm_runtime_put_sync(&pdev->dev); 241 241 - pm_runtime_disable(&pdev->dev); 131 131 + 132 132 + if (dev_priv->rx_chan) 133 133 + dma_release_channel(dev_priv->rx_chan); 242 134 243 135 return ret; 244 136 }

+170

drivers/mtd/hyperbus/rpc-if.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0 2 2 + /* 3 3 + * Linux driver for RPC-IF HyperFlash 4 4 + * 5 5 + * Copyright (C) 2019-2020 Cogent Embedded, Inc. 6 6 + */ 7 7 + 8 8 + #include <linux/err.h> 9 9 + #include <linux/kernel.h> 10 10 + #include <linux/module.h> 11 11 + #include <linux/mtd/hyperbus.h> 12 12 + #include <linux/mtd/mtd.h> 13 13 + #include <linux/mux/consumer.h> 14 14 + #include <linux/of.h> 15 15 + #include <linux/platform_device.h> 16 16 + #include <linux/types.h> 17 17 + 18 18 + #include <memory/renesas-rpc-if.h> 19 19 + 20 20 + struct rpcif_hyperbus { 21 21 + struct rpcif rpc; 22 22 + struct hyperbus_ctlr ctlr; 23 23 + struct hyperbus_device hbdev; 24 24 + }; 25 25 + 26 26 + static const struct rpcif_op rpcif_op_tmpl = { 27 27 + .cmd = { 28 28 + .buswidth = 8, 29 29 + .ddr = true, 30 30 + }, 31 31 + .ocmd = { 32 32 + .buswidth = 8, 33 33 + .ddr = true, 34 34 + }, 35 35 + .addr = { 36 36 + .nbytes = 1, 37 37 + .buswidth = 8, 38 38 + .ddr = true, 39 39 + }, 40 40 + .data = { 41 41 + .buswidth = 8, 42 42 + .ddr = true, 43 43 + }, 44 44 + }; 45 45 + 46 46 + static void rpcif_hb_prepare_read(struct rpcif *rpc, void *to, 47 47 + unsigned long from, ssize_t len) 48 48 + { 49 49 + struct rpcif_op op = rpcif_op_tmpl; 50 50 + 51 51 + op.cmd.opcode = HYPERBUS_RW_READ | HYPERBUS_AS_MEM; 52 52 + op.addr.val = from >> 1; 53 53 + op.dummy.buswidth = 1; 54 54 + op.dummy.ncycles = 15; 55 55 + op.data.dir = RPCIF_DATA_IN; 56 56 + op.data.nbytes = len; 57 57 + op.data.buf.in = to; 58 58 + 59 59 + rpcif_prepare(rpc, &op, NULL, NULL); 60 60 + } 61 61 + 62 62 + static void rpcif_hb_prepare_write(struct rpcif *rpc, unsigned long to, 63 63 + void *from, ssize_t len) 64 64 + { 65 65 + struct rpcif_op op = rpcif_op_tmpl; 66 66 + 67 67 + op.cmd.opcode = HYPERBUS_RW_WRITE | HYPERBUS_AS_MEM; 68 68 + op.addr.val = to >> 1; 69 69 + op.data.dir = RPCIF_DATA_OUT; 70 70 + op.data.nbytes = len; 71 71 + op.data.buf.out = from; 72 72 + 73 73 + rpcif_prepare(rpc, &op, NULL, NULL); 74 74 + } 75 75 + 76 76 + static u16 rpcif_hb_read16(struct hyperbus_device *hbdev, unsigned long addr) 77 77 + { 78 78 + struct rpcif_hyperbus *hyperbus = 79 79 + container_of(hbdev, struct rpcif_hyperbus, hbdev); 80 80 + map_word data; 81 81 + 82 82 + rpcif_hb_prepare_read(&hyperbus->rpc, &data, addr, 2); 83 83 + 84 84 + rpcif_manual_xfer(&hyperbus->rpc); 85 85 + 86 86 + return data.x[0]; 87 87 + } 88 88 + 89 89 + static void rpcif_hb_write16(struct hyperbus_device *hbdev, unsigned long addr, 90 90 + u16 data) 91 91 + { 92 92 + struct rpcif_hyperbus *hyperbus = 93 93 + container_of(hbdev, struct rpcif_hyperbus, hbdev); 94 94 + 95 95 + rpcif_hb_prepare_write(&hyperbus->rpc, addr, &data, 2); 96 96 + 97 97 + rpcif_manual_xfer(&hyperbus->rpc); 98 98 + } 99 99 + 100 100 + static void rpcif_hb_copy_from(struct hyperbus_device *hbdev, void *to, 101 101 + unsigned long from, ssize_t len) 102 102 + { 103 103 + struct rpcif_hyperbus *hyperbus = 104 104 + container_of(hbdev, struct rpcif_hyperbus, hbdev); 105 105 + 106 106 + rpcif_hb_prepare_read(&hyperbus->rpc, to, from, len); 107 107 + 108 108 + rpcif_dirmap_read(&hyperbus->rpc, from, len, to); 109 109 + } 110 110 + 111 111 + static const struct hyperbus_ops rpcif_hb_ops = { 112 112 + .read16 = rpcif_hb_read16, 113 113 + .write16 = rpcif_hb_write16, 114 114 + .copy_from = rpcif_hb_copy_from, 115 115 + }; 116 116 + 117 117 + static int rpcif_hb_probe(struct platform_device *pdev) 118 118 + { 119 119 + struct device *dev = &pdev->dev; 120 120 + struct rpcif_hyperbus *hyperbus; 121 121 + int error; 122 122 + 123 123 + hyperbus = devm_kzalloc(dev, sizeof(*hyperbus), GFP_KERNEL); 124 124 + if (!hyperbus) 125 125 + return -ENOMEM; 126 126 + 127 127 + rpcif_sw_init(&hyperbus->rpc, pdev->dev.parent); 128 128 + 129 129 + platform_set_drvdata(pdev, hyperbus); 130 130 + 131 131 + rpcif_enable_rpm(&hyperbus->rpc); 132 132 + 133 133 + rpcif_hw_init(&hyperbus->rpc, true); 134 134 + 135 135 + hyperbus->hbdev.map.size = hyperbus->rpc.size; 136 136 + hyperbus->hbdev.map.virt = hyperbus->rpc.dirmap; 137 137 + 138 138 + hyperbus->ctlr.dev = dev; 139 139 + hyperbus->ctlr.ops = &rpcif_hb_ops; 140 140 + hyperbus->hbdev.ctlr = &hyperbus->ctlr; 141 141 + hyperbus->hbdev.np = of_get_next_child(pdev->dev.parent->of_node, NULL); 142 142 + error = hyperbus_register_device(&hyperbus->hbdev); 143 143 + if (error) 144 144 + rpcif_disable_rpm(&hyperbus->rpc); 145 145 + 146 146 + return error; 147 147 + } 148 148 + 149 149 + static int rpcif_hb_remove(struct platform_device *pdev) 150 150 + { 151 151 + struct rpcif_hyperbus *hyperbus = platform_get_drvdata(pdev); 152 152 + int error = hyperbus_unregister_device(&hyperbus->hbdev); 153 153 + struct rpcif *rpc = dev_get_drvdata(pdev->dev.parent); 154 154 + 155 155 + rpcif_disable_rpm(rpc); 156 156 + return error; 157 157 + } 158 158 + 159 159 + static struct platform_driver rpcif_platform_driver = { 160 160 + .probe = rpcif_hb_probe, 161 161 + .remove = rpcif_hb_remove, 162 162 + .driver = { 163 163 + .name = "rpc-if-hyperflash", 164 164 + }, 165 165 + }; 166 166 + 167 167 + module_platform_driver(rpcif_platform_driver); 168 168 + 169 169 + MODULE_DESCRIPTION("Renesas RPC-IF HyperFlash driver"); 170 170 + MODULE_LICENSE("GPL v2");

+19 -16

drivers/mtd/lpddr/lpddr2_nvm.c

reviewed

··· 393 393 return lpddr2_nvm_do_block_op(mtd, start_add, len, LPDDR2_NVM_LOCK); 394 394 } 395 395 396 396 + static const struct mtd_info lpddr2_nvm_mtd_info = { 397 397 + .type = MTD_RAM, 398 398 + .writesize = 1, 399 399 + .flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK), 400 400 + ._read = lpddr2_nvm_read, 401 401 + ._write = lpddr2_nvm_write, 402 402 + ._erase = lpddr2_nvm_erase, 403 403 + ._unlock = lpddr2_nvm_unlock, 404 404 + ._lock = lpddr2_nvm_lock, 405 405 + }; 406 406 + 396 407 /* 397 408 * lpddr2_nvm driver probe method 398 409 */ ··· 444 433 .pfow_base = OW_BASE_ADDRESS, 445 434 .fldrv_priv = pcm_data, 446 435 }; 436 436 + 447 437 if (IS_ERR(map->virt)) 448 438 return PTR_ERR(map->virt); 449 439 ··· 456 444 return PTR_ERR(pcm_data->ctl_regs); 457 445 458 446 /* Populate mtd_info data structure */ 459 459 - *mtd = (struct mtd_info) { 460 460 - .dev = { .parent = &pdev->dev }, 461 461 - .name = pdev->dev.init_name, 462 462 - .type = MTD_RAM, 463 463 - .priv = map, 464 464 - .size = resource_size(add_range), 465 465 - .erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width, 466 466 - .writesize = 1, 467 467 - .writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width, 468 468 - .flags = (MTD_CAP_NVRAM | MTD_POWERUP_LOCK), 469 469 - ._read = lpddr2_nvm_read, 470 470 - ._write = lpddr2_nvm_write, 471 471 - ._erase = lpddr2_nvm_erase, 472 472 - ._unlock = lpddr2_nvm_unlock, 473 473 - ._lock = lpddr2_nvm_lock, 474 474 - }; 447 447 + *mtd = lpddr2_nvm_mtd_info; 448 448 + mtd->dev.parent = &pdev->dev; 449 449 + mtd->name = pdev->dev.init_name; 450 450 + mtd->priv = map; 451 451 + mtd->size = resource_size(add_range); 452 452 + mtd->erasesize = ERASE_BLOCKSIZE * pcm_data->bus_width; 453 453 + mtd->writebufsize = WRITE_BUFFSIZE * pcm_data->bus_width; 475 454 476 455 /* Verify the presence of the device looking for PFOW string */ 477 456 if (!lpddr2_nvm_pfow_present(map)) {

+28

drivers/mtd/lpddr/lpddr_cmds.c

reviewed

··· 94 94 } 95 95 EXPORT_SYMBOL(lpddr_cmdset); 96 96 97 97 + static void print_drs_error(unsigned int dsr) 98 98 + { 99 99 + int prog_status = (dsr & DSR_RPS) >> 8; 100 100 + 101 101 + if (!(dsr & DSR_AVAILABLE)) 102 102 + pr_notice("DSR.15: (0) Device not Available\n"); 103 103 + if ((prog_status & 0x03) == 0x03) 104 104 + pr_notice("DSR.9,8: (11) Attempt to program invalid half with 41h command\n"); 105 105 + else if (prog_status & 0x02) 106 106 + pr_notice("DSR.9,8: (10) Object Mode Program attempt in region with Control Mode data\n"); 107 107 + else if (prog_status & 0x01) 108 108 + pr_notice("DSR.9,8: (01) Program attempt in region with Object Mode data\n"); 109 109 + if (!(dsr & DSR_READY_STATUS)) 110 110 + pr_notice("DSR.7: (0) Device is Busy\n"); 111 111 + if (dsr & DSR_ESS) 112 112 + pr_notice("DSR.6: (1) Erase Suspended\n"); 113 113 + if (dsr & DSR_ERASE_STATUS) 114 114 + pr_notice("DSR.5: (1) Erase/Blank check error\n"); 115 115 + if (dsr & DSR_PROGRAM_STATUS) 116 116 + pr_notice("DSR.4: (1) Program Error\n"); 117 117 + if (dsr & DSR_VPPS) 118 118 + pr_notice("DSR.3: (1) Vpp low detect, operation aborted\n"); 119 119 + if (dsr & DSR_PSS) 120 120 + pr_notice("DSR.2: (1) Program suspended\n"); 121 121 + if (dsr & DSR_DPS) 122 122 + pr_notice("DSR.1: (1) Aborted Erase/Program attempt on locked block\n"); 123 123 + } 124 124 + 97 125 static int wait_for_ready(struct map_info *map, struct flchip *chip, 98 126 unsigned int chip_op_time) 99 127 {

+11

drivers/mtd/maps/Kconfig

reviewed

··· 75 75 physically into the CPU's memory. The mapping description here is 76 76 taken from OF device tree. 77 77 78 78 + config MTD_PHYSMAP_BT1_ROM 79 79 + bool "Baikal-T1 Boot ROMs OF-based physical memory map handling" 80 80 + depends on MTD_PHYSMAP_OF 81 81 + depends on MIPS_BAIKAL_T1 || COMPILE_TEST 82 82 + select MTD_COMPLEX_MAPPINGS 83 83 + select MULTIPLEXER 84 84 + select MUX_MMIO 85 85 + help 86 86 + This provides some extra DT physmap parsing for the Baikal-T1 87 87 + platforms, some detection and setting up ROMs-specific accessors. 88 88 + 78 89 config MTD_PHYSMAP_VERSATILE 79 90 bool "ARM Versatile OF-based physical memory map handling" 80 91 depends on MTD_PHYSMAP_OF

+1

drivers/mtd/maps/Makefile

reviewed

··· 18 18 obj-$(CONFIG_MTD_TSUNAMI) += tsunami_flash.o 19 19 obj-$(CONFIG_MTD_PXA2XX) += pxa2xx-flash.o 20 20 physmap-objs-y += physmap-core.o 21 21 + physmap-objs-$(CONFIG_MTD_PHYSMAP_BT1_ROM) += physmap-bt1-rom.o 21 22 physmap-objs-$(CONFIG_MTD_PHYSMAP_VERSATILE) += physmap-versatile.o 22 23 physmap-objs-$(CONFIG_MTD_PHYSMAP_GEMINI) += physmap-gemini.o 23 24 physmap-objs-$(CONFIG_MTD_PHYSMAP_IXP4XX) += physmap-ixp4xx.o

+126

drivers/mtd/maps/physmap-bt1-rom.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0-only 2 2 + /* 3 3 + * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC 4 4 + * 5 5 + * Authors: 6 6 + * Serge Semin <Sergey.Semin@baikalelectronics.ru> 7 7 + * 8 8 + * Baikal-T1 Physically Mapped Internal ROM driver 9 9 + */ 10 10 + #include <linux/bits.h> 11 11 + #include <linux/device.h> 12 12 + #include <linux/kernel.h> 13 13 + #include <linux/mtd/map.h> 14 14 + #include <linux/mtd/xip.h> 15 15 + #include <linux/mux/consumer.h> 16 16 + #include <linux/of.h> 17 17 + #include <linux/of_device.h> 18 18 + #include <linux/platform_device.h> 19 19 + #include <linux/string.h> 20 20 + #include <linux/types.h> 21 21 + 22 22 + #include "physmap-bt1-rom.h" 23 23 + 24 24 + /* 25 25 + * Baikal-T1 SoC ROMs are only accessible by the dword-aligned instructions. 26 26 + * We have to take this into account when implementing the data read-methods. 27 27 + * Note there is no need in bothering with endianness, since both Baikal-T1 28 28 + * CPU and MMIO are LE. 29 29 + */ 30 30 + static map_word __xipram bt1_rom_map_read(struct map_info *map, 31 31 + unsigned long ofs) 32 32 + { 33 33 + void __iomem *src = map->virt + ofs; 34 34 + unsigned long shift; 35 35 + map_word ret; 36 36 + u32 data; 37 37 + 38 38 + /* Read data within offset dword. */ 39 39 + shift = (unsigned long)src & 0x3; 40 40 + data = readl_relaxed(src - shift); 41 41 + if (!shift) { 42 42 + ret.x[0] = data; 43 43 + return ret; 44 44 + } 45 45 + ret.x[0] = data >> (shift * BITS_PER_BYTE); 46 46 + 47 47 + /* Read data from the next dword. */ 48 48 + shift = 4 - shift; 49 49 + if (ofs + shift >= map->size) 50 50 + return ret; 51 51 + 52 52 + data = readl_relaxed(src + shift); 53 53 + ret.x[0] |= data << (shift * BITS_PER_BYTE); 54 54 + 55 55 + return ret; 56 56 + } 57 57 + 58 58 + static void __xipram bt1_rom_map_copy_from(struct map_info *map, 59 59 + void *to, unsigned long from, 60 60 + ssize_t len) 61 61 + { 62 62 + void __iomem *src = map->virt + from; 63 63 + ssize_t shift, chunk; 64 64 + u32 data; 65 65 + 66 66 + if (len <= 0 || from >= map->size) 67 67 + return; 68 68 + 69 69 + /* Make sure we don't go over the map limit. */ 70 70 + len = min_t(ssize_t, map->size - from, len); 71 71 + 72 72 + /* 73 73 + * Since requested data size can be pretty big we have to implement 74 74 + * the copy procedure as optimal as possible. That's why it's split 75 75 + * up into the next three stages: unaligned head, aligned body, 76 76 + * unaligned tail. 77 77 + */ 78 78 + shift = (ssize_t)src & 0x3; 79 79 + if (shift) { 80 80 + chunk = min_t(ssize_t, 4 - shift, len); 81 81 + data = readl_relaxed(src - shift); 82 82 + memcpy(to, &data + shift, chunk); 83 83 + src += chunk; 84 84 + to += chunk; 85 85 + len -= chunk; 86 86 + } 87 87 + 88 88 + while (len >= 4) { 89 89 + data = readl_relaxed(src); 90 90 + memcpy(to, &data, 4); 91 91 + src += 4; 92 92 + to += 4; 93 93 + len -= 4; 94 94 + } 95 95 + 96 96 + if (len) { 97 97 + data = readl_relaxed(src); 98 98 + memcpy(to, &data, len); 99 99 + } 100 100 + } 101 101 + 102 102 + int of_flash_probe_bt1_rom(struct platform_device *pdev, 103 103 + struct device_node *np, 104 104 + struct map_info *map) 105 105 + { 106 106 + struct device *dev = &pdev->dev; 107 107 + 108 108 + /* It's supposed to be read-only MTD. */ 109 109 + if (!of_device_is_compatible(np, "mtd-rom")) { 110 110 + dev_info(dev, "No mtd-rom compatible string\n"); 111 111 + return 0; 112 112 + } 113 113 + 114 114 + /* Multiplatform guard. */ 115 115 + if (!of_device_is_compatible(np, "baikal,bt1-int-rom")) 116 116 + return 0; 117 117 + 118 118 + /* Sanity check the device parameters retrieved from DTB. */ 119 119 + if (map->bankwidth != 4) 120 120 + dev_warn(dev, "Bank width is supposed to be 32 bits wide\n"); 121 121 + 122 122 + map->read = bt1_rom_map_read; 123 123 + map->copy_from = bt1_rom_map_copy_from; 124 124 + 125 125 + return 0; 126 126 + }

+17

drivers/mtd/maps/physmap-bt1-rom.h

reviewed

··· 1 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 2 + #include <linux/mtd/map.h> 3 3 + #include <linux/of.h> 4 4 + 5 5 + #ifdef CONFIG_MTD_PHYSMAP_BT1_ROM 6 6 + int of_flash_probe_bt1_rom(struct platform_device *pdev, 7 7 + struct device_node *np, 8 8 + struct map_info *map); 9 9 + #else 10 10 + static inline 11 11 + int of_flash_probe_bt1_rom(struct platform_device *pdev, 12 12 + struct device_node *np, 13 13 + struct map_info *map) 14 14 + { 15 15 + return 0; 16 16 + } 17 17 + #endif

+7 -1

drivers/mtd/maps/physmap-core.c

reviewed

··· 41 41 #include <linux/pm_runtime.h> 42 42 #include <linux/gpio/consumer.h> 43 43 44 44 + #include "physmap-bt1-rom.h" 44 45 #include "physmap-gemini.h" 45 46 #include "physmap-ixp4xx.h" 46 47 #include "physmap-versatile.h" ··· 372 371 info->maps[i].bankwidth = bankwidth; 373 372 info->maps[i].device_node = dp; 374 373 374 374 + err = of_flash_probe_bt1_rom(dev, dp, &info->maps[i]); 375 375 + if (err) 376 376 + return err; 377 377 + 375 378 err = of_flash_probe_gemini(dev, dp, &info->maps[i]); 376 379 if (err) 377 380 return err; ··· 520 515 dev_notice(&dev->dev, "physmap platform flash device: %pR\n", 521 516 res); 522 517 523 523 - info->maps[i].name = dev_name(&dev->dev); 518 518 + if (!info->maps[i].name) 519 519 + info->maps[i].name = dev_name(&dev->dev); 524 520 525 521 if (!info->maps[i].phys) 526 522 info->maps[i].phys = res->start;

+3 -8

drivers/mtd/maps/vmu-flash.c

reviewed

··· 40 40 u32 blocklen; 41 41 u32 writecnt; 42 42 u32 readcnt; 43 43 - u32 removeable; 43 43 + u32 removable; 44 44 int partition; 45 45 int read; 46 46 unsigned char *blockread; ··· 619 619 card->blocklen = ((basic_flash_data >> 16 & 0xFF) + 1) << 5; 620 620 card->writecnt = basic_flash_data >> 12 & 0xF; 621 621 card->readcnt = basic_flash_data >> 8 & 0xF; 622 622 - card->removeable = basic_flash_data >> 7 & 1; 622 622 + card->removable = basic_flash_data >> 7 & 1; 623 623 624 624 card->partition = 0; 625 625 ··· 772 772 773 773 static int probe_maple_vmu(struct device *dev) 774 774 { 775 775 - int error; 776 775 struct maple_device *mdev = to_maple_dev(dev); 777 776 struct maple_driver *mdrv = to_maple_driver(dev->driver); 778 777 ··· 779 780 mdev->fileerr_handler = vmu_file_error; 780 781 mdev->driver = mdrv; 781 782 782 782 - error = vmu_connect(mdev); 783 783 - if (error) 784 784 - return error; 785 785 - 786 786 - return 0; 783 783 + return vmu_connect(mdev); 787 784 } 788 785 789 786 static int remove_maple_vmu(struct device *dev)

+43

drivers/mtd/mtdconcat.c

reviewed

··· 103 103 } 104 104 105 105 static int 106 106 + concat_panic_write(struct mtd_info *mtd, loff_t to, size_t len, 107 107 + size_t * retlen, const u_char * buf) 108 108 + { 109 109 + struct mtd_concat *concat = CONCAT(mtd); 110 110 + int err = -EINVAL; 111 111 + int i; 112 112 + for (i = 0; i < concat->num_subdev; i++) { 113 113 + struct mtd_info *subdev = concat->subdev[i]; 114 114 + size_t size, retsize; 115 115 + 116 116 + if (to >= subdev->size) { 117 117 + to -= subdev->size; 118 118 + continue; 119 119 + } 120 120 + if (to + len > subdev->size) 121 121 + size = subdev->size - to; 122 122 + else 123 123 + size = len; 124 124 + 125 125 + err = mtd_panic_write(subdev, to, size, &retsize, buf); 126 126 + if (err == -EOPNOTSUPP) { 127 127 + printk(KERN_ERR "mtdconcat: Cannot write from panic without panic_write\n"); 128 128 + return err; 129 129 + } 130 130 + if (err) 131 131 + break; 132 132 + 133 133 + *retlen += retsize; 134 134 + len -= size; 135 135 + if (len == 0) 136 136 + break; 137 137 + 138 138 + err = -EINVAL; 139 139 + buf += size; 140 140 + to = 0; 141 141 + } 142 142 + return err; 143 143 + } 144 144 + 145 145 + 146 146 + static int 106 147 concat_write(struct mtd_info *mtd, loff_t to, size_t len, 107 148 size_t * retlen, const u_char * buf) 108 149 { ··· 689 648 concat->mtd._block_isbad = concat_block_isbad; 690 649 if (subdev[0]->_block_markbad) 691 650 concat->mtd._block_markbad = concat_block_markbad; 651 651 + if (subdev[0]->_panic_write) 652 652 + concat->mtd._panic_write = concat_panic_write; 692 653 693 654 concat->mtd.ecc_stats.badblocks = subdev[0]->ecc_stats.badblocks; 694 655

+4 -24

drivers/mtd/mtdcore.c

reviewed

··· 335 335 .release = mtd_release, 336 336 }; 337 337 338 338 - static int mtd_partid_show(struct seq_file *s, void *p) 338 338 + static int mtd_partid_debug_show(struct seq_file *s, void *p) 339 339 { 340 340 struct mtd_info *mtd = s->private; 341 341 ··· 344 344 return 0; 345 345 } 346 346 347 347 - static int mtd_partid_debugfs_open(struct inode *inode, struct file *file) 348 348 - { 349 349 - return single_open(file, mtd_partid_show, inode->i_private); 350 350 - } 347 347 + DEFINE_SHOW_ATTRIBUTE(mtd_partid_debug); 351 348 352 352 - static const struct file_operations mtd_partid_debug_fops = { 353 353 - .open = mtd_partid_debugfs_open, 354 354 - .read = seq_read, 355 355 - .llseek = seq_lseek, 356 356 - .release = single_release, 357 357 - }; 358 358 - 359 359 - static int mtd_partname_show(struct seq_file *s, void *p) 349 349 + static int mtd_partname_debug_show(struct seq_file *s, void *p) 360 350 { 361 351 struct mtd_info *mtd = s->private; 362 352 ··· 355 365 return 0; 356 366 } 357 367 358 358 - static int mtd_partname_debugfs_open(struct inode *inode, struct file *file) 359 359 - { 360 360 - return single_open(file, mtd_partname_show, inode->i_private); 361 361 - } 362 362 - 363 363 - static const struct file_operations mtd_partname_debug_fops = { 364 364 - .open = mtd_partname_debugfs_open, 365 365 - .read = seq_read, 366 366 - .llseek = seq_lseek, 367 367 - .release = single_release, 368 368 - }; 368 368 + DEFINE_SHOW_ATTRIBUTE(mtd_partname_debug); 369 369 370 370 static struct dentry *dfs_dir_mtd; 371 371

+6 -5

drivers/mtd/mtdoops.c

reviewed

··· 279 279 kmsg_dump_get_buffer(dumper, true, cxt->oops_buf + MTDOOPS_HEADER_SIZE, 280 280 record_size - MTDOOPS_HEADER_SIZE, NULL); 281 281 282 282 - /* Panics must be written immediately */ 283 283 - if (reason != KMSG_DUMP_OOPS) 282 282 + if (reason != KMSG_DUMP_OOPS) { 283 283 + /* Panics must be written immediately */ 284 284 mtdoops_write(cxt, 1); 285 285 - 286 286 - /* For other cases, schedule work to write it "nicely" */ 287 287 - schedule_work(&cxt->work_write); 285 285 + } else { 286 286 + /* For other cases, schedule work to write it "nicely" */ 287 287 + schedule_work(&cxt->work_write); 288 288 + } 288 289 } 289 290 290 291 static void mtdoops_notify_add(struct mtd_info *mtd)

+8

drivers/mtd/nand/Kconfig

reviewed

··· 9 9 source "drivers/mtd/nand/raw/Kconfig" 10 10 source "drivers/mtd/nand/spi/Kconfig" 11 11 12 12 + menu "ECC engine support" 13 13 + 14 14 + config MTD_NAND_ECC 15 15 + bool 16 16 + depends on MTD_NAND_CORE 17 17 + 18 18 + endmenu 19 19 + 12 20 endmenu

+2

drivers/mtd/nand/Makefile

reviewed

··· 6 6 obj-y += onenand/ 7 7 obj-y += raw/ 8 8 obj-y += spi/ 9 9 + 10 10 + nandcore-$(CONFIG_MTD_NAND_ECC) += ecc.o

+484

drivers/mtd/nand/ecc.c

reviewed

··· 1 1 + // SPDX-License-Identifier: GPL-2.0+ 2 2 + /* 3 3 + * Generic Error-Correcting Code (ECC) engine 4 4 + * 5 5 + * Copyright (C) 2019 Macronix 6 6 + * Author: 7 7 + * Miquèl RAYNAL <miquel.raynal@bootlin.com> 8 8 + * 9 9 + * 10 10 + * This file describes the abstraction of any NAND ECC engine. It has been 11 11 + * designed to fit most cases, including parallel NANDs and SPI-NANDs. 12 12 + * 13 13 + * There are three main situations where instantiating this ECC engine makes 14 14 + * sense: 15 15 + * - external: The ECC engine is outside the NAND pipeline, typically this 16 16 + * is a software ECC engine, or an hardware engine that is 17 17 + * outside the NAND controller pipeline. 18 18 + * - pipelined: The ECC engine is inside the NAND pipeline, ie. on the 19 19 + * controller's side. This is the case of most of the raw NAND 20 20 + * controllers. In the pipeline case, the ECC bytes are 21 21 + * generated/data corrected on the fly when a page is 22 22 + * written/read. 23 23 + * - ondie: The ECC engine is inside the NAND pipeline, on the chip's side. 24 24 + * Some NAND chips can correct themselves the data. 25 25 + * 26 26 + * Besides the initial setup and final cleanups, the interfaces are rather 27 27 + * simple: 28 28 + * - prepare: Prepare an I/O request. Enable/disable the ECC engine based on 29 29 + * the I/O request type. In case of software correction or external 30 30 + * engine, this step may involve to derive the ECC bytes and place 31 31 + * them in the OOB area before a write. 32 32 + * - finish: Finish an I/O request. Correct the data in case of a read 33 33 + * request and report the number of corrected bits/uncorrectable 34 34 + * errors. Most likely empty for write operations, unless you have 35 35 + * hardware specific stuff to do, like shutting down the engine to 36 36 + * save power. 37 37 + * 38 38 + * The I/O request should be enclosed in a prepare()/finish() pair of calls 39 39 + * and will behave differently depending on the requested I/O type: 40 40 + * - raw: Correction disabled 41 41 + * - ecc: Correction enabled 42 42 + * 43 43 + * The request direction is impacting the logic as well: 44 44 + * - read: Load data from the NAND chip 45 45 + * - write: Store data in the NAND chip 46 46 + * 47 47 + * Mixing all this combinations together gives the following behavior. 48 48 + * Those are just examples, drivers are free to add custom steps in their 49 49 + * prepare/finish hook. 50 50 + * 51 51 + * [external ECC engine] 52 52 + * - external + prepare + raw + read: do nothing 53 53 + * - external + finish + raw + read: do nothing 54 54 + * - external + prepare + raw + write: do nothing 55 55 + * - external + finish + raw + write: do nothing 56 56 + * - external + prepare + ecc + read: do nothing 57 57 + * - external + finish + ecc + read: calculate expected ECC bytes, extract 58 58 + * ECC bytes from OOB buffer, correct 59 59 + * and report any bitflip/error 60 60 + * - external + prepare + ecc + write: calculate ECC bytes and store them at 61 61 + * the right place in the OOB buffer based 62 62 + * on the OOB layout 63 63 + * - external + finish + ecc + write: do nothing 64 64 + * 65 65 + * [pipelined ECC engine] 66 66 + * - pipelined + prepare + raw + read: disable the controller's ECC engine if 67 67 + * activated 68 68 + * - pipelined + finish + raw + read: do nothing 69 69 + * - pipelined + prepare + raw + write: disable the controller's ECC engine if 70 70 + * activated 71 71 + * - pipelined + finish + raw + write: do nothing 72 72 + * - pipelined + prepare + ecc + read: enable the controller's ECC engine if 73 73 + * deactivated 74 74 + * - pipelined + finish + ecc + read: check the status, report any 75 75 + * error/bitflip 76 76 + * - pipelined + prepare + ecc + write: enable the controller's ECC engine if 77 77 + * deactivated 78 78 + * - pipelined + finish + ecc + write: do nothing 79 79 + * 80 80 + * [ondie ECC engine] 81 81 + * - ondie + prepare + raw + read: send commands to disable the on-chip ECC 82 82 + * engine if activated 83 83 + * - ondie + finish + raw + read: do nothing 84 84 + * - ondie + prepare + raw + write: send commands to disable the on-chip ECC 85 85 + * engine if activated 86 86 + * - ondie + finish + raw + write: do nothing 87 87 + * - ondie + prepare + ecc + read: send commands to enable the on-chip ECC 88 88 + * engine if deactivated 89 89 + * - ondie + finish + ecc + read: send commands to check the status, report 90 90 + * any error/bitflip 91 91 + * - ondie + prepare + ecc + write: send commands to enable the on-chip ECC 92 92 + * engine if deactivated 93 93 + * - ondie + finish + ecc + write: do nothing 94 94 + */ 95 95 + 96 96 + #include <linux/module.h> 97 97 + #include <linux/mtd/nand.h> 98 98 + 99 99 + /** 100 100 + * nand_ecc_init_ctx - Init the ECC engine context 101 101 + * @nand: the NAND device 102 102 + * 103 103 + * On success, the caller is responsible of calling @nand_ecc_cleanup_ctx(). 104 104 + */ 105 105 + int nand_ecc_init_ctx(struct nand_device *nand) 106 106 + { 107 107 + if (!nand->ecc.engine->ops->init_ctx) 108 108 + return 0; 109 109 + 110 110 + return nand->ecc.engine->ops->init_ctx(nand); 111 111 + } 112 112 + EXPORT_SYMBOL(nand_ecc_init_ctx); 113 113 + 114 114 + /** 115 115 + * nand_ecc_cleanup_ctx - Cleanup the ECC engine context 116 116 + * @nand: the NAND device 117 117 + */ 118 118 + void nand_ecc_cleanup_ctx(struct nand_device *nand) 119 119 + { 120 120 + if (nand->ecc.engine->ops->cleanup_ctx) 121 121 + nand->ecc.engine->ops->cleanup_ctx(nand); 122 122 + } 123 123 + EXPORT_SYMBOL(nand_ecc_cleanup_ctx); 124 124 + 125 125 + /** 126 126 + * nand_ecc_prepare_io_req - Prepare an I/O request 127 127 + * @nand: the NAND device 128 128 + * @req: the I/O request 129 129 + */ 130 130 + int nand_ecc_prepare_io_req(struct nand_device *nand, 131 131 + struct nand_page_io_req *req) 132 132 + { 133 133 + if (!nand->ecc.engine->ops->prepare_io_req) 134 134 + return 0; 135 135 + 136 136 + return nand->ecc.engine->ops->prepare_io_req(nand, req); 137 137 + } 138 138 + EXPORT_SYMBOL(nand_ecc_prepare_io_req); 139 139 + 140 140 + /** 141 141 + * nand_ecc_finish_io_req - Finish an I/O request 142 142 + * @nand: the NAND device 143 143 + * @req: the I/O request 144 144 + */ 145 145 + int nand_ecc_finish_io_req(struct nand_device *nand, 146 146 + struct nand_page_io_req *req) 147 147 + { 148 148 + if (!nand->ecc.engine->ops->finish_io_req) 149 149 + return 0; 150 150 + 151 151 + return nand->ecc.engine->ops->finish_io_req(nand, req); 152 152 + } 153 153 + EXPORT_SYMBOL(nand_ecc_finish_io_req); 154 154 + 155 155 + /* Define default OOB placement schemes for large and small page devices */ 156 156 + static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, 157 157 + struct mtd_oob_region *oobregion) 158 158 + { 159 159 + struct nand_device *nand = mtd_to_nanddev(mtd); 160 160 + unsigned int total_ecc_bytes = nand->ecc.ctx.total; 161 161 + 162 162 + if (section > 1) 163 163 + return -ERANGE; 164 164 + 165 165 + if (!section) { 166 166 + oobregion->offset = 0; 167 167 + if (mtd->oobsize == 16) 168 168 + oobregion->length = 4; 169 169 + else 170 170 + oobregion->length = 3; 171 171 + } else { 172 172 + if (mtd->oobsize == 8) 173 173 + return -ERANGE; 174 174 + 175 175 + oobregion->offset = 6; 176 176 + oobregion->length = total_ecc_bytes - 4; 177 177 + } 178 178 + 179 179 + return 0; 180 180 + } 181 181 + 182 182 + static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, 183 183 + struct mtd_oob_region *oobregion) 184 184 + { 185 185 + if (section > 1) 186 186 + return -ERANGE; 187 187 + 188 188 + if (mtd->oobsize == 16) { 189 189 + if (section) 190 190 + return -ERANGE; 191 191 + 192 192 + oobregion->length = 8; 193 193 + oobregion->offset = 8; 194 194 + } else { 195 195 + oobregion->length = 2; 196 196 + if (!section) 197 197 + oobregion->offset = 3; 198 198 + else 199 199 + oobregion->offset = 6; 200 200 + } 201 201 + 202 202 + return 0; 203 203 + } 204 204 + 205 205 + static const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { 206 206 + .ecc = nand_ooblayout_ecc_sp, 207 207 + .free = nand_ooblayout_free_sp, 208 208 + }; 209 209 + 210 210 + const struct mtd_ooblayout_ops *nand_get_small_page_ooblayout(void) 211 211 + { 212 212 + return &nand_ooblayout_sp_ops; 213 213 + } 214 214 + EXPORT_SYMBOL_GPL(nand_get_small_page_ooblayout); 215 215 + 216 216 + static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, 217 217 + struct mtd_oob_region *oobregion) 218 218 + { 219 219 + struct nand_device *nand = mtd_to_nanddev(mtd); 220 220 + unsigned int total_ecc_bytes = nand->ecc.ctx.total; 221 221 + 222 222 + if (section || !total_ecc_bytes) 223 223 + return -ERANGE; 224 224 + 225 225 + oobregion->length = total_ecc_bytes; 226 226 + oobregion->offset = mtd->oobsize - oobregion->length; 227 227 + 228 228 + return 0; 229 229 + } 230 230 + 231 231 + static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, 232 232 + struct mtd_oob_region *oobregion) 233 233 + { 234 234 + struct nand_device *nand = mtd_to_nanddev(mtd); 235 235 + unsigned int total_ecc_bytes = nand->ecc.ctx.total; 236 236 + 237 237 + if (section) 238 238 + return -ERANGE; 239 239 + 240 240 + oobregion->length = mtd->oobsize - total_ecc_bytes - 2; 241 241 + oobregion->offset = 2; 242 242 + 243 243 + return 0; 244 244 + } 245 245 + 246 246 + static const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { 247 247 + .ecc = nand_ooblayout_ecc_lp, 248 248 + .free = nand_ooblayout_free_lp, 249 249 + }; 250 250 + 251 251 + const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void) 252 252 + { 253 253 + return &nand_ooblayout_lp_ops; 254 254 + } 255 255 + EXPORT_SYMBOL_GPL(nand_get_large_page_ooblayout); 256 256 + 257 257 + /* 258 258 + * Support the old "large page" layout used for 1-bit Hamming ECC where ECC 259 259 + * are placed at a fixed offset. 260 260 + */ 261 261 + static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section, 262 262 + struct mtd_oob_region *oobregion) 263 263 + { 264 264 + struct nand_device *nand = mtd_to_nanddev(mtd); 265 265 + unsigned int total_ecc_bytes = nand->ecc.ctx.total; 266 266 + 267 267 + if (section) 268 268 + return -ERANGE; 269 269 + 270 270 + switch (mtd->oobsize) { 271 271 + case 64: 272 272 + oobregion->offset = 40; 273 273 + break; 274 274 + case 128: 275 275 + oobregion->offset = 80; 276 276 + break; 277 277 + default: 278 278 + return -EINVAL; 279 279 + } 280 280 + 281 281 + oobregion->length = total_ecc_bytes; 282 282 + if (oobregion->offset + oobregion->length > mtd->oobsize) 283 283 + return -ERANGE; 284 284 + 285 285 + return 0; 286 286 + } 287 287 + 288 288 + static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section, 289 289 + struct mtd_oob_region *oobregion) 290 290 + { 291 291 + struct nand_device *nand = mtd_to_nanddev(mtd); 292 292 + unsigned int total_ecc_bytes = nand->ecc.ctx.total; 293 293 + int ecc_offset = 0; 294 294 + 295 295 + if (section < 0 || section > 1) 296 296 + return -ERANGE; 297 297 + 298 298 + switch (mtd->oobsize) { 299 299 + case 64: 300 300 + ecc_offset = 40; 301 301 + break; 302 302 + case 128: 303 303 + ecc_offset = 80; 304 304 + break; 305 305 + default: 306 306 + return -EINVAL; 307 307 + } 308 308 + 309 309 + if (section == 0) { 310 310 + oobregion->offset = 2; 311 311 + oobregion->length = ecc_offset - 2; 312 312 + } else { 313 313 + oobregion->offset = ecc_offset + total_ecc_bytes; 314 314 + oobregion->length = mtd->oobsize - oobregion->offset; 315 315 + } 316 316 + 317 317 + return 0; 318 318 + } 319 319 + 320 320 + static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = { 321 321 + .ecc = nand_ooblayout_ecc_lp_hamming, 322 322 + .free = nand_ooblayout_free_lp_hamming, 323 323 + }; 324 324 + 325 325 + const struct mtd_ooblayout_ops *nand_get_large_page_hamming_ooblayout(void) 326 326 + { 327 327 + return &nand_ooblayout_lp_hamming_ops; 328 328 + } 329 329 + EXPORT_SYMBOL_GPL(nand_get_large_page_hamming_ooblayout); 330 330 + 331 331 + static enum nand_ecc_engine_type 332 332 + of_get_nand_ecc_engine_type(struct device_node *np) 333 333 + { 334 334 + struct device_node *eng_np; 335 335 + 336 336 + if (of_property_read_bool(np, "nand-no-ecc-engine")) 337 337 + return NAND_ECC_ENGINE_TYPE_NONE; 338 338 + 339 339 + if (of_property_read_bool(np, "nand-use-soft-ecc-engine")) 340 340 + return NAND_ECC_ENGINE_TYPE_SOFT; 341 341 + 342 342 + eng_np = of_parse_phandle(np, "nand-ecc-engine", 0); 343 343 + of_node_put(eng_np); 344 344 + 345 345 + if (eng_np) { 346 346 + if (eng_np == np) 347 347 + return NAND_ECC_ENGINE_TYPE_ON_DIE; 348 348 + else 349 349 + return NAND_ECC_ENGINE_TYPE_ON_HOST; 350 350 + } 351 351 + 352 352 + return NAND_ECC_ENGINE_TYPE_INVALID; 353 353 + } 354 354 + 355 355 + static const char * const nand_ecc_placement[] = { 356 356 + [NAND_ECC_PLACEMENT_OOB] = "oob", 357 357 + [NAND_ECC_PLACEMENT_INTERLEAVED] = "interleaved", 358 358 + }; 359 359 + 360 360 + static enum nand_ecc_placement of_get_nand_ecc_placement(struct device_node *np) 361 361 + { 362 362 + enum nand_ecc_placement placement; 363 363 + const char *pm; 364 364 + int err; 365 365 + 366 366 + err = of_property_read_string(np, "nand-ecc-placement", &pm); 367 367 + if (!err) { 368 368 + for (placement = NAND_ECC_PLACEMENT_OOB; 369 369 + placement < ARRAY_SIZE(nand_ecc_placement); placement++) { 370 370 + if (!strcasecmp(pm, nand_ecc_placement[placement])) 371 371 + return placement; 372 372 + } 373 373 + } 374 374 + 375 375 + return NAND_ECC_PLACEMENT_UNKNOWN; 376 376 + } 377 377 + 378 378 + static const char * const nand_ecc_algos[] = { 379 379 + [NAND_ECC_ALGO_HAMMING] = "hamming", 380 380 + [NAND_ECC_ALGO_BCH] = "bch", 381 381 + [NAND_ECC_ALGO_RS] = "rs", 382 382 + }; 383 383 + 384 384 + static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np) 385 385 + { 386 386 + enum nand_ecc_algo ecc_algo; 387 387 + const char *pm; 388 388 + int err; 389 389 + 390 390 + err = of_property_read_string(np, "nand-ecc-algo", &pm); 391 391 + if (!err) { 392 392 + for (ecc_algo = NAND_ECC_ALGO_HAMMING; 393 393 + ecc_algo < ARRAY_SIZE(nand_ecc_algos); 394 394 + ecc_algo++) { 395 395 + if (!strcasecmp(pm, nand_ecc_algos[ecc_algo])) 396 396 + return ecc_algo; 397 397 + } 398 398 + } 399 399 + 400 400 + return NAND_ECC_ALGO_UNKNOWN; 401 401 + } 402 402 + 403 403 + static int of_get_nand_ecc_step_size(struct device_node *np) 404 404 + { 405 405 + int ret; 406 406 + u32 val; 407 407 + 408 408 + ret = of_property_read_u32(np, "nand-ecc-step-size", &val); 409 409 + return ret ? ret : val; 410 410 + } 411 411 + 412 412 + static int of_get_nand_ecc_strength(struct device_node *np) 413 413 + { 414 414 + int ret; 415 415 + u32 val; 416 416 + 417 417 + ret = of_property_read_u32(np, "nand-ecc-strength", &val); 418 418 + return ret ? ret : val; 419 419 + } 420 420 + 421 421 + void of_get_nand_ecc_user_config(struct nand_device *nand) 422 422 + { 423 423 + struct device_node *dn = nanddev_get_of_node(nand); 424 424 + int strength, size; 425 425 + 426 426 + nand->ecc.user_conf.engine_type = of_get_nand_ecc_engine_type(dn); 427 427 + nand->ecc.user_conf.algo = of_get_nand_ecc_algo(dn); 428 428 + nand->ecc.user_conf.placement = of_get_nand_ecc_placement(dn); 429 429 + 430 430 + strength = of_get_nand_ecc_strength(dn); 431 431 + if (strength >= 0) 432 432 + nand->ecc.user_conf.strength = strength; 433 433 + 434 434 + size = of_get_nand_ecc_step_size(dn); 435 435 + if (size >= 0) 436 436 + nand->ecc.user_conf.step_size = size; 437 437 + 438 438 + if (of_property_read_bool(dn, "nand-ecc-maximize")) 439 439 + nand->ecc.user_conf.flags |= NAND_ECC_MAXIMIZE_STRENGTH; 440 440 + } 441 441 + EXPORT_SYMBOL(of_get_nand_ecc_user_config); 442 442 + 443 443 + /** 444 444 + * nand_ecc_is_strong_enough - Check if the chip configuration meets the 445 445 + * datasheet requirements. 446 446 + * 447 447 + * @nand: Device to check 448 448 + * 449 449 + * If our configuration corrects A bits per B bytes and the minimum 450 450 + * required correction level is X bits per Y bytes, then we must ensure 451 451 + * both of the following are true: 452 452 + * 453 453 + * (1) A / B >= X / Y 454 454 + * (2) A >= X 455 455 + * 456 456 + * Requirement (1) ensures we can correct for the required bitflip density. 457 457 + * Requirement (2) ensures we can correct even when all bitflips are clumped 458 458 + * in the same sector. 459 459 + */ 460 460 + bool nand_ecc_is_strong_enough(struct nand_device *nand) 461 461 + { 462 462 + const struct nand_ecc_props *reqs = nanddev_get_ecc_requirements(nand); 463 463 + const struct nand_ecc_props *conf = nanddev_get_ecc_conf(nand); 464 464 + struct mtd_info *mtd = nanddev_to_mtd(nand); 465 465 + int corr, ds_corr; 466 466 + 467 467 + if (conf->step_size == 0 || reqs->step_size == 0) 468 468 + /* Not enough information */ 469 469 + return true; 470 470 + 471 471 + /* 472 472 + * We get the number of corrected bits per page to compare 473 473 + * the correction density. 474 474 + */ 475 475 + corr = (mtd->writesize * conf->strength) / conf->step_size; 476 476 + ds_corr = (mtd->writesize * reqs->strength) / reqs->step_size; 477 477 + 478 478 + return corr >= ds_corr && conf->strength >= reqs->strength; 479 479 + } 480 480 + EXPORT_SYMBOL(nand_ecc_is_strong_enough); 481 481 + 482 482 + MODULE_LICENSE("GPL"); 483 483 + MODULE_AUTHOR("Miquel Raynal <miquel.raynal@bootlin.com>"); 484 484 + MODULE_DESCRIPTION("Generic ECC engine");

+2 -7

drivers/mtd/nand/onenand/onenand_base.c

reviewed

··· 1052 1052 int thislen) 1053 1053 { 1054 1054 struct onenand_chip *this = mtd->priv; 1055 1055 - int ret; 1056 1055 1057 1056 this->read_bufferram(mtd, ONENAND_SPARERAM, this->oob_buf, 0, 1058 1057 mtd->oobsize); 1059 1059 - ret = mtd_ooblayout_get_databytes(mtd, buf, this->oob_buf, 1060 1060 - column, thislen); 1061 1061 - if (ret) 1062 1062 - return ret; 1063 1063 - 1064 1064 - return 0; 1058 1058 + return mtd_ooblayout_get_databytes(mtd, buf, this->oob_buf, 1059 1059 + column, thislen); 1065 1060 } 1066 1061 1067 1062 /**

+1 -4

drivers/mtd/nand/onenand/onenand_omap2.c

reviewed

··· 494 494 495 495 c->int_gpiod = devm_gpiod_get_optional(dev, "int", GPIOD_IN); 496 496 if (IS_ERR(c->int_gpiod)) { 497 497 - r = PTR_ERR(c->int_gpiod); 498 497 /* Just try again if this happens */ 499 499 - if (r != -EPROBE_DEFER) 500 500 - dev_err(dev, "error getting gpio: %d\n", r); 501 501 - return r; 498 498 + return dev_err_probe(dev, PTR_ERR(c->int_gpiod), "error getting gpio\n"); 502 499 } 503 500 504 501 if (c->int_gpiod) {

+1

drivers/mtd/nand/raw/Kconfig

reviewed

··· 13 13 menuconfig MTD_RAW_NAND 14 14 tristate "Raw/Parallel NAND Device Support" 15 15 select MTD_NAND_CORE 16 16 + select MTD_NAND_ECC 16 17 select MTD_NAND_ECC_SW_HAMMING 17 18 help 18 19 This enables support for accessing all type of raw/parallel

+4 -2

drivers/mtd/nand/raw/ams-delta.c

reviewed

··· 260 260 return err; 261 261 } 262 262 263 263 - this->ecc.mode = NAND_ECC_SOFT; 264 264 - this->ecc.algo = NAND_ECC_HAMMING; 263 263 + this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 264 264 + this->ecc.algo = NAND_ECC_ALGO_HAMMING; 265 265 266 266 platform_set_drvdata(pdev, priv); 267 267 ··· 400 400 return 0; 401 401 } 402 402 403 403 + #ifdef CONFIG_OF 403 404 static const struct of_device_id gpio_nand_of_id_table[] = { 404 405 { 405 406 /* sentinel */ 406 407 }, 407 408 }; 408 409 MODULE_DEVICE_TABLE(of, gpio_nand_of_id_table); 410 410 + #endif 409 411 410 412 static const struct platform_device_id gpio_nand_plat_id_table[] = { 411 413 {

+8 -8

drivers/mtd/nand/raw/arasan-nand-controller.c

reviewed

··· 980 980 return -EINVAL; 981 981 } 982 982 983 983 - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 983 983 + mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 984 984 985 985 ecc->steps = mtd->writesize / ecc->size; 986 986 - ecc->algo = NAND_ECC_BCH; 986 986 + ecc->algo = NAND_ECC_ALGO_BCH; 987 987 anand->ecc_bits = bch_gf_mag * ecc->strength; 988 988 ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8); 989 989 anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8); ··· 1056 1056 chip->ecc.read_page_raw = nand_monolithic_read_page_raw; 1057 1057 chip->ecc.write_page_raw = nand_monolithic_write_page_raw; 1058 1058 1059 1059 - switch (chip->ecc.mode) { 1060 1060 - case NAND_ECC_NONE: 1061 1061 - case NAND_ECC_SOFT: 1062 1062 - case NAND_ECC_ON_DIE: 1059 1059 + switch (chip->ecc.engine_type) { 1060 1060 + case NAND_ECC_ENGINE_TYPE_NONE: 1061 1061 + case NAND_ECC_ENGINE_TYPE_SOFT: 1062 1062 + case NAND_ECC_ENGINE_TYPE_ON_DIE: 1063 1063 break; 1064 1064 - case NAND_ECC_HW: 1064 1064 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 1065 1065 ret = anfc_init_hw_ecc_controller(nfc, chip); 1066 1066 break; 1067 1067 default: 1068 1068 dev_err(nfc->dev, "Unsupported ECC mode: %d\n", 1069 1069 - chip->ecc.mode); 1069 1069 + chip->ecc.engine_type); 1070 1070 return -EINVAL; 1071 1071 } 1072 1072

+288 -227

drivers/mtd/nand/raw/atmel/nand-controller.c

reviewed

··· 202 202 int (*ecc_init)(struct nand_chip *chip); 203 203 int (*setup_interface)(struct atmel_nand *nand, int csline, 204 204 const struct nand_interface_config *conf); 205 205 + int (*exec_op)(struct atmel_nand *nand, 206 206 + const struct nand_operation *op, bool check_only); 205 207 }; 206 208 207 209 struct atmel_nand_controller_caps { ··· 261 259 struct regmap *io; 262 260 struct atmel_nfc_op op; 263 261 struct completion complete; 262 262 + u32 cfg; 264 263 int irq; 265 264 266 265 /* Only used when instantiating from legacy DT bindings. */ ··· 417 414 return -EIO; 418 415 } 419 416 420 420 - static u8 atmel_nand_read_byte(struct nand_chip *chip) 421 421 - { 422 422 - struct atmel_nand *nand = to_atmel_nand(chip); 423 423 - 424 424 - return ioread8(nand->activecs->io.virt); 425 425 - } 426 426 - 427 427 - static void atmel_nand_write_byte(struct nand_chip *chip, u8 byte) 428 428 - { 429 429 - struct atmel_nand *nand = to_atmel_nand(chip); 430 430 - 431 431 - if (chip->options & NAND_BUSWIDTH_16) 432 432 - iowrite16(byte | (byte << 8), nand->activecs->io.virt); 433 433 - else 434 434 - iowrite8(byte, nand->activecs->io.virt); 435 435 - } 436 436 - 437 437 - static void atmel_nand_read_buf(struct nand_chip *chip, u8 *buf, int len) 438 438 - { 439 439 - struct atmel_nand *nand = to_atmel_nand(chip); 440 440 - struct atmel_nand_controller *nc; 441 441 - 442 442 - nc = to_nand_controller(chip->controller); 443 443 - 444 444 - /* 445 445 - * If the controller supports DMA, the buffer address is DMA-able and 446 446 - * len is long enough to make DMA transfers profitable, let's trigger 447 447 - * a DMA transfer. If it fails, fallback to PIO mode. 448 448 - */ 449 449 - if (nc->dmac && virt_addr_valid(buf) && 450 450 - len >= MIN_DMA_LEN && 451 451 - !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len, 452 452 - DMA_FROM_DEVICE)) 453 453 - return; 454 454 - 455 455 - if (chip->options & NAND_BUSWIDTH_16) 456 456 - ioread16_rep(nand->activecs->io.virt, buf, len / 2); 457 457 - else 458 458 - ioread8_rep(nand->activecs->io.virt, buf, len); 459 459 - } 460 460 - 461 461 - static void atmel_nand_write_buf(struct nand_chip *chip, const u8 *buf, int len) 462 462 - { 463 463 - struct atmel_nand *nand = to_atmel_nand(chip); 464 464 - struct atmel_nand_controller *nc; 465 465 - 466 466 - nc = to_nand_controller(chip->controller); 467 467 - 468 468 - /* 469 469 - * If the controller supports DMA, the buffer address is DMA-able and 470 470 - * len is long enough to make DMA transfers profitable, let's trigger 471 471 - * a DMA transfer. If it fails, fallback to PIO mode. 472 472 - */ 473 473 - if (nc->dmac && virt_addr_valid(buf) && 474 474 - len >= MIN_DMA_LEN && 475 475 - !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma, 476 476 - len, DMA_TO_DEVICE)) 477 477 - return; 478 478 - 479 479 - if (chip->options & NAND_BUSWIDTH_16) 480 480 - iowrite16_rep(nand->activecs->io.virt, buf, len / 2); 481 481 - else 482 482 - iowrite8_rep(nand->activecs->io.virt, buf, len); 483 483 - } 484 484 - 485 485 - static int atmel_nand_dev_ready(struct nand_chip *chip) 486 486 - { 487 487 - struct atmel_nand *nand = to_atmel_nand(chip); 488 488 - 489 489 - return gpiod_get_value(nand->activecs->rb.gpio); 490 490 - } 491 491 - 492 492 - static void atmel_nand_select_chip(struct nand_chip *chip, int cs) 493 493 - { 494 494 - struct atmel_nand *nand = to_atmel_nand(chip); 495 495 - 496 496 - if (cs < 0 || cs >= nand->numcs) { 497 497 - nand->activecs = NULL; 498 498 - chip->legacy.dev_ready = NULL; 499 499 - return; 500 500 - } 501 501 - 502 502 - nand->activecs = &nand->cs[cs]; 503 503 - 504 504 - if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB) 505 505 - chip->legacy.dev_ready = atmel_nand_dev_ready; 506 506 - } 507 507 - 508 508 - static int atmel_hsmc_nand_dev_ready(struct nand_chip *chip) 509 509 - { 510 510 - struct atmel_nand *nand = to_atmel_nand(chip); 511 511 - struct atmel_hsmc_nand_controller *nc; 512 512 - u32 status; 513 513 - 514 514 - nc = to_hsmc_nand_controller(chip->controller); 515 515 - 516 516 - regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status); 517 517 - 518 518 - return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); 519 519 - } 520 520 - 521 521 - static void atmel_hsmc_nand_select_chip(struct nand_chip *chip, int cs) 522 522 - { 523 523 - struct mtd_info *mtd = nand_to_mtd(chip); 524 524 - struct atmel_nand *nand = to_atmel_nand(chip); 525 525 - struct atmel_hsmc_nand_controller *nc; 526 526 - 527 527 - nc = to_hsmc_nand_controller(chip->controller); 528 528 - 529 529 - atmel_nand_select_chip(chip, cs); 530 530 - 531 531 - if (!nand->activecs) { 532 532 - regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, 533 533 - ATMEL_HSMC_NFC_CTRL_DIS); 534 534 - return; 535 535 - } 536 536 - 537 537 - if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB) 538 538 - chip->legacy.dev_ready = atmel_hsmc_nand_dev_ready; 539 539 - 540 540 - regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, 541 541 - ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK | 542 542 - ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK | 543 543 - ATMEL_HSMC_NFC_CFG_RSPARE | 544 544 - ATMEL_HSMC_NFC_CFG_WSPARE, 545 545 - ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | 546 546 - ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | 547 547 - ATMEL_HSMC_NFC_CFG_RSPARE); 548 548 - regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, 549 549 - ATMEL_HSMC_NFC_CTRL_EN); 550 550 - } 551 551 - 552 417 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll) 553 418 { 554 419 u8 *addrs = nc->op.addrs; ··· 467 596 return ret; 468 597 } 469 598 470 470 - static void atmel_hsmc_nand_cmd_ctrl(struct nand_chip *chip, int dat, 471 471 - unsigned int ctrl) 599 599 + static void atmel_nand_data_in(struct atmel_nand *nand, void *buf, 600 600 + unsigned int len, bool force_8bit) 601 601 + { 602 602 + struct atmel_nand_controller *nc; 603 603 + 604 604 + nc = to_nand_controller(nand->base.controller); 605 605 + 606 606 + /* 607 607 + * If the controller supports DMA, the buffer address is DMA-able and 608 608 + * len is long enough to make DMA transfers profitable, let's trigger 609 609 + * a DMA transfer. If it fails, fallback to PIO mode. 610 610 + */ 611 611 + if (nc->dmac && virt_addr_valid(buf) && 612 612 + len >= MIN_DMA_LEN && !force_8bit && 613 613 + !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len, 614 614 + DMA_FROM_DEVICE)) 615 615 + return; 616 616 + 617 617 + if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) 618 618 + ioread16_rep(nand->activecs->io.virt, buf, len / 2); 619 619 + else 620 620 + ioread8_rep(nand->activecs->io.virt, buf, len); 621 621 + } 622 622 + 623 623 + static void atmel_nand_data_out(struct atmel_nand *nand, const void *buf, 624 624 + unsigned int len, bool force_8bit) 625 625 + { 626 626 + struct atmel_nand_controller *nc; 627 627 + 628 628 + nc = to_nand_controller(nand->base.controller); 629 629 + 630 630 + /* 631 631 + * If the controller supports DMA, the buffer address is DMA-able and 632 632 + * len is long enough to make DMA transfers profitable, let's trigger 633 633 + * a DMA transfer. If it fails, fallback to PIO mode. 634 634 + */ 635 635 + if (nc->dmac && virt_addr_valid(buf) && 636 636 + len >= MIN_DMA_LEN && !force_8bit && 637 637 + !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma, 638 638 + len, DMA_TO_DEVICE)) 639 639 + return; 640 640 + 641 641 + if ((nand->base.options & NAND_BUSWIDTH_16) && !force_8bit) 642 642 + iowrite16_rep(nand->activecs->io.virt, buf, len / 2); 643 643 + else 644 644 + iowrite8_rep(nand->activecs->io.virt, buf, len); 645 645 + } 646 646 + 647 647 + static int atmel_nand_waitrdy(struct atmel_nand *nand, unsigned int timeout_ms) 648 648 + { 649 649 + if (nand->activecs->rb.type == ATMEL_NAND_NO_RB) 650 650 + return nand_soft_waitrdy(&nand->base, timeout_ms); 651 651 + 652 652 + return nand_gpio_waitrdy(&nand->base, nand->activecs->rb.gpio, 653 653 + timeout_ms); 654 654 + } 655 655 + 656 656 + static int atmel_hsmc_nand_waitrdy(struct atmel_nand *nand, 657 657 + unsigned int timeout_ms) 658 658 + { 659 659 + struct atmel_hsmc_nand_controller *nc; 660 660 + u32 status, mask; 661 661 + 662 662 + if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) 663 663 + return atmel_nand_waitrdy(nand, timeout_ms); 664 664 + 665 665 + nc = to_hsmc_nand_controller(nand->base.controller); 666 666 + mask = ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id); 667 667 + return regmap_read_poll_timeout_atomic(nc->base.smc, ATMEL_HSMC_NFC_SR, 668 668 + status, status & mask, 669 669 + 10, timeout_ms * 1000); 670 670 + } 671 671 + 672 672 + static void atmel_nand_select_target(struct atmel_nand *nand, 673 673 + unsigned int cs) 674 674 + { 675 675 + nand->activecs = &nand->cs[cs]; 676 676 + } 677 677 + 678 678 + static void atmel_hsmc_nand_select_target(struct atmel_nand *nand, 679 679 + unsigned int cs) 680 680 + { 681 681 + struct mtd_info *mtd = nand_to_mtd(&nand->base); 682 682 + struct atmel_hsmc_nand_controller *nc; 683 683 + u32 cfg = ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) | 684 684 + ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) | 685 685 + ATMEL_HSMC_NFC_CFG_RSPARE; 686 686 + 687 687 + nand->activecs = &nand->cs[cs]; 688 688 + nc = to_hsmc_nand_controller(nand->base.controller); 689 689 + if (nc->cfg == cfg) 690 690 + return; 691 691 + 692 692 + regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG, 693 693 + ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK | 694 694 + ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK | 695 695 + ATMEL_HSMC_NFC_CFG_RSPARE | 696 696 + ATMEL_HSMC_NFC_CFG_WSPARE, 697 697 + cfg); 698 698 + nc->cfg = cfg; 699 699 + } 700 700 + 701 701 + static int atmel_smc_nand_exec_instr(struct atmel_nand *nand, 702 702 + const struct nand_op_instr *instr) 703 703 + { 704 704 + struct atmel_nand_controller *nc; 705 705 + unsigned int i; 706 706 + 707 707 + nc = to_nand_controller(nand->base.controller); 708 708 + switch (instr->type) { 709 709 + case NAND_OP_CMD_INSTR: 710 710 + writeb(instr->ctx.cmd.opcode, 711 711 + nand->activecs->io.virt + nc->caps->cle_offs); 712 712 + return 0; 713 713 + case NAND_OP_ADDR_INSTR: 714 714 + for (i = 0; i < instr->ctx.addr.naddrs; i++) 715 715 + writeb(instr->ctx.addr.addrs[i], 716 716 + nand->activecs->io.virt + nc->caps->ale_offs); 717 717 + return 0; 718 718 + case NAND_OP_DATA_IN_INSTR: 719 719 + atmel_nand_data_in(nand, instr->ctx.data.buf.in, 720 720 + instr->ctx.data.len, 721 721 + instr->ctx.data.force_8bit); 722 722 + return 0; 723 723 + case NAND_OP_DATA_OUT_INSTR: 724 724 + atmel_nand_data_out(nand, instr->ctx.data.buf.out, 725 725 + instr->ctx.data.len, 726 726 + instr->ctx.data.force_8bit); 727 727 + return 0; 728 728 + case NAND_OP_WAITRDY_INSTR: 729 729 + return atmel_nand_waitrdy(nand, 730 730 + instr->ctx.waitrdy.timeout_ms); 731 731 + default: 732 732 + break; 733 733 + } 734 734 + 735 735 + return -EINVAL; 736 736 + } 737 737 + 738 738 + static int atmel_smc_nand_exec_op(struct atmel_nand *nand, 739 739 + const struct nand_operation *op, 740 740 + bool check_only) 741 741 + { 742 742 + unsigned int i; 743 743 + int ret = 0; 744 744 + 745 745 + if (check_only) 746 746 + return 0; 747 747 + 748 748 + atmel_nand_select_target(nand, op->cs); 749 749 + gpiod_set_value(nand->activecs->csgpio, 0); 750 750 + for (i = 0; i < op->ninstrs; i++) { 751 751 + ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]); 752 752 + if (ret) 753 753 + break; 754 754 + } 755 755 + gpiod_set_value(nand->activecs->csgpio, 1); 756 756 + 757 757 + return ret; 758 758 + } 759 759 + 760 760 + static int atmel_hsmc_exec_cmd_addr(struct nand_chip *chip, 761 761 + const struct nand_subop *subop) 472 762 { 473 763 struct atmel_nand *nand = to_atmel_nand(chip); 474 764 struct atmel_hsmc_nand_controller *nc; 765 765 + unsigned int i, j; 475 766 476 767 nc = to_hsmc_nand_controller(chip->controller); 477 768 478 478 - if (ctrl & NAND_ALE) { 479 479 - if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES) 480 480 - return; 769 769 + nc->op.cs = nand->activecs->id; 770 770 + for (i = 0; i < subop->ninstrs; i++) { 771 771 + const struct nand_op_instr *instr = &subop->instrs[i]; 481 772 482 482 - nc->op.addrs[nc->op.naddrs++] = dat; 483 483 - } else if (ctrl & NAND_CLE) { 484 484 - if (nc->op.ncmds > 1) 485 485 - return; 773 773 + if (instr->type == NAND_OP_CMD_INSTR) { 774 774 + nc->op.cmds[nc->op.ncmds++] = instr->ctx.cmd.opcode; 775 775 + continue; 776 776 + } 486 777 487 487 - nc->op.cmds[nc->op.ncmds++] = dat; 778 778 + for (j = nand_subop_get_addr_start_off(subop, i); 779 779 + j < nand_subop_get_num_addr_cyc(subop, i); j++) { 780 780 + nc->op.addrs[nc->op.naddrs] = instr->ctx.addr.addrs[j]; 781 781 + nc->op.naddrs++; 782 782 + } 488 783 } 489 784 490 490 - if (dat == NAND_CMD_NONE) { 491 491 - nc->op.cs = nand->activecs->id; 492 492 - atmel_nfc_exec_op(nc, true); 493 493 - } 785 785 + return atmel_nfc_exec_op(nc, true); 494 786 } 495 787 496 496 - static void atmel_nand_cmd_ctrl(struct nand_chip *chip, int cmd, 497 497 - unsigned int ctrl) 788 788 + static int atmel_hsmc_exec_rw(struct nand_chip *chip, 789 789 + const struct nand_subop *subop) 498 790 { 791 791 + const struct nand_op_instr *instr = subop->instrs; 499 792 struct atmel_nand *nand = to_atmel_nand(chip); 500 500 - struct atmel_nand_controller *nc; 501 793 502 502 - nc = to_nand_controller(chip->controller); 794 794 + if (instr->type == NAND_OP_DATA_IN_INSTR) 795 795 + atmel_nand_data_in(nand, instr->ctx.data.buf.in, 796 796 + instr->ctx.data.len, 797 797 + instr->ctx.data.force_8bit); 798 798 + else 799 799 + atmel_nand_data_out(nand, instr->ctx.data.buf.out, 800 800 + instr->ctx.data.len, 801 801 + instr->ctx.data.force_8bit); 503 802 504 504 - if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) { 505 505 - if (ctrl & NAND_NCE) 506 506 - gpiod_set_value(nand->activecs->csgpio, 0); 507 507 - else 508 508 - gpiod_set_value(nand->activecs->csgpio, 1); 509 509 - } 803 803 + return 0; 804 804 + } 510 805 511 511 - if (ctrl & NAND_ALE) 512 512 - writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs); 513 513 - else if (ctrl & NAND_CLE) 514 514 - writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs); 806 806 + static int atmel_hsmc_exec_waitrdy(struct nand_chip *chip, 807 807 + const struct nand_subop *subop) 808 808 + { 809 809 + const struct nand_op_instr *instr = subop->instrs; 810 810 + struct atmel_nand *nand = to_atmel_nand(chip); 811 811 + 812 812 + return atmel_hsmc_nand_waitrdy(nand, instr->ctx.waitrdy.timeout_ms); 813 813 + } 814 814 + 815 815 + static const struct nand_op_parser atmel_hsmc_op_parser = NAND_OP_PARSER( 816 816 + NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_cmd_addr, 817 817 + NAND_OP_PARSER_PAT_CMD_ELEM(true), 818 818 + NAND_OP_PARSER_PAT_ADDR_ELEM(true, 5), 819 819 + NAND_OP_PARSER_PAT_CMD_ELEM(true)), 820 820 + NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw, 821 821 + NAND_OP_PARSER_PAT_DATA_IN_ELEM(false, 0)), 822 822 + NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_rw, 823 823 + NAND_OP_PARSER_PAT_DATA_OUT_ELEM(false, 0)), 824 824 + NAND_OP_PARSER_PATTERN(atmel_hsmc_exec_waitrdy, 825 825 + NAND_OP_PARSER_PAT_WAITRDY_ELEM(false)), 826 826 + ); 827 827 + 828 828 + static int atmel_hsmc_nand_exec_op(struct atmel_nand *nand, 829 829 + const struct nand_operation *op, 830 830 + bool check_only) 831 831 + { 832 832 + int ret; 833 833 + 834 834 + if (check_only) 835 835 + return nand_op_parser_exec_op(&nand->base, 836 836 + &atmel_hsmc_op_parser, op, true); 837 837 + 838 838 + atmel_hsmc_nand_select_target(nand, op->cs); 839 839 + ret = nand_op_parser_exec_op(&nand->base, &atmel_hsmc_op_parser, op, 840 840 + false); 841 841 + 842 842 + return ret; 515 843 } 516 844 517 845 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf, ··· 908 838 if (ret) 909 839 return ret; 910 840 911 911 - atmel_nand_write_buf(chip, buf, mtd->writesize); 841 841 + nand_write_data_op(chip, buf, mtd->writesize, false); 912 842 913 843 ret = atmel_nand_pmecc_generate_eccbytes(chip, raw); 914 844 if (ret) { ··· 918 848 919 849 atmel_nand_pmecc_disable(chip, raw); 920 850 921 921 - atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize); 851 851 + nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 922 852 923 853 return nand_prog_page_end_op(chip); 924 854 } ··· 948 878 if (ret) 949 879 return ret; 950 880 951 951 - atmel_nand_read_buf(chip, buf, mtd->writesize); 952 952 - atmel_nand_read_buf(chip, chip->oob_poi, mtd->oobsize); 881 881 + ret = nand_read_data_op(chip, buf, mtd->writesize, false, false); 882 882 + if (ret) 883 883 + goto out_disable; 884 884 + 885 885 + ret = nand_read_data_op(chip, chip->oob_poi, mtd->oobsize, false, false); 886 886 + if (ret) 887 887 + goto out_disable; 953 888 954 889 ret = atmel_nand_pmecc_correct_data(chip, buf, raw); 955 890 891 891 + out_disable: 956 892 atmel_nand_pmecc_disable(chip, raw); 957 893 958 894 return ret; ··· 983 907 struct mtd_info *mtd = nand_to_mtd(chip); 984 908 struct atmel_nand *nand = to_atmel_nand(chip); 985 909 struct atmel_hsmc_nand_controller *nc; 986 986 - int ret, status; 910 910 + int ret; 987 911 912 912 + atmel_hsmc_nand_select_target(nand, chip->cur_cs); 988 913 nc = to_hsmc_nand_controller(chip->controller); 989 914 990 915 atmel_nfc_copy_to_sram(chip, buf, false); ··· 1016 939 if (ret) 1017 940 return ret; 1018 941 1019 1019 - atmel_nand_write_buf(chip, chip->oob_poi, mtd->oobsize); 942 942 + nand_write_data_op(chip, chip->oob_poi, mtd->oobsize, false); 1020 943 1021 1021 - nc->op.cmds[0] = NAND_CMD_PAGEPROG; 1022 1022 - nc->op.ncmds = 1; 1023 1023 - nc->op.cs = nand->activecs->id; 1024 1024 - ret = atmel_nfc_exec_op(nc, false); 1025 1025 - if (ret) 1026 1026 - dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n", 1027 1027 - ret); 1028 1028 - 1029 1029 - status = chip->legacy.waitfunc(chip); 1030 1030 - if (status & NAND_STATUS_FAIL) 1031 1031 - return -EIO; 1032 1032 - 1033 1033 - return ret; 944 944 + return nand_prog_page_end_op(chip); 1034 945 } 1035 946 1036 947 static int atmel_hsmc_nand_pmecc_write_page(struct nand_chip *chip, ··· 1046 981 struct atmel_hsmc_nand_controller *nc; 1047 982 int ret; 1048 983 984 984 + atmel_hsmc_nand_select_target(nand, chip->cur_cs); 1049 985 nc = to_hsmc_nand_controller(chip->controller); 1050 986 1051 987 /* ··· 1054 988 * connected to a native SoC R/B pin. If that's not the case, fallback 1055 989 * to the non-optimized one. 1056 990 */ 1057 1057 - if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) { 1058 1058 - nand_read_page_op(chip, page, 0, NULL, 0); 1059 1059 - 991 991 + if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) 1060 992 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, 1061 993 raw); 1062 1062 - } 1063 994 1064 995 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0; 1065 996 ··· 1106 1043 1107 1044 static int atmel_nand_pmecc_init(struct nand_chip *chip) 1108 1045 { 1046 1046 + const struct nand_ecc_props *requirements = 1047 1047 + nanddev_get_ecc_requirements(&chip->base); 1109 1048 struct mtd_info *mtd = nand_to_mtd(chip); 1049 1049 + struct nand_device *nanddev = mtd_to_nanddev(mtd); 1110 1050 struct atmel_nand *nand = to_atmel_nand(chip); 1111 1051 struct atmel_nand_controller *nc; 1112 1052 struct atmel_pmecc_user_req req; ··· 1134 1068 chip->ecc.size = val; 1135 1069 } 1136 1070 1137 1137 - if (chip->ecc.options & NAND_ECC_MAXIMIZE) 1071 1071 + if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) 1138 1072 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; 1139 1073 else if (chip->ecc.strength) 1140 1074 req.ecc.strength = chip->ecc.strength; 1141 1141 - else if (chip->base.eccreq.strength) 1142 1142 - req.ecc.strength = chip->base.eccreq.strength; 1075 1075 + else if (requirements->strength) 1076 1076 + req.ecc.strength = requirements->strength; 1143 1077 else 1144 1078 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH; 1145 1079 1146 1080 if (chip->ecc.size) 1147 1081 req.ecc.sectorsize = chip->ecc.size; 1148 1148 - else if (chip->base.eccreq.step_size) 1149 1149 - req.ecc.sectorsize = chip->base.eccreq.step_size; 1082 1082 + else if (requirements->step_size) 1083 1083 + req.ecc.sectorsize = requirements->step_size; 1150 1084 else 1151 1085 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO; 1152 1086 ··· 1165 1099 if (IS_ERR(nand->pmecc)) 1166 1100 return PTR_ERR(nand->pmecc); 1167 1101 1168 1168 - chip->ecc.algo = NAND_ECC_BCH; 1102 1102 + chip->ecc.algo = NAND_ECC_ALGO_BCH; 1169 1103 chip->ecc.size = req.ecc.sectorsize; 1170 1104 chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors; 1171 1105 chip->ecc.strength = req.ecc.strength; 1172 1106 1173 1107 chip->options |= NAND_NO_SUBPAGE_WRITE; 1174 1108 1175 1175 - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 1109 1109 + mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 1176 1110 1177 1111 return 0; 1178 1112 } ··· 1184 1118 1185 1119 nc = to_nand_controller(chip->controller); 1186 1120 1187 1187 - switch (chip->ecc.mode) { 1188 1188 - case NAND_ECC_NONE: 1189 1189 - case NAND_ECC_SOFT: 1121 1121 + switch (chip->ecc.engine_type) { 1122 1122 + case NAND_ECC_ENGINE_TYPE_NONE: 1123 1123 + case NAND_ECC_ENGINE_TYPE_SOFT: 1190 1124 /* 1191 1125 * Nothing to do, the core will initialize everything for us. 1192 1126 */ 1193 1127 break; 1194 1128 1195 1195 - case NAND_ECC_HW: 1129 1129 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 1196 1130 ret = atmel_nand_pmecc_init(chip); 1197 1131 if (ret) 1198 1132 return ret; ··· 1206 1140 default: 1207 1141 /* Other modes are not supported. */ 1208 1142 dev_err(nc->dev, "Unsupported ECC mode: %d\n", 1209 1209 - chip->ecc.mode); 1143 1143 + chip->ecc.engine_type); 1210 1144 return -ENOTSUPP; 1211 1145 } 1212 1146 ··· 1221 1155 if (ret) 1222 1156 return ret; 1223 1157 1224 1224 - if (chip->ecc.mode != NAND_ECC_HW) 1158 1158 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 1225 1159 return 0; 1226 1160 1227 1161 /* Adjust the ECC operations for the HSMC IP. */ ··· 1533 1467 return nc->caps->ops->setup_interface(nand, csline, conf); 1534 1468 } 1535 1469 1470 1470 + static int atmel_nand_exec_op(struct nand_chip *chip, 1471 1471 + const struct nand_operation *op, 1472 1472 + bool check_only) 1473 1473 + { 1474 1474 + struct atmel_nand *nand = to_atmel_nand(chip); 1475 1475 + struct atmel_nand_controller *nc; 1476 1476 + 1477 1477 + nc = to_nand_controller(nand->base.controller); 1478 1478 + 1479 1479 + return nc->caps->ops->exec_op(nand, op, check_only); 1480 1480 + } 1481 1481 + 1536 1482 static void atmel_nand_init(struct atmel_nand_controller *nc, 1537 1483 struct atmel_nand *nand) 1538 1484 { ··· 1554 1476 mtd->dev.parent = nc->dev; 1555 1477 nand->base.controller = &nc->base; 1556 1478 1557 1557 - chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl; 1558 1558 - chip->legacy.read_byte = atmel_nand_read_byte; 1559 1559 - chip->legacy.write_byte = atmel_nand_write_byte; 1560 1560 - chip->legacy.read_buf = atmel_nand_read_buf; 1561 1561 - chip->legacy.write_buf = atmel_nand_write_buf; 1562 1562 - chip->legacy.select_chip = atmel_nand_select_chip; 1563 1563 - 1564 1479 if (!nc->mck || !nc->caps->ops->setup_interface) 1565 1480 chip->options |= NAND_KEEP_TIMINGS; 1566 1566 - 1567 1567 - /* Some NANDs require a longer delay than the default one (20us). */ 1568 1568 - chip->legacy.chip_delay = 40; 1569 1481 1570 1482 /* 1571 1483 * Use a bounce buffer when the buffer passed by the MTD user is not ··· 1566 1498 1567 1499 /* Default to HW ECC if pmecc is available. */ 1568 1500 if (nc->pmecc) 1569 1569 - chip->ecc.mode = NAND_ECC_HW; 1501 1501 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1570 1502 } 1571 1503 1572 1504 static void atmel_smc_nand_init(struct atmel_nand_controller *nc, ··· 1593 1525 smc_nc->ebi_csa->offs, 1594 1526 smc_nc->ebi_csa->nfd0_on_d16, 1595 1527 smc_nc->ebi_csa->nfd0_on_d16); 1596 1596 - } 1597 1597 - 1598 1598 - static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc, 1599 1599 - struct atmel_nand *nand) 1600 1600 - { 1601 1601 - struct nand_chip *chip = &nand->base; 1602 1602 - 1603 1603 - atmel_nand_init(nc, nand); 1604 1604 - 1605 1605 - /* Overload some methods for the HSMC controller. */ 1606 1606 - chip->legacy.cmd_ctrl = atmel_hsmc_nand_cmd_ctrl; 1607 1607 - chip->legacy.select_chip = atmel_hsmc_nand_select_chip; 1608 1528 } 1609 1529 1610 1530 static int atmel_nand_controller_remove_nand(struct atmel_nand *nand) ··· 2013 1957 static const struct nand_controller_ops atmel_nand_controller_ops = { 2014 1958 .attach_chip = atmel_nand_attach_chip, 2015 1959 .setup_interface = atmel_nand_setup_interface, 1960 1960 + .exec_op = atmel_nand_exec_op, 2016 1961 }; 2017 1962 2018 1963 static int atmel_nand_controller_init(struct atmel_nand_controller *nc, ··· 2033 1976 platform_set_drvdata(pdev, nc); 2034 1977 2035 1978 nc->pmecc = devm_atmel_pmecc_get(dev); 2036 2036 - if (IS_ERR(nc->pmecc)) { 2037 2037 - ret = PTR_ERR(nc->pmecc); 2038 2038 - if (ret != -EPROBE_DEFER) 2039 2039 - dev_err(dev, "Could not get PMECC object (err = %d)\n", 2040 2040 - ret); 2041 2041 - return ret; 2042 2042 - } 1979 1979 + if (IS_ERR(nc->pmecc)) 1980 1980 + return dev_err_probe(dev, PTR_ERR(nc->pmecc), 1981 1981 + "Could not get PMECC object\n"); 2043 1982 2044 1983 if (nc->caps->has_dma && !atmel_nand_avoid_dma) { 2045 1984 dma_cap_mask_t mask; ··· 2301 2248 return ret; 2302 2249 2303 2250 hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base); 2251 2251 + regmap_write(hsmc_nc->base.smc, ATMEL_HSMC_NFC_CTRL, 2252 2252 + ATMEL_HSMC_NFC_CTRL_DIS); 2253 2253 + 2304 2254 if (hsmc_nc->sram.pool) 2305 2255 gen_pool_free(hsmc_nc->sram.pool, 2306 2256 (unsigned long)hsmc_nc->sram.virt, ··· 2356 2300 /* Initial NFC configuration. */ 2357 2301 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG, 2358 2302 ATMEL_HSMC_NFC_CFG_DTO_MAX); 2303 2303 + regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL, 2304 2304 + ATMEL_HSMC_NFC_CTRL_EN); 2359 2305 2360 2306 ret = atmel_nand_controller_add_nands(&nc->base); 2361 2307 if (ret) ··· 2375 2317 .probe = atmel_hsmc_nand_controller_probe, 2376 2318 .remove = atmel_hsmc_nand_controller_remove, 2377 2319 .ecc_init = atmel_hsmc_nand_ecc_init, 2378 2378 - .nand_init = atmel_hsmc_nand_init, 2320 2320 + .nand_init = atmel_nand_init, 2379 2321 .setup_interface = atmel_hsmc_nand_setup_interface, 2322 2322 + .exec_op = atmel_hsmc_nand_exec_op, 2380 2323 }; 2381 2324 2382 2325 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = { ··· 2444 2385 .remove = atmel_smc_nand_controller_remove, 2445 2386 .ecc_init = atmel_nand_ecc_init, 2446 2387 .nand_init = atmel_smc_nand_init, 2388 2388 + .exec_op = atmel_smc_nand_exec_op, 2447 2389 }; 2448 2390 2449 2391 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = { ··· 2460 2400 .ecc_init = atmel_nand_ecc_init, 2461 2401 .nand_init = atmel_smc_nand_init, 2462 2402 .setup_interface = atmel_smc_nand_setup_interface, 2403 2403 + .exec_op = atmel_smc_nand_exec_op, 2463 2404 }; 2464 2405 2465 2406 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {

+2 -2

drivers/mtd/nand/raw/au1550nd.c

reviewed

··· 294 294 nand_controller_init(&ctx->controller); 295 295 ctx->controller.ops = &au1550nd_ops; 296 296 this->controller = &ctx->controller; 297 297 - this->ecc.mode = NAND_ECC_SOFT; 298 298 - this->ecc.algo = NAND_ECC_HAMMING; 297 297 + this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 298 298 + this->ecc.algo = NAND_ECC_ALGO_HAMMING; 299 299 300 300 if (pd->devwidth) 301 301 this->options |= NAND_BUSWIDTH_16;

+2 -1

drivers/mtd/nand/raw/bcm47xxnflash/ops_bcm4706.c

reviewed

··· 391 391 392 392 nand_chip->legacy.chip_delay = 50; 393 393 b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH; 394 394 - b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */ 394 394 + /* TODO: implement ECC */ 395 395 + b47n->nand_chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_NONE; 395 396 396 397 /* Enable NAND flash access */ 397 398 bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG,

+15 -13

drivers/mtd/nand/raw/brcmnand/brcmnand.c

reviewed

··· 2532 2532 { 2533 2533 struct mtd_info *mtd = nand_to_mtd(&host->chip); 2534 2534 struct nand_chip *chip = &host->chip; 2535 2535 + const struct nand_ecc_props *requirements = 2536 2536 + nanddev_get_ecc_requirements(&chip->base); 2535 2537 struct brcmnand_controller *ctrl = host->ctrl; 2536 2538 struct brcmnand_cfg *cfg = &host->hwcfg; 2537 2539 char msg[128]; ··· 2567 2565 cfg->col_adr_bytes = 2; 2568 2566 cfg->blk_adr_bytes = get_blk_adr_bytes(mtd->size, mtd->writesize); 2569 2567 2570 2570 - if (chip->ecc.mode != NAND_ECC_HW) { 2568 2568 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { 2571 2569 dev_err(ctrl->dev, "only HW ECC supported; selected: %d\n", 2572 2572 - chip->ecc.mode); 2570 2570 + chip->ecc.engine_type); 2573 2571 return -EINVAL; 2574 2572 } 2575 2573 2576 2576 - if (chip->ecc.algo == NAND_ECC_UNKNOWN) { 2574 2574 + if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { 2577 2575 if (chip->ecc.strength == 1 && chip->ecc.size == 512) 2578 2576 /* Default to Hamming for 1-bit ECC, if unspecified */ 2579 2579 - chip->ecc.algo = NAND_ECC_HAMMING; 2577 2577 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2580 2578 else 2581 2579 /* Otherwise, BCH */ 2582 2582 - chip->ecc.algo = NAND_ECC_BCH; 2580 2580 + chip->ecc.algo = NAND_ECC_ALGO_BCH; 2583 2581 } 2584 2582 2585 2585 - if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 || 2586 2586 - chip->ecc.size != 512)) { 2583 2583 + if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING && 2584 2584 + (chip->ecc.strength != 1 || chip->ecc.size != 512)) { 2587 2585 dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n", 2588 2586 chip->ecc.strength, chip->ecc.size); 2589 2587 return -EINVAL; 2590 2588 } 2591 2589 2592 2592 - if (chip->ecc.mode != NAND_ECC_NONE && 2590 2590 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2593 2591 (!chip->ecc.size || !chip->ecc.strength)) { 2594 2594 - if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { 2592 2592 + if (requirements->step_size && requirements->strength) { 2595 2593 /* use detected ECC parameters */ 2596 2596 - chip->ecc.size = chip->base.eccreq.step_size; 2597 2597 - chip->ecc.strength = chip->base.eccreq.strength; 2594 2594 + chip->ecc.size = requirements->step_size; 2595 2595 + chip->ecc.strength = requirements->strength; 2598 2596 dev_info(ctrl->dev, "Using ECC step-size %d, strength %d\n", 2599 2597 chip->ecc.size, chip->ecc.strength); 2600 2598 } ··· 2602 2600 2603 2601 switch (chip->ecc.size) { 2604 2602 case 512: 2605 2605 - if (chip->ecc.algo == NAND_ECC_HAMMING) 2603 2603 + if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) 2606 2604 cfg->ecc_level = 15; 2607 2605 else 2608 2606 cfg->ecc_level = chip->ecc.strength; ··· 2730 2728 chip->legacy.read_buf = brcmnand_read_buf; 2731 2729 chip->legacy.write_buf = brcmnand_write_buf; 2732 2730 2733 2733 - chip->ecc.mode = NAND_ECC_HW; 2731 2731 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2734 2732 chip->ecc.read_page = brcmnand_read_page; 2735 2733 chip->ecc.write_page = brcmnand_write_page; 2736 2734 chip->ecc.read_page_raw = brcmnand_read_page_raw;

+4 -8

drivers/mtd/nand/raw/cadence-nand-controller.c

reviewed

··· 2611 2611 2612 2612 chip->bbt_options |= NAND_BBT_USE_FLASH; 2613 2613 chip->bbt_options |= NAND_BBT_NO_OOB; 2614 2614 - chip->ecc.mode = NAND_ECC_HW; 2614 2614 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2615 2615 2616 2616 chip->options |= NAND_NO_SUBPAGE_WRITE; 2617 2617 ··· 2757 2757 * Default to HW ECC engine mode. If the nand-ecc-mode property is given 2758 2758 * in the DT node, this entry will be overwritten in nand_scan_ident(). 2759 2759 */ 2760 2760 - chip->ecc.mode = NAND_ECC_HW; 2760 2760 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2761 2761 2762 2762 ret = nand_scan(chip, cdns_chip->nsels); 2763 2763 if (ret) { ··· 2980 2980 dev_info(cdns_ctrl->dev, "IRQ: nr %d\n", cdns_ctrl->irq); 2981 2981 2982 2982 cdns_ctrl->reg = devm_platform_ioremap_resource(ofdev, 0); 2983 2983 - if (IS_ERR(cdns_ctrl->reg)) { 2984 2984 - dev_err(&ofdev->dev, "devm_ioremap_resource res 0 failed\n"); 2983 2983 + if (IS_ERR(cdns_ctrl->reg)) 2985 2984 return PTR_ERR(cdns_ctrl->reg); 2986 2986 - } 2987 2985 2988 2986 res = platform_get_resource(ofdev, IORESOURCE_MEM, 1); 2989 2987 cdns_ctrl->io.dma = res->start; 2990 2988 cdns_ctrl->io.virt = devm_ioremap_resource(&ofdev->dev, res); 2991 2991 - if (IS_ERR(cdns_ctrl->io.virt)) { 2992 2992 - dev_err(cdns_ctrl->dev, "devm_ioremap_resource res 1 failed\n"); 2989 2989 + if (IS_ERR(cdns_ctrl->io.virt)) 2993 2990 return PTR_ERR(cdns_ctrl->io.virt); 2994 2994 - } 2995 2991 2996 2992 dt->clk = devm_clk_get(cdns_ctrl->dev, "nf_clk"); 2997 2993 if (IS_ERR(dt->clk))

+2 -1

drivers/mtd/nand/raw/cafe_nand.c

reviewed

··· 629 629 goto out_free_dma; 630 630 } 631 631 632 632 - cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME; 632 632 + cafe->nand.ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 633 633 + cafe->nand.ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 633 634 cafe->nand.ecc.size = mtd->writesize; 634 635 cafe->nand.ecc.bytes = 14; 635 636 cafe->nand.ecc.strength = 4;

+1 -1

drivers/mtd/nand/raw/cs553x_nand.c

reviewed

··· 286 286 goto out_mtd; 287 287 } 288 288 289 289 - this->ecc.mode = NAND_ECC_HW; 289 289 + this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 290 290 this->ecc.size = 256; 291 291 this->ecc.bytes = 3; 292 292 this->ecc.hwctl = cs_enable_hwecc;

+20 -18

drivers/mtd/nand/raw/davinci_nand.c

reviewed

··· 168 168 /* 169 169 * 4-bit hardware ECC ... context maintained over entire AEMIF 170 170 * 171 171 - * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME 171 171 + * This is a syndrome engine, but we avoid NAND_ECC_PLACEMENT_INTERLEAVED 172 172 * since that forces use of a problematic "infix OOB" layout. 173 173 * Among other things, it trashes manufacturer bad block markers. 174 174 * Also, and specific to this hardware, it ECC-protects the "prepad" ··· 530 530 if (!of_property_read_string(pdev->dev.of_node, 531 531 "ti,davinci-ecc-mode", &mode)) { 532 532 if (!strncmp("none", mode, 4)) 533 533 - pdata->ecc_mode = NAND_ECC_NONE; 533 533 + pdata->engine_type = NAND_ECC_ENGINE_TYPE_NONE; 534 534 if (!strncmp("soft", mode, 4)) 535 535 - pdata->ecc_mode = NAND_ECC_SOFT; 535 535 + pdata->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 536 536 if (!strncmp("hw", mode, 2)) 537 537 - pdata->ecc_mode = NAND_ECC_HW; 537 537 + pdata->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 538 538 } 539 539 if (!of_property_read_u32(pdev->dev.of_node, 540 540 "ti,davinci-ecc-bits", &prop)) ··· 585 585 if (IS_ERR(pdata)) 586 586 return PTR_ERR(pdata); 587 587 588 588 - switch (info->chip.ecc.mode) { 589 589 - case NAND_ECC_NONE: 588 588 + switch (info->chip.ecc.engine_type) { 589 589 + case NAND_ECC_ENGINE_TYPE_NONE: 590 590 pdata->ecc_bits = 0; 591 591 break; 592 592 - case NAND_ECC_SOFT: 592 592 + case NAND_ECC_ENGINE_TYPE_SOFT: 593 593 pdata->ecc_bits = 0; 594 594 /* 595 595 - * This driver expects Hamming based ECC when ecc_mode is set 596 596 - * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to 597 597 - * avoid adding an extra ->ecc_algo field to 598 598 - * davinci_nand_pdata. 595 595 + * This driver expects Hamming based ECC when engine_type is set 596 596 + * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to 597 597 + * NAND_ECC_ALGO_HAMMING to avoid adding an extra ->ecc_algo 598 598 + * field to davinci_nand_pdata. 599 599 */ 600 600 - info->chip.ecc.algo = NAND_ECC_HAMMING; 600 600 + info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 601 601 break; 602 602 - case NAND_ECC_HW: 602 602 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 603 603 if (pdata->ecc_bits == 4) { 604 604 int chunks = mtd->writesize / 512; 605 605 ··· 629 629 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit; 630 630 info->chip.ecc.bytes = 10; 631 631 info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK; 632 632 - info->chip.ecc.algo = NAND_ECC_BCH; 632 632 + info->chip.ecc.algo = NAND_ECC_ALGO_BCH; 633 633 634 634 /* 635 635 * Update ECC layout if needed ... for 1-bit HW ECC, the ··· 645 645 mtd_set_ooblayout(mtd, 646 646 &hwecc4_small_ooblayout_ops); 647 647 } else if (chunks == 4 || chunks == 8) { 648 648 - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 648 648 + mtd_set_ooblayout(mtd, 649 649 + nand_get_large_page_ooblayout()); 649 650 info->chip.ecc.read_page = nand_davinci_read_page_hwecc_oob_first; 650 651 } else { 651 652 return -EIO; ··· 657 656 info->chip.ecc.correct = nand_davinci_correct_1bit; 658 657 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit; 659 658 info->chip.ecc.bytes = 3; 660 660 - info->chip.ecc.algo = NAND_ECC_HAMMING; 659 659 + info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 661 660 } 662 661 info->chip.ecc.size = 512; 663 662 info->chip.ecc.strength = pdata->ecc_bits; ··· 851 850 info->mask_cle = pdata->mask_cle ? : MASK_CLE; 852 851 853 852 /* Use board-specific ECC config */ 854 854 - info->chip.ecc.mode = pdata->ecc_mode; 853 853 + info->chip.ecc.engine_type = pdata->engine_type; 854 854 + info->chip.ecc.placement = pdata->ecc_placement; 855 855 856 856 spin_lock_irq(&davinci_nand_lock); 857 857 ··· 899 897 int ret; 900 898 901 899 spin_lock_irq(&davinci_nand_lock); 902 902 - if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) 900 900 + if (info->chip.ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED) 903 901 ecc4_busy = false; 904 902 spin_unlock_irq(&davinci_nand_lock); 905 903

+2 -1

drivers/mtd/nand/raw/denali.c

reviewed

··· 1237 1237 chip->bbt_options |= NAND_BBT_USE_FLASH; 1238 1238 chip->bbt_options |= NAND_BBT_NO_OOB; 1239 1239 chip->options |= NAND_NO_SUBPAGE_WRITE; 1240 1240 - chip->ecc.mode = NAND_ECC_HW_SYNDROME; 1240 1240 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1241 1241 + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 1241 1242 chip->ecc.read_page = denali_read_page; 1242 1243 chip->ecc.write_page = denali_write_page; 1243 1244 chip->ecc.read_page_raw = denali_read_page_raw;

+1 -1

drivers/mtd/nand/raw/denali_pci.c

reviewed

··· 100 100 goto out_remove_denali; 101 101 } 102 102 103 103 - dchip->chip.ecc.options |= NAND_ECC_MAXIMIZE; 103 103 + dchip->chip.base.ecc.user_conf.flags |= NAND_ECC_MAXIMIZE_STRENGTH; 104 104 105 105 dchip->nsels = nsels; 106 106

+2 -1

drivers/mtd/nand/raw/diskonchip.c

reviewed

··· 1456 1456 nand->ecc.calculate = doc200x_calculate_ecc; 1457 1457 nand->ecc.correct = doc200x_correct_data; 1458 1458 1459 1459 - nand->ecc.mode = NAND_ECC_HW_SYNDROME; 1459 1459 + nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1460 1460 + nand->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 1460 1461 nand->ecc.size = 512; 1461 1462 nand->ecc.bytes = 6; 1462 1463 nand->ecc.strength = 2;

+10 -10

drivers/mtd/nand/raw/fsl_elbc_nand.c

reviewed

··· 244 244 return -EIO; 245 245 } 246 246 247 247 - if (chip->ecc.mode != NAND_ECC_HW) 247 247 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 248 248 return 0; 249 249 250 250 elbc_fcm_ctrl->max_bitflips = 0; ··· 727 727 struct fsl_lbc_regs __iomem *lbc = ctrl->regs; 728 728 unsigned int al; 729 729 730 730 - switch (chip->ecc.mode) { 730 730 + switch (chip->ecc.engine_type) { 731 731 /* 732 732 * if ECC was not chosen in DT, decide whether to use HW or SW ECC from 733 733 * CS Base Register 734 734 */ 735 735 - case NAND_ECC_NONE: 735 735 + case NAND_ECC_ENGINE_TYPE_NONE: 736 736 /* If CS Base Register selects full hardware ECC then use it */ 737 737 if ((in_be32(&lbc->bank[priv->bank].br) & BR_DECC) == 738 738 BR_DECC_CHK_GEN) { ··· 740 740 chip->ecc.write_page = fsl_elbc_write_page; 741 741 chip->ecc.write_subpage = fsl_elbc_write_subpage; 742 742 743 743 - chip->ecc.mode = NAND_ECC_HW; 743 743 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 744 744 mtd_set_ooblayout(mtd, &fsl_elbc_ooblayout_ops); 745 745 chip->ecc.size = 512; 746 746 chip->ecc.bytes = 3; 747 747 chip->ecc.strength = 1; 748 748 } else { 749 749 /* otherwise fall back to default software ECC */ 750 750 - chip->ecc.mode = NAND_ECC_SOFT; 751 751 - chip->ecc.algo = NAND_ECC_HAMMING; 750 750 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 751 751 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 752 752 } 753 753 break; 754 754 755 755 /* if SW ECC was chosen in DT, we do not need to set anything here */ 756 756 - case NAND_ECC_SOFT: 756 756 + case NAND_ECC_ENGINE_TYPE_SOFT: 757 757 break; 758 758 759 759 - /* should we also implement NAND_ECC_HW to do as the code above? */ 759 759 + /* should we also implement *_ECC_ENGINE_CONTROLLER to do as above? */ 760 760 default: 761 761 return -EINVAL; 762 762 } ··· 786 786 chip->page_shift); 787 787 dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", 788 788 chip->phys_erase_shift); 789 789 - dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", 790 790 - chip->ecc.mode); 789 789 + dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.engine_type = %d\n", 790 790 + chip->ecc.engine_type); 791 791 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", 792 792 chip->ecc.steps); 793 793 dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n",

+6 -6

drivers/mtd/nand/raw/fsl_ifc_nand.c

reviewed

··· 309 309 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize; 310 310 ifc_nand_ctrl->index += column; 311 311 312 312 - if (chip->ecc.mode == NAND_ECC_HW) 312 312 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 313 313 ifc_nand_ctrl->eccread = 1; 314 314 315 315 fsl_ifc_do_read(chip, 0, mtd); ··· 724 724 chip->page_shift); 725 725 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__, 726 726 chip->phys_erase_shift); 727 727 - dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__, 728 728 - chip->ecc.mode); 727 727 + dev_dbg(priv->dev, "%s: nand->ecc.engine_type = %d\n", __func__, 728 728 + chip->ecc.engine_type); 729 729 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__, 730 730 chip->ecc.steps); 731 731 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__, ··· 912 912 913 913 /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */ 914 914 if (csor & CSOR_NAND_ECC_DEC_EN) { 915 915 - chip->ecc.mode = NAND_ECC_HW; 915 915 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 916 916 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops); 917 917 918 918 /* Hardware generates ECC per 512 Bytes */ ··· 925 925 chip->ecc.strength = 8; 926 926 } 927 927 } else { 928 928 - chip->ecc.mode = NAND_ECC_SOFT; 929 929 - chip->ecc.algo = NAND_ECC_HAMMING; 928 928 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 929 929 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 930 930 } 931 931 932 932 ret = fsl_ifc_sram_init(priv);

+2 -2

drivers/mtd/nand/raw/fsl_upm.c

reviewed

··· 47 47 int ret; 48 48 struct device_node *flash_np; 49 49 50 50 - fun->chip.ecc.mode = NAND_ECC_SOFT; 51 51 - fun->chip.ecc.algo = NAND_ECC_HAMMING; 50 50 + fun->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 51 51 + fun->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 52 52 fun->chip.controller = &fun->base; 53 53 mtd->dev.parent = fun->dev; 54 54

+7 -7

drivers/mtd/nand/raw/fsmc_nand.c

reviewed

··· 900 900 return 0; 901 901 } 902 902 903 903 - switch (nand->ecc.mode) { 904 904 - case NAND_ECC_HW: 903 903 + switch (nand->ecc.engine_type) { 904 904 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 905 905 dev_info(host->dev, "Using 1-bit HW ECC scheme\n"); 906 906 nand->ecc.calculate = fsmc_read_hwecc_ecc1; 907 907 nand->ecc.correct = nand_correct_data; ··· 910 910 nand->ecc.options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; 911 911 break; 912 912 913 913 - case NAND_ECC_SOFT: 914 914 - if (nand->ecc.algo == NAND_ECC_BCH) { 913 913 + case NAND_ECC_ENGINE_TYPE_SOFT: 914 914 + if (nand->ecc.algo == NAND_ECC_ALGO_BCH) { 915 915 dev_info(host->dev, 916 916 "Using 4-bit SW BCH ECC scheme\n"); 917 917 break; 918 918 } 919 919 920 920 - case NAND_ECC_ON_DIE: 920 920 + case NAND_ECC_ENGINE_TYPE_ON_DIE: 921 921 break; 922 922 923 923 default: ··· 929 929 * Don't set layout for BCH4 SW ECC. This will be 930 930 * generated later in nand_bch_init() later. 931 931 */ 932 932 - if (nand->ecc.mode == NAND_ECC_HW) { 932 932 + if (nand->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 933 933 switch (mtd->oobsize) { 934 934 case 16: 935 935 case 64: ··· 1059 1059 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() 1060 1060 * can overwrite this value if the DT provides a different value. 1061 1061 */ 1062 1062 - nand->ecc.mode = NAND_ECC_HW; 1062 1062 + nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1063 1063 nand->ecc.hwctl = fsmc_enable_hwecc; 1064 1064 nand->ecc.size = 512; 1065 1065 nand->badblockbits = 7;

+2 -2

drivers/mtd/nand/raw/gpio.c

reviewed

··· 342 342 gpiomtd->base.ops = &gpio_nand_ops; 343 343 344 344 nand_set_flash_node(chip, pdev->dev.of_node); 345 345 - chip->ecc.mode = NAND_ECC_SOFT; 346 346 - chip->ecc.algo = NAND_ECC_HAMMING; 345 345 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 346 346 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 347 347 chip->options = gpiomtd->plat.options; 348 348 chip->controller = &gpiomtd->base; 349 349

+10 -11

drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c

reviewed

··· 272 272 default: 273 273 dev_err(this->dev, 274 274 "unsupported nand chip. ecc bits : %d, ecc size : %d\n", 275 275 - chip->base.eccreq.strength, 276 276 - chip->base.eccreq.step_size); 275 275 + nanddev_get_ecc_requirements(&chip->base)->strength, 276 276 + nanddev_get_ecc_requirements(&chip->base)->step_size); 277 277 return -EINVAL; 278 278 } 279 279 geo->ecc_chunk_size = ecc_step; ··· 510 510 static int common_nfc_set_geometry(struct gpmi_nand_data *this) 511 511 { 512 512 struct nand_chip *chip = &this->nand; 513 513 + const struct nand_ecc_props *requirements = 514 514 + nanddev_get_ecc_requirements(&chip->base); 513 515 514 516 if (chip->ecc.strength > 0 && chip->ecc.size > 0) 515 517 return set_geometry_by_ecc_info(this, chip->ecc.strength, ··· 519 517 520 518 if ((of_property_read_bool(this->dev->of_node, "fsl,use-minimum-ecc")) 521 519 || legacy_set_geometry(this)) { 522 522 - if (!(chip->base.eccreq.strength > 0 && 523 523 - chip->base.eccreq.step_size > 0)) 520 520 + if (!(requirements->strength > 0 && requirements->step_size > 0)) 524 521 return -EINVAL; 525 522 526 523 return set_geometry_by_ecc_info(this, 527 527 - chip->base.eccreq.strength, 528 528 - chip->base.eccreq.step_size); 524 524 + requirements->strength, 525 525 + requirements->step_size); 529 526 } 530 527 531 528 return 0; ··· 1004 1003 /* request dma channel */ 1005 1004 dma_chan = dma_request_chan(&pdev->dev, "rx-tx"); 1006 1005 if (IS_ERR(dma_chan)) { 1007 1007 - ret = PTR_ERR(dma_chan); 1008 1008 - if (ret != -EPROBE_DEFER) 1009 1009 - dev_err(this->dev, "DMA channel request failed: %d\n", 1010 1010 - ret); 1006 1006 + ret = dev_err_probe(this->dev, PTR_ERR(dma_chan), 1007 1007 + "DMA channel request failed\n"); 1011 1008 release_dma_channels(this); 1012 1009 } else { 1013 1010 this->dma_chans[0] = dma_chan; ··· 2031 2032 ecc->write_page_raw = gpmi_ecc_write_page_raw; 2032 2033 ecc->read_oob_raw = gpmi_ecc_read_oob_raw; 2033 2034 ecc->write_oob_raw = gpmi_ecc_write_oob_raw; 2034 2034 - ecc->mode = NAND_ECC_HW; 2035 2035 + ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2035 2036 ecc->size = bch_geo->ecc_chunk_size; 2036 2037 ecc->strength = bch_geo->ecc_strength; 2037 2038 mtd_set_ooblayout(mtd, &gpmi_ooblayout_ops);

+3 -3

drivers/mtd/nand/raw/hisi504_nand.c

reviewed

··· 186 186 hinfc_write(host, host->dma_buffer, HINFC504_DMA_ADDR_DATA); 187 187 hinfc_write(host, host->dma_oob, HINFC504_DMA_ADDR_OOB); 188 188 189 189 - if (chip->ecc.mode == NAND_ECC_NONE) { 189 189 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_NONE) { 190 190 hinfc_write(host, ((mtd->oobsize & HINFC504_DMA_LEN_OOB_MASK) 191 191 << HINFC504_DMA_LEN_OOB_SHIFT), HINFC504_DMA_LEN); 192 192 ··· 468 468 469 469 case NAND_CMD_STATUS: 470 470 flag = hinfc_read(host, HINFC504_CON); 471 471 - if (chip->ecc.mode == NAND_ECC_HW) 471 471 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 472 472 hinfc_write(host, 473 473 flag & ~(HINFC504_CON_ECCTYPE_MASK << 474 474 HINFC504_CON_ECCTYPE_SHIFT), HINFC504_CON); ··· 721 721 } 722 722 hinfc_write(host, flag, HINFC504_CON); 723 723 724 724 - if (chip->ecc.mode == NAND_ECC_HW) 724 724 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 725 725 hisi_nfc_ecc_probe(host); 726 726 727 727 return 0;

+10 -10

drivers/mtd/nand/raw/ingenic/ingenic_nand_drv.c

reviewed

··· 194 194 (chip->ecc.strength / 8); 195 195 } 196 196 197 197 - switch (chip->ecc.mode) { 198 198 - case NAND_ECC_HW: 197 197 + switch (chip->ecc.engine_type) { 198 198 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 199 199 if (!nfc->ecc) { 200 200 dev_err(nfc->dev, "HW ECC selected, but ECC controller not found\n"); 201 201 return -ENODEV; ··· 205 205 chip->ecc.calculate = ingenic_nand_ecc_calculate; 206 206 chip->ecc.correct = ingenic_nand_ecc_correct; 207 207 fallthrough; 208 208 - case NAND_ECC_SOFT: 208 208 + case NAND_ECC_ENGINE_TYPE_SOFT: 209 209 dev_info(nfc->dev, "using %s (strength %d, size %d, bytes %d)\n", 210 210 (nfc->ecc) ? "hardware ECC" : "software ECC", 211 211 chip->ecc.strength, chip->ecc.size, chip->ecc.bytes); 212 212 break; 213 213 - case NAND_ECC_NONE: 213 213 + case NAND_ECC_ENGINE_TYPE_NONE: 214 214 dev_info(nfc->dev, "not using ECC\n"); 215 215 break; 216 216 default: 217 217 dev_err(nfc->dev, "ECC mode %d not supported\n", 218 218 - chip->ecc.mode); 218 218 + chip->ecc.engine_type); 219 219 return -EINVAL; 220 220 } 221 221 222 222 /* The NAND core will generate the ECC layout for SW ECC */ 223 223 - if (chip->ecc.mode != NAND_ECC_HW) 223 223 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 224 224 return 0; 225 225 226 226 /* Generate ECC layout. ECC codes are right aligned in the OOB area. */ ··· 243 243 /* For legacy reasons we use a different layout on the qi,lb60 board. */ 244 244 if (of_machine_is_compatible("qi,lb60")) 245 245 mtd_set_ooblayout(mtd, &qi_lb60_ooblayout_ops); 246 246 - else 246 246 + else if (nfc->soc_info->oob_layout) 247 247 mtd_set_ooblayout(mtd, nfc->soc_info->oob_layout); 248 248 + else 249 249 + mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 248 250 249 251 return 0; 250 252 } ··· 406 404 mtd->dev.parent = dev; 407 405 408 406 chip->options = NAND_NO_SUBPAGE_WRITE; 409 409 - chip->ecc.mode = NAND_ECC_HW; 407 407 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 410 408 chip->controller = &nfc->controller; 411 409 nand_set_flash_node(chip, np); 412 410 ··· 534 532 .data_offset = 0x00000000, 535 533 .cmd_offset = 0x00008000, 536 534 .addr_offset = 0x00010000, 537 537 - .oob_layout = &nand_ooblayout_lp_ops, 538 535 }; 539 536 540 537 static const struct jz_soc_info jz4725b_soc_info = { ··· 547 546 .data_offset = 0x00000000, 548 547 .cmd_offset = 0x00400000, 549 548 .addr_offset = 0x00800000, 550 550 - .oob_layout = &nand_ooblayout_lp_ops, 551 549 }; 552 550 553 551 static const struct of_device_id ingenic_nand_dt_match[] = {

+1 -1

drivers/mtd/nand/raw/lpc32xx_mlc.c

reviewed

··· 656 656 if (!host->dummy_buf) 657 657 return -ENOMEM; 658 658 659 659 - chip->ecc.mode = NAND_ECC_HW; 659 659 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 660 660 chip->ecc.size = 512; 661 661 mtd_set_ooblayout(mtd, &lpc32xx_ooblayout_ops); 662 662 host->mlcsubpages = mtd->writesize / 512;

+2 -1

drivers/mtd/nand/raw/lpc32xx_slc.c

reviewed

··· 881 881 platform_set_drvdata(pdev, host); 882 882 883 883 /* NAND callbacks for LPC32xx SLC hardware */ 884 884 - chip->ecc.mode = NAND_ECC_HW_SYNDROME; 884 884 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 885 885 + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 885 886 chip->legacy.read_byte = lpc32xx_nand_read_byte; 886 887 chip->legacy.read_buf = lpc32xx_nand_read_buf; 887 888 chip->legacy.write_buf = lpc32xx_nand_write_buf;

+69 -32

drivers/mtd/nand/raw/marvell_nand.c

reviewed

··· 227 227 #define XTYPE_MASK 7 228 228 229 229 /** 230 230 + * struct marvell_hw_ecc_layout - layout of Marvell ECC 231 231 + * 230 232 * Marvell ECC engine works differently than the others, in order to limit the 231 233 * size of the IP, hardware engineers chose to set a fixed strength at 16 bits 232 234 * per subpage, and depending on a the desired strength needed by the NAND chip, ··· 294 292 }; 295 293 296 294 /** 295 295 + * struct marvell_nand_chip_sel - CS line description 296 296 + * 297 297 * The Nand Flash Controller has up to 4 CE and 2 RB pins. The CE selection 298 298 * is made by a field in NDCB0 register, and in another field in NDCB2 register. 299 299 * The datasheet describes the logic with an error: ADDR5 field is once ··· 316 312 }; 317 313 318 314 /** 319 319 - * NAND chip structure: stores NAND chip device related information 315 315 + * struct marvell_nand_chip - stores NAND chip device related information 320 316 * 321 317 * @chip: Base NAND chip structure 322 318 * @node: Used to store NAND chips into a list 323 323 - * @layout NAND layout when using hardware ECC 319 319 + * @layout: NAND layout when using hardware ECC 324 320 * @ndcr: Controller register value for this NAND chip 325 321 * @ndtr0: Timing registers 0 value for this NAND chip 326 322 * @ndtr1: Timing registers 1 value for this NAND chip 323 323 + * @addr_cyc: Amount of cycles needed to pass column address 327 324 * @selected_die: Current active CS 328 325 * @nsels: Number of CS lines required by the NAND chip 329 326 * @sels: Array of CS lines descriptions ··· 354 349 } 355 350 356 351 /** 357 357 - * NAND controller capabilities for distinction between compatible strings 352 352 + * struct marvell_nfc_caps - NAND controller capabilities for distinction 353 353 + * between compatible strings 358 354 * 359 355 * @max_cs_nb: Number of Chip Select lines available 360 356 * @max_rb_nb: Number of Ready/Busy lines available ··· 378 372 }; 379 373 380 374 /** 381 381 - * NAND controller structure: stores Marvell NAND controller information 375 375 + * struct marvell_nfc - stores Marvell NAND controller information 382 376 * 383 377 * @controller: Base controller structure 384 378 * @dev: Parent device (used to print error messages) ··· 389 383 * @assigned_cs: Bitmask describing already assigned CS lines 390 384 * @chips: List containing all the NAND chips attached to 391 385 * this NAND controller 386 386 + * @selected_chip: Currently selected target chip 392 387 * @caps: NAND controller capabilities for each compatible string 388 388 + * @use_dma: Whetner DMA is used 393 389 * @dma_chan: DMA channel (NFCv1 only) 394 390 * @dma_buf: 32-bit aligned buffer for DMA transfers (NFCv1 only) 395 391 */ ··· 419 411 } 420 412 421 413 /** 422 422 - * NAND controller timings expressed in NAND Controller clock cycles 414 414 + * struct marvell_nfc_timings - NAND controller timings expressed in NAND 415 415 + * Controller clock cycles 423 416 * 424 417 * @tRP: ND_nRE pulse width 425 418 * @tRH: ND_nRE high duration ··· 464 455 period_ns)) 465 456 466 457 /** 467 467 - * NAND driver structure filled during the parsing of the ->exec_op() subop 468 468 - * subset of instructions. 458 458 + * struct marvell_nfc_op - filled during the parsing of the ->exec_op() 459 459 + * subop subset of instructions. 469 460 * 470 461 * @ndcb: Array of values written to NDCBx registers 471 462 * @cle_ale_delay_ns: Optional delay after the last CMD or ADDR cycle ··· 694 685 return marvell_nfc_end_cmd(chip, cs_flag, "CMDD"); 695 686 } 696 687 688 688 + static int marvell_nfc_poll_status(struct marvell_nfc *nfc, u32 mask, 689 689 + u32 expected_val, unsigned long timeout_ms) 690 690 + { 691 691 + unsigned long limit; 692 692 + u32 st; 693 693 + 694 694 + limit = jiffies + msecs_to_jiffies(timeout_ms); 695 695 + do { 696 696 + st = readl_relaxed(nfc->regs + NDSR); 697 697 + if (st & NDSR_RDY(1)) 698 698 + st |= NDSR_RDY(0); 699 699 + 700 700 + if ((st & mask) == expected_val) 701 701 + return 0; 702 702 + 703 703 + cpu_relax(); 704 704 + } while (time_after(limit, jiffies)); 705 705 + 706 706 + return -ETIMEDOUT; 707 707 + } 708 708 + 697 709 static int marvell_nfc_wait_op(struct nand_chip *chip, unsigned int timeout_ms) 698 710 { 699 711 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 712 712 + struct mtd_info *mtd = nand_to_mtd(chip); 700 713 u32 pending; 701 714 int ret; 702 715 ··· 726 695 if (!timeout_ms) 727 696 timeout_ms = IRQ_TIMEOUT; 728 697 729 729 - init_completion(&nfc->complete); 698 698 + if (mtd->oops_panic_write) { 699 699 + ret = marvell_nfc_poll_status(nfc, NDSR_RDY(0), 700 700 + NDSR_RDY(0), 701 701 + timeout_ms); 702 702 + } else { 703 703 + init_completion(&nfc->complete); 730 704 731 731 - marvell_nfc_enable_int(nfc, NDCR_RDYM); 732 732 - ret = wait_for_completion_timeout(&nfc->complete, 733 733 - msecs_to_jiffies(timeout_ms)); 734 734 - marvell_nfc_disable_int(nfc, NDCR_RDYM); 705 705 + marvell_nfc_enable_int(nfc, NDCR_RDYM); 706 706 + ret = wait_for_completion_timeout(&nfc->complete, 707 707 + msecs_to_jiffies(timeout_ms)); 708 708 + marvell_nfc_disable_int(nfc, NDCR_RDYM); 709 709 + } 735 710 pending = marvell_nfc_clear_int(nfc, NDSR_RDY(0) | NDSR_RDY(1)); 736 711 737 712 /* ··· 817 780 * When enabling BCH, set threshold to 0 to always know the 818 781 * number of corrected bitflips. 819 782 */ 820 820 - if (chip->ecc.algo == NAND_ECC_BCH) 783 783 + if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 821 784 writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL); 822 785 } 823 786 } ··· 829 792 830 793 if (ndcr & NDCR_ECC_EN) { 831 794 writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR); 832 832 - if (chip->ecc.algo == NAND_ECC_BCH) 795 795 + if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 833 796 writel_relaxed(0, nfc->regs + NDECCCTRL); 834 797 } 835 798 } ··· 1003 966 if (ndsr & NDSR_CORERR) { 1004 967 writel_relaxed(ndsr, nfc->regs + NDSR); 1005 968 1006 1006 - if (chip->ecc.algo == NAND_ECC_BCH) 969 969 + if (chip->ecc.algo == NAND_ECC_ALGO_BCH) 1007 970 bf = NDSR_ERRCNT(ndsr); 1008 971 else 1009 972 bf = 1; ··· 2255 2218 ecc->size = l->data_bytes; 2256 2219 2257 2220 if (ecc->strength == 1) { 2258 2258 - chip->ecc.algo = NAND_ECC_HAMMING; 2221 2221 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2259 2222 ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw; 2260 2223 ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page; 2261 2224 ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw; ··· 2265 2228 ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw; 2266 2229 ecc->write_oob = ecc->write_oob_raw; 2267 2230 } else { 2268 2268 - chip->ecc.algo = NAND_ECC_BCH; 2231 2231 + chip->ecc.algo = NAND_ECC_ALGO_BCH; 2269 2232 ecc->strength = 16; 2270 2233 ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw; 2271 2234 ecc->read_page = marvell_nfc_hw_ecc_bch_read_page; ··· 2284 2247 struct nand_ecc_ctrl *ecc) 2285 2248 { 2286 2249 struct nand_chip *chip = mtd_to_nand(mtd); 2250 2250 + const struct nand_ecc_props *requirements = 2251 2251 + nanddev_get_ecc_requirements(&chip->base); 2287 2252 struct marvell_nfc *nfc = to_marvell_nfc(chip->controller); 2288 2253 int ret; 2289 2254 2290 2290 - if (ecc->mode != NAND_ECC_NONE && (!ecc->size || !ecc->strength)) { 2291 2291 - if (chip->base.eccreq.step_size && chip->base.eccreq.strength) { 2292 2292 - ecc->size = chip->base.eccreq.step_size; 2293 2293 - ecc->strength = chip->base.eccreq.strength; 2255 2255 + if (ecc->engine_type != NAND_ECC_ENGINE_TYPE_NONE && 2256 2256 + (!ecc->size || !ecc->strength)) { 2257 2257 + if (requirements->step_size && requirements->strength) { 2258 2258 + ecc->size = requirements->step_size; 2259 2259 + ecc->strength = requirements->strength; 2294 2260 } else { 2295 2261 dev_info(nfc->dev, 2296 2262 "No minimum ECC strength, using 1b/512B\n"); ··· 2302 2262 } 2303 2263 } 2304 2264 2305 2305 - switch (ecc->mode) { 2306 2306 - case NAND_ECC_HW: 2265 2265 + switch (ecc->engine_type) { 2266 2266 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 2307 2267 ret = marvell_nand_hw_ecc_controller_init(mtd, ecc); 2308 2268 if (ret) 2309 2269 return ret; 2310 2270 break; 2311 2311 - case NAND_ECC_NONE: 2312 2312 - case NAND_ECC_SOFT: 2313 2313 - case NAND_ECC_ON_DIE: 2271 2271 + case NAND_ECC_ENGINE_TYPE_NONE: 2272 2272 + case NAND_ECC_ENGINE_TYPE_SOFT: 2273 2273 + case NAND_ECC_ENGINE_TYPE_ON_DIE: 2314 2274 if (!nfc->caps->is_nfcv2 && mtd->writesize != SZ_512 && 2315 2275 mtd->writesize != SZ_2K) { 2316 2276 dev_err(nfc->dev, "NFCv1 cannot write %d bytes pages\n", ··· 2507 2467 return ret; 2508 2468 } 2509 2469 2510 2510 - if (chip->ecc.mode == NAND_ECC_HW) { 2470 2470 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 2511 2471 /* 2512 2472 * Subpage write not available with hardware ECC, prohibit also 2513 2473 * subpage read as in userspace subpage access would still be ··· 2682 2642 * Default to HW ECC engine mode. If the nand-ecc-mode property is given 2683 2643 * in the DT node, this entry will be overwritten in nand_scan_ident(). 2684 2644 */ 2685 2685 - chip->ecc.mode = NAND_ECC_HW; 2645 2645 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2686 2646 2687 2647 /* 2688 2648 * Save a reference value for timing registers before ··· 2799 2759 if (IS_ERR(nfc->dma_chan)) { 2800 2760 ret = PTR_ERR(nfc->dma_chan); 2801 2761 nfc->dma_chan = NULL; 2802 2802 - if (ret != -EPROBE_DEFER) 2803 2803 - dev_err(nfc->dev, "DMA channel request failed: %d\n", 2804 2804 - ret); 2805 2805 - return ret; 2762 2762 + return dev_err_probe(nfc->dev, ret, "DMA channel request failed\n"); 2806 2763 } 2807 2764 2808 2765 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);

+1 -1

drivers/mtd/nand/raw/meson_nand.c

reviewed

··· 1197 1197 if (ret) 1198 1198 return -EINVAL; 1199 1199 1200 1200 - nand->ecc.mode = NAND_ECC_HW; 1200 1200 + nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1201 1201 nand->ecc.write_page_raw = meson_nfc_write_page_raw; 1202 1202 nand->ecc.write_page = meson_nfc_write_page_hwecc; 1203 1203 nand->ecc.write_oob_raw = nand_write_oob_std;

+2 -2

drivers/mtd/nand/raw/mpc5121_nfc.c

reviewed

··· 688 688 chip->legacy.set_features = nand_get_set_features_notsupp; 689 689 chip->legacy.get_features = nand_get_set_features_notsupp; 690 690 chip->bbt_options = NAND_BBT_USE_FLASH; 691 691 - chip->ecc.mode = NAND_ECC_SOFT; 692 692 - chip->ecc.algo = NAND_ECC_HAMMING; 691 691 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 692 692 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 693 693 694 694 /* Support external chip-select logic on ADS5121 board */ 695 695 if (of_machine_is_compatible("fsl,mpc5121ads")) {

+7 -5

drivers/mtd/nand/raw/mtk_nand.c

reviewed

··· 1253 1253 static int mtk_nfc_ecc_init(struct device *dev, struct mtd_info *mtd) 1254 1254 { 1255 1255 struct nand_chip *nand = mtd_to_nand(mtd); 1256 1256 + const struct nand_ecc_props *requirements = 1257 1257 + nanddev_get_ecc_requirements(&nand->base); 1256 1258 struct mtk_nfc *nfc = nand_get_controller_data(nand); 1257 1259 u32 spare; 1258 1260 int free, ret; 1259 1261 1260 1262 /* support only ecc hw mode */ 1261 1261 - if (nand->ecc.mode != NAND_ECC_HW) { 1262 1262 - dev_err(dev, "ecc.mode not supported\n"); 1263 1263 + if (nand->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { 1264 1264 + dev_err(dev, "ecc.engine_type not supported\n"); 1263 1265 return -EINVAL; 1264 1266 } 1265 1267 1266 1268 /* if optional dt settings not present */ 1267 1269 if (!nand->ecc.size || !nand->ecc.strength) { 1268 1270 /* use datasheet requirements */ 1269 1269 - nand->ecc.strength = nand->base.eccreq.strength; 1270 1270 - nand->ecc.size = nand->base.eccreq.step_size; 1271 1271 + nand->ecc.strength = requirements->strength; 1272 1272 + nand->ecc.size = requirements->step_size; 1271 1273 1272 1274 /* 1273 1275 * align eccstrength and eccsize ··· 1418 1416 nand->options |= NAND_USES_DMA | NAND_SUBPAGE_READ; 1419 1417 1420 1418 /* set default mode in case dt entry is missing */ 1421 1421 - nand->ecc.mode = NAND_ECC_HW; 1419 1419 + nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1422 1420 1423 1421 nand->ecc.write_subpage = mtk_nfc_write_subpage_hwecc; 1424 1422 nand->ecc.write_page_raw = mtk_nfc_write_page_raw;

+13 -12

drivers/mtd/nand/raw/mxc_nand.c

reviewed

··· 669 669 struct mxc_nand_host *host = nand_get_controller_data(chip); 670 670 uint16_t config1; 671 671 672 672 - if (chip->ecc.mode != NAND_ECC_HW) 672 672 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 673 673 return; 674 674 675 675 config1 = readw(NFC_V1_V2_CONFIG1); ··· 687 687 struct mxc_nand_host *host = nand_get_controller_data(chip); 688 688 uint32_t config2; 689 689 690 690 - if (chip->ecc.mode != NAND_ECC_HW) 690 690 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 691 691 return; 692 692 693 693 config2 = readl(NFC_V3_CONFIG2); ··· 1117 1117 struct mxc_nand_host *host = nand_get_controller_data(nand_chip); 1118 1118 uint16_t config1 = 0; 1119 1119 1120 1120 - if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize) 1120 1120 + if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST && 1121 1121 + mtd->writesize) 1121 1122 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1122 1123 1123 1124 if (!host->devtype_data->irqpending_quirk) ··· 1228 1227 if (mtd->writesize) { 1229 1228 uint16_t pages_per_block = mtd->erasesize / mtd->writesize; 1230 1229 1231 1231 - if (nand_chip->ecc.mode == NAND_ECC_HW) 1230 1230 + if (nand_chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1232 1231 config1 |= NFC_V1_V2_CONFIG1_ECC_EN; 1233 1232 1234 1233 host->eccsize = get_eccsize(mtd); ··· 1304 1303 } 1305 1304 1306 1305 if (mtd->writesize) { 1307 1307 - if (chip->ecc.mode == NAND_ECC_HW) 1306 1306 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) 1308 1307 config2 |= NFC_V3_CONFIG2_ECC_EN; 1309 1308 1310 1309 config2 |= NFC_V3_CONFIG2_PPB( ··· 1681 1680 struct mxc_nand_host *host = nand_get_controller_data(chip); 1682 1681 struct device *dev = mtd->dev.parent; 1683 1682 1684 1684 - switch (chip->ecc.mode) { 1685 1685 - case NAND_ECC_HW: 1683 1683 + switch (chip->ecc.engine_type) { 1684 1684 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 1686 1685 chip->ecc.read_page = mxc_nand_read_page; 1687 1686 chip->ecc.read_page_raw = mxc_nand_read_page_raw; 1688 1687 chip->ecc.read_oob = mxc_nand_read_oob; ··· 1691 1690 chip->ecc.write_oob = mxc_nand_write_oob; 1692 1691 break; 1693 1692 1694 1694 - case NAND_ECC_SOFT: 1693 1693 + case NAND_ECC_ENGINE_TYPE_SOFT: 1695 1694 break; 1696 1695 1697 1696 default: ··· 1729 1728 */ 1730 1729 host->used_oobsize = min(mtd->oobsize, 218U); 1731 1730 1732 1732 - if (chip->ecc.mode == NAND_ECC_HW) { 1731 1731 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 1733 1732 if (is_imx21_nfc(host) || is_imx27_nfc(host)) 1734 1733 chip->ecc.strength = 1; 1735 1734 else ··· 1844 1843 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout); 1845 1844 1846 1845 if (host->pdata.hw_ecc) { 1847 1847 - this->ecc.mode = NAND_ECC_HW; 1846 1846 + this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1848 1847 } else { 1849 1849 - this->ecc.mode = NAND_ECC_SOFT; 1850 1850 - this->ecc.algo = NAND_ECC_HAMMING; 1848 1848 + this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 1849 1849 + this->ecc.algo = NAND_ECC_ALGO_HAMMING; 1851 1850 } 1852 1851 1853 1852 /* NAND bus width determines access functions used by upper layer */

+210 -358

drivers/mtd/nand/raw/nand_base.c

reviewed

··· 34 34 #include <linux/mm.h> 35 35 #include <linux/types.h> 36 36 #include <linux/mtd/mtd.h> 37 37 + #include <linux/mtd/nand.h> 37 38 #include <linux/mtd/nand_ecc.h> 38 39 #include <linux/mtd/nand_bch.h> 39 40 #include <linux/interrupt.h> ··· 45 44 #include <linux/gpio/consumer.h> 46 45 47 46 #include "internals.h" 48 48 - 49 49 - /* Define default oob placement schemes for large and small page devices */ 50 50 - static int nand_ooblayout_ecc_sp(struct mtd_info *mtd, int section, 51 51 - struct mtd_oob_region *oobregion) 52 52 - { 53 53 - struct nand_chip *chip = mtd_to_nand(mtd); 54 54 - struct nand_ecc_ctrl *ecc = &chip->ecc; 55 55 - 56 56 - if (section > 1) 57 57 - return -ERANGE; 58 58 - 59 59 - if (!section) { 60 60 - oobregion->offset = 0; 61 61 - if (mtd->oobsize == 16) 62 62 - oobregion->length = 4; 63 63 - else 64 64 - oobregion->length = 3; 65 65 - } else { 66 66 - if (mtd->oobsize == 8) 67 67 - return -ERANGE; 68 68 - 69 69 - oobregion->offset = 6; 70 70 - oobregion->length = ecc->total - 4; 71 71 - } 72 72 - 73 73 - return 0; 74 74 - } 75 75 - 76 76 - static int nand_ooblayout_free_sp(struct mtd_info *mtd, int section, 77 77 - struct mtd_oob_region *oobregion) 78 78 - { 79 79 - if (section > 1) 80 80 - return -ERANGE; 81 81 - 82 82 - if (mtd->oobsize == 16) { 83 83 - if (section) 84 84 - return -ERANGE; 85 85 - 86 86 - oobregion->length = 8; 87 87 - oobregion->offset = 8; 88 88 - } else { 89 89 - oobregion->length = 2; 90 90 - if (!section) 91 91 - oobregion->offset = 3; 92 92 - else 93 93 - oobregion->offset = 6; 94 94 - } 95 95 - 96 96 - return 0; 97 97 - } 98 98 - 99 99 - const struct mtd_ooblayout_ops nand_ooblayout_sp_ops = { 100 100 - .ecc = nand_ooblayout_ecc_sp, 101 101 - .free = nand_ooblayout_free_sp, 102 102 - }; 103 103 - EXPORT_SYMBOL_GPL(nand_ooblayout_sp_ops); 104 104 - 105 105 - static int nand_ooblayout_ecc_lp(struct mtd_info *mtd, int section, 106 106 - struct mtd_oob_region *oobregion) 107 107 - { 108 108 - struct nand_chip *chip = mtd_to_nand(mtd); 109 109 - struct nand_ecc_ctrl *ecc = &chip->ecc; 110 110 - 111 111 - if (section || !ecc->total) 112 112 - return -ERANGE; 113 113 - 114 114 - oobregion->length = ecc->total; 115 115 - oobregion->offset = mtd->oobsize - oobregion->length; 116 116 - 117 117 - return 0; 118 118 - } 119 119 - 120 120 - static int nand_ooblayout_free_lp(struct mtd_info *mtd, int section, 121 121 - struct mtd_oob_region *oobregion) 122 122 - { 123 123 - struct nand_chip *chip = mtd_to_nand(mtd); 124 124 - struct nand_ecc_ctrl *ecc = &chip->ecc; 125 125 - 126 126 - if (section) 127 127 - return -ERANGE; 128 128 - 129 129 - oobregion->length = mtd->oobsize - ecc->total - 2; 130 130 - oobregion->offset = 2; 131 131 - 132 132 - return 0; 133 133 - } 134 134 - 135 135 - const struct mtd_ooblayout_ops nand_ooblayout_lp_ops = { 136 136 - .ecc = nand_ooblayout_ecc_lp, 137 137 - .free = nand_ooblayout_free_lp, 138 138 - }; 139 139 - EXPORT_SYMBOL_GPL(nand_ooblayout_lp_ops); 140 140 - 141 141 - /* 142 142 - * Support the old "large page" layout used for 1-bit Hamming ECC where ECC 143 143 - * are placed at a fixed offset. 144 144 - */ 145 145 - static int nand_ooblayout_ecc_lp_hamming(struct mtd_info *mtd, int section, 146 146 - struct mtd_oob_region *oobregion) 147 147 - { 148 148 - struct nand_chip *chip = mtd_to_nand(mtd); 149 149 - struct nand_ecc_ctrl *ecc = &chip->ecc; 150 150 - 151 151 - if (section) 152 152 - return -ERANGE; 153 153 - 154 154 - switch (mtd->oobsize) { 155 155 - case 64: 156 156 - oobregion->offset = 40; 157 157 - break; 158 158 - case 128: 159 159 - oobregion->offset = 80; 160 160 - break; 161 161 - default: 162 162 - return -EINVAL; 163 163 - } 164 164 - 165 165 - oobregion->length = ecc->total; 166 166 - if (oobregion->offset + oobregion->length > mtd->oobsize) 167 167 - return -ERANGE; 168 168 - 169 169 - return 0; 170 170 - } 171 171 - 172 172 - static int nand_ooblayout_free_lp_hamming(struct mtd_info *mtd, int section, 173 173 - struct mtd_oob_region *oobregion) 174 174 - { 175 175 - struct nand_chip *chip = mtd_to_nand(mtd); 176 176 - struct nand_ecc_ctrl *ecc = &chip->ecc; 177 177 - int ecc_offset = 0; 178 178 - 179 179 - if (section < 0 || section > 1) 180 180 - return -ERANGE; 181 181 - 182 182 - switch (mtd->oobsize) { 183 183 - case 64: 184 184 - ecc_offset = 40; 185 185 - break; 186 186 - case 128: 187 187 - ecc_offset = 80; 188 188 - break; 189 189 - default: 190 190 - return -EINVAL; 191 191 - } 192 192 - 193 193 - if (section == 0) { 194 194 - oobregion->offset = 2; 195 195 - oobregion->length = ecc_offset - 2; 196 196 - } else { 197 197 - oobregion->offset = ecc_offset + ecc->total; 198 198 - oobregion->length = mtd->oobsize - oobregion->offset; 199 199 - } 200 200 - 201 201 - return 0; 202 202 - } 203 203 - 204 204 - static const struct mtd_ooblayout_ops nand_ooblayout_lp_hamming_ops = { 205 205 - .ecc = nand_ooblayout_ecc_lp_hamming, 206 206 - .free = nand_ooblayout_free_lp_hamming, 207 207 - }; 208 47 209 48 static int nand_pairing_dist3_get_info(struct mtd_info *mtd, int page, 210 49 struct mtd_pairing_info *info) ··· 4591 4750 static bool find_full_id_nand(struct nand_chip *chip, 4592 4751 struct nand_flash_dev *type) 4593 4752 { 4753 4753 + struct nand_device *base = &chip->base; 4754 4754 + struct nand_ecc_props requirements; 4594 4755 struct mtd_info *mtd = nand_to_mtd(chip); 4595 4756 struct nand_memory_organization *memorg; 4596 4757 u8 *id_data = chip->id.data; ··· 4614 4771 memorg->pagesize * 4615 4772 memorg->pages_per_eraseblock); 4616 4773 chip->options |= type->options; 4617 4617 - chip->base.eccreq.strength = NAND_ECC_STRENGTH(type); 4618 4618 - chip->base.eccreq.step_size = NAND_ECC_STEP(type); 4774 4774 + requirements.strength = NAND_ECC_STRENGTH(type); 4775 4775 + requirements.step_size = NAND_ECC_STEP(type); 4776 4776 + nanddev_set_ecc_requirements(base, &requirements); 4619 4777 4620 4778 chip->parameters.model = kstrdup(type->name, GFP_KERNEL); 4621 4779 if (!chip->parameters.model) ··· 4877 5033 return ret; 4878 5034 } 4879 5035 4880 4880 - static const char * const nand_ecc_modes[] = { 4881 4881 - [NAND_ECC_NONE] = "none", 4882 4882 - [NAND_ECC_SOFT] = "soft", 4883 4883 - [NAND_ECC_HW] = "hw", 4884 4884 - [NAND_ECC_HW_SYNDROME] = "hw_syndrome", 4885 4885 - [NAND_ECC_ON_DIE] = "on-die", 4886 4886 - }; 4887 4887 - 4888 4888 - static int of_get_nand_ecc_mode(struct device_node *np) 5036 5036 + static enum nand_ecc_engine_type 5037 5037 + of_get_rawnand_ecc_engine_type_legacy(struct device_node *np) 4889 5038 { 4890 4890 - const char *pm; 4891 4891 - int err, i; 4892 4892 - 4893 4893 - err = of_property_read_string(np, "nand-ecc-mode", &pm); 4894 4894 - if (err < 0) 4895 4895 - return err; 4896 4896 - 4897 4897 - for (i = NAND_ECC_NONE; i < ARRAY_SIZE(nand_ecc_modes); i++) 4898 4898 - if (!strcasecmp(pm, nand_ecc_modes[i])) 4899 4899 - return i; 4900 4900 - 4901 4901 - /* 4902 4902 - * For backward compatibility we support few obsoleted values that don't 4903 4903 - * have their mappings into the nand_ecc_mode enum anymore (they were 4904 4904 - * merged with other enums). 4905 4905 - */ 4906 4906 - if (!strcasecmp(pm, "soft_bch")) 4907 4907 - return NAND_ECC_SOFT; 4908 4908 - 4909 4909 - return -ENODEV; 4910 4910 - } 4911 4911 - 4912 4912 - static const char * const nand_ecc_algos[] = { 4913 4913 - [NAND_ECC_HAMMING] = "hamming", 4914 4914 - [NAND_ECC_BCH] = "bch", 4915 4915 - [NAND_ECC_RS] = "rs", 4916 4916 - }; 4917 4917 - 4918 4918 - static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np) 4919 4919 - { 4920 4920 - enum nand_ecc_algo ecc_algo; 5039 5039 + enum nand_ecc_legacy_mode { 5040 5040 + NAND_ECC_INVALID, 5041 5041 + NAND_ECC_NONE, 5042 5042 + NAND_ECC_SOFT, 5043 5043 + NAND_ECC_SOFT_BCH, 5044 5044 + NAND_ECC_HW, 5045 5045 + NAND_ECC_HW_SYNDROME, 5046 5046 + NAND_ECC_ON_DIE, 5047 5047 + }; 5048 5048 + const char * const nand_ecc_legacy_modes[] = { 5049 5049 + [NAND_ECC_NONE] = "none", 5050 5050 + [NAND_ECC_SOFT] = "soft", 5051 5051 + [NAND_ECC_SOFT_BCH] = "soft_bch", 5052 5052 + [NAND_ECC_HW] = "hw", 5053 5053 + [NAND_ECC_HW_SYNDROME] = "hw_syndrome", 5054 5054 + [NAND_ECC_ON_DIE] = "on-die", 5055 5055 + }; 5056 5056 + enum nand_ecc_legacy_mode eng_type; 4921 5057 const char *pm; 4922 5058 int err; 4923 5059 4924 4924 - err = of_property_read_string(np, "nand-ecc-algo", &pm); 4925 4925 - if (!err) { 4926 4926 - for (ecc_algo = NAND_ECC_HAMMING; 4927 4927 - ecc_algo < ARRAY_SIZE(nand_ecc_algos); 4928 4928 - ecc_algo++) { 4929 4929 - if (!strcasecmp(pm, nand_ecc_algos[ecc_algo])) 4930 4930 - return ecc_algo; 5060 5060 + err = of_property_read_string(np, "nand-ecc-mode", &pm); 5061 5061 + if (err) 5062 5062 + return NAND_ECC_ENGINE_TYPE_INVALID; 5063 5063 + 5064 5064 + for (eng_type = NAND_ECC_NONE; 5065 5065 + eng_type < ARRAY_SIZE(nand_ecc_legacy_modes); eng_type++) { 5066 5066 + if (!strcasecmp(pm, nand_ecc_legacy_modes[eng_type])) { 5067 5067 + switch (eng_type) { 5068 5068 + case NAND_ECC_NONE: 5069 5069 + return NAND_ECC_ENGINE_TYPE_NONE; 5070 5070 + case NAND_ECC_SOFT: 5071 5071 + case NAND_ECC_SOFT_BCH: 5072 5072 + return NAND_ECC_ENGINE_TYPE_SOFT; 5073 5073 + case NAND_ECC_HW: 5074 5074 + case NAND_ECC_HW_SYNDROME: 5075 5075 + return NAND_ECC_ENGINE_TYPE_ON_HOST; 5076 5076 + case NAND_ECC_ON_DIE: 5077 5077 + return NAND_ECC_ENGINE_TYPE_ON_DIE; 5078 5078 + default: 5079 5079 + break; 5080 5080 + } 4931 5081 } 4932 5082 } 4933 5083 4934 4934 - /* 4935 4935 - * For backward compatibility we also read "nand-ecc-mode" checking 4936 4936 - * for some obsoleted values that were specifying ECC algorithm. 4937 4937 - */ 5084 5084 + return NAND_ECC_ENGINE_TYPE_INVALID; 5085 5085 + } 5086 5086 + 5087 5087 + static enum nand_ecc_placement 5088 5088 + of_get_rawnand_ecc_placement_legacy(struct device_node *np) 5089 5089 + { 5090 5090 + const char *pm; 5091 5091 + int err; 5092 5092 + 5093 5093 + err = of_property_read_string(np, "nand-ecc-mode", &pm); 5094 5094 + if (!err) { 5095 5095 + if (!strcasecmp(pm, "hw_syndrome")) 5096 5096 + return NAND_ECC_PLACEMENT_INTERLEAVED; 5097 5097 + } 5098 5098 + 5099 5099 + return NAND_ECC_PLACEMENT_UNKNOWN; 5100 5100 + } 5101 5101 + 5102 5102 + static enum nand_ecc_algo of_get_rawnand_ecc_algo_legacy(struct device_node *np) 5103 5103 + { 5104 5104 + const char *pm; 5105 5105 + int err; 5106 5106 + 4938 5107 err = of_property_read_string(np, "nand-ecc-mode", &pm); 4939 5108 if (!err) { 4940 5109 if (!strcasecmp(pm, "soft")) 4941 4941 - return NAND_ECC_HAMMING; 5110 5110 + return NAND_ECC_ALGO_HAMMING; 4942 5111 else if (!strcasecmp(pm, "soft_bch")) 4943 4943 - return NAND_ECC_BCH; 5112 5112 + return NAND_ECC_ALGO_BCH; 4944 5113 } 4945 5114 4946 4946 - return NAND_ECC_UNKNOWN; 5115 5115 + return NAND_ECC_ALGO_UNKNOWN; 4947 5116 } 4948 5117 4949 4949 - static int of_get_nand_ecc_step_size(struct device_node *np) 5118 5118 + static void of_get_nand_ecc_legacy_user_config(struct nand_chip *chip) 4950 5119 { 4951 4951 - int ret; 4952 4952 - u32 val; 5120 5120 + struct device_node *dn = nand_get_flash_node(chip); 5121 5121 + struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf; 4953 5122 4954 4954 - ret = of_property_read_u32(np, "nand-ecc-step-size", &val); 4955 4955 - return ret ? ret : val; 4956 4956 - } 5123 5123 + if (user_conf->engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 5124 5124 + user_conf->engine_type = of_get_rawnand_ecc_engine_type_legacy(dn); 4957 5125 4958 4958 - static int of_get_nand_ecc_strength(struct device_node *np) 4959 4959 - { 4960 4960 - int ret; 4961 4961 - u32 val; 5126 5126 + if (user_conf->algo == NAND_ECC_ALGO_UNKNOWN) 5127 5127 + user_conf->algo = of_get_rawnand_ecc_algo_legacy(dn); 4962 5128 4963 4963 - ret = of_property_read_u32(np, "nand-ecc-strength", &val); 4964 4964 - return ret ? ret : val; 5129 5129 + if (user_conf->placement == NAND_ECC_PLACEMENT_UNKNOWN) 5130 5130 + user_conf->placement = of_get_rawnand_ecc_placement_legacy(dn); 4965 5131 } 4966 5132 4967 5133 static int of_get_nand_bus_width(struct device_node *np) ··· 4995 5141 return of_property_read_bool(np, "nand-on-flash-bbt"); 4996 5142 } 4997 5143 4998 4998 - static int nand_dt_init(struct nand_chip *chip) 5144 5144 + static int rawnand_dt_init(struct nand_chip *chip) 4999 5145 { 5146 5146 + struct nand_device *nand = mtd_to_nanddev(nand_to_mtd(chip)); 5000 5147 struct device_node *dn = nand_get_flash_node(chip); 5001 5001 - enum nand_ecc_algo ecc_algo; 5002 5002 - int ecc_mode, ecc_strength, ecc_step; 5003 5148 5004 5149 if (!dn) 5005 5150 return 0; ··· 5012 5159 if (of_get_nand_on_flash_bbt(dn)) 5013 5160 chip->bbt_options |= NAND_BBT_USE_FLASH; 5014 5161 5015 5015 - ecc_mode = of_get_nand_ecc_mode(dn); 5016 5016 - ecc_algo = of_get_nand_ecc_algo(dn); 5017 5017 - ecc_strength = of_get_nand_ecc_strength(dn); 5018 5018 - ecc_step = of_get_nand_ecc_step_size(dn); 5162 5162 + of_get_nand_ecc_user_config(nand); 5163 5163 + of_get_nand_ecc_legacy_user_config(chip); 5019 5164 5020 5020 - if (ecc_mode >= 0) 5021 5021 - chip->ecc.mode = ecc_mode; 5165 5165 + /* 5166 5166 + * If neither the user nor the NAND controller have requested a specific 5167 5167 + * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST. 5168 5168 + */ 5169 5169 + nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 5022 5170 5023 5023 - if (ecc_algo != NAND_ECC_UNKNOWN) 5024 5024 - chip->ecc.algo = ecc_algo; 5171 5171 + /* 5172 5172 + * Use the user requested engine type, unless there is none, in this 5173 5173 + * case default to the NAND controller choice, otherwise fallback to 5174 5174 + * the raw NAND default one. 5175 5175 + */ 5176 5176 + if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID) 5177 5177 + chip->ecc.engine_type = nand->ecc.user_conf.engine_type; 5178 5178 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) 5179 5179 + chip->ecc.engine_type = nand->ecc.defaults.engine_type; 5025 5180 5026 5026 - if (ecc_strength >= 0) 5027 5027 - chip->ecc.strength = ecc_strength; 5028 5028 - 5029 5029 - if (ecc_step > 0) 5030 5030 - chip->ecc.size = ecc_step; 5031 5031 - 5032 5032 - if (of_property_read_bool(dn, "nand-ecc-maximize")) 5033 5033 - chip->ecc.options |= NAND_ECC_MAXIMIZE; 5181 5181 + chip->ecc.placement = nand->ecc.user_conf.placement; 5182 5182 + chip->ecc.algo = nand->ecc.user_conf.algo; 5183 5183 + chip->ecc.strength = nand->ecc.user_conf.strength; 5184 5184 + chip->ecc.size = nand->ecc.user_conf.step_size; 5034 5185 5035 5186 return 0; 5036 5187 } ··· 5072 5215 /* Enforce the right timings for reset/detection */ 5073 5216 chip->current_interface_config = nand_get_reset_interface_config(); 5074 5217 5075 5075 - ret = nand_dt_init(chip); 5218 5218 + ret = rawnand_dt_init(chip); 5076 5219 if (ret) 5077 5220 return ret; 5078 5221 ··· 5139 5282 kfree(chip->parameters.onfi); 5140 5283 } 5141 5284 5285 5285 + static int nand_set_ecc_on_host_ops(struct nand_chip *chip) 5286 5286 + { 5287 5287 + struct nand_ecc_ctrl *ecc = &chip->ecc; 5288 5288 + 5289 5289 + switch (ecc->placement) { 5290 5290 + case NAND_ECC_PLACEMENT_UNKNOWN: 5291 5291 + case NAND_ECC_PLACEMENT_OOB: 5292 5292 + /* Use standard hwecc read page function? */ 5293 5293 + if (!ecc->read_page) 5294 5294 + ecc->read_page = nand_read_page_hwecc; 5295 5295 + if (!ecc->write_page) 5296 5296 + ecc->write_page = nand_write_page_hwecc; 5297 5297 + if (!ecc->read_page_raw) 5298 5298 + ecc->read_page_raw = nand_read_page_raw; 5299 5299 + if (!ecc->write_page_raw) 5300 5300 + ecc->write_page_raw = nand_write_page_raw; 5301 5301 + if (!ecc->read_oob) 5302 5302 + ecc->read_oob = nand_read_oob_std; 5303 5303 + if (!ecc->write_oob) 5304 5304 + ecc->write_oob = nand_write_oob_std; 5305 5305 + if (!ecc->read_subpage) 5306 5306 + ecc->read_subpage = nand_read_subpage; 5307 5307 + if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 5308 5308 + ecc->write_subpage = nand_write_subpage_hwecc; 5309 5309 + fallthrough; 5310 5310 + 5311 5311 + case NAND_ECC_PLACEMENT_INTERLEAVED: 5312 5312 + if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 5313 5313 + (!ecc->read_page || 5314 5314 + ecc->read_page == nand_read_page_hwecc || 5315 5315 + !ecc->write_page || 5316 5316 + ecc->write_page == nand_write_page_hwecc)) { 5317 5317 + WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); 5318 5318 + return -EINVAL; 5319 5319 + } 5320 5320 + /* Use standard syndrome read/write page function? */ 5321 5321 + if (!ecc->read_page) 5322 5322 + ecc->read_page = nand_read_page_syndrome; 5323 5323 + if (!ecc->write_page) 5324 5324 + ecc->write_page = nand_write_page_syndrome; 5325 5325 + if (!ecc->read_page_raw) 5326 5326 + ecc->read_page_raw = nand_read_page_raw_syndrome; 5327 5327 + if (!ecc->write_page_raw) 5328 5328 + ecc->write_page_raw = nand_write_page_raw_syndrome; 5329 5329 + if (!ecc->read_oob) 5330 5330 + ecc->read_oob = nand_read_oob_syndrome; 5331 5331 + if (!ecc->write_oob) 5332 5332 + ecc->write_oob = nand_write_oob_syndrome; 5333 5333 + break; 5334 5334 + 5335 5335 + default: 5336 5336 + pr_warn("Invalid NAND_ECC_PLACEMENT %d\n", 5337 5337 + ecc->placement); 5338 5338 + return -EINVAL; 5339 5339 + } 5340 5340 + 5341 5341 + return 0; 5342 5342 + } 5343 5343 + 5142 5344 static int nand_set_ecc_soft_ops(struct nand_chip *chip) 5143 5345 { 5144 5346 struct mtd_info *mtd = nand_to_mtd(chip); 5347 5347 + struct nand_device *nanddev = mtd_to_nanddev(mtd); 5145 5348 struct nand_ecc_ctrl *ecc = &chip->ecc; 5146 5349 5147 5147 - if (WARN_ON(ecc->mode != NAND_ECC_SOFT)) 5350 5350 + if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT)) 5148 5351 return -EINVAL; 5149 5352 5150 5353 switch (ecc->algo) { 5151 5151 - case NAND_ECC_HAMMING: 5354 5354 + case NAND_ECC_ALGO_HAMMING: 5152 5355 ecc->calculate = nand_calculate_ecc; 5153 5356 ecc->correct = nand_correct_data; 5154 5357 ecc->read_page = nand_read_page_swecc; ··· 5229 5312 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; 5230 5313 5231 5314 return 0; 5232 5232 - case NAND_ECC_BCH: 5315 5315 + case NAND_ECC_ALGO_BCH: 5233 5316 if (!mtd_nand_has_bch()) { 5234 5317 WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n"); 5235 5318 return -EINVAL; ··· 5267 5350 return -EINVAL; 5268 5351 } 5269 5352 5270 5270 - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 5353 5353 + mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 5271 5354 5272 5355 } 5273 5356 ··· 5276 5359 * used, otherwise we don't know how many bytes can really be 5277 5360 * used. 5278 5361 */ 5279 5279 - if (mtd->ooblayout == &nand_ooblayout_lp_ops && 5280 5280 - ecc->options & NAND_ECC_MAXIMIZE) { 5362 5362 + if (mtd->ooblayout == nand_get_large_page_ooblayout() && 5363 5363 + nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) { 5281 5364 int steps, bytes; 5282 5365 5283 5366 /* Always prefer 1k blocks over 512bytes ones */ ··· 5371 5454 nand_match_ecc_req(struct nand_chip *chip, 5372 5455 const struct nand_ecc_caps *caps, int oobavail) 5373 5456 { 5457 5457 + const struct nand_ecc_props *requirements = 5458 5458 + nanddev_get_ecc_requirements(&chip->base); 5374 5459 struct mtd_info *mtd = nand_to_mtd(chip); 5375 5460 const struct nand_ecc_step_info *stepinfo; 5376 5376 - int req_step = chip->base.eccreq.step_size; 5377 5377 - int req_strength = chip->base.eccreq.strength; 5461 5461 + int req_step = requirements->step_size; 5462 5462 + int req_strength = requirements->strength; 5378 5463 int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total; 5379 5464 int best_step, best_strength, best_ecc_bytes; 5380 5465 int best_ecc_bytes_total = INT_MAX; ··· 5517 5598 * @caps: ECC engine caps info structure 5518 5599 * @oobavail: OOB size that the ECC engine can use 5519 5600 * 5520 5520 - * Choose the ECC configuration according to following logic 5601 5601 + * Choose the ECC configuration according to following logic. 5521 5602 * 5522 5603 * 1. If both ECC step size and ECC strength are already set (usually by DT) 5523 5604 * then check if it is supported by this controller. 5524 5524 - * 2. If NAND_ECC_MAXIMIZE is set, then select maximum ECC strength. 5605 5605 + * 2. If the user provided the nand-ecc-maximize property, then select maximum 5606 5606 + * ECC strength. 5525 5607 * 3. Otherwise, try to match the ECC step size and ECC strength closest 5526 5608 * to the chip's requirement. If available OOB size can't fit the chip 5527 5609 * requirement then fallback to the maximum ECC step size and ECC strength. ··· 5533 5613 const struct nand_ecc_caps *caps, int oobavail) 5534 5614 { 5535 5615 struct mtd_info *mtd = nand_to_mtd(chip); 5616 5616 + struct nand_device *nanddev = mtd_to_nanddev(mtd); 5536 5617 5537 5618 if (WARN_ON(oobavail < 0 || oobavail > mtd->oobsize)) 5538 5619 return -EINVAL; ··· 5541 5620 if (chip->ecc.size && chip->ecc.strength) 5542 5621 return nand_check_ecc_caps(chip, caps, oobavail); 5543 5622 5544 5544 - if (chip->ecc.options & NAND_ECC_MAXIMIZE) 5623 5623 + if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) 5545 5624 return nand_maximize_ecc(chip, caps, oobavail); 5546 5625 5547 5626 if (!nand_match_ecc_req(chip, caps, oobavail)) ··· 5550 5629 return nand_maximize_ecc(chip, caps, oobavail); 5551 5630 } 5552 5631 EXPORT_SYMBOL_GPL(nand_ecc_choose_conf); 5553 5553 - 5554 5554 - /* 5555 5555 - * Check if the chip configuration meet the datasheet requirements. 5556 5556 - 5557 5557 - * If our configuration corrects A bits per B bytes and the minimum 5558 5558 - * required correction level is X bits per Y bytes, then we must ensure 5559 5559 - * both of the following are true: 5560 5560 - * 5561 5561 - * (1) A / B >= X / Y 5562 5562 - * (2) A >= X 5563 5563 - * 5564 5564 - * Requirement (1) ensures we can correct for the required bitflip density. 5565 5565 - * Requirement (2) ensures we can correct even when all bitflips are clumped 5566 5566 - * in the same sector. 5567 5567 - */ 5568 5568 - static bool nand_ecc_strength_good(struct nand_chip *chip) 5569 5569 - { 5570 5570 - struct mtd_info *mtd = nand_to_mtd(chip); 5571 5571 - struct nand_ecc_ctrl *ecc = &chip->ecc; 5572 5572 - int corr, ds_corr; 5573 5573 - 5574 5574 - if (ecc->size == 0 || chip->base.eccreq.step_size == 0) 5575 5575 - /* Not enough information */ 5576 5576 - return true; 5577 5577 - 5578 5578 - /* 5579 5579 - * We get the number of corrected bits per page to compare 5580 5580 - * the correction density. 5581 5581 - */ 5582 5582 - corr = (mtd->writesize * ecc->strength) / ecc->size; 5583 5583 - ds_corr = (mtd->writesize * chip->base.eccreq.strength) / 5584 5584 - chip->base.eccreq.step_size; 5585 5585 - 5586 5586 - return corr >= ds_corr && ecc->strength >= chip->base.eccreq.strength; 5587 5587 - } 5588 5632 5589 5633 static int rawnand_erase(struct nand_device *nand, const struct nand_pos *pos) 5590 5634 { ··· 5638 5752 * If no default placement scheme is given, select an appropriate one. 5639 5753 */ 5640 5754 if (!mtd->ooblayout && 5641 5641 - !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) { 5755 5755 + !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 5756 5756 + ecc->algo == NAND_ECC_ALGO_BCH)) { 5642 5757 switch (mtd->oobsize) { 5643 5758 case 8: 5644 5759 case 16: 5645 5645 - mtd_set_ooblayout(mtd, &nand_ooblayout_sp_ops); 5760 5760 + mtd_set_ooblayout(mtd, nand_get_small_page_ooblayout()); 5646 5761 break; 5647 5762 case 64: 5648 5763 case 128: 5649 5649 - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_hamming_ops); 5764 5764 + mtd_set_ooblayout(mtd, 5765 5765 + nand_get_large_page_hamming_ooblayout()); 5650 5766 break; 5651 5767 default: 5652 5768 /* ··· 5658 5770 * page with ECC layout when ->oobsize <= 128 for 5659 5771 * compatibility reasons. 5660 5772 */ 5661 5661 - if (ecc->mode == NAND_ECC_NONE) { 5773 5773 + if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) { 5662 5774 mtd_set_ooblayout(mtd, 5663 5663 - &nand_ooblayout_lp_ops); 5775 5775 + nand_get_large_page_ooblayout()); 5664 5776 break; 5665 5777 } 5666 5778 ··· 5676 5788 * selected and we have 256 byte pagesize fallback to software ECC 5677 5789 */ 5678 5790 5679 5679 - switch (ecc->mode) { 5680 5680 - case NAND_ECC_HW: 5681 5681 - /* Use standard hwecc read page function? */ 5682 5682 - if (!ecc->read_page) 5683 5683 - ecc->read_page = nand_read_page_hwecc; 5684 5684 - if (!ecc->write_page) 5685 5685 - ecc->write_page = nand_write_page_hwecc; 5686 5686 - if (!ecc->read_page_raw) 5687 5687 - ecc->read_page_raw = nand_read_page_raw; 5688 5688 - if (!ecc->write_page_raw) 5689 5689 - ecc->write_page_raw = nand_write_page_raw; 5690 5690 - if (!ecc->read_oob) 5691 5691 - ecc->read_oob = nand_read_oob_std; 5692 5692 - if (!ecc->write_oob) 5693 5693 - ecc->write_oob = nand_write_oob_std; 5694 5694 - if (!ecc->read_subpage) 5695 5695 - ecc->read_subpage = nand_read_subpage; 5696 5696 - if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) 5697 5697 - ecc->write_subpage = nand_write_subpage_hwecc; 5698 5698 - fallthrough; 5699 5699 - case NAND_ECC_HW_SYNDROME: 5700 5700 - if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && 5701 5701 - (!ecc->read_page || 5702 5702 - ecc->read_page == nand_read_page_hwecc || 5703 5703 - !ecc->write_page || 5704 5704 - ecc->write_page == nand_write_page_hwecc)) { 5705 5705 - WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); 5706 5706 - ret = -EINVAL; 5791 5791 + switch (ecc->engine_type) { 5792 5792 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 5793 5793 + ret = nand_set_ecc_on_host_ops(chip); 5794 5794 + if (ret) 5707 5795 goto err_nand_manuf_cleanup; 5708 5708 - } 5709 5709 - /* Use standard syndrome read/write page function? */ 5710 5710 - if (!ecc->read_page) 5711 5711 - ecc->read_page = nand_read_page_syndrome; 5712 5712 - if (!ecc->write_page) 5713 5713 - ecc->write_page = nand_write_page_syndrome; 5714 5714 - if (!ecc->read_page_raw) 5715 5715 - ecc->read_page_raw = nand_read_page_raw_syndrome; 5716 5716 - if (!ecc->write_page_raw) 5717 5717 - ecc->write_page_raw = nand_write_page_raw_syndrome; 5718 5718 - if (!ecc->read_oob) 5719 5719 - ecc->read_oob = nand_read_oob_syndrome; 5720 5720 - if (!ecc->write_oob) 5721 5721 - ecc->write_oob = nand_write_oob_syndrome; 5722 5796 5723 5797 if (mtd->writesize >= ecc->size) { 5724 5798 if (!ecc->strength) { ··· 5692 5842 } 5693 5843 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", 5694 5844 ecc->size, mtd->writesize); 5695 5695 - ecc->mode = NAND_ECC_SOFT; 5696 5696 - ecc->algo = NAND_ECC_HAMMING; 5845 5845 + ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 5846 5846 + ecc->algo = NAND_ECC_ALGO_HAMMING; 5697 5847 fallthrough; 5698 5698 - case NAND_ECC_SOFT: 5848 5848 + 5849 5849 + case NAND_ECC_ENGINE_TYPE_SOFT: 5699 5850 ret = nand_set_ecc_soft_ops(chip); 5700 5700 - if (ret) { 5701 5701 - ret = -EINVAL; 5851 5851 + if (ret) 5702 5852 goto err_nand_manuf_cleanup; 5703 5703 - } 5704 5853 break; 5705 5854 5706 5706 - case NAND_ECC_ON_DIE: 5855 5855 + case NAND_ECC_ENGINE_TYPE_ON_DIE: 5707 5856 if (!ecc->read_page || !ecc->write_page) { 5708 5857 WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); 5709 5858 ret = -EINVAL; ··· 5714 5865 ecc->write_oob = nand_write_oob_std; 5715 5866 break; 5716 5867 5717 5717 - case NAND_ECC_NONE: 5718 5718 - pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n"); 5868 5868 + case NAND_ECC_ENGINE_TYPE_NONE: 5869 5869 + pr_warn("NAND_ECC_ENGINE_TYPE_NONE selected by board driver. This is not recommended!\n"); 5719 5870 ecc->read_page = nand_read_page_raw; 5720 5871 ecc->write_page = nand_write_page_raw; 5721 5872 ecc->read_oob = nand_read_oob_std; ··· 5728 5879 break; 5729 5880 5730 5881 default: 5731 5731 - WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->mode); 5882 5882 + WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type); 5732 5883 ret = -EINVAL; 5733 5884 goto err_nand_manuf_cleanup; 5734 5885 } ··· 5762 5913 ret = -EINVAL; 5763 5914 goto err_nand_manuf_cleanup; 5764 5915 } 5916 5916 + 5765 5917 ecc->total = ecc->steps * ecc->bytes; 5918 5918 + chip->base.ecc.ctx.total = ecc->total; 5919 5919 + 5766 5920 if (ecc->total > mtd->oobsize) { 5767 5921 WARN(1, "Total number of ECC bytes exceeded oobsize\n"); 5768 5922 ret = -EINVAL; ··· 5783 5931 mtd->oobavail = ret; 5784 5932 5785 5933 /* ECC sanity check: warn if it's too weak */ 5786 5786 - if (!nand_ecc_strength_good(chip)) 5934 5934 + if (!nand_ecc_is_strong_enough(&chip->base)) 5787 5935 pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one required by the NAND chip (%db/%dB)\n", 5788 5936 mtd->name, chip->ecc.strength, chip->ecc.size, 5789 5789 - chip->base.eccreq.strength, 5790 5790 - chip->base.eccreq.step_size); 5937 5937 + nanddev_get_ecc_requirements(&chip->base)->strength, 5938 5938 + nanddev_get_ecc_requirements(&chip->base)->step_size); 5791 5939 5792 5940 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ 5793 5941 if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) { ··· 5808 5956 chip->pagecache.page = -1; 5809 5957 5810 5958 /* Large page NAND with SOFT_ECC should support subpage reads */ 5811 5811 - switch (ecc->mode) { 5812 5812 - case NAND_ECC_SOFT: 5959 5959 + switch (ecc->engine_type) { 5960 5960 + case NAND_ECC_ENGINE_TYPE_SOFT: 5813 5961 if (chip->page_shift > 9) 5814 5962 chip->options |= NAND_SUBPAGE_READ; 5815 5963 break; ··· 5953 6101 */ 5954 6102 void nand_cleanup(struct nand_chip *chip) 5955 6103 { 5956 5956 - if (chip->ecc.mode == NAND_ECC_SOFT && 5957 5957 - chip->ecc.algo == NAND_ECC_BCH) 6104 6104 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT && 6105 6105 + chip->ecc.algo == NAND_ECC_ALGO_BCH) 5958 6106 nand_bch_free((struct nand_bch_control *)chip->ecc.priv); 5959 6107 5960 6108 nanddev_cleanup(&chip->base);

+1

drivers/mtd/nand/raw/nand_bch.c

reviewed

··· 165 165 */ 166 166 nand->ecc.steps = eccsteps; 167 167 nand->ecc.total = eccsteps * eccbytes; 168 168 + nand->base.ecc.ctx.total = nand->ecc.total; 168 169 if (mtd_ooblayout_count_eccbytes(mtd) != (eccsteps*eccbytes)) { 169 170 pr_warn("invalid ecc layout\n"); 170 171 goto fail;

+10 -5

drivers/mtd/nand/raw/nand_esmt.c

reviewed

··· 10 10 11 11 static void esmt_nand_decode_id(struct nand_chip *chip) 12 12 { 13 13 + struct nand_device *base = &chip->base; 14 14 + struct nand_ecc_props requirements = {}; 15 15 + 13 16 nand_decode_ext_id(chip); 14 17 15 18 /* Extract ECC requirements from 5th id byte. */ 16 19 if (chip->id.len >= 5 && nand_is_slc(chip)) { 17 17 - chip->base.eccreq.step_size = 512; 20 20 + requirements.step_size = 512; 18 21 switch (chip->id.data[4] & 0x3) { 19 22 case 0x0: 20 20 - chip->base.eccreq.strength = 4; 23 23 + requirements.strength = 4; 21 24 break; 22 25 case 0x1: 23 23 - chip->base.eccreq.strength = 2; 26 26 + requirements.strength = 2; 24 27 break; 25 28 case 0x2: 26 26 - chip->base.eccreq.strength = 1; 29 29 + requirements.strength = 1; 27 30 break; 28 31 default: 29 32 WARN(1, "Could not get ECC info"); 30 30 - chip->base.eccreq.step_size = 0; 33 33 + requirements.step_size = 0; 31 34 break; 32 35 } 33 36 } 37 37 + 38 38 + nanddev_set_ecc_requirements(base, &requirements); 34 39 } 35 40 36 41 static int esmt_nand_init(struct nand_chip *chip)

+24 -20

drivers/mtd/nand/raw/nand_hynix.c

reviewed

··· 495 495 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip, 496 496 bool valid_jedecid) 497 497 { 498 498 + struct nand_device *base = &chip->base; 499 499 + struct nand_ecc_props requirements = {}; 498 500 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7; 499 501 500 502 if (valid_jedecid) { 501 503 /* Reference: H27UCG8T2E datasheet */ 502 502 - chip->base.eccreq.step_size = 1024; 504 504 + requirements.step_size = 1024; 503 505 504 506 switch (ecc_level) { 505 507 case 0: 506 506 - chip->base.eccreq.step_size = 0; 507 507 - chip->base.eccreq.strength = 0; 508 508 + requirements.step_size = 0; 509 509 + requirements.strength = 0; 508 510 break; 509 511 case 1: 510 510 - chip->base.eccreq.strength = 4; 512 512 + requirements.strength = 4; 511 513 break; 512 514 case 2: 513 513 - chip->base.eccreq.strength = 24; 515 515 + requirements.strength = 24; 514 516 break; 515 517 case 3: 516 516 - chip->base.eccreq.strength = 32; 518 518 + requirements.strength = 32; 517 519 break; 518 520 case 4: 519 519 - chip->base.eccreq.strength = 40; 521 521 + requirements.strength = 40; 520 522 break; 521 523 case 5: 522 522 - chip->base.eccreq.strength = 50; 524 524 + requirements.strength = 50; 523 525 break; 524 526 case 6: 525 525 - chip->base.eccreq.strength = 60; 527 527 + requirements.strength = 60; 526 528 break; 527 529 default: 528 530 /* ··· 545 543 if (nand_tech < 3) { 546 544 /* > 26nm, reference: H27UBG8T2A datasheet */ 547 545 if (ecc_level < 5) { 548 548 - chip->base.eccreq.step_size = 512; 549 549 - chip->base.eccreq.strength = 1 << ecc_level; 546 546 + requirements.step_size = 512; 547 547 + requirements.strength = 1 << ecc_level; 550 548 } else if (ecc_level < 7) { 551 549 if (ecc_level == 5) 552 552 - chip->base.eccreq.step_size = 2048; 550 550 + requirements.step_size = 2048; 553 551 else 554 554 - chip->base.eccreq.step_size = 1024; 555 555 - chip->base.eccreq.strength = 24; 552 552 + requirements.step_size = 1024; 553 553 + requirements.strength = 24; 556 554 } else { 557 555 /* 558 556 * We should never reach this case, but if that ··· 565 563 } else { 566 564 /* <= 26nm, reference: H27UBG8T2B datasheet */ 567 565 if (!ecc_level) { 568 568 - chip->base.eccreq.step_size = 0; 569 569 - chip->base.eccreq.strength = 0; 566 566 + requirements.step_size = 0; 567 567 + requirements.strength = 0; 570 568 } else if (ecc_level < 5) { 571 571 - chip->base.eccreq.step_size = 512; 572 572 - chip->base.eccreq.strength = 1 << (ecc_level - 1); 569 569 + requirements.step_size = 512; 570 570 + requirements.strength = 1 << (ecc_level - 1); 573 571 } else { 574 574 - chip->base.eccreq.step_size = 1024; 575 575 - chip->base.eccreq.strength = 24 + 572 572 + requirements.step_size = 1024; 573 573 + requirements.strength = 24 + 576 574 (8 * (ecc_level - 5)); 577 575 } 578 576 } 579 577 } 578 578 + 579 579 + nanddev_set_ecc_requirements(base, &requirements); 580 580 } 581 581 582 582 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip,

+7 -2

drivers/mtd/nand/raw/nand_jedec.c

reviewed

··· 23 23 */ 24 24 int nand_jedec_detect(struct nand_chip *chip) 25 25 { 26 26 + struct nand_device *base = &chip->base; 26 27 struct mtd_info *mtd = nand_to_mtd(chip); 27 28 struct nand_memory_organization *memorg; 28 29 struct nand_jedec_params *p; ··· 121 120 ecc = &p->ecc_info[0]; 122 121 123 122 if (ecc->codeword_size >= 9) { 124 124 - chip->base.eccreq.strength = ecc->ecc_bits; 125 125 - chip->base.eccreq.step_size = 1 << ecc->codeword_size; 123 123 + struct nand_ecc_props requirements = { 124 124 + .strength = ecc->ecc_bits, 125 125 + .step_size = 1 << ecc->codeword_size, 126 126 + }; 127 127 + 128 128 + nanddev_set_ecc_requirements(base, &requirements); 126 129 } else { 127 130 pr_warn("Invalid codeword size\n"); 128 131 }

+14 -9

drivers/mtd/nand/raw/nand_micron.c

reviewed

··· 413 413 */ 414 414 static int micron_supports_on_die_ecc(struct nand_chip *chip) 415 415 { 416 416 + const struct nand_ecc_props *requirements = 417 417 + nanddev_get_ecc_requirements(&chip->base); 416 418 u8 id[5]; 417 419 int ret; 418 420 ··· 427 425 /* 428 426 * We only support on-die ECC of 4/512 or 8/512 429 427 */ 430 430 - if (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8) 428 428 + if (requirements->strength != 4 && requirements->strength != 8) 431 429 return MICRON_ON_DIE_UNSUPPORTED; 432 430 433 431 /* 0x2 means on-die ECC is available. */ ··· 468 466 /* 469 467 * We only support on-die ECC of 4/512 or 8/512 470 468 */ 471 471 - if (chip->base.eccreq.strength != 4 && chip->base.eccreq.strength != 8) 469 469 + if (requirements->strength != 4 && requirements->strength != 8) 472 470 return MICRON_ON_DIE_UNSUPPORTED; 473 471 474 472 return MICRON_ON_DIE_SUPPORTED; ··· 476 474 477 475 static int micron_nand_init(struct nand_chip *chip) 478 476 { 477 477 + struct nand_device *base = &chip->base; 478 478 + const struct nand_ecc_props *requirements = 479 479 + nanddev_get_ecc_requirements(base); 479 480 struct mtd_info *mtd = nand_to_mtd(chip); 480 481 struct micron_nand *micron; 481 482 int ondie; ··· 502 497 ondie = micron_supports_on_die_ecc(chip); 503 498 504 499 if (ondie == MICRON_ON_DIE_MANDATORY && 505 505 - chip->ecc.mode != NAND_ECC_ON_DIE) { 500 500 + chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_DIE) { 506 501 pr_err("On-die ECC forcefully enabled, not supported\n"); 507 502 ret = -EINVAL; 508 503 goto err_free_manuf_data; 509 504 } 510 505 511 511 - if (chip->ecc.mode == NAND_ECC_ON_DIE) { 506 506 + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE) { 512 507 if (ondie == MICRON_ON_DIE_UNSUPPORTED) { 513 508 pr_err("On-die ECC selected but not supported\n"); 514 509 ret = -EINVAL; ··· 528 523 * That's not needed for 8-bit ECC, because the status expose 529 524 * a better approximation of the number of bitflips in a page. 530 525 */ 531 531 - if (chip->base.eccreq.strength == 4) { 526 526 + if (requirements->strength == 4) { 532 527 micron->ecc.rawbuf = kmalloc(mtd->writesize + 533 528 mtd->oobsize, 534 529 GFP_KERNEL); ··· 538 533 } 539 534 } 540 535 541 541 - if (chip->base.eccreq.strength == 4) 536 536 + if (requirements->strength == 4) 542 537 mtd_set_ooblayout(mtd, 543 538 &micron_nand_on_die_4_ooblayout_ops); 544 539 else 545 540 mtd_set_ooblayout(mtd, 546 541 &micron_nand_on_die_8_ooblayout_ops); 547 542 548 548 - chip->ecc.bytes = chip->base.eccreq.strength * 2; 543 543 + chip->ecc.bytes = requirements->strength * 2; 549 544 chip->ecc.size = 512; 550 550 - chip->ecc.strength = chip->base.eccreq.strength; 551 551 - chip->ecc.algo = NAND_ECC_BCH; 545 545 + chip->ecc.strength = requirements->strength; 546 546 + chip->ecc.algo = NAND_ECC_ALGO_BCH; 552 547 chip->ecc.read_page = micron_nand_read_page_on_die_ecc; 553 548 chip->ecc.write_page = micron_nand_write_page_on_die_ecc; 554 549

+13 -4

drivers/mtd/nand/raw/nand_onfi.c

reviewed

··· 34 34 static int nand_flash_detect_ext_param_page(struct nand_chip *chip, 35 35 struct nand_onfi_params *p) 36 36 { 37 37 + struct nand_device *base = &chip->base; 38 38 + struct nand_ecc_props requirements; 37 39 struct onfi_ext_param_page *ep; 38 40 struct onfi_ext_section *s; 39 41 struct onfi_ext_ecc_info *ecc; ··· 96 94 goto ext_out; 97 95 } 98 96 99 99 - chip->base.eccreq.strength = ecc->ecc_bits; 100 100 - chip->base.eccreq.step_size = 1 << ecc->codeword_size; 97 97 + requirements.strength = ecc->ecc_bits; 98 98 + requirements.step_size = 1 << ecc->codeword_size; 99 99 + nanddev_set_ecc_requirements(base, &requirements); 100 100 + 101 101 ret = 0; 102 102 103 103 ext_out: ··· 143 139 */ 144 140 int nand_onfi_detect(struct nand_chip *chip) 145 141 { 142 142 + struct nand_device *base = &chip->base; 146 143 struct mtd_info *mtd = nand_to_mtd(chip); 147 144 struct nand_memory_organization *memorg; 148 145 struct nand_onfi_params *p = NULL, *pbuf; ··· 270 265 chip->options |= NAND_BUSWIDTH_16; 271 266 272 267 if (p->ecc_bits != 0xff) { 273 273 - chip->base.eccreq.strength = p->ecc_bits; 274 274 - chip->base.eccreq.step_size = 512; 268 268 + struct nand_ecc_props requirements = { 269 269 + .strength = p->ecc_bits, 270 270 + .step_size = 512, 271 271 + }; 272 272 + 273 273 + nanddev_set_ecc_requirements(base, &requirements); 275 274 } else if (onfi_version >= 21 && 276 275 (le16_to_cpu(p->features) & ONFI_FEATURE_EXT_PARAM_PAGE)) { 277 276

+13 -9

drivers/mtd/nand/raw/nand_samsung.c

reviewed

··· 10 10 11 11 static void samsung_nand_decode_id(struct nand_chip *chip) 12 12 { 13 13 + struct nand_device *base = &chip->base; 14 14 + struct nand_ecc_props requirements = {}; 13 15 struct mtd_info *mtd = nand_to_mtd(chip); 14 16 struct nand_memory_organization *memorg; 15 17 ··· 73 71 /* Extract ECC requirements from 5th id byte*/ 74 72 extid = (chip->id.data[4] >> 4) & 0x07; 75 73 if (extid < 5) { 76 76 - chip->base.eccreq.step_size = 512; 77 77 - chip->base.eccreq.strength = 1 << extid; 74 74 + requirements.step_size = 512; 75 75 + requirements.strength = 1 << extid; 78 76 } else { 79 79 - chip->base.eccreq.step_size = 1024; 77 77 + requirements.step_size = 1024; 80 78 switch (extid) { 81 79 case 5: 82 82 - chip->base.eccreq.strength = 24; 80 80 + requirements.strength = 24; 83 81 break; 84 82 case 6: 85 85 - chip->base.eccreq.strength = 40; 83 83 + requirements.strength = 40; 86 84 break; 87 85 case 7: 88 88 - chip->base.eccreq.strength = 60; 86 86 + requirements.strength = 60; 89 87 break; 90 88 default: 91 89 WARN(1, "Could not decode ECC info"); 92 92 - chip->base.eccreq.step_size = 0; 90 90 + requirements.step_size = 0; 93 91 } 94 92 } 95 93 } else { ··· 99 97 switch (chip->id.data[1]) { 100 98 /* K9F4G08U0D-S[I|C]B0(T00) */ 101 99 case 0xDC: 102 102 - chip->base.eccreq.step_size = 512; 103 103 - chip->base.eccreq.strength = 1; 100 100 + requirements.step_size = 512; 101 101 + requirements.strength = 1; 104 102 break; 105 103 106 104 /* K9F1G08U0E 21nm chips do not support subpage write */ ··· 114 112 } 115 113 } 116 114 } 115 115 + 116 116 + nanddev_set_ecc_requirements(base, &requirements); 117 117 } 118 118 119 119 static int samsung_nand_init(struct nand_chip *chip)

+12 -7

drivers/mtd/nand/raw/nand_toshiba.c

reviewed

··· 140 140 141 141 chip->options |= NAND_SUBPAGE_READ; 142 142 143 143 - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 143 143 + mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 144 144 } 145 145 146 146 static void toshiba_nand_decode_id(struct nand_chip *chip) 147 147 { 148 148 + struct nand_device *base = &chip->base; 149 149 + struct nand_ecc_props requirements = {}; 148 150 struct mtd_info *mtd = nand_to_mtd(chip); 149 151 struct nand_memory_organization *memorg; 150 152 ··· 177 175 * - 24nm: 8 bit ECC for each 512Byte is required. 178 176 */ 179 177 if (chip->id.len >= 6 && nand_is_slc(chip)) { 180 180 - chip->base.eccreq.step_size = 512; 178 178 + requirements.step_size = 512; 181 179 switch (chip->id.data[5] & 0x7) { 182 180 case 0x4: 183 183 - chip->base.eccreq.strength = 1; 181 181 + requirements.strength = 1; 184 182 break; 185 183 case 0x5: 186 186 - chip->base.eccreq.strength = 4; 184 184 + requirements.strength = 4; 187 185 break; 188 186 case 0x6: 189 189 - chip->base.eccreq.strength = 8; 187 187 + requirements.strength = 8; 190 188 break; 191 189 default: 192 190 WARN(1, "Could not get ECC info"); 193 193 - chip->base.eccreq.step_size = 0; 191 191 + requirements.step_size = 0; 194 192 break; 195 193 } 196 194 } 195 195 + 196 196 + nanddev_set_ecc_requirements(base, &requirements); 197 197 } 198 198 199 199 static int ··· 277 273 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE; 278 274 279 275 /* Check that chip is BENAND and ECC mode is on-die */ 280 280 - if (nand_is_slc(chip) && chip->ecc.mode == NAND_ECC_ON_DIE && 276 276 + if (nand_is_slc(chip) && 277 277 + chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE && 281 278 chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND) 282 279 toshiba_nand_benand_init(chip); 283 280

+4 -4

drivers/mtd/nand/raw/nandsim.c

reviewed

··· 2234 2234 return -EINVAL; 2235 2235 } 2236 2236 2237 2237 - chip->ecc.mode = NAND_ECC_SOFT; 2238 2238 - chip->ecc.algo = NAND_ECC_BCH; 2237 2237 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 2238 2238 + chip->ecc.algo = NAND_ECC_ALGO_BCH; 2239 2239 chip->ecc.size = 512; 2240 2240 chip->ecc.strength = bch; 2241 2241 chip->ecc.bytes = eccbytes; ··· 2274 2274 nsmtd = nand_to_mtd(chip); 2275 2275 nand_set_controller_data(chip, (void *)ns); 2276 2276 2277 2277 - chip->ecc.mode = NAND_ECC_SOFT; 2278 2278 - chip->ecc.algo = NAND_ECC_HAMMING; 2277 2277 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 2278 2278 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2279 2279 /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */ 2280 2280 /* and 'badblocks' parameters to work */ 2281 2281 chip->options |= NAND_SKIP_BBTSCAN;

+1 -1

drivers/mtd/nand/raw/ndfc.c

reviewed

··· 149 149 chip->ecc.correct = nand_correct_data; 150 150 chip->ecc.hwctl = ndfc_enable_hwecc; 151 151 chip->ecc.calculate = ndfc_calculate_ecc; 152 152 - chip->ecc.mode = NAND_ECC_HW; 152 152 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 153 153 chip->ecc.size = 256; 154 154 chip->ecc.bytes = 3; 155 155 chip->ecc.strength = 1;

+11 -11

drivers/mtd/nand/raw/omap2.c

reviewed

··· 884 884 int stat = 0; 885 885 886 886 /* Ex NAND_ECC_HW12_2048 */ 887 887 - if ((info->nand.ecc.mode == NAND_ECC_HW) && 888 888 - (info->nand.ecc.size == 2048)) 887 887 + if (info->nand.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST && 888 888 + info->nand.ecc.size == 2048) 889 889 blockCnt = 4; 890 890 else 891 891 blockCnt = 1; ··· 2006 2006 return -EINVAL; 2007 2007 2008 2008 /* 2009 2009 - * Bail out earlier to let NAND_ECC_SOFT code create its own 2009 2009 + * Bail out earlier to let NAND_ECC_ENGINE_TYPE_SOFT code create its own 2010 2010 * ooblayout instead of using ours. 2011 2011 */ 2012 2012 if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) { 2013 2013 - chip->ecc.mode = NAND_ECC_SOFT; 2014 2014 - chip->ecc.algo = NAND_ECC_HAMMING; 2013 2013 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 2014 2014 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 2015 2015 return 0; 2016 2016 } 2017 2017 ··· 2019 2019 switch (info->ecc_opt) { 2020 2020 case OMAP_ECC_HAM1_CODE_HW: 2021 2021 dev_info(dev, "nand: using OMAP_ECC_HAM1_CODE_HW\n"); 2022 2022 - chip->ecc.mode = NAND_ECC_HW; 2022 2022 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2023 2023 chip->ecc.bytes = 3; 2024 2024 chip->ecc.size = 512; 2025 2025 chip->ecc.strength = 1; ··· 2036 2036 2037 2037 case OMAP_ECC_BCH4_CODE_HW_DETECTION_SW: 2038 2038 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW_DETECTION_SW\n"); 2039 2039 - chip->ecc.mode = NAND_ECC_HW; 2039 2039 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2040 2040 chip->ecc.size = 512; 2041 2041 chip->ecc.bytes = 7; 2042 2042 chip->ecc.strength = 4; ··· 2056 2056 2057 2057 case OMAP_ECC_BCH4_CODE_HW: 2058 2058 pr_info("nand: using OMAP_ECC_BCH4_CODE_HW ECC scheme\n"); 2059 2059 - chip->ecc.mode = NAND_ECC_HW; 2059 2059 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2060 2060 chip->ecc.size = 512; 2061 2061 /* 14th bit is kept reserved for ROM-code compatibility */ 2062 2062 chip->ecc.bytes = 7 + 1; ··· 2078 2078 2079 2079 case OMAP_ECC_BCH8_CODE_HW_DETECTION_SW: 2080 2080 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW_DETECTION_SW\n"); 2081 2081 - chip->ecc.mode = NAND_ECC_HW; 2081 2081 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2082 2082 chip->ecc.size = 512; 2083 2083 chip->ecc.bytes = 13; 2084 2084 chip->ecc.strength = 8; ··· 2098 2098 2099 2099 case OMAP_ECC_BCH8_CODE_HW: 2100 2100 pr_info("nand: using OMAP_ECC_BCH8_CODE_HW ECC scheme\n"); 2101 2101 - chip->ecc.mode = NAND_ECC_HW; 2101 2101 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2102 2102 chip->ecc.size = 512; 2103 2103 /* 14th bit is kept reserved for ROM-code compatibility */ 2104 2104 chip->ecc.bytes = 13 + 1; ··· 2121 2121 2122 2122 case OMAP_ECC_BCH16_CODE_HW: 2123 2123 pr_info("Using OMAP_ECC_BCH16_CODE_HW ECC scheme\n"); 2124 2124 - chip->ecc.mode = NAND_ECC_HW; 2124 2124 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2125 2125 chip->ecc.size = 512; 2126 2126 chip->ecc.bytes = 26; 2127 2127 chip->ecc.strength = 16;

+2 -2

drivers/mtd/nand/raw/orion_nand.c

reviewed

··· 139 139 nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base; 140 140 nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl; 141 141 nc->legacy.read_buf = orion_nand_read_buf; 142 142 - nc->ecc.mode = NAND_ECC_SOFT; 143 143 - nc->ecc.algo = NAND_ECC_HAMMING; 142 142 + nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 143 143 + nc->ecc.algo = NAND_ECC_ALGO_HAMMING; 144 144 145 145 if (board->chip_delay) 146 146 nc->legacy.chip_delay = board->chip_delay;

+3 -3

drivers/mtd/nand/raw/pasemi_nand.c

reviewed

··· 68 68 inl(lpcctl); 69 69 } 70 70 71 71 - int pasemi_device_ready(struct nand_chip *chip) 71 71 + static int pasemi_device_ready(struct nand_chip *chip) 72 72 { 73 73 return !!(inl(lpcctl) & LBICTRL_LPCCTL_NR); 74 74 } ··· 132 132 chip->legacy.read_buf = pasemi_read_buf; 133 133 chip->legacy.write_buf = pasemi_write_buf; 134 134 chip->legacy.chip_delay = 0; 135 135 - chip->ecc.mode = NAND_ECC_SOFT; 136 136 - chip->ecc.algo = NAND_ECC_HAMMING; 135 135 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 136 136 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 137 137 138 138 /* Enable the following for a flash based bad block table */ 139 139 chip->bbt_options = NAND_BBT_USE_FLASH;

+2 -2

drivers/mtd/nand/raw/plat_nand.c

reviewed

··· 66 66 data->chip.options |= pdata->chip.options; 67 67 data->chip.bbt_options |= pdata->chip.bbt_options; 68 68 69 69 - data->chip.ecc.mode = NAND_ECC_SOFT; 70 70 - data->chip.ecc.algo = NAND_ECC_HAMMING; 69 69 + data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 70 70 + data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 71 71 72 72 platform_set_drvdata(pdev, data); 73 73

+9 -17

drivers/mtd/nand/raw/qcom_nandc.c

reviewed

··· 2550 2550 ecc->write_page_raw = qcom_nandc_write_page_raw; 2551 2551 ecc->write_oob = qcom_nandc_write_oob; 2552 2552 2553 2553 - ecc->mode = NAND_ECC_HW; 2553 2553 + ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 2554 2554 2555 2555 mtd_set_ooblayout(mtd, &qcom_nand_ooblayout_ops); 2556 2556 ··· 2702 2702 if (IS_ERR(nandc->tx_chan)) { 2703 2703 ret = PTR_ERR(nandc->tx_chan); 2704 2704 nandc->tx_chan = NULL; 2705 2705 - if (ret != -EPROBE_DEFER) 2706 2706 - dev_err(nandc->dev, 2707 2707 - "tx DMA channel request failed: %d\n", 2708 2708 - ret); 2705 2705 + dev_err_probe(nandc->dev, ret, 2706 2706 + "tx DMA channel request failed\n"); 2709 2707 goto unalloc; 2710 2708 } 2711 2709 ··· 2711 2713 if (IS_ERR(nandc->rx_chan)) { 2712 2714 ret = PTR_ERR(nandc->rx_chan); 2713 2715 nandc->rx_chan = NULL; 2714 2714 - if (ret != -EPROBE_DEFER) 2715 2715 - dev_err(nandc->dev, 2716 2716 - "rx DMA channel request failed: %d\n", 2717 2717 - ret); 2716 2716 + dev_err_probe(nandc->dev, ret, 2717 2717 + "rx DMA channel request failed\n"); 2718 2718 goto unalloc; 2719 2719 } 2720 2720 ··· 2720 2724 if (IS_ERR(nandc->cmd_chan)) { 2721 2725 ret = PTR_ERR(nandc->cmd_chan); 2722 2726 nandc->cmd_chan = NULL; 2723 2723 - if (ret != -EPROBE_DEFER) 2724 2724 - dev_err(nandc->dev, 2725 2725 - "cmd DMA channel request failed: %d\n", 2726 2726 - ret); 2727 2727 + dev_err_probe(nandc->dev, ret, 2728 2728 + "cmd DMA channel request failed\n"); 2727 2729 goto unalloc; 2728 2730 } 2729 2731 ··· 2744 2750 if (IS_ERR(nandc->chan)) { 2745 2751 ret = PTR_ERR(nandc->chan); 2746 2752 nandc->chan = NULL; 2747 2747 - if (ret != -EPROBE_DEFER) 2748 2748 - dev_err(nandc->dev, 2749 2749 - "rxtx DMA channel request failed: %d\n", 2750 2750 - ret); 2753 2753 + dev_err_probe(nandc->dev, ret, 2754 2754 + "rxtx DMA channel request failed\n"); 2751 2755 return ret; 2752 2756 } 2753 2757 }

+2 -1

drivers/mtd/nand/raw/r852.c

reviewed

··· 859 859 chip->legacy.write_buf = r852_write_buf; 860 860 861 861 /* ecc */ 862 862 - chip->ecc.mode = NAND_ECC_HW_SYNDROME; 862 862 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 863 863 + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED; 863 864 chip->ecc.size = R852_DMA_LEN; 864 865 chip->ecc.bytes = SM_OOB_SIZE; 865 866 chip->ecc.strength = 2;

+10 -10

drivers/mtd/nand/raw/s3c2410.c

reviewed

··· 904 904 nmtd->info = info; 905 905 nmtd->set = set; 906 906 907 907 - chip->ecc.mode = info->platform->ecc_mode; 907 907 + chip->ecc.engine_type = info->platform->engine_type; 908 908 909 909 /* 910 910 * If you use u-boot BBT creation code, specifying this flag will ··· 929 929 struct mtd_info *mtd = nand_to_mtd(chip); 930 930 struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd); 931 931 932 932 - switch (chip->ecc.mode) { 932 932 + switch (chip->ecc.engine_type) { 933 933 934 934 - case NAND_ECC_NONE: 934 934 + case NAND_ECC_ENGINE_TYPE_NONE: 935 935 dev_info(info->device, "ECC disabled\n"); 936 936 break; 937 937 938 938 - case NAND_ECC_SOFT: 938 938 + case NAND_ECC_ENGINE_TYPE_SOFT: 939 939 /* 940 940 - * This driver expects Hamming based ECC when ecc_mode is set 941 941 - * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to 942 942 - * avoid adding an extra ecc_algo field to 943 943 - * s3c2410_platform_nand. 940 940 + * This driver expects Hamming based ECC when engine_type is set 941 941 + * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to 942 942 + * NAND_ECC_ALGO_HAMMING to avoid adding an extra ecc_algo field 943 943 + * to s3c2410_platform_nand. 944 944 */ 945 945 - chip->ecc.algo = NAND_ECC_HAMMING; 945 945 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 946 946 dev_info(info->device, "soft ECC\n"); 947 947 break; 948 948 949 949 - case NAND_ECC_HW: 949 949 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 950 950 chip->ecc.calculate = s3c2410_nand_calculate_ecc; 951 951 chip->ecc.correct = s3c2410_nand_correct_data; 952 952 chip->ecc.strength = 1;

+3 -3

drivers/mtd/nand/raw/sh_flctl.c

reviewed

··· 1039 1039 chip->ecc.strength = 4; 1040 1040 chip->ecc.read_page = flctl_read_page_hwecc; 1041 1041 chip->ecc.write_page = flctl_write_page_hwecc; 1042 1042 - chip->ecc.mode = NAND_ECC_HW; 1042 1042 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1043 1043 1044 1044 /* 4 symbols ECC enabled */ 1045 1045 flctl->flcmncr_base |= _4ECCEN; 1046 1046 } else { 1047 1047 - chip->ecc.mode = NAND_ECC_SOFT; 1048 1048 - chip->ecc.algo = NAND_ECC_HAMMING; 1047 1047 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 1048 1048 + chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 1049 1049 } 1050 1050 1051 1051 return 0;

+1 -1

drivers/mtd/nand/raw/sharpsl.c

reviewed

··· 157 157 /* 15 us command delay time */ 158 158 this->legacy.chip_delay = 15; 159 159 /* set eccmode using hardware ECC */ 160 160 - this->ecc.mode = NAND_ECC_HW; 160 160 + this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 161 161 this->ecc.size = 256; 162 162 this->ecc.bytes = 3; 163 163 this->ecc.strength = 1;

+3 -2

drivers/mtd/nand/raw/socrates_nand.c

reviewed

··· 153 153 nand_chip->legacy.read_buf = socrates_nand_read_buf; 154 154 nand_chip->legacy.dev_ready = socrates_nand_device_ready; 155 155 156 156 - nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */ 157 157 - nand_chip->ecc.algo = NAND_ECC_HAMMING; 156 156 + /* enable ECC */ 157 157 + nand_chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 158 158 + nand_chip->ecc.algo = NAND_ECC_ALGO_HAMMING; 158 159 159 160 /* TODO: I have no idea what real delay is. */ 160 161 nand_chip->legacy.chip_delay = 20; /* 20us command delay time */

+6 -5

drivers/mtd/nand/raw/stm32_fmc2_nand.c

reviewed

··· 1696 1696 int ret; 1697 1697 1698 1698 /* 1699 1699 - * Only NAND_ECC_HW mode is actually supported 1699 1699 + * Only NAND_ECC_ENGINE_TYPE_ON_HOST mode is actually supported 1700 1700 * Hamming => ecc.strength = 1 1701 1701 * BCH4 => ecc.strength = 4 1702 1702 * BCH8 => ecc.strength = 8 1703 1703 * ECC sector size = 512 1704 1704 */ 1705 1705 - if (chip->ecc.mode != NAND_ECC_HW) { 1706 1706 - dev_err(nfc->dev, "nand_ecc_mode is not well defined in the DT\n"); 1705 1705 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) { 1706 1706 + dev_err(nfc->dev, 1707 1707 + "nand_ecc_engine_type is not well defined in the DT\n"); 1707 1708 return -EINVAL; 1708 1709 } 1709 1710 ··· 1763 1762 return ret; 1764 1763 } 1765 1764 1766 1766 - if (cs > FMC2_MAX_CE) { 1765 1765 + if (cs >= FMC2_MAX_CE) { 1767 1766 dev_err(nfc->dev, "invalid reg value: %d\n", cs); 1768 1767 return -EINVAL; 1769 1768 } ··· 1953 1952 NAND_USES_DMA; 1954 1953 1955 1954 /* Default ECC settings */ 1956 1956 - chip->ecc.mode = NAND_ECC_HW; 1955 1955 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1957 1956 chip->ecc.size = FMC2_ECC_STEP_SIZE; 1958 1957 chip->ecc.strength = FMC2_ECC_BCH8; 1959 1958

+15 -12

drivers/mtd/nand/raw/sunxi_nand.c

reviewed

··· 1575 1575 * only have 2 bytes available in the first user data 1576 1576 * section. 1577 1577 */ 1578 1578 - if (!section && ecc->mode == NAND_ECC_HW) { 1578 1578 + if (!section && ecc->engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 1579 1579 oobregion->offset = 2; 1580 1580 oobregion->length = 2; 1581 1581 ··· 1609 1609 static const u8 strengths[] = { 16, 24, 28, 32, 40, 48, 56, 60, 64 }; 1610 1610 struct sunxi_nfc *nfc = to_sunxi_nfc(nand->controller); 1611 1611 struct mtd_info *mtd = nand_to_mtd(nand); 1612 1612 + struct nand_device *nanddev = mtd_to_nanddev(mtd); 1612 1613 struct sunxi_nand_hw_ecc *data; 1613 1614 int nsectors; 1614 1615 int ret; 1615 1616 int i; 1616 1617 1617 1617 - if (ecc->options & NAND_ECC_MAXIMIZE) { 1618 1618 + if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) { 1618 1619 int bytes; 1619 1620 1620 1621 ecc->size = 1024; ··· 1721 1720 1722 1721 static void sunxi_nand_ecc_cleanup(struct nand_ecc_ctrl *ecc) 1723 1722 { 1724 1724 - switch (ecc->mode) { 1725 1725 - case NAND_ECC_HW: 1723 1723 + switch (ecc->engine_type) { 1724 1724 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 1726 1725 sunxi_nand_hw_ecc_ctrl_cleanup(ecc); 1727 1726 break; 1728 1728 - case NAND_ECC_NONE: 1727 1727 + case NAND_ECC_ENGINE_TYPE_NONE: 1729 1728 default: 1730 1729 break; 1731 1730 } ··· 1733 1732 1734 1733 static int sunxi_nand_attach_chip(struct nand_chip *nand) 1735 1734 { 1735 1735 + const struct nand_ecc_props *requirements = 1736 1736 + nanddev_get_ecc_requirements(&nand->base); 1736 1737 struct nand_ecc_ctrl *ecc = &nand->ecc; 1737 1738 struct device_node *np = nand_get_flash_node(nand); 1738 1739 int ret; ··· 1748 1745 nand->options |= NAND_SUBPAGE_READ; 1749 1746 1750 1747 if (!ecc->size) { 1751 1751 - ecc->size = nand->base.eccreq.step_size; 1752 1752 - ecc->strength = nand->base.eccreq.strength; 1748 1748 + ecc->size = requirements->step_size; 1749 1749 + ecc->strength = requirements->strength; 1753 1750 } 1754 1751 1755 1752 if (!ecc->size || !ecc->strength) 1756 1753 return -EINVAL; 1757 1754 1758 1758 - switch (ecc->mode) { 1759 1759 - case NAND_ECC_HW: 1755 1755 + switch (ecc->engine_type) { 1756 1756 + case NAND_ECC_ENGINE_TYPE_ON_HOST: 1760 1757 ret = sunxi_nand_hw_ecc_ctrl_init(nand, ecc, np); 1761 1758 if (ret) 1762 1759 return ret; 1763 1760 break; 1764 1764 - case NAND_ECC_NONE: 1765 1765 - case NAND_ECC_SOFT: 1761 1761 + case NAND_ECC_ENGINE_TYPE_NONE: 1762 1762 + case NAND_ECC_ENGINE_TYPE_SOFT: 1766 1763 break; 1767 1764 default: 1768 1765 return -EINVAL; ··· 1994 1991 * Set the ECC mode to the default value in case nothing is specified 1995 1992 * in the DT. 1996 1993 */ 1997 1997 - nand->ecc.mode = NAND_ECC_HW; 1994 1994 + nand->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 1998 1995 nand_set_flash_node(nand, np); 1999 1996 2000 1997 mtd = nand_to_mtd(nand);

+2 -2

drivers/mtd/nand/raw/tango_nand.c

reviewed

··· 549 549 { 550 550 struct nand_ecc_ctrl *ecc = &chip->ecc; 551 551 552 552 - ecc->mode = NAND_ECC_HW; 553 553 - ecc->algo = NAND_ECC_BCH; 552 552 + ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 553 553 + ecc->algo = NAND_ECC_ALGO_BCH; 554 554 ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE); 555 555 556 556 ecc->read_page_raw = tango_read_page_raw;

+21 -16

drivers/mtd/nand/raw/tegra_nand.c

reviewed

··· 479 479 { 480 480 struct tegra_nand_chip *nand = to_tegra_chip(chip); 481 481 482 482 - if (chip->ecc.algo == NAND_ECC_BCH && enable) 482 482 + if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable) 483 483 writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG); 484 484 else 485 485 writel_relaxed(0, ctrl->regs + BCH_CONFIG); ··· 840 840 int strength_len, int bits_per_step, 841 841 int oobsize) 842 842 { 843 843 - bool maximize = chip->ecc.options & NAND_ECC_MAXIMIZE; 843 843 + struct nand_device *base = mtd_to_nanddev(nand_to_mtd(chip)); 844 844 + const struct nand_ecc_props *requirements = 845 845 + nanddev_get_ecc_requirements(base); 846 846 + bool maximize = base->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH; 844 847 int i; 845 848 846 849 /* ··· 858 855 } else { 859 856 strength_sel = strength[i]; 860 857 861 861 - if (strength_sel < chip->base.eccreq.strength) 858 858 + if (strength_sel < requirements->strength) 862 859 continue; 863 860 } 864 861 ··· 880 877 int strength_len, bits_per_step; 881 878 882 879 switch (chip->ecc.algo) { 883 883 - case NAND_ECC_RS: 880 880 + case NAND_ECC_ALGO_RS: 884 881 bits_per_step = BITS_PER_STEP_RS; 885 882 if (chip->options & NAND_IS_BOOT_MEDIUM) { 886 883 strength = rs_strength_bootable; ··· 890 887 strength_len = ARRAY_SIZE(rs_strength); 891 888 } 892 889 break; 893 893 - case NAND_ECC_BCH: 890 890 + case NAND_ECC_ALGO_BCH: 894 891 bits_per_step = BITS_PER_STEP_BCH; 895 892 if (chip->options & NAND_IS_BOOT_MEDIUM) { 896 893 strength = bch_strength_bootable; ··· 911 908 static int tegra_nand_attach_chip(struct nand_chip *chip) 912 909 { 913 910 struct tegra_nand_controller *ctrl = to_tegra_ctrl(chip->controller); 911 911 + const struct nand_ecc_props *requirements = 912 912 + nanddev_get_ecc_requirements(&chip->base); 914 913 struct tegra_nand_chip *nand = to_tegra_chip(chip); 915 914 struct mtd_info *mtd = nand_to_mtd(chip); 916 915 int bits_per_step; ··· 921 916 if (chip->bbt_options & NAND_BBT_USE_FLASH) 922 917 chip->bbt_options |= NAND_BBT_NO_OOB; 923 918 924 924 - chip->ecc.mode = NAND_ECC_HW; 919 919 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 925 920 chip->ecc.size = 512; 926 921 chip->ecc.steps = mtd->writesize / chip->ecc.size; 927 927 - if (chip->base.eccreq.step_size != 512) { 922 922 + if (requirements->step_size != 512) { 928 923 dev_err(ctrl->dev, "Unsupported step size %d\n", 929 929 - chip->base.eccreq.step_size); 924 924 + requirements->step_size); 930 925 return -EINVAL; 931 926 } 932 927 ··· 940 935 if (chip->options & NAND_BUSWIDTH_16) 941 936 nand->config |= CONFIG_BUS_WIDTH_16; 942 937 943 943 - if (chip->ecc.algo == NAND_ECC_UNKNOWN) { 938 938 + if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) { 944 939 if (mtd->writesize < 2048) 945 945 - chip->ecc.algo = NAND_ECC_RS; 940 940 + chip->ecc.algo = NAND_ECC_ALGO_RS; 946 941 else 947 947 - chip->ecc.algo = NAND_ECC_BCH; 942 942 + chip->ecc.algo = NAND_ECC_ALGO_BCH; 948 943 } 949 944 950 950 - if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) { 945 945 + if (chip->ecc.algo == NAND_ECC_ALGO_BCH && mtd->writesize < 2048) { 951 946 dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n"); 952 947 return -EINVAL; 953 948 } ··· 957 952 if (ret < 0) { 958 953 dev_err(ctrl->dev, 959 954 "No valid strength found, minimum %d\n", 960 960 - chip->base.eccreq.strength); 955 955 + requirements->strength); 961 956 return ret; 962 957 } 963 958 ··· 968 963 CONFIG_SKIP_SPARE_SIZE_4; 969 964 970 965 switch (chip->ecc.algo) { 971 971 - case NAND_ECC_RS: 966 966 + case NAND_ECC_ALGO_RS: 972 967 bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength; 973 968 mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops); 974 969 nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL | ··· 989 984 return -EINVAL; 990 985 } 991 986 break; 992 992 - case NAND_ECC_BCH: 987 987 + case NAND_ECC_ALGO_BCH: 993 988 bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength; 994 989 mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops); 995 990 nand->bch_config = BCH_ENABLE; ··· 1018 1013 } 1019 1014 1020 1015 dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n", 1021 1021 - chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS", 1016 1016 + chip->ecc.algo == NAND_ECC_ALGO_BCH ? "BCH" : "RS", 1022 1017 chip->ecc.strength); 1023 1018 1024 1019 chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE);

+1 -1

drivers/mtd/nand/raw/tmio_nand.c

reviewed

··· 410 410 nand_chip->legacy.read_buf = tmio_nand_read_buf; 411 411 412 412 /* set eccmode using hardware ECC */ 413 413 - nand_chip->ecc.mode = NAND_ECC_HW; 413 413 + nand_chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 414 414 nand_chip->ecc.size = 512; 415 415 nand_chip->ecc.bytes = 6; 416 416 nand_chip->ecc.strength = 2;

+1 -1

drivers/mtd/nand/raw/txx9ndfmc.c

reviewed

··· 329 329 chip->ecc.calculate = txx9ndfmc_calculate_ecc; 330 330 chip->ecc.correct = txx9ndfmc_correct_data; 331 331 chip->ecc.hwctl = txx9ndfmc_enable_hwecc; 332 332 - chip->ecc.mode = NAND_ECC_HW; 332 332 + chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; 333 333 chip->ecc.strength = 1; 334 334 chip->legacy.chip_delay = 100; 335 335 chip->controller = &drvdata->controller;

+7 -10

drivers/mtd/nand/raw/vf610_nfc.c

reviewed

··· 323 323 CONFIG_ECC_MODE_SHIFT, ecc_mode); 324 324 } 325 325 326 326 - static inline void vf610_nfc_transfer_size(struct vf610_nfc *nfc, int size) 327 327 - { 328 328 - vf610_nfc_write(nfc, NFC_SECTOR_SIZE, size); 329 329 - } 330 330 - 331 326 static inline void vf610_nfc_run(struct vf610_nfc *nfc, u32 col, u32 row, 332 327 u32 cmd1, u32 cmd2, u32 trfr_sz) 333 328 { ··· 727 732 else 728 733 vf610_nfc_clear(nfc, NFC_FLASH_CONFIG, CONFIG_16BIT); 729 734 730 730 - if (nfc->chip.ecc.mode == NAND_ECC_HW) { 735 735 + if (nfc->chip.ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_HOST) { 731 736 /* Set ECC status offset in SRAM */ 732 737 vf610_nfc_set_field(nfc, NFC_FLASH_CONFIG, 733 738 CONFIG_ECC_SRAM_ADDR_MASK, ··· 756 761 return -ENXIO; 757 762 } 758 763 759 759 - if (chip->ecc.mode != NAND_ECC_HW) 764 764 + if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST) 760 765 return 0; 761 766 762 767 if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) { ··· 774 779 mtd->oobsize = 64; 775 780 776 781 /* Use default large page ECC layout defined in NAND core */ 777 777 - mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops); 782 782 + mtd_set_ooblayout(mtd, nand_get_large_page_ooblayout()); 778 783 if (chip->ecc.strength == 32) { 779 784 nfc->ecc_mode = ECC_60_BYTE; 780 785 chip->ecc.bytes = 60; ··· 847 852 } 848 853 849 854 of_id = of_match_device(vf610_nfc_dt_ids, &pdev->dev); 850 850 - if (!of_id) 851 851 - return -ENODEV; 855 855 + if (!of_id) { 856 856 + err = -ENODEV; 857 857 + goto err_disable_clk; 858 858 + } 852 859 853 860 nfc->variant = (enum vf610_nfc_variant)of_id->data; 854 861

+2 -2

drivers/mtd/nand/raw/xway_nand.c

reviewed

··· 180 180 data->chip.legacy.read_byte = xway_read_byte; 181 181 data->chip.legacy.chip_delay = 30; 182 182 183 183 - data->chip.ecc.mode = NAND_ECC_SOFT; 184 184 - data->chip.ecc.algo = NAND_ECC_HAMMING; 183 183 + data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; 184 184 + data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING; 185 185 186 186 platform_set_drvdata(pdev, data); 187 187 nand_set_controller_data(&data->chip, data);

+6 -6

drivers/mtd/nand/spi/core.c

reviewed

··· 419 419 * fixed, so let's return the maximum possible value so that 420 420 * wear-leveling layers move the data immediately. 421 421 */ 422 422 - return nand->eccreq.strength; 422 422 + return nanddev_get_ecc_conf(nand)->strength; 423 423 424 424 case STATUS_ECC_UNCOR_ERROR: 425 425 return -EBADMSG; ··· 497 497 498 498 mutex_lock(&spinand->lock); 499 499 500 500 - nanddev_io_for_each_page(nand, from, ops, &iter) { 500 500 + nanddev_io_for_each_page(nand, NAND_PAGE_READ, from, ops, &iter) { 501 501 ret = spinand_select_target(spinand, iter.req.pos.target); 502 502 if (ret) 503 503 break; ··· 545 545 546 546 mutex_lock(&spinand->lock); 547 547 548 548 - nanddev_io_for_each_page(nand, to, ops, &iter) { 548 548 + nanddev_io_for_each_page(nand, NAND_PAGE_WRITE, to, ops, &iter) { 549 549 ret = spinand_select_target(spinand, iter.req.pos.target); 550 550 if (ret) 551 551 break; ··· 902 902 continue; 903 903 904 904 nand->memorg = table[i].memorg; 905 905 - nand->eccreq = table[i].eccreq; 905 905 + nanddev_set_ecc_requirements(nand, &table[i].eccreq); 906 906 spinand->eccinfo = table[i].eccinfo; 907 907 spinand->flags = table[i].flags; 908 908 spinand->id.len = 1 + table[i].devid.len; ··· 1090 1090 mtd->oobavail = ret; 1091 1091 1092 1092 /* Propagate ECC information to mtd_info */ 1093 1093 - mtd->ecc_strength = nand->eccreq.strength; 1094 1094 - mtd->ecc_step_size = nand->eccreq.step_size; 1093 1093 + mtd->ecc_strength = nanddev_get_ecc_conf(nand)->strength; 1094 1094 + mtd->ecc_step_size = nanddev_get_ecc_conf(nand)->step_size; 1095 1095 1096 1096 return 0; 1097 1097

+56 -7

drivers/mtd/nand/spi/gigadevice.c

reviewed

··· 21 21 #define GD5FXGQ4UXFXXG_STATUS_ECC_UNCOR_ERROR (7 << 4) 22 22 23 23 static SPINAND_OP_VARIANTS(read_cache_variants, 24 24 - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), 24 24 + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), 25 25 SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), 26 26 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), 27 27 SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ··· 29 29 SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); 30 30 31 31 static SPINAND_OP_VARIANTS(read_cache_variants_f, 32 32 - SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), 32 32 + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), 33 33 SPINAND_PAGE_READ_FROM_CACHE_X4_OP_3A(0, 1, NULL, 0), 34 34 SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), 35 35 SPINAND_PAGE_READ_FROM_CACHE_X2_OP_3A(0, 1, NULL, 0), ··· 132 132 .free = gd5fxgq4_variant2_ooblayout_free, 133 133 }; 134 134 135 135 + static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section, 136 136 + struct mtd_oob_region *oobregion) 137 137 + { 138 138 + if (section) 139 139 + return -ERANGE; 140 140 + 141 141 + oobregion->offset = 128; 142 142 + oobregion->length = 128; 143 143 + 144 144 + return 0; 145 145 + } 146 146 + 147 147 + static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section, 148 148 + struct mtd_oob_region *oobregion) 149 149 + { 150 150 + if (section) 151 151 + return -ERANGE; 152 152 + 153 153 + oobregion->offset = 1; 154 154 + oobregion->length = 127; 155 155 + 156 156 + return 0; 157 157 + } 158 158 + 159 159 + static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = { 160 160 + .ecc = gd5fxgq4xc_ooblayout_256_ecc, 161 161 + .free = gd5fxgq4xc_ooblayout_256_free, 162 162 + }; 163 163 + 135 164 static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand, 136 165 u8 status) 137 166 { ··· 231 202 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 232 203 &write_cache_variants, 233 204 &update_cache_variants), 234 234 - 0, 205 205 + SPINAND_HAS_QE_BIT, 235 206 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, 236 207 gd5fxgq4xa_ecc_get_status)), 237 208 SPINAND_INFO("GD5F2GQ4xA", ··· 241 212 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 242 213 &write_cache_variants, 243 214 &update_cache_variants), 244 244 - 0, 215 215 + SPINAND_HAS_QE_BIT, 245 216 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, 246 217 gd5fxgq4xa_ecc_get_status)), 247 218 SPINAND_INFO("GD5F4GQ4xA", ··· 251 222 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 252 223 &write_cache_variants, 253 224 &update_cache_variants), 254 254 - 0, 225 225 + SPINAND_HAS_QE_BIT, 255 226 SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, 256 227 gd5fxgq4xa_ecc_get_status)), 228 228 + SPINAND_INFO("GD5F4GQ4RC", 229 229 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xa4, 0x68), 230 230 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 231 231 + NAND_ECCREQ(8, 512), 232 232 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, 233 233 + &write_cache_variants, 234 234 + &update_cache_variants), 235 235 + SPINAND_HAS_QE_BIT, 236 236 + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, 237 237 + gd5fxgq4ufxxg_ecc_get_status)), 238 238 + SPINAND_INFO("GD5F4GQ4UC", 239 239 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb4, 0x68), 240 240 + NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1), 241 241 + NAND_ECCREQ(8, 512), 242 242 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, 243 243 + &write_cache_variants, 244 244 + &update_cache_variants), 245 245 + SPINAND_HAS_QE_BIT, 246 246 + SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops, 247 247 + gd5fxgq4ufxxg_ecc_get_status)), 257 248 SPINAND_INFO("GD5F1GQ4UExxG", 258 249 SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xd1), 259 250 NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ··· 281 232 SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 282 233 &write_cache_variants, 283 234 &update_cache_variants), 284 284 - 0, 235 235 + SPINAND_HAS_QE_BIT, 285 236 SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, 286 237 gd5fxgq4uexxg_ecc_get_status)), 287 238 SPINAND_INFO("GD5F1GQ4UFxxG", ··· 291 242 SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, 292 243 &write_cache_variants, 293 244 &update_cache_variants), 294 294 - 0, 245 245 + SPINAND_HAS_QE_BIT, 295 246 SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, 296 247 gd5fxgq4ufxxg_ecc_get_status)), 297 248 };

+24 -3

drivers/mtd/nand/spi/macronix.c

reviewed

··· 84 84 * data around if it's not necessary. 85 85 */ 86 86 if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr)) 87 87 - return nand->eccreq.strength; 87 87 + return nanddev_get_ecc_conf(nand)->strength; 88 88 89 89 - if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr)) 90 90 - return nand->eccreq.strength; 89 89 + if (WARN_ON(eccsr > nanddev_get_ecc_conf(nand)->strength || 90 90 + !eccsr)) 91 91 + return nanddev_get_ecc_conf(nand)->strength; 91 92 92 93 return eccsr; 93 94 ··· 119 118 &update_cache_variants), 120 119 SPINAND_HAS_QE_BIT, 121 120 SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)), 121 121 + SPINAND_INFO("MX31LF1GE4BC", 122 122 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x1e), 123 123 + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 124 124 + NAND_ECCREQ(8, 512), 125 125 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 126 126 + &write_cache_variants, 127 127 + &update_cache_variants), 128 128 + 0 /*SPINAND_HAS_QE_BIT*/, 129 129 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, 130 130 + mx35lf1ge4ab_ecc_get_status)), 131 131 + SPINAND_INFO("MX31UF1GE4BC", 132 132 + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x9e), 133 133 + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), 134 134 + NAND_ECCREQ(8, 512), 135 135 + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, 136 136 + &write_cache_variants, 137 137 + &update_cache_variants), 138 138 + 0 /*SPINAND_HAS_QE_BIT*/, 139 139 + SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, 140 140 + mx35lf1ge4ab_ecc_get_status)), 122 141 }; 123 142 124 143 static const struct spinand_manufacturer_ops macronix_spinand_manuf_ops = {

+3 -3

drivers/mtd/nand/spi/toshiba.c

reviewed

··· 90 90 * data around if it's not necessary. 91 91 */ 92 92 if (spi_mem_exec_op(spinand->spimem, &op)) 93 93 - return nand->eccreq.strength; 93 93 + return nanddev_get_ecc_conf(nand)->strength; 94 94 95 95 mbf >>= 4; 96 96 97 97 - if (WARN_ON(mbf > nand->eccreq.strength || !mbf)) 98 98 - return nand->eccreq.strength; 97 97 + if (WARN_ON(mbf > nanddev_get_ecc_conf(nand)->strength || !mbf)) 98 98 + return nanddev_get_ecc_conf(nand)->strength; 99 99 100 100 return mbf; 101 101

+1 -1

drivers/mtd/parsers/Kconfig

reviewed

··· 12 12 boards. 13 13 14 14 config MTD_BCM63XX_PARTS 15 15 - tristate "BCM63XX CFE partitioning parser" 15 15 + bool "BCM63XX CFE partitioning parser" 16 16 depends on BCM63XX || BMIPS_GENERIC || COMPILE_TEST 17 17 select CRC32 18 18 select MTD_PARSER_IMAGETAG

+1

drivers/mtd/spi-nor/controllers/intel-spi-pci.c

reviewed

··· 73 73 { PCI_VDEVICE(INTEL, 0x43a4), (unsigned long)&cnl_info }, 74 74 { PCI_VDEVICE(INTEL, 0x4b24), (unsigned long)&bxt_info }, 75 75 { PCI_VDEVICE(INTEL, 0x4da4), (unsigned long)&bxt_info }, 76 76 + { PCI_VDEVICE(INTEL, 0x7aa4), (unsigned long)&cnl_info }, 76 77 { PCI_VDEVICE(INTEL, 0xa0a4), (unsigned long)&bxt_info }, 77 78 { PCI_VDEVICE(INTEL, 0xa1a4), (unsigned long)&bxt_info }, 78 79 { PCI_VDEVICE(INTEL, 0xa224), (unsigned long)&bxt_info },

+1 -1

drivers/mtd/spi-nor/macronix.c

reviewed

··· 50 50 { "mx25u4035", INFO(0xc22533, 0, 64 * 1024, 8, SECT_4K) }, 51 51 { "mx25u8035", INFO(0xc22534, 0, 64 * 1024, 16, SECT_4K) }, 52 52 { "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) }, 53 53 - { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, 53 53 + { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, SECT_4K) }, 54 54 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, 55 55 { "mx25r1635f", INFO(0xc22815, 0, 64 * 1024, 32, 56 56 SECT_4K | SPI_NOR_DUAL_READ |

+9

drivers/mtd/spi-nor/winbond.c

reviewed

··· 63 63 { "w25q32jwm", INFO(0xef8016, 0, 64 * 1024, 64, 64 64 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 65 65 SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 66 66 + { "w25q64jwm", INFO(0xef8017, 0, 64 * 1024, 128, 67 67 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 68 68 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 69 69 + { "w25q128jwm", INFO(0xef8018, 0, 64 * 1024, 256, 70 70 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 71 71 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 72 72 + { "w25q256jwm", INFO(0xef8019, 0, 64 * 1024, 512, 73 73 + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | 74 74 + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, 66 75 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 67 76 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, 68 77 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },

+13

include/linux/mtd/hyperbus.h

reviewed

··· 8 8 9 9 #include <linux/mtd/map.h> 10 10 11 11 + /* HyperBus command bits */ 12 12 + #define HYPERBUS_RW 0x80 /* R/W# */ 13 13 + #define HYPERBUS_RW_WRITE 0 14 14 + #define HYPERBUS_RW_READ 0x80 15 15 + #define HYPERBUS_AS 0x40 /* Address Space */ 16 16 + #define HYPERBUS_AS_MEM 0 17 17 + #define HYPERBUS_AS_REG 0x40 18 18 + #define HYPERBUS_BT 0x20 /* Burst Type */ 19 19 + #define HYPERBUS_BT_WRAPPED 0 20 20 + #define HYPERBUS_BT_LINEAR 0x20 21 21 + 11 22 enum hyperbus_memtype { 12 23 HYPERFLASH, 13 24 HYPERRAM, ··· 31 20 * @mtd: pointer to MTD struct 32 21 * @ctlr: pointer to HyperBus controller struct 33 22 * @memtype: type of memory device: HyperFlash or HyperRAM 23 23 + * @priv: pointer to controller specific per device private data 34 24 */ 35 25 36 26 struct hyperbus_device { ··· 40 28 struct mtd_info *mtd; 41 29 struct hyperbus_ctlr *ctlr; 42 30 enum hyperbus_memtype memtype; 31 31 + void *priv; 43 32 }; 44 33 45 34 /**

+182 -6

include/linux/mtd/nand.h

reviewed

··· 83 83 }; 84 84 85 85 /** 86 86 + * enum nand_page_io_req_type - Direction of an I/O request 87 87 + * @NAND_PAGE_READ: from the chip, to the controller 88 88 + * @NAND_PAGE_WRITE: from the controller, to the chip 89 89 + */ 90 90 + enum nand_page_io_req_type { 91 91 + NAND_PAGE_READ = 0, 92 92 + NAND_PAGE_WRITE, 93 93 + }; 94 94 + 95 95 + /** 86 96 * struct nand_page_io_req - NAND I/O request object 97 97 + * @type: the type of page I/O: read or write 87 98 * @pos: the position this I/O request is targeting 88 99 * @dataoffs: the offset within the page 89 100 * @datalen: number of data bytes to read from/write to this page ··· 110 99 * specific commands/operations. 111 100 */ 112 101 struct nand_page_io_req { 102 102 + enum nand_page_io_req_type type; 113 103 struct nand_pos pos; 114 104 unsigned int dataoffs; 115 105 unsigned int datalen; ··· 127 115 int mode; 128 116 }; 129 117 118 118 + const struct mtd_ooblayout_ops *nand_get_small_page_ooblayout(void); 119 119 + const struct mtd_ooblayout_ops *nand_get_large_page_ooblayout(void); 120 120 + const struct mtd_ooblayout_ops *nand_get_large_page_hamming_ooblayout(void); 121 121 + 122 122 + /** 123 123 + * enum nand_ecc_engine_type - NAND ECC engine type 124 124 + * @NAND_ECC_ENGINE_TYPE_INVALID: Invalid value 125 125 + * @NAND_ECC_ENGINE_TYPE_NONE: No ECC correction 126 126 + * @NAND_ECC_ENGINE_TYPE_SOFT: Software ECC correction 127 127 + * @NAND_ECC_ENGINE_TYPE_ON_HOST: On host hardware ECC correction 128 128 + * @NAND_ECC_ENGINE_TYPE_ON_DIE: On chip hardware ECC correction 129 129 + */ 130 130 + enum nand_ecc_engine_type { 131 131 + NAND_ECC_ENGINE_TYPE_INVALID, 132 132 + NAND_ECC_ENGINE_TYPE_NONE, 133 133 + NAND_ECC_ENGINE_TYPE_SOFT, 134 134 + NAND_ECC_ENGINE_TYPE_ON_HOST, 135 135 + NAND_ECC_ENGINE_TYPE_ON_DIE, 136 136 + }; 137 137 + 138 138 + /** 139 139 + * enum nand_ecc_placement - NAND ECC bytes placement 140 140 + * @NAND_ECC_PLACEMENT_UNKNOWN: The actual position of the ECC bytes is unknown 141 141 + * @NAND_ECC_PLACEMENT_OOB: The ECC bytes are located in the OOB area 142 142 + * @NAND_ECC_PLACEMENT_INTERLEAVED: Syndrome layout, there are ECC bytes 143 143 + * interleaved with regular data in the main 144 144 + * area 145 145 + */ 146 146 + enum nand_ecc_placement { 147 147 + NAND_ECC_PLACEMENT_UNKNOWN, 148 148 + NAND_ECC_PLACEMENT_OOB, 149 149 + NAND_ECC_PLACEMENT_INTERLEAVED, 150 150 + }; 151 151 + 152 152 + /** 153 153 + * enum nand_ecc_algo - NAND ECC algorithm 154 154 + * @NAND_ECC_ALGO_UNKNOWN: Unknown algorithm 155 155 + * @NAND_ECC_ALGO_HAMMING: Hamming algorithm 156 156 + * @NAND_ECC_ALGO_BCH: Bose-Chaudhuri-Hocquenghem algorithm 157 157 + * @NAND_ECC_ALGO_RS: Reed-Solomon algorithm 158 158 + */ 159 159 + enum nand_ecc_algo { 160 160 + NAND_ECC_ALGO_UNKNOWN, 161 161 + NAND_ECC_ALGO_HAMMING, 162 162 + NAND_ECC_ALGO_BCH, 163 163 + NAND_ECC_ALGO_RS, 164 164 + }; 165 165 + 130 166 /** 131 167 * struct nand_ecc_props - NAND ECC properties 168 168 + * @engine_type: ECC engine type 169 169 + * @placement: OOB placement (if relevant) 170 170 + * @algo: ECC algorithm (if relevant) 132 171 * @strength: ECC strength 133 172 * @step_size: Number of bytes per step 173 173 + * @flags: Misc properties 134 174 */ 135 175 struct nand_ecc_props { 176 176 + enum nand_ecc_engine_type engine_type; 177 177 + enum nand_ecc_placement placement; 178 178 + enum nand_ecc_algo algo; 136 179 unsigned int strength; 137 180 unsigned int step_size; 181 181 + unsigned int flags; 138 182 }; 139 183 140 184 #define NAND_ECCREQ(str, stp) { .strength = (str), .step_size = (stp) } 185 185 + 186 186 + /* NAND ECC misc flags */ 187 187 + #define NAND_ECC_MAXIMIZE_STRENGTH BIT(0) 141 188 142 189 /** 143 190 * struct nand_bbt - bad block table object ··· 229 158 }; 230 159 231 160 /** 161 161 + * struct nand_ecc_context - Context for the ECC engine 162 162 + * @conf: basic ECC engine parameters 163 163 + * @total: total number of bytes used for storing ECC codes, this is used by 164 164 + * generic OOB layouts 165 165 + * @priv: ECC engine driver private data 166 166 + */ 167 167 + struct nand_ecc_context { 168 168 + struct nand_ecc_props conf; 169 169 + unsigned int total; 170 170 + void *priv; 171 171 + }; 172 172 + 173 173 + /** 174 174 + * struct nand_ecc_engine_ops - ECC engine operations 175 175 + * @init_ctx: given a desired user configuration for the pointed NAND device, 176 176 + * requests the ECC engine driver to setup a configuration with 177 177 + * values it supports. 178 178 + * @cleanup_ctx: clean the context initialized by @init_ctx. 179 179 + * @prepare_io_req: is called before reading/writing a page to prepare the I/O 180 180 + * request to be performed with ECC correction. 181 181 + * @finish_io_req: is called after reading/writing a page to terminate the I/O 182 182 + * request and ensure proper ECC correction. 183 183 + */ 184 184 + struct nand_ecc_engine_ops { 185 185 + int (*init_ctx)(struct nand_device *nand); 186 186 + void (*cleanup_ctx)(struct nand_device *nand); 187 187 + int (*prepare_io_req)(struct nand_device *nand, 188 188 + struct nand_page_io_req *req); 189 189 + int (*finish_io_req)(struct nand_device *nand, 190 190 + struct nand_page_io_req *req); 191 191 + }; 192 192 + 193 193 + /** 194 194 + * struct nand_ecc_engine - ECC engine abstraction for NAND devices 195 195 + * @ops: ECC engine operations 196 196 + */ 197 197 + struct nand_ecc_engine { 198 198 + struct nand_ecc_engine_ops *ops; 199 199 + }; 200 200 + 201 201 + void of_get_nand_ecc_user_config(struct nand_device *nand); 202 202 + int nand_ecc_init_ctx(struct nand_device *nand); 203 203 + void nand_ecc_cleanup_ctx(struct nand_device *nand); 204 204 + int nand_ecc_prepare_io_req(struct nand_device *nand, 205 205 + struct nand_page_io_req *req); 206 206 + int nand_ecc_finish_io_req(struct nand_device *nand, 207 207 + struct nand_page_io_req *req); 208 208 + bool nand_ecc_is_strong_enough(struct nand_device *nand); 209 209 + 210 210 + /** 211 211 + * struct nand_ecc - Information relative to the ECC 212 212 + * @defaults: Default values, depend on the underlying subsystem 213 213 + * @requirements: ECC requirements from the NAND chip perspective 214 214 + * @user_conf: User desires in terms of ECC parameters 215 215 + * @ctx: ECC context for the ECC engine, derived from the device @requirements 216 216 + * the @user_conf and the @defaults 217 217 + * @ondie_engine: On-die ECC engine reference, if any 218 218 + * @engine: ECC engine actually bound 219 219 + */ 220 220 + struct nand_ecc { 221 221 + struct nand_ecc_props defaults; 222 222 + struct nand_ecc_props requirements; 223 223 + struct nand_ecc_props user_conf; 224 224 + struct nand_ecc_context ctx; 225 225 + struct nand_ecc_engine *ondie_engine; 226 226 + struct nand_ecc_engine *engine; 227 227 + }; 228 228 + 229 229 + /** 232 230 * struct nand_device - NAND device 233 231 * @mtd: MTD instance attached to the NAND device 234 232 * @memorg: memory layout 235 235 - * @eccreq: ECC requirements 233 233 + * @ecc: NAND ECC object attached to the NAND device 236 234 * @rowconv: position to row address converter 237 235 * @bbt: bad block table info 238 236 * @ops: NAND operations attached to the NAND device ··· 309 169 * Generic NAND object. Specialized NAND layers (raw NAND, SPI NAND, OneNAND) 310 170 * should declare their own NAND object embedding a nand_device struct (that's 311 171 * how inheritance is done). 312 312 - * struct_nand_device->memorg and struct_nand_device->eccreq should be filled 313 313 - * at device detection time to reflect the NAND device 172 172 + * struct_nand_device->memorg and struct_nand_device->ecc.requirements should 173 173 + * be filled at device detection time to reflect the NAND device 314 174 * capabilities/requirements. Once this is done nanddev_init() can be called. 315 175 * It will take care of converting NAND information into MTD ones, which means 316 176 * the specialized NAND layers should never manually tweak ··· 319 179 struct nand_device { 320 180 struct mtd_info mtd; 321 181 struct nand_memory_organization memorg; 322 322 - struct nand_ecc_props eccreq; 182 182 + struct nand_ecc ecc; 323 183 struct nand_row_converter rowconv; 324 184 struct nand_bbt bbt; 325 185 const struct nand_ops *ops; ··· 521 381 nanddev_get_memorg(struct nand_device *nand) 522 382 { 523 383 return &nand->memorg; 384 384 + } 385 385 + 386 386 + /** 387 387 + * nanddev_get_ecc_conf() - Extract the ECC configuration from a NAND device 388 388 + * @nand: NAND device 389 389 + */ 390 390 + static inline const struct nand_ecc_props * 391 391 + nanddev_get_ecc_conf(struct nand_device *nand) 392 392 + { 393 393 + return &nand->ecc.ctx.conf; 394 394 + } 395 395 + 396 396 + /** 397 397 + * nanddev_get_ecc_requirements() - Extract the ECC requirements from a NAND 398 398 + * device 399 399 + * @nand: NAND device 400 400 + */ 401 401 + static inline const struct nand_ecc_props * 402 402 + nanddev_get_ecc_requirements(struct nand_device *nand) 403 403 + { 404 404 + return &nand->ecc.requirements; 405 405 + } 406 406 + 407 407 + /** 408 408 + * nanddev_set_ecc_requirements() - Assign the ECC requirements of a NAND 409 409 + * device 410 410 + * @nand: NAND device 411 411 + * @reqs: Requirements 412 412 + */ 413 413 + static inline void 414 414 + nanddev_set_ecc_requirements(struct nand_device *nand, 415 415 + const struct nand_ecc_props *reqs) 416 416 + { 417 417 + nand->ecc.requirements = *reqs; 524 418 } 525 419 526 420 int nanddev_init(struct nand_device *nand, const struct nand_ops *ops, ··· 798 624 * layer. 799 625 */ 800 626 static inline void nanddev_io_iter_init(struct nand_device *nand, 627 627 + enum nand_page_io_req_type reqtype, 801 628 loff_t offs, struct mtd_oob_ops *req, 802 629 struct nand_io_iter *iter) 803 630 { 804 631 struct mtd_info *mtd = nanddev_to_mtd(nand); 805 632 633 633 + iter->req.type = reqtype; 806 634 iter->req.mode = req->mode; 807 635 iter->req.dataoffs = nanddev_offs_to_pos(nand, offs, &iter->req.pos); 808 636 iter->req.ooboffs = req->ooboffs; ··· 874 698 * 875 699 * Should be used for iterate over pages that are contained in an MTD request. 876 700 */ 877 877 - #define nanddev_io_for_each_page(nand, start, req, iter) \ 878 878 - for (nanddev_io_iter_init(nand, start, req, iter); \ 701 701 + #define nanddev_io_for_each_page(nand, type, start, req, iter) \ 702 702 + for (nanddev_io_iter_init(nand, type, start, req, iter); \ 879 703 !nanddev_io_iter_end(nand, iter); \ 880 704 nanddev_io_iter_next_page(nand, iter)) 881 705

-33

include/linux/mtd/pfow.h

reviewed

··· 121 121 map_write(map, CMD(LPDDR_START_EXECUTION), 122 122 map->pfow_base + PFOW_COMMAND_EXECUTE); 123 123 } 124 124 - 125 125 - static inline void print_drs_error(unsigned dsr) 126 126 - { 127 127 - int prog_status = (dsr & DSR_RPS) >> 8; 128 128 - 129 129 - if (!(dsr & DSR_AVAILABLE)) 130 130 - printk(KERN_NOTICE"DSR.15: (0) Device not Available\n"); 131 131 - if (prog_status & 0x03) 132 132 - printk(KERN_NOTICE"DSR.9,8: (11) Attempt to program invalid " 133 133 - "half with 41h command\n"); 134 134 - else if (prog_status & 0x02) 135 135 - printk(KERN_NOTICE"DSR.9,8: (10) Object Mode Program attempt " 136 136 - "in region with Control Mode data\n"); 137 137 - else if (prog_status & 0x01) 138 138 - printk(KERN_NOTICE"DSR.9,8: (01) Program attempt in region " 139 139 - "with Object Mode data\n"); 140 140 - if (!(dsr & DSR_READY_STATUS)) 141 141 - printk(KERN_NOTICE"DSR.7: (0) Device is Busy\n"); 142 142 - if (dsr & DSR_ESS) 143 143 - printk(KERN_NOTICE"DSR.6: (1) Erase Suspended\n"); 144 144 - if (dsr & DSR_ERASE_STATUS) 145 145 - printk(KERN_NOTICE"DSR.5: (1) Erase/Blank check error\n"); 146 146 - if (dsr & DSR_PROGRAM_STATUS) 147 147 - printk(KERN_NOTICE"DSR.4: (1) Program Error\n"); 148 148 - if (dsr & DSR_VPPS) 149 149 - printk(KERN_NOTICE"DSR.3: (1) Vpp low detect, operation " 150 150 - "aborted\n"); 151 151 - if (dsr & DSR_PSS) 152 152 - printk(KERN_NOTICE"DSR.2: (1) Program suspended\n"); 153 153 - if (dsr & DSR_DPS) 154 154 - printk(KERN_NOTICE"DSR.1: (1) Aborted Erase/Program attempt " 155 155 - "on locked block\n"); 156 156 - } 157 124 #endif /* __LINUX_MTD_PFOW_H */

+7 -27

include/linux/mtd/rawnand.h

reviewed

··· 14 14 #define __LINUX_MTD_RAWNAND_H 15 15 16 16 #include <linux/mtd/mtd.h> 17 17 + #include <linux/mtd/nand.h> 17 18 #include <linux/mtd/flashchip.h> 18 19 #include <linux/mtd/bbm.h> 19 20 #include <linux/mtd/jedec.h> ··· 82 81 #define NAND_DATA_IFACE_CHECK_ONLY -1 83 82 84 83 /* 85 85 - * Constants for ECC_MODES 86 86 - */ 87 87 - enum nand_ecc_mode { 88 88 - NAND_ECC_INVALID, 89 89 - NAND_ECC_NONE, 90 90 - NAND_ECC_SOFT, 91 91 - NAND_ECC_HW, 92 92 - NAND_ECC_HW_SYNDROME, 93 93 - NAND_ECC_ON_DIE, 94 94 - }; 95 95 - 96 96 - enum nand_ecc_algo { 97 97 - NAND_ECC_UNKNOWN, 98 98 - NAND_ECC_HAMMING, 99 99 - NAND_ECC_BCH, 100 100 - NAND_ECC_RS, 101 101 - }; 102 102 - 103 103 - /* 104 84 * Constants for Hardware ECC 105 85 */ 106 86 /* Reset Hardware ECC for read */ ··· 98 116 * pages and you want to rely on the default implementation. 99 117 */ 100 118 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0) 101 101 - #define NAND_ECC_MAXIMIZE BIT(1) 102 119 103 120 /* 104 121 * Option constants for bizarre disfunctionality and real ··· 291 310 292 311 /** 293 312 * struct nand_ecc_ctrl - Control structure for ECC 294 294 - * @mode: ECC mode 313 313 + * @engine_type: ECC engine type 314 314 + * @placement: OOB bytes placement 295 315 * @algo: ECC algorithm 296 316 * @steps: number of ECC steps per page 297 317 * @size: data bytes per ECC step ··· 320 338 * controller and always return contiguous in-band and 321 339 * out-of-band data even if they're not stored 322 340 * contiguously on the NAND chip (e.g. 323 323 - * NAND_ECC_HW_SYNDROME interleaves in-band and 341 341 + * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and 324 342 * out-of-band data). 325 343 * @write_page_raw: function to write a raw page without ECC. This function 326 344 * should hide the specific layout used by the ECC ··· 328 346 * in-band and out-of-band data. ECC controller is 329 347 * responsible for doing the appropriate transformations 330 348 * to adapt to its specific layout (e.g. 331 331 - * NAND_ECC_HW_SYNDROME interleaves in-band and 349 349 + * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and 332 350 * out-of-band data). 333 351 * @read_page: function to read a page according to the ECC generator 334 352 * requirements; returns maximum number of bitflips corrected in ··· 344 362 * @write_oob: function to write chip OOB data 345 363 */ 346 364 struct nand_ecc_ctrl { 347 347 - enum nand_ecc_mode mode; 365 365 + enum nand_ecc_engine_type engine_type; 366 366 + enum nand_ecc_placement placement; 348 367 enum nand_ecc_algo algo; 349 368 int steps; 350 369 int size; ··· 1143 1160 struct nand_ecc_ctrl ecc; 1144 1161 void *priv; 1145 1162 }; 1146 1146 - 1147 1147 - extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops; 1148 1148 - extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops; 1149 1163 1150 1164 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd) 1151 1165 {

+5 -4

include/linux/platform_data/mtd-davinci.h

reviewed

··· 60 60 struct mtd_partition *parts; 61 61 unsigned nr_parts; 62 62 63 63 - /* none == NAND_ECC_NONE (strongly *not* advised!!) 64 64 - * soft == NAND_ECC_SOFT 65 65 - * else == NAND_ECC_HW, according to ecc_bits 63 63 + /* none == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!) 64 64 + * soft == NAND_ECC_ENGINE_TYPE_SOFT 65 65 + * else == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits 66 66 * 67 67 * All DaVinci-family chips support 1-bit hardware ECC. 68 68 * Newer ones also support 4-bit ECC, but are awkward 69 69 * using it with large page chips. 70 70 */ 71 71 - enum nand_ecc_mode ecc_mode; 71 71 + enum nand_ecc_engine_type engine_type; 72 72 + enum nand_ecc_placement ecc_placement; 72 73 u8 ecc_bits; 73 74 74 75 /* e.g. NAND_BUSWIDTH_16 */

+1 -1

include/linux/platform_data/mtd-nand-s3c2410.h

reviewed

··· 49 49 50 50 unsigned int ignore_unset_ecc:1; 51 51 52 52 - enum nand_ecc_mode ecc_mode; 52 52 + enum nand_ecc_engine_type engine_type; 53 53 54 54 int nr_sets; 55 55 struct s3c2410_nand_set *sets;