Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge branch 'fixes' into next
This brings in the rz-dmac fixes which are in fixes
+138
-79
+6
-2
drivers/dma/dw-edma/dw-edma-core.c
+6
-2
drivers/dma/dw-edma/dw-edma-core.c
···
954
954
{
955
955
struct dw_edma_chip *chip = dw->chip;
956
956
struct device *dev = dw->chip->dev;
957
+
struct msi_desc *msi_desc;
957
958
u32 wr_mask = 1;
958
959
u32 rd_mask = 1;
959
960
int i, err = 0;
···
1006
1005
&dw->irq[i]);
1007
1006
if (err)
1008
1007
goto err_irq_free;
1009
-
1010
-
if (irq_get_msi_desc(irq))
1008
+
msi_desc = irq_get_msi_desc(irq);
1009
+
if (msi_desc) {
1011
1010
get_cached_msi_msg(irq, &dw->irq[i].msi);
1011
+
if (!msi_desc->pci.msi_attrib.is_msix)
1012
+
dw->irq[i].msi.data = dw->irq[0].msi.data + i;
1013
+
}
1012
1014
}
1013
1015
1014
1016
dw->nr_irqs = i;
+3
-3
drivers/dma/dw-edma/dw-hdma-v0-core.c
+3
-3
drivers/dma/dw-edma/dw-hdma-v0-core.c
···
252
252
lower_32_bits(chunk->ll_region.paddr));
253
253
SET_CH_32(dw, chan->dir, chan->id, llp.msb,
254
254
upper_32_bits(chunk->ll_region.paddr));
255
+
/* Set consumer cycle */
256
+
SET_CH_32(dw, chan->dir, chan->id, cycle_sync,
257
+
HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT);
255
258
}
256
-
/* Set consumer cycle */
257
-
SET_CH_32(dw, chan->dir, chan->id, cycle_sync,
258
-
HDMA_V0_CONSUMER_CYCLE_STAT | HDMA_V0_CONSUMER_CYCLE_BIT);
259
259
260
260
dw_hdma_v0_sync_ll_data(chunk);
261
261
+11
-15
drivers/dma/fsl-edma-main.c
+11
-15
drivers/dma/fsl-edma-main.c
···
317
317
return NULL;
318
318
i = fsl_chan - fsl_edma->chans;
319
319
320
-
fsl_chan->priority = dma_spec->args[1];
321
-
fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
322
-
fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
323
-
fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
320
+
if (!b_chmux && i != dma_spec->args[0])
321
+
continue;
324
322
325
323
if ((dma_spec->args[2] & FSL_EDMA_EVEN_CH) && (i & 0x1))
326
324
continue;
···
326
328
if ((dma_spec->args[2] & FSL_EDMA_ODD_CH) && !(i & 0x1))
327
329
continue;
328
330
329
-
if (!b_chmux && i == dma_spec->args[0]) {
330
-
chan = dma_get_slave_channel(chan);
331
-
chan->device->privatecnt++;
332
-
return chan;
333
-
} else if (b_chmux && !fsl_chan->srcid) {
334
-
/* if controller support channel mux, choose a free channel */
335
-
chan = dma_get_slave_channel(chan);
336
-
chan->device->privatecnt++;
337
-
fsl_chan->srcid = dma_spec->args[0];
338
-
return chan;
339
-
}
331
+
fsl_chan->srcid = dma_spec->args[0];
332
+
fsl_chan->priority = dma_spec->args[1];
333
+
fsl_chan->is_rxchan = dma_spec->args[2] & FSL_EDMA_RX;
334
+
fsl_chan->is_remote = dma_spec->args[2] & FSL_EDMA_REMOTE;
335
+
fsl_chan->is_multi_fifo = dma_spec->args[2] & FSL_EDMA_MULTI_FIFO;
336
+
337
+
chan = dma_get_slave_channel(chan);
338
+
chan->device->privatecnt++;
339
+
return chan;
340
340
}
341
341
return NULL;
342
342
}
+4
-4
drivers/dma/idxd/cdev.c
+4
-4
drivers/dma/idxd/cdev.c
···
158
158
static void idxd_cdev_dev_release(struct device *dev)
159
159
{
160
160
struct idxd_cdev *idxd_cdev = dev_to_cdev(dev);
161
-
struct idxd_cdev_context *cdev_ctx;
162
-
struct idxd_wq *wq = idxd_cdev->wq;
163
161
164
-
cdev_ctx = &ictx[wq->idxd->data->type];
165
-
ida_free(&cdev_ctx->minor_ida, idxd_cdev->minor);
166
162
kfree(idxd_cdev);
167
163
}
168
164
···
578
582
579
583
void idxd_wq_del_cdev(struct idxd_wq *wq)
580
584
{
585
+
struct idxd_cdev_context *cdev_ctx;
581
586
struct idxd_cdev *idxd_cdev;
582
587
583
588
idxd_cdev = wq->idxd_cdev;
584
589
wq->idxd_cdev = NULL;
585
590
cdev_device_del(&idxd_cdev->cdev, cdev_dev(idxd_cdev));
591
+
592
+
cdev_ctx = &ictx[wq->idxd->data->type];
593
+
ida_free(&cdev_ctx->minor_ida, idxd_cdev->minor);
586
594
put_device(cdev_dev(idxd_cdev));
587
595
}
588
596
+31
-14
drivers/dma/idxd/device.c
+31
-14
drivers/dma/idxd/device.c
···
175
175
free_descs(wq);
176
176
dma_free_coherent(dev, wq->compls_size, wq->compls, wq->compls_addr);
177
177
sbitmap_queue_free(&wq->sbq);
178
+
wq->type = IDXD_WQT_NONE;
178
179
}
179
180
EXPORT_SYMBOL_NS_GPL(idxd_wq_free_resources, "IDXD");
180
181
···
383
382
lockdep_assert_held(&wq->wq_lock);
384
383
wq->state = IDXD_WQ_DISABLED;
385
384
memset(wq->wqcfg, 0, idxd->wqcfg_size);
386
-
wq->type = IDXD_WQT_NONE;
387
385
wq->threshold = 0;
388
386
wq->priority = 0;
389
387
wq->enqcmds_retries = IDXD_ENQCMDS_RETRIES;
···
831
831
struct device *dev = &idxd->pdev->dev;
832
832
struct idxd_evl *evl = idxd->evl;
833
833
834
-
gencfg.bits = ioread32(idxd->reg_base + IDXD_GENCFG_OFFSET);
835
-
if (!gencfg.evl_en)
834
+
if (!evl)
836
835
return;
837
836
838
837
mutex_lock(&evl->lock);
···
1124
1125
{
1125
1126
int rc;
1126
1127
1127
-
lockdep_assert_held(&idxd->dev_lock);
1128
+
guard(spinlock)(&idxd->dev_lock);
1129
+
1130
+
if (!test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1131
+
return 0;
1132
+
1128
1133
rc = idxd_wqs_setup(idxd);
1129
1134
if (rc < 0)
1130
1135
return rc;
···
1335
1332
1336
1333
free_irq(ie->vector, ie);
1337
1334
idxd_flush_pending_descs(ie);
1335
+
1336
+
/* The interrupt might have been already released by FLR */
1337
+
if (ie->int_handle == INVALID_INT_HANDLE)
1338
+
return;
1339
+
1338
1340
if (idxd->request_int_handles)
1339
1341
idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX);
1340
1342
idxd_device_clear_perm_entry(idxd, ie);
1341
1343
ie->vector = -1;
1342
1344
ie->int_handle = INVALID_INT_HANDLE;
1343
1345
ie->pasid = IOMMU_PASID_INVALID;
1346
+
}
1347
+
1348
+
void idxd_wq_flush_descs(struct idxd_wq *wq)
1349
+
{
1350
+
struct idxd_irq_entry *ie = &wq->ie;
1351
+
struct idxd_device *idxd = wq->idxd;
1352
+
1353
+
guard(mutex)(&wq->wq_lock);
1354
+
1355
+
if (wq->state != IDXD_WQ_ENABLED || wq->type != IDXD_WQT_KERNEL)
1356
+
return;
1357
+
1358
+
idxd_flush_pending_descs(ie);
1359
+
if (idxd->request_int_handles)
1360
+
idxd_device_release_int_handle(idxd, ie->int_handle, IDXD_IRQ_MSIX);
1361
+
idxd_device_clear_perm_entry(idxd, ie);
1362
+
ie->int_handle = INVALID_INT_HANDLE;
1344
1363
}
1345
1364
1346
1365
int idxd_wq_request_irq(struct idxd_wq *wq)
···
1479
1454
}
1480
1455
}
1481
1456
1482
-
rc = 0;
1483
-
spin_lock(&idxd->dev_lock);
1484
-
if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1485
-
rc = idxd_device_config(idxd);
1486
-
spin_unlock(&idxd->dev_lock);
1457
+
rc = idxd_device_config(idxd);
1487
1458
if (rc < 0) {
1488
1459
dev_dbg(dev, "Writing wq %d config failed: %d\n", wq->id, rc);
1489
1460
goto err;
···
1554
1533
idxd_wq_reset(wq);
1555
1534
idxd_wq_free_resources(wq);
1556
1535
percpu_ref_exit(&wq->wq_active);
1557
-
wq->type = IDXD_WQT_NONE;
1558
1536
wq->client_count = 0;
1559
1537
}
1560
1538
EXPORT_SYMBOL_NS_GPL(idxd_drv_disable_wq, "IDXD");
···
1574
1554
}
1575
1555
1576
1556
/* Device configuration */
1577
-
spin_lock(&idxd->dev_lock);
1578
-
if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags))
1579
-
rc = idxd_device_config(idxd);
1580
-
spin_unlock(&idxd->dev_lock);
1557
+
rc = idxd_device_config(idxd);
1581
1558
if (rc < 0)
1582
1559
return -ENXIO;
1583
1560
+18
drivers/dma/idxd/dma.c
+18
drivers/dma/idxd/dma.c
···
194
194
kfree(idxd_dma);
195
195
}
196
196
197
+
static int idxd_dma_terminate_all(struct dma_chan *c)
198
+
{
199
+
struct idxd_wq *wq = to_idxd_wq(c);
200
+
201
+
idxd_wq_flush_descs(wq);
202
+
203
+
return 0;
204
+
}
205
+
206
+
static void idxd_dma_synchronize(struct dma_chan *c)
207
+
{
208
+
struct idxd_wq *wq = to_idxd_wq(c);
209
+
210
+
idxd_wq_drain(wq);
211
+
}
212
+
197
213
int idxd_register_dma_device(struct idxd_device *idxd)
198
214
{
199
215
struct idxd_dma_dev *idxd_dma;
···
240
224
dma->device_issue_pending = idxd_dma_issue_pending;
241
225
dma->device_alloc_chan_resources = idxd_dma_alloc_chan_resources;
242
226
dma->device_free_chan_resources = idxd_dma_free_chan_resources;
227
+
dma->device_terminate_all = idxd_dma_terminate_all;
228
+
dma->device_synchronize = idxd_dma_synchronize;
243
229
244
230
rc = dma_async_device_register(dma);
245
231
if (rc < 0) {
+1
drivers/dma/idxd/idxd.h
+1
drivers/dma/idxd/idxd.h
···
803
803
int idxd_wq_init_percpu_ref(struct idxd_wq *wq);
804
804
void idxd_wq_free_irq(struct idxd_wq *wq);
805
805
int idxd_wq_request_irq(struct idxd_wq *wq);
806
+
void idxd_wq_flush_descs(struct idxd_wq *wq);
806
807
807
808
/* submission */
808
809
int idxd_submit_desc(struct idxd_wq *wq, struct idxd_desc *desc);
+7
-7
drivers/dma/idxd/init.c
+7
-7
drivers/dma/idxd/init.c
···
973
973
974
974
idxd->rdbuf_limit = idxd_saved->saved_idxd.rdbuf_limit;
975
975
976
-
idxd->evl->size = saved_evl->size;
976
+
if (idxd->evl)
977
+
idxd->evl->size = saved_evl->size;
977
978
978
979
for (i = 0; i < idxd->max_groups; i++) {
979
980
struct idxd_group *saved_group, *group;
···
1105
1104
idxd_device_config_restore(idxd, idxd->idxd_saved);
1106
1105
1107
1106
/* Re-configure IDXD device if allowed. */
1108
-
if (test_bit(IDXD_FLAG_CONFIGURABLE, &idxd->flags)) {
1109
-
rc = idxd_device_config(idxd);
1110
-
if (rc < 0) {
1111
-
dev_err(dev, "HALT: %s config fails\n", idxd_name);
1112
-
goto out;
1113
-
}
1107
+
rc = idxd_device_config(idxd);
1108
+
if (rc < 0) {
1109
+
dev_err(dev, "HALT: %s config fails\n", idxd_name);
1110
+
goto out;
1114
1111
}
1115
1112
1116
1113
/* Bind IDXD device to driver. */
···
1146
1147
}
1147
1148
out:
1148
1149
kfree(idxd->idxd_saved);
1150
+
idxd->idxd_saved = NULL;
1149
1151
}
1150
1152
1151
1153
static const struct pci_error_handlers idxd_error_handler = {
+16
drivers/dma/idxd/irq.c
+16
drivers/dma/idxd/irq.c
···
397
397
dev_err(&idxd->pdev->dev, "FLR failed\n");
398
398
}
399
399
400
+
static void idxd_wqs_flush_descs(struct idxd_device *idxd)
401
+
{
402
+
int i;
403
+
404
+
for (i = 0; i < idxd->max_wqs; i++) {
405
+
struct idxd_wq *wq = idxd->wqs[i];
406
+
407
+
idxd_wq_flush_descs(wq);
408
+
}
409
+
}
410
+
400
411
static irqreturn_t idxd_halt(struct idxd_device *idxd)
401
412
{
402
413
union gensts_reg gensts;
···
426
415
} else if (gensts.reset_type == IDXD_DEVICE_RESET_FLR) {
427
416
idxd->state = IDXD_DEV_HALTED;
428
417
idxd_mask_error_interrupts(idxd);
418
+
/* Flush all pending descriptors, and disable
419
+
* interrupts, they will be re-enabled when FLR
420
+
* concludes.
421
+
*/
422
+
idxd_wqs_flush_descs(idxd);
429
423
dev_dbg(&idxd->pdev->dev,
430
424
"idxd halted, doing FLR. After FLR, configs are restored\n");
431
425
INIT_WORK(&idxd->work, idxd_device_flr);
+1
-1
drivers/dma/idxd/submit.c
+1
-1
drivers/dma/idxd/submit.c
+1
drivers/dma/idxd/sysfs.c
+1
drivers/dma/idxd/sysfs.c
+37
-31
drivers/dma/sh/rz-dmac.c
+37
-31
drivers/dma/sh/rz-dmac.c
···
10
10
*/
11
11
12
12
#include <linux/bitfield.h>
13
+
#include <linux/cleanup.h>
13
14
#include <linux/dma-mapping.h>
14
15
#include <linux/dmaengine.h>
15
16
#include <linux/interrupt.h>
···
303
302
{
304
303
struct dma_chan *chan = &channel->vc.chan;
305
304
struct rz_dmac *dmac = to_rz_dmac(chan->device);
306
-
unsigned long flags;
307
305
308
306
dev_dbg(dmac->dev, "%s channel %d\n", __func__, channel->index);
309
307
310
-
local_irq_save(flags);
311
308
rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
312
-
local_irq_restore(flags);
313
309
}
314
310
315
311
static void rz_dmac_set_dmars_register(struct rz_dmac *dmac, int nr, u32 dmars)
···
450
452
if (!desc)
451
453
break;
452
454
455
+
/* No need to lock. This is called only for the 1st client. */
453
456
list_add_tail(&desc->node, &channel->ld_free);
454
457
channel->descs_allocated++;
455
458
}
···
506
507
dev_dbg(dmac->dev, "%s channel: %d src=0x%pad dst=0x%pad len=%zu\n",
507
508
__func__, channel->index, &src, &dest, len);
508
509
509
-
if (list_empty(&channel->ld_free))
510
-
return NULL;
510
+
scoped_guard(spinlock_irqsave, &channel->vc.lock) {
511
+
if (list_empty(&channel->ld_free))
512
+
return NULL;
511
513
512
-
desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
514
+
desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
513
515
514
-
desc->type = RZ_DMAC_DESC_MEMCPY;
515
-
desc->src = src;
516
-
desc->dest = dest;
517
-
desc->len = len;
518
-
desc->direction = DMA_MEM_TO_MEM;
516
+
desc->type = RZ_DMAC_DESC_MEMCPY;
517
+
desc->src = src;
518
+
desc->dest = dest;
519
+
desc->len = len;
520
+
desc->direction = DMA_MEM_TO_MEM;
519
521
520
-
list_move_tail(channel->ld_free.next, &channel->ld_queue);
522
+
list_move_tail(channel->ld_free.next, &channel->ld_queue);
523
+
}
524
+
521
525
return vchan_tx_prep(&channel->vc, &desc->vd, flags);
522
526
}
523
527
···
536
534
int dma_length = 0;
537
535
int i = 0;
538
536
539
-
if (list_empty(&channel->ld_free))
540
-
return NULL;
537
+
scoped_guard(spinlock_irqsave, &channel->vc.lock) {
538
+
if (list_empty(&channel->ld_free))
539
+
return NULL;
541
540
542
-
desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
541
+
desc = list_first_entry(&channel->ld_free, struct rz_dmac_desc, node);
543
542
544
-
for_each_sg(sgl, sg, sg_len, i) {
545
-
dma_length += sg_dma_len(sg);
543
+
for_each_sg(sgl, sg, sg_len, i)
544
+
dma_length += sg_dma_len(sg);
545
+
546
+
desc->type = RZ_DMAC_DESC_SLAVE_SG;
547
+
desc->sg = sgl;
548
+
desc->sgcount = sg_len;
549
+
desc->len = dma_length;
550
+
desc->direction = direction;
551
+
552
+
if (direction == DMA_DEV_TO_MEM)
553
+
desc->src = channel->src_per_address;
554
+
else
555
+
desc->dest = channel->dst_per_address;
556
+
557
+
list_move_tail(channel->ld_free.next, &channel->ld_queue);
546
558
}
547
559
548
-
desc->type = RZ_DMAC_DESC_SLAVE_SG;
549
-
desc->sg = sgl;
550
-
desc->sgcount = sg_len;
551
-
desc->len = dma_length;
552
-
desc->direction = direction;
553
-
554
-
if (direction == DMA_DEV_TO_MEM)
555
-
desc->src = channel->src_per_address;
556
-
else
557
-
desc->dest = channel->dst_per_address;
558
-
559
-
list_move_tail(channel->ld_free.next, &channel->ld_queue);
560
560
return vchan_tx_prep(&channel->vc, &desc->vd, flags);
561
561
}
562
562
···
570
566
unsigned int i;
571
567
LIST_HEAD(head);
572
568
573
-
rz_dmac_disable_hw(channel);
574
569
spin_lock_irqsave(&channel->vc.lock, flags);
570
+
rz_dmac_disable_hw(channel);
575
571
for (i = 0; i < DMAC_NR_LMDESC; i++)
576
572
lmdesc[i].header = 0;
577
573
···
702
698
if (chstat & CHSTAT_ER) {
703
699
dev_err(dmac->dev, "DMAC err CHSTAT_%d = %08X\n",
704
700
channel->index, chstat);
705
-
rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
701
+
702
+
scoped_guard(spinlock_irqsave, &channel->vc.lock)
703
+
rz_dmac_ch_writel(channel, CHCTRL_DEFAULT, CHCTRL, 1);
706
704
goto done;
707
705
}
708
706
+2
-2
drivers/dma/xilinx/xdma.c
+2
-2
drivers/dma/xilinx/xdma.c
···
1236
1236
1237
1237
xdev->rmap = devm_regmap_init_mmio(&pdev->dev, reg_base,
1238
1238
&xdma_regmap_config);
1239
-
if (!xdev->rmap) {
1240
-
xdma_err(xdev, "config regmap failed: %d", ret);
1239
+
if (IS_ERR(xdev->rmap)) {
1240
+
xdma_err(xdev, "config regmap failed: %pe", xdev->rmap);
1241
1241
goto failed;
1242
1242
}
1243
1243
INIT_LIST_HEAD(&xdev->dma_dev.channels);