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git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
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linux
dma-engine: sun4i: Add support for Allwinner suniv F1C100s
DMA of Allwinner suniv F1C100s is similar to sun4i. It has 4 NDMA, 4
DDMA channels and endpoints are different. Also F1C100s has reset bit
for DMA in CCU. Add support for it.
Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com>
[ csokas.bence: Rebased on current master ]
Signed-off-by: Csókás Bence <csokas.bence@prolan.hu>
Link: https://lore.kernel.org/r/20241122161128.2619172-5-csokas.bence@prolan.hu
Signed-off-by: Vinod Koul <vkoul@kernel.org>
authored by
Mesih Kilinc
and committed by
Vinod Koul
6faf1cca
fdcdcc57
+62
-2
+2
-2
drivers/dma/Kconfig
+2
-2
drivers/dma/Kconfig
···
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config DMA_SUN4I
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tristate "Allwinner A10 DMA SoCs support"
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-
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
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-
default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
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+
depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV
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+
default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNIV)
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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help
+60
drivers/dma/sun4i-dma.c
+60
drivers/dma/sun4i-dma.c
···
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#define SUN4I_DMA_CFG_SRC_ADDR_MODE(mode) ((mode) << 5)
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#define SUN4I_DMA_CFG_SRC_DRQ_TYPE(type) (type)
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+
#define SUNIV_DMA_CFG_DST_DATA_WIDTH(width) ((width) << 24)
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+
#define SUNIV_DMA_CFG_SRC_DATA_WIDTH(width) ((width) << 8)
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+
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#define SUN4I_MAX_BURST 8
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+
#define SUNIV_MAX_BURST 4
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/** Normal DMA register values **/
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/* Normal DMA source/destination data request type values */
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#define SUN4I_NDMA_DRQ_TYPE_SDRAM 0x16
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#define SUN4I_NDMA_DRQ_TYPE_LIMIT (0x1F + 1)
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+
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+
#define SUNIV_NDMA_DRQ_TYPE_SDRAM 0x11
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+
#define SUNIV_NDMA_DRQ_TYPE_LIMIT (0x17 + 1)
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/** Normal DMA register layout **/
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···
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#define SUN4I_NDMA_CFG_BYTE_COUNT_MODE_REMAIN BIT(15)
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#define SUN4I_NDMA_CFG_SRC_NON_SECURE BIT(6)
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+
#define SUNIV_NDMA_CFG_CONT_MODE BIT(29)
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#define SUNIV_NDMA_CFG_WAIT_STATE(n) ((n) << 26)
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+
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/** Dedicated DMA register values **/
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/* Dedicated DMA source/destination address mode values */
···
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/* Dedicated DMA source/destination data request type values */
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#define SUN4I_DDMA_DRQ_TYPE_SDRAM 0x1
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#define SUN4I_DDMA_DRQ_TYPE_LIMIT (0x1F + 1)
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+
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+
#define SUNIV_DDMA_DRQ_TYPE_SDRAM 0x1
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+
#define SUNIV_DDMA_DRQ_TYPE_LIMIT (0x9 + 1)
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/** Dedicated DMA register layout **/
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···
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#define SUN4I_DDMA_NR_MAX_VCHANS 21
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#define SUN4I_DMA_NR_MAX_VCHANS \
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(SUN4I_NDMA_NR_MAX_VCHANS + SUN4I_DDMA_NR_MAX_VCHANS)
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+
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+
#define SUNIV_NDMA_NR_MAX_CHANNELS 4
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+
#define SUNIV_DDMA_NR_MAX_CHANNELS 4
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+
#define SUNIV_NDMA_NR_MAX_VCHANS (24 * 2 - 1)
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#define SUNIV_DDMA_NR_MAX_VCHANS 10
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/* This set of SUN4I_DDMA timing parameters were found experimentally while
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* working with the SPI driver and seem to make it behave correctly */
···
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*p_cfg |= SUN4I_DMA_CFG_SRC_DATA_WIDTH(data_width);
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}
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+
static void set_dst_data_width_f1c100s(u32 *p_cfg, s8 data_width)
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+
{
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*p_cfg |= SUNIV_DMA_CFG_DST_DATA_WIDTH(data_width);
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+
}
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+
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+
static void set_src_data_width_f1c100s(u32 *p_cfg, s8 data_width)
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+
{
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*p_cfg |= SUNIV_DMA_CFG_SRC_DATA_WIDTH(data_width);
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+
}
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+
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static int convert_burst_a10(u32 maxburst)
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{
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if (maxburst > 8)
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return -EINVAL;
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/* 1 -> 0, 4 -> 1, 8 -> 2 */
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return (maxburst >> 2);
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+
}
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+
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+
static int convert_burst_f1c100s(u32 maxburst)
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+
{
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+
if (maxburst > 4)
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return -EINVAL;
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+
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+
/* 1 -> 0, 4 -> 1 */
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return (maxburst >> 2);
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}
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···
1405
1368
.has_reset = false,
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};
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+
static struct sun4i_dma_config suniv_f1c100s_dma_cfg = {
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.ndma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS,
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+
.ndma_nr_max_vchans = SUNIV_NDMA_NR_MAX_VCHANS,
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+
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.ddma_nr_max_channels = SUNIV_DDMA_NR_MAX_CHANNELS,
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+
.ddma_nr_max_vchans = SUNIV_DDMA_NR_MAX_VCHANS,
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+
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+
.dma_nr_max_channels = SUNIV_NDMA_NR_MAX_CHANNELS +
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+
SUNIV_DDMA_NR_MAX_CHANNELS,
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+
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+
.set_dst_data_width = set_dst_data_width_f1c100s,
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+
.set_src_data_width = set_src_data_width_f1c100s,
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+
.convert_burst = convert_burst_f1c100s,
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+
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+
.ndma_drq_sdram = SUNIV_NDMA_DRQ_TYPE_SDRAM,
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+
.ddma_drq_sdram = SUNIV_DDMA_DRQ_TYPE_SDRAM,
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+
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+
.max_burst = SUNIV_MAX_BURST,
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+
.has_reset = true,
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+
};
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+
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static const struct of_device_id sun4i_dma_match[] = {
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{ .compatible = "allwinner,sun4i-a10-dma", .data = &sun4i_a10_dma_cfg },
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+
{ .compatible = "allwinner,suniv-f1c100s-dma",
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.data = &suniv_f1c100s_dma_cfg },
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{ /* sentinel */ },
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};
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MODULE_DEVICE_TABLE(of, sun4i_dma_match);