Merge tag 'dmaengine-fix-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine

+4

drivers/dma/idma64.c

··· 171 171 u32 status_err; 172 172 unsigned short i; 173 173 174 + /* Since IRQ may be shared, check if DMA controller is powered on */ 175 + if (status == GENMASK(31, 0)) 176 + return IRQ_NONE; 177 + 174 178 dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status); 175 179 176 180 /* Check if we have any interrupt from the DMA controller */

+2 -3

drivers/dma/idxd/cdev.c

··· 342 342 if (!evl) 343 343 return; 344 344 345 - spin_lock(&evl->lock); 345 + mutex_lock(&evl->lock); 346 346 status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET); 347 347 t = status.tail; 348 348 h = status.head; ··· 354 354 set_bit(h, evl->bmap); 355 355 h = (h + 1) % size; 356 356 } 357 - spin_unlock(&evl->lock); 358 - 359 357 drain_workqueue(wq->wq); 358 + mutex_unlock(&evl->lock); 360 359 } 361 360 362 361 static int idxd_cdev_release(struct inode *node, struct file *filep)

+2 -2

drivers/dma/idxd/debugfs.c

··· 66 66 if (!evl || !evl->log) 67 67 return 0; 68 68 69 - spin_lock(&evl->lock); 69 + mutex_lock(&evl->lock); 70 70 71 71 evl_status.bits = ioread64(idxd->reg_base + IDXD_EVLSTATUS_OFFSET); 72 72 t = evl_status.tail; ··· 87 87 dump_event_entry(idxd, s, i, &count, processed); 88 88 } 89 89 90 - spin_unlock(&evl->lock); 90 + mutex_unlock(&evl->lock); 91 91 return 0; 92 92 } 93 93

+4 -4

drivers/dma/idxd/device.c

··· 775 775 goto err_alloc; 776 776 } 777 777 778 - spin_lock(&evl->lock); 778 + mutex_lock(&evl->lock); 779 779 evl->log = addr; 780 780 evl->dma = dma_addr; 781 781 evl->log_size = size; ··· 796 796 gencfg.evl_en = 1; 797 797 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 798 798 799 - spin_unlock(&evl->lock); 799 + mutex_unlock(&evl->lock); 800 800 return 0; 801 801 802 802 err_alloc: ··· 819 819 if (!gencfg.evl_en) 820 820 return; 821 821 822 - spin_lock(&evl->lock); 822 + mutex_lock(&evl->lock); 823 823 gencfg.evl_en = 0; 824 824 iowrite32(gencfg.bits, idxd->reg_base + IDXD_GENCFG_OFFSET); 825 825 ··· 836 836 evl_dma = evl->dma; 837 837 evl->log = NULL; 838 838 evl->size = IDXD_EVL_SIZE_MIN; 839 - spin_unlock(&evl->lock); 839 + mutex_unlock(&evl->lock); 840 840 841 841 dma_free_coherent(dev, evl_log_size, evl_log, evl_dma); 842 842 }

+1 -1

drivers/dma/idxd/idxd.h

··· 293 293 294 294 struct idxd_evl { 295 295 /* Lock to protect event log access. */ 296 - spinlock_t lock; 296 + struct mutex lock; 297 297 void *log; 298 298 dma_addr_t dma; 299 299 /* Total size of event log = number of entries * entry size. */

+1 -1

drivers/dma/idxd/init.c

··· 354 354 if (!evl) 355 355 return -ENOMEM; 356 356 357 - spin_lock_init(&evl->lock); 357 + mutex_init(&evl->lock); 358 358 evl->size = IDXD_EVL_SIZE_MIN; 359 359 360 360 idxd_name = dev_name(idxd_confdev(idxd));

+2 -2

drivers/dma/idxd/irq.c

··· 363 363 evl_status.bits = 0; 364 364 evl_status.int_pending = 1; 365 365 366 - spin_lock(&evl->lock); 366 + mutex_lock(&evl->lock); 367 367 /* Clear interrupt pending bit */ 368 368 iowrite32(evl_status.bits_upper32, 369 369 idxd->reg_base + IDXD_EVLSTATUS_OFFSET + sizeof(u32)); ··· 380 380 381 381 evl_status.head = h; 382 382 iowrite32(evl_status.bits_lower32, idxd->reg_base + IDXD_EVLSTATUS_OFFSET); 383 - spin_unlock(&evl->lock); 383 + mutex_unlock(&evl->lock); 384 384 } 385 385 386 386 irqreturn_t idxd_misc_thread(int vec, void *data)

+3 -6

drivers/dma/idxd/perfmon.c

··· 528 528 return 0; 529 529 530 530 target = cpumask_any_but(cpu_online_mask, cpu); 531 - 532 531 /* migrate events if there is a valid target */ 533 - if (target < nr_cpu_ids) 532 + if (target < nr_cpu_ids) { 534 533 cpumask_set_cpu(target, &perfmon_dsa_cpu_mask); 535 - else 536 - target = -1; 537 - 538 - perf_pmu_migrate_context(&idxd_pmu->pmu, cpu, target); 534 + perf_pmu_migrate_context(&idxd_pmu->pmu, cpu, target); 535 + } 539 536 540 537 return 0; 541 538 }

+2 -2

drivers/dma/owl-dma.c

··· 250 250 else 251 251 regval &= ~val; 252 252 253 - writel(val, pchan->base + reg); 253 + writel(regval, pchan->base + reg); 254 254 } 255 255 256 256 static void pchan_writel(struct owl_dma_pchan *pchan, u32 reg, u32 data) ··· 274 274 else 275 275 regval &= ~val; 276 276 277 - writel(val, od->base + reg); 277 + writel(regval, od->base + reg); 278 278 } 279 279 280 280 static void dma_writel(struct owl_dma *od, u32 reg, u32 data)

-3

drivers/dma/pl330.c

··· 1053 1053 1054 1054 thrd->req_running = idx; 1055 1055 1056 - if (desc->rqtype == DMA_MEM_TO_DEV || desc->rqtype == DMA_DEV_TO_MEM) 1057 - UNTIL(thrd, PL330_STATE_WFP); 1058 - 1059 1056 return true; 1060 1057 } 1061 1058

+3

drivers/dma/tegra186-gpc-dma.c

··· 746 746 bytes_xfer = dma_desc->bytes_xfer + 747 747 sg_req[dma_desc->sg_idx].len - (wcount * 4); 748 748 749 + if (dma_desc->bytes_req == bytes_xfer) 750 + return 0; 751 + 749 752 residual = dma_desc->bytes_req - (bytes_xfer % dma_desc->bytes_req); 750 753 751 754 return residual;

+3

drivers/dma/xilinx/xdma-regs.h

··· 117 117 CHAN_CTRL_IE_WRITE_ERROR | \ 118 118 CHAN_CTRL_IE_DESC_ERROR) 119 119 120 + /* bits of the channel status register */ 121 + #define XDMA_CHAN_STATUS_BUSY BIT(0) 122 + 120 123 #define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START 121 124 122 125 #define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH | \

+27 -15

drivers/dma/xilinx/xdma.c

··· 71 71 enum dma_transfer_direction dir; 72 72 struct dma_slave_config cfg; 73 73 u32 irq; 74 + struct completion last_interrupt; 75 + bool stop_requested; 74 76 }; 75 77 76 78 /** ··· 378 376 return ret; 379 377 380 378 xchan->busy = true; 379 + xchan->stop_requested = false; 380 + reinit_completion(&xchan->last_interrupt); 381 381 382 382 return 0; 383 383 } ··· 391 387 static int xdma_xfer_stop(struct xdma_chan *xchan) 392 388 { 393 389 int ret; 394 - u32 val; 395 390 struct xdma_device *xdev = xchan->xdev_hdl; 396 391 397 392 /* clear run stop bit to prevent any further auto-triggering */ ··· 398 395 CHAN_CTRL_RUN_STOP); 399 396 if (ret) 400 397 return ret; 401 - 402 - /* Clear the channel status register */ 403 - ret = regmap_read(xdev->rmap, xchan->base + XDMA_CHAN_STATUS_RC, &val); 404 - if (ret) 405 - return ret; 406 - 407 - return 0; 398 + return ret; 408 399 } 409 400 410 401 /** ··· 471 474 xchan->xdev_hdl = xdev; 472 475 xchan->base = base + i * XDMA_CHAN_STRIDE; 473 476 xchan->dir = dir; 477 + xchan->stop_requested = false; 478 + init_completion(&xchan->last_interrupt); 474 479 475 480 ret = xdma_channel_init(xchan); 476 481 if (ret) ··· 520 521 spin_lock_irqsave(&xdma_chan->vchan.lock, flags); 521 522 522 523 xdma_chan->busy = false; 524 + xdma_chan->stop_requested = true; 523 525 vd = vchan_next_desc(&xdma_chan->vchan); 524 526 if (vd) { 525 527 list_del(&vd->node); ··· 542 542 static void xdma_synchronize(struct dma_chan *chan) 543 543 { 544 544 struct xdma_chan *xdma_chan = to_xdma_chan(chan); 545 + struct xdma_device *xdev = xdma_chan->xdev_hdl; 546 + int st = 0; 547 + 548 + /* If the engine continues running, wait for the last interrupt */ 549 + regmap_read(xdev->rmap, xdma_chan->base + XDMA_CHAN_STATUS, &st); 550 + if (st & XDMA_CHAN_STATUS_BUSY) 551 + wait_for_completion_timeout(&xdma_chan->last_interrupt, msecs_to_jiffies(1000)); 545 552 546 553 vchan_synchronize(&xdma_chan->vchan); 547 554 } 548 555 549 556 /** 550 - * xdma_fill_descs - Fill hardware descriptors with contiguous memory block addresses 551 - * @sw_desc: tx descriptor state container 552 - * @src_addr: Value for a ->src_addr field of a first descriptor 553 - * @dst_addr: Value for a ->dst_addr field of a first descriptor 554 - * @size: Total size of a contiguous memory block 555 - * @filled_descs_num: Number of filled hardware descriptors for corresponding sw_desc 557 + * xdma_fill_descs() - Fill hardware descriptors for one contiguous memory chunk. 558 + * More than one descriptor will be used if the size is bigger 559 + * than XDMA_DESC_BLEN_MAX. 560 + * @sw_desc: Descriptor container 561 + * @src_addr: First value for the ->src_addr field 562 + * @dst_addr: First value for the ->dst_addr field 563 + * @size: Size of the contiguous memory block 564 + * @filled_descs_num: Index of the first descriptor to take care of in @sw_desc 556 565 */ 557 566 static inline u32 xdma_fill_descs(struct xdma_desc *sw_desc, u64 src_addr, 558 567 u64 dst_addr, u32 size, u32 filled_descs_num) ··· 713 704 desc_num = 0; 714 705 for (i = 0; i < periods; i++) { 715 706 desc_num += xdma_fill_descs(sw_desc, *src, *dst, period_size, desc_num); 716 - addr += i * period_size; 707 + addr += period_size; 717 708 } 718 709 719 710 tx_desc = vchan_tx_prep(&xdma_chan->vchan, &sw_desc->vdesc, flags); ··· 884 875 int ret; 885 876 u32 st; 886 877 bool repeat_tx; 878 + 879 + if (xchan->stop_requested) 880 + complete(&xchan->last_interrupt); 887 881 888 882 spin_lock(&xchan->vchan.lock); 889 883

+10 -3

drivers/dma/xilinx/xilinx_dpdma.c

··· 214 214 * @running: true if the channel is running 215 215 * @first_frame: flag for the first frame of stream 216 216 * @video_group: flag if multi-channel operation is needed for video channels 217 - * @lock: lock to access struct xilinx_dpdma_chan 217 + * @lock: lock to access struct xilinx_dpdma_chan. Must be taken before 218 + * @vchan.lock, if both are to be held. 218 219 * @desc_pool: descriptor allocation pool 219 220 * @err_task: error IRQ bottom half handler 220 221 * @desc: References to descriptors being processed ··· 1098 1097 * Complete the active descriptor, if any, promote the pending 1099 1098 * descriptor to active, and queue the next transfer, if any. 1100 1099 */ 1100 + spin_lock(&chan->vchan.lock); 1101 1101 if (chan->desc.active) 1102 1102 vchan_cookie_complete(&chan->desc.active->vdesc); 1103 1103 chan->desc.active = pending; 1104 1104 chan->desc.pending = NULL; 1105 1105 1106 1106 xilinx_dpdma_chan_queue_transfer(chan); 1107 + spin_unlock(&chan->vchan.lock); 1107 1108 1108 1109 out: 1109 1110 spin_unlock_irqrestore(&chan->lock, flags); ··· 1267 1264 struct xilinx_dpdma_chan *chan = to_xilinx_chan(dchan); 1268 1265 unsigned long flags; 1269 1266 1270 - spin_lock_irqsave(&chan->vchan.lock, flags); 1267 + spin_lock_irqsave(&chan->lock, flags); 1268 + spin_lock(&chan->vchan.lock); 1271 1269 if (vchan_issue_pending(&chan->vchan)) 1272 1270 xilinx_dpdma_chan_queue_transfer(chan); 1273 - spin_unlock_irqrestore(&chan->vchan.lock, flags); 1271 + spin_unlock(&chan->vchan.lock); 1272 + spin_unlock_irqrestore(&chan->lock, flags); 1274 1273 } 1275 1274 1276 1275 static int xilinx_dpdma_config(struct dma_chan *dchan, ··· 1500 1495 XILINX_DPDMA_EINTR_CHAN_ERR_MASK << chan->id); 1501 1496 1502 1497 spin_lock_irqsave(&chan->lock, flags); 1498 + spin_lock(&chan->vchan.lock); 1503 1499 xilinx_dpdma_chan_queue_transfer(chan); 1500 + spin_unlock(&chan->vchan.lock); 1504 1501 spin_unlock_irqrestore(&chan->lock, flags); 1505 1502 } 1506 1503

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