Merge branch 'net-bcmasp-add-v3-0-and-remove-v2-0'

+11 -12

Documentation/devicetree/bindings/net/brcm,asp-v2.0.yaml

··· 4 4 $id: http://devicetree.org/schemas/net/brcm,asp-v2.0.yaml# 5 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 6 6 7 - title: Broadcom ASP 2.0 Ethernet controller 7 + title: Broadcom ASP Ethernet controller 8 8 9 9 maintainers: 10 10 - Justin Chen <justin.chen@broadcom.com> ··· 17 17 oneOf: 18 18 - items: 19 19 - enum: 20 + - brcm,bcm74110-asp 21 + - const: brcm,asp-v3.0 22 + - items: 23 + - enum: 20 24 - brcm,bcm74165b0-asp 21 25 - const: brcm,asp-v2.2 22 26 - items: 23 27 - enum: 24 28 - brcm,bcm74165-asp 25 29 - const: brcm,asp-v2.1 26 - - items: 27 - - enum: 28 - - brcm,bcm72165-asp 29 - - const: brcm,asp-v2.0 30 30 31 31 "#address-cells": 32 32 const: 1 ··· 39 39 ranges: true 40 40 41 41 interrupts: 42 - minItems: 1 43 42 items: 44 43 - description: RX/TX interrupt 45 - - description: Port 0 Wake-on-LAN 46 - - description: Port 1 Wake-on-LAN 44 + - description: Wake-on-LAN interrupt 47 45 48 46 clocks: 49 47 maxItems: 1 ··· 104 106 #include <dt-bindings/interrupt-controller/arm-gic.h> 105 107 106 108 ethernet@9c00000 { 107 - compatible = "brcm,bcm72165-asp", "brcm,asp-v2.0"; 109 + compatible = "brcm,bcm74165-asp", "brcm,asp-v2.1"; 108 110 reg = <0x9c00000 0x1fff14>; 109 - interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 111 + interrupts-extended = <&intc GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 112 + <&aon_pm_l2_intc 14>; 110 113 ranges = <0x0 0x9c00000 0x1fff14>; 111 114 clocks = <&scmi 14>; 112 115 #address-cells = <1>; 113 116 #size-cells = <1>; 114 117 115 118 mdio@c614 { 116 - compatible = "brcm,asp-v2.0-mdio"; 119 + compatible = "brcm,asp-v2.1-mdio"; 117 120 reg = <0xc614 0x8>; 118 121 reg-names = "mdio"; 119 122 #address-cells = <1>; ··· 126 127 }; 127 128 128 129 mdio@ce14 { 129 - compatible = "brcm,asp-v2.0-mdio"; 130 + compatible = "brcm,asp-v2.1-mdio"; 130 131 reg = <0xce14 0x8>; 131 132 reg-names = "mdio"; 132 133 #address-cells = <1>;

+1 -1

Documentation/devicetree/bindings/net/brcm,unimac-mdio.yaml

··· 22 22 - brcm,genet-mdio-v3 23 23 - brcm,genet-mdio-v4 24 24 - brcm,genet-mdio-v5 25 - - brcm,asp-v2.0-mdio 26 25 - brcm,asp-v2.1-mdio 27 26 - brcm,asp-v2.2-mdio 27 + - brcm,asp-v3.0-mdio 28 28 - brcm,unimac-mdio 29 29 - brcm,bcm6846-mdio 30 30

+65 -111

drivers/net/ethernet/broadcom/asp2/bcmasp.c

··· 141 141 return; 142 142 } 143 143 144 - rx_ctrl_core_wl(priv, mask, priv->hw_info->rx_ctrl_flush); 144 + rx_ctrl_core_wl(priv, mask, ASP_RX_CTRL_FLUSH); 145 145 } 146 146 147 147 static void bcmasp_netfilt_hw_en_wake(struct bcmasp_priv *priv, ··· 518 518 int ret, i; 519 519 520 520 /* Write all filters to HW */ 521 - for (i = 0; i < NUM_NET_FILTERS; i++) { 521 + for (i = 0; i < priv->num_net_filters; i++) { 522 522 /* If the filter does not match the port, skip programming. */ 523 523 if (!priv->net_filters[i].claimed || 524 524 priv->net_filters[i].port != intf->port) ··· 551 551 struct bcmasp_priv *priv = intf->parent; 552 552 int j = 0, i; 553 553 554 - for (i = 0; i < NUM_NET_FILTERS; i++) { 554 + for (i = 0; i < priv->num_net_filters; i++) { 555 555 if (!priv->net_filters[i].claimed || 556 556 priv->net_filters[i].port != intf->port) 557 557 continue; ··· 577 577 struct bcmasp_priv *priv = intf->parent; 578 578 int cnt = 0, i; 579 579 580 - for (i = 0; i < NUM_NET_FILTERS; i++) { 580 + for (i = 0; i < priv->num_net_filters; i++) { 581 581 if (!priv->net_filters[i].claimed || 582 582 priv->net_filters[i].port != intf->port) 583 583 continue; ··· 602 602 size_t fs_size = 0; 603 603 int i; 604 604 605 - for (i = 0; i < NUM_NET_FILTERS; i++) { 605 + for (i = 0; i < priv->num_net_filters; i++) { 606 606 if (!priv->net_filters[i].claimed || 607 607 priv->net_filters[i].port != intf->port) 608 608 continue; ··· 670 670 int i, open_index = -1; 671 671 672 672 /* Check whether we exceed the filter table capacity */ 673 - if (loc != RX_CLS_LOC_ANY && loc >= NUM_NET_FILTERS) 673 + if (loc != RX_CLS_LOC_ANY && loc >= priv->num_net_filters) 674 674 return ERR_PTR(-EINVAL); 675 675 676 676 /* If the filter location is busy (already claimed) and we are initializing ··· 686 686 /* Initialize the loop index based on the desired location or from 0 */ 687 687 i = loc == RX_CLS_LOC_ANY ? 0 : loc; 688 688 689 - for ( ; i < NUM_NET_FILTERS; i++) { 689 + for ( ; i < priv->num_net_filters; i++) { 690 690 /* Found matching network filter */ 691 691 if (!init && 692 692 priv->net_filters[i].claimed && ··· 779 779 priv->mda_filters[i].en = en; 780 780 priv->mda_filters[i].port = intf->port; 781 781 782 - rx_filter_core_wl(priv, ((intf->channel + 8) | 782 + rx_filter_core_wl(priv, ((intf->channel + priv->tx_chan_offset) | 783 783 (en << ASP_RX_FILTER_MDA_CFG_EN_SHIFT) | 784 784 ASP_RX_FILTER_MDA_CFG_UMC_SEL(intf->port)), 785 785 ASP_RX_FILTER_MDA_CFG(i)); ··· 865 865 res_count = bcmasp_total_res_mda_cnt(intf->parent); 866 866 867 867 /* Disable all filters held by this port */ 868 - for (i = res_count; i < NUM_MDA_FILTERS; i++) { 868 + for (i = res_count; i < priv->num_mda_filters; i++) { 869 869 if (priv->mda_filters[i].en && 870 870 priv->mda_filters[i].port == intf->port) 871 871 bcmasp_en_mda_filter(intf, 0, i); ··· 909 909 910 910 res_count = bcmasp_total_res_mda_cnt(intf->parent); 911 911 912 - for (i = res_count; i < NUM_MDA_FILTERS; i++) { 912 + for (i = res_count; i < priv->num_mda_filters; i++) { 913 913 /* If filter not enabled or belongs to another port skip */ 914 914 if (!priv->mda_filters[i].en || 915 915 priv->mda_filters[i].port != intf->port) ··· 924 924 } 925 925 926 926 /* Create new filter if possible */ 927 - for (i = res_count; i < NUM_MDA_FILTERS; i++) { 927 + for (i = res_count; i < priv->num_mda_filters; i++) { 928 928 if (priv->mda_filters[i].en) 929 929 continue; 930 930 ··· 944 944 /* Disable all filters and reset software view since the HW 945 945 * can lose context while in deep sleep suspend states 946 946 */ 947 - for (i = 0; i < NUM_MDA_FILTERS; i++) { 947 + for (i = 0; i < priv->num_mda_filters; i++) { 948 948 rx_filter_core_wl(priv, 0x0, ASP_RX_FILTER_MDA_CFG(i)); 949 949 priv->mda_filters[i].en = 0; 950 950 } 951 951 952 - for (i = 0; i < NUM_NET_FILTERS; i++) 952 + for (i = 0; i < priv->num_net_filters; i++) 953 953 rx_filter_core_wl(priv, 0x0, ASP_RX_FILTER_NET_CFG(i)); 954 954 955 955 /* Top level filter enable bit should be enabled at all times, set ··· 966 966 /* ASP core initialization */ 967 967 static void bcmasp_core_init(struct bcmasp_priv *priv) 968 968 { 969 - tx_analytics_core_wl(priv, 0x0, ASP_TX_ANALYTICS_CTRL); 970 - rx_analytics_core_wl(priv, 0x4, ASP_RX_ANALYTICS_CTRL); 971 - 972 - rx_edpkt_core_wl(priv, (ASP_EDPKT_HDR_SZ_128 << ASP_EDPKT_HDR_SZ_SHIFT), 973 - ASP_EDPKT_HDR_CFG); 974 - rx_edpkt_core_wl(priv, 975 - (ASP_EDPKT_ENDI_BT_SWP_WD << ASP_EDPKT_ENDI_DESC_SHIFT), 976 - ASP_EDPKT_ENDI); 977 - 978 969 rx_edpkt_core_wl(priv, 0x1b, ASP_EDPKT_BURST_BUF_PSCAL_TOUT); 979 970 rx_edpkt_core_wl(priv, 0x3e8, ASP_EDPKT_BURST_BUF_WRITE_TOUT); 980 - rx_edpkt_core_wl(priv, 0x3e8, ASP_EDPKT_BURST_BUF_READ_TOUT); 981 971 982 972 rx_edpkt_core_wl(priv, ASP_EDPKT_ENABLE_EN, ASP_EDPKT_ENABLE); 983 973 ··· 1008 1018 else 1009 1019 reg |= ASP_CTRL_CORE_CLOCK_SELECT_MAIN; 1010 1020 ctrl_core_wl(priv, reg, ASP_CTRL_CORE_CLOCK_SELECT); 1021 + } 1022 + 1023 + static void bcmasp_core_clock_select_one_ctrl2(struct bcmasp_priv *priv, bool slow) 1024 + { 1025 + u32 reg; 1026 + 1027 + reg = ctrl2_core_rl(priv, ASP_CTRL2_CORE_CLOCK_SELECT); 1028 + if (slow) 1029 + reg &= ~ASP_CTRL2_CORE_CLOCK_SELECT_MAIN; 1030 + else 1031 + reg |= ASP_CTRL2_CORE_CLOCK_SELECT_MAIN; 1032 + ctrl2_core_wl(priv, reg, ASP_CTRL2_CORE_CLOCK_SELECT); 1011 1033 } 1012 1034 1013 1035 static void bcmasp_core_clock_set_ll(struct bcmasp_priv *priv, u32 clr, u32 set) ··· 1110 1108 return irq; 1111 1109 } 1112 1110 1113 - static void bcmasp_init_wol_shared(struct bcmasp_priv *priv) 1111 + static void bcmasp_init_wol(struct bcmasp_priv *priv) 1114 1112 { 1115 1113 struct platform_device *pdev = priv->pdev; 1116 1114 struct device *dev = &pdev->dev; ··· 1127 1125 device_set_wakeup_capable(&pdev->dev, 1); 1128 1126 } 1129 1127 1130 - static void bcmasp_enable_wol_shared(struct bcmasp_intf *intf, bool en) 1128 + void bcmasp_enable_wol(struct bcmasp_intf *intf, bool en) 1131 1129 { 1132 1130 struct bcmasp_priv *priv = intf->parent; 1133 1131 struct device *dev = &priv->pdev->dev; ··· 1156 1154 } 1157 1155 } 1158 1156 1159 - static void bcmasp_wol_irq_destroy_shared(struct bcmasp_priv *priv) 1157 + static void bcmasp_wol_irq_destroy(struct bcmasp_priv *priv) 1160 1158 { 1161 1159 if (priv->wol_irq > 0) 1162 1160 free_irq(priv->wol_irq, priv); 1163 - } 1164 - 1165 - static void bcmasp_init_wol_per_intf(struct bcmasp_priv *priv) 1166 - { 1167 - struct platform_device *pdev = priv->pdev; 1168 - struct device *dev = &pdev->dev; 1169 - struct bcmasp_intf *intf; 1170 - int irq; 1171 - 1172 - list_for_each_entry(intf, &priv->intfs, list) { 1173 - irq = bcmasp_get_and_request_irq(priv, intf->port + 1); 1174 - if (irq < 0) { 1175 - dev_warn(dev, "Failed to init WoL irq(port %d): %d\n", 1176 - intf->port, irq); 1177 - continue; 1178 - } 1179 - 1180 - intf->wol_irq = irq; 1181 - intf->wol_irq_enabled = false; 1182 - device_set_wakeup_capable(&pdev->dev, 1); 1183 - } 1184 - } 1185 - 1186 - static void bcmasp_enable_wol_per_intf(struct bcmasp_intf *intf, bool en) 1187 - { 1188 - struct device *dev = &intf->parent->pdev->dev; 1189 - 1190 - if (en ^ intf->wol_irq_enabled) 1191 - irq_set_irq_wake(intf->wol_irq, en); 1192 - 1193 - intf->wol_irq_enabled = en; 1194 - device_set_wakeup_enable(dev, en); 1195 - } 1196 - 1197 - static void bcmasp_wol_irq_destroy_per_intf(struct bcmasp_priv *priv) 1198 - { 1199 - struct bcmasp_intf *intf; 1200 - 1201 - list_for_each_entry(intf, &priv->intfs, list) { 1202 - if (intf->wol_irq > 0) 1203 - free_irq(intf->wol_irq, priv); 1204 - } 1205 1161 } 1206 1162 1207 1163 static void bcmasp_eee_fixup(struct bcmasp_intf *intf, bool en) ··· 1180 1220 usleep_range(50, 100); 1181 1221 } 1182 1222 1183 - static struct bcmasp_hw_info v20_hw_info = { 1184 - .rx_ctrl_flush = ASP_RX_CTRL_FLUSH, 1185 - .umac2fb = UMAC2FB_OFFSET, 1186 - .rx_ctrl_fb_out_frame_count = ASP_RX_CTRL_FB_OUT_FRAME_COUNT, 1187 - .rx_ctrl_fb_filt_out_frame_count = ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT, 1188 - .rx_ctrl_fb_rx_fifo_depth = ASP_RX_CTRL_FB_RX_FIFO_DEPTH, 1189 - }; 1190 - 1191 - static const struct bcmasp_plat_data v20_plat_data = { 1192 - .init_wol = bcmasp_init_wol_per_intf, 1193 - .enable_wol = bcmasp_enable_wol_per_intf, 1194 - .destroy_wol = bcmasp_wol_irq_destroy_per_intf, 1195 - .core_clock_select = bcmasp_core_clock_select_one, 1196 - .hw_info = &v20_hw_info, 1197 - }; 1198 - 1199 - static struct bcmasp_hw_info v21_hw_info = { 1200 - .rx_ctrl_flush = ASP_RX_CTRL_FLUSH_2_1, 1201 - .umac2fb = UMAC2FB_OFFSET_2_1, 1202 - .rx_ctrl_fb_out_frame_count = ASP_RX_CTRL_FB_OUT_FRAME_COUNT_2_1, 1203 - .rx_ctrl_fb_filt_out_frame_count = 1204 - ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT_2_1, 1205 - .rx_ctrl_fb_rx_fifo_depth = ASP_RX_CTRL_FB_RX_FIFO_DEPTH_2_1, 1206 - }; 1207 - 1208 1223 static const struct bcmasp_plat_data v21_plat_data = { 1209 - .init_wol = bcmasp_init_wol_shared, 1210 - .enable_wol = bcmasp_enable_wol_shared, 1211 - .destroy_wol = bcmasp_wol_irq_destroy_shared, 1212 1224 .core_clock_select = bcmasp_core_clock_select_one, 1213 - .hw_info = &v21_hw_info, 1225 + .num_mda_filters = 32, 1226 + .num_net_filters = 32, 1227 + .tx_chan_offset = 8, 1228 + .rx_ctrl_offset = 0x0, 1214 1229 }; 1215 1230 1216 1231 static const struct bcmasp_plat_data v22_plat_data = { 1217 - .init_wol = bcmasp_init_wol_shared, 1218 - .enable_wol = bcmasp_enable_wol_shared, 1219 - .destroy_wol = bcmasp_wol_irq_destroy_shared, 1220 1232 .core_clock_select = bcmasp_core_clock_select_many, 1221 - .hw_info = &v21_hw_info, 1222 1233 .eee_fixup = bcmasp_eee_fixup, 1234 + .num_mda_filters = 32, 1235 + .num_net_filters = 32, 1236 + .tx_chan_offset = 8, 1237 + .rx_ctrl_offset = 0x0, 1238 + }; 1239 + 1240 + static const struct bcmasp_plat_data v30_plat_data = { 1241 + .core_clock_select = bcmasp_core_clock_select_one_ctrl2, 1242 + .num_mda_filters = 20, 1243 + .num_net_filters = 16, 1244 + .tx_chan_offset = 0, 1245 + .rx_ctrl_offset = 0x10000, 1223 1246 }; 1224 1247 1225 1248 static void bcmasp_set_pdata(struct bcmasp_priv *priv, const struct bcmasp_plat_data *pdata) 1226 1249 { 1227 - priv->init_wol = pdata->init_wol; 1228 - priv->enable_wol = pdata->enable_wol; 1229 - priv->destroy_wol = pdata->destroy_wol; 1230 1250 priv->core_clock_select = pdata->core_clock_select; 1231 1251 priv->eee_fixup = pdata->eee_fixup; 1232 - priv->hw_info = pdata->hw_info; 1252 + priv->num_mda_filters = pdata->num_mda_filters; 1253 + priv->num_net_filters = pdata->num_net_filters; 1254 + priv->tx_chan_offset = pdata->tx_chan_offset; 1255 + priv->rx_ctrl_offset = pdata->rx_ctrl_offset; 1233 1256 } 1234 1257 1235 1258 static const struct of_device_id bcmasp_of_match[] = { 1236 - { .compatible = "brcm,asp-v2.0", .data = &v20_plat_data }, 1237 1259 { .compatible = "brcm,asp-v2.1", .data = &v21_plat_data }, 1238 1260 { .compatible = "brcm,asp-v2.2", .data = &v22_plat_data }, 1261 + { .compatible = "brcm,asp-v3.0", .data = &v30_plat_data }, 1239 1262 { /* sentinel */ }, 1240 1263 }; 1241 1264 MODULE_DEVICE_TABLE(of, bcmasp_of_match); 1242 1265 1243 1266 static const struct of_device_id bcmasp_mdio_of_match[] = { 1244 - { .compatible = "brcm,asp-v2.2-mdio", }, 1245 1267 { .compatible = "brcm,asp-v2.1-mdio", }, 1246 - { .compatible = "brcm,asp-v2.0-mdio", }, 1268 + { .compatible = "brcm,asp-v2.2-mdio", }, 1269 + { .compatible = "brcm,asp-v3.0-mdio", }, 1247 1270 { /* sentinel */ }, 1248 1271 }; 1249 1272 MODULE_DEVICE_TABLE(of, bcmasp_mdio_of_match); ··· 1308 1365 * how many interfaces come up. 1309 1366 */ 1310 1367 bcmasp_core_init(priv); 1368 + 1369 + priv->mda_filters = devm_kcalloc(dev, priv->num_mda_filters, 1370 + sizeof(*priv->mda_filters), GFP_KERNEL); 1371 + if (!priv->mda_filters) 1372 + return -ENOMEM; 1373 + 1374 + priv->net_filters = devm_kcalloc(dev, priv->num_net_filters, 1375 + sizeof(*priv->net_filters), GFP_KERNEL); 1376 + if (!priv->net_filters) 1377 + return -ENOMEM; 1378 + 1311 1379 bcmasp_core_init_filters(priv); 1312 1380 1313 1381 ports_node = of_find_node_by_name(dev->of_node, "ethernet-ports"); ··· 1341 1387 } 1342 1388 1343 1389 /* Check and enable WoL */ 1344 - priv->init_wol(priv); 1390 + bcmasp_init_wol(priv); 1345 1391 1346 1392 /* Drop the clock reference count now and let ndo_open()/ndo_close() 1347 1393 * manage it for us from now on. ··· 1358 1404 if (ret) { 1359 1405 netdev_err(intf->ndev, 1360 1406 "failed to register net_device: %d\n", ret); 1361 - priv->destroy_wol(priv); 1407 + bcmasp_wol_irq_destroy(priv); 1362 1408 bcmasp_remove_intfs(priv); 1363 1409 goto of_put_exit; 1364 1410 } ··· 1379 1425 if (!priv) 1380 1426 return; 1381 1427 1382 - priv->destroy_wol(priv); 1428 + bcmasp_wol_irq_destroy(priv); 1383 1429 bcmasp_remove_intfs(priv); 1384 1430 } 1385 1431

+38 -40

drivers/net/ethernet/broadcom/asp2/bcmasp.h

··· 53 53 #define ASP_RX_CTRL_FB_0_FRAME_COUNT 0x14 54 54 #define ASP_RX_CTRL_FB_1_FRAME_COUNT 0x18 55 55 #define ASP_RX_CTRL_FB_8_FRAME_COUNT 0x1c 56 - /* asp2.1 diverges offsets here */ 57 - /* ASP2.0 */ 58 - #define ASP_RX_CTRL_FB_OUT_FRAME_COUNT 0x20 59 - #define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT 0x24 60 - #define ASP_RX_CTRL_FLUSH 0x28 61 - #define ASP_CTRL_UMAC0_FLUSH_MASK (BIT(0) | BIT(12)) 62 - #define ASP_CTRL_UMAC1_FLUSH_MASK (BIT(1) | BIT(13)) 63 - #define ASP_CTRL_SPB_FLUSH_MASK (BIT(8) | BIT(20)) 64 - #define ASP_RX_CTRL_FB_RX_FIFO_DEPTH 0x30 65 - /* ASP2.1 */ 66 - #define ASP_RX_CTRL_FB_9_FRAME_COUNT_2_1 0x20 67 - #define ASP_RX_CTRL_FB_10_FRAME_COUNT_2_1 0x24 68 - #define ASP_RX_CTRL_FB_OUT_FRAME_COUNT_2_1 0x28 69 - #define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT_2_1 0x2c 70 - #define ASP_RX_CTRL_FLUSH_2_1 0x30 71 - #define ASP_RX_CTRL_FB_RX_FIFO_DEPTH_2_1 0x38 56 + #define ASP_RX_CTRL_FB_9_FRAME_COUNT 0x20 57 + #define ASP_RX_CTRL_FB_10_FRAME_COUNT 0x24 58 + #define ASP_RX_CTRL_FB_OUT_FRAME_COUNT 0x28 59 + #define ASP_RX_CTRL_FB_FILT_OUT_FRAME_COUNT 0x2c 60 + #define ASP_RX_CTRL_FLUSH 0x30 61 + #define ASP_CTRL_UMAC0_FLUSH_MASK (BIT(0) | BIT(12)) 62 + #define ASP_CTRL_UMAC1_FLUSH_MASK (BIT(1) | BIT(13)) 63 + #define ASP_CTRL_SPB_FLUSH_MASK (BIT(8) | BIT(20)) 64 + #define ASP_RX_CTRL_FB_RX_FIFO_DEPTH 0x38 72 65 73 66 #define ASP_RX_FILTER_OFFSET 0x80000 74 67 #define ASP_RX_FILTER_BLK_CTRL 0x0 ··· 338 345 339 346 u32 wolopts; 340 347 u8 sopass[SOPASS_MAX]; 341 - /* Used if per intf wol irq */ 342 - int wol_irq; 343 - unsigned int wol_irq_enabled:1; 344 348 }; 345 349 346 350 #define NUM_NET_FILTERS 32 ··· 360 370 u8 mask[ETH_ALEN]; 361 371 }; 362 372 363 - struct bcmasp_hw_info { 364 - u32 rx_ctrl_flush; 365 - u32 umac2fb; 366 - u32 rx_ctrl_fb_out_frame_count; 367 - u32 rx_ctrl_fb_filt_out_frame_count; 368 - u32 rx_ctrl_fb_rx_fifo_depth; 369 - }; 370 - 371 373 struct bcmasp_plat_data { 372 - void (*init_wol)(struct bcmasp_priv *priv); 373 - void (*enable_wol)(struct bcmasp_intf *intf, bool en); 374 - void (*destroy_wol)(struct bcmasp_priv *priv); 375 374 void (*core_clock_select)(struct bcmasp_priv *priv, bool slow); 376 375 void (*eee_fixup)(struct bcmasp_intf *priv, bool en); 377 - struct bcmasp_hw_info *hw_info; 376 + unsigned int num_mda_filters; 377 + unsigned int num_net_filters; 378 + unsigned int tx_chan_offset; 379 + unsigned int rx_ctrl_offset; 378 380 }; 379 381 380 382 struct bcmasp_priv { ··· 381 399 int wol_irq; 382 400 unsigned long wol_irq_enabled_mask; 383 401 384 - void (*init_wol)(struct bcmasp_priv *priv); 385 - void (*enable_wol)(struct bcmasp_intf *intf, bool en); 386 - void (*destroy_wol)(struct bcmasp_priv *priv); 387 402 void (*core_clock_select)(struct bcmasp_priv *priv, bool slow); 388 403 void (*eee_fixup)(struct bcmasp_intf *intf, bool en); 404 + unsigned int num_mda_filters; 405 + unsigned int num_net_filters; 406 + unsigned int tx_chan_offset; 407 + unsigned int rx_ctrl_offset; 389 408 390 409 void __iomem *base; 391 - struct bcmasp_hw_info *hw_info; 392 410 393 411 struct list_head intfs; 394 412 395 - struct bcmasp_mda_filter mda_filters[NUM_MDA_FILTERS]; 413 + struct bcmasp_mda_filter *mda_filters; 396 414 397 415 /* MAC destination address filters lock */ 398 416 spinlock_t mda_lock; ··· 400 418 /* Protects accesses to ASP_CTRL_CLOCK_CTRL */ 401 419 spinlock_t clk_lock; 402 420 403 - struct bcmasp_net_filter net_filters[NUM_NET_FILTERS]; 421 + struct bcmasp_net_filter *net_filters; 404 422 405 423 /* Network filter lock */ 406 424 struct mutex net_lock; ··· 490 508 #define PKT_OFFLOAD_EPKT_IP(x) ((x) << 21) 491 509 #define PKT_OFFLOAD_EPKT_TP(x) ((x) << 19) 492 510 #define PKT_OFFLOAD_EPKT_LEN(x) ((x) << 16) 493 - #define PKT_OFFLOAD_EPKT_CSUM_L3 BIT(15) 494 - #define PKT_OFFLOAD_EPKT_CSUM_L2 BIT(14) 511 + #define PKT_OFFLOAD_EPKT_CSUM_L4 BIT(15) 512 + #define PKT_OFFLOAD_EPKT_CSUM_L3 BIT(14) 495 513 #define PKT_OFFLOAD_EPKT_ID(x) ((x) << 12) 496 514 #define PKT_OFFLOAD_EPKT_SEQ(x) ((x) << 10) 497 515 #define PKT_OFFLOAD_EPKT_TS(x) ((x) << 8) ··· 523 541 BCMASP_CORE_IO_MACRO(wakeup_intr2, ASP_WAKEUP_INTR2_OFFSET); 524 542 BCMASP_CORE_IO_MACRO(tx_analytics, ASP_TX_ANALYTICS_OFFSET); 525 543 BCMASP_CORE_IO_MACRO(rx_analytics, ASP_RX_ANALYTICS_OFFSET); 526 - BCMASP_CORE_IO_MACRO(rx_ctrl, ASP_RX_CTRL_OFFSET); 527 544 BCMASP_CORE_IO_MACRO(rx_filter, ASP_RX_FILTER_OFFSET); 528 545 BCMASP_CORE_IO_MACRO(rx_edpkt, ASP_EDPKT_OFFSET); 529 546 BCMASP_CORE_IO_MACRO(ctrl, ASP_CTRL_OFFSET); 530 547 BCMASP_CORE_IO_MACRO(ctrl2, ASP_CTRL2_OFFSET); 548 + 549 + #define BCMASP_CORE_IO_MACRO_OFFSET(name, offset) \ 550 + static inline u32 name##_core_rl(struct bcmasp_priv *priv, \ 551 + u32 off) \ 552 + { \ 553 + u32 reg = readl_relaxed(priv->base + priv->name##_offset + \ 554 + (offset) + off); \ 555 + return reg; \ 556 + } \ 557 + static inline void name##_core_wl(struct bcmasp_priv *priv, \ 558 + u32 val, u32 off) \ 559 + { \ 560 + writel_relaxed(val, priv->base + priv->name##_offset + \ 561 + (offset) + off); \ 562 + } 563 + BCMASP_CORE_IO_MACRO_OFFSET(rx_ctrl, ASP_RX_CTRL_OFFSET); 531 564 532 565 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 533 566 struct device_node *ndev_dn, int i); ··· 596 599 597 600 void bcmasp_netfilt_suspend(struct bcmasp_intf *intf); 598 601 602 + void bcmasp_enable_wol(struct bcmasp_intf *intf, bool en); 599 603 #endif

+4 -32

drivers/net/ethernet/broadcom/asp2/bcmasp_ethtool.c

··· 10 10 #include "bcmasp_intf_defs.h" 11 11 12 12 enum bcmasp_stat_type { 13 - BCMASP_STAT_RX_EDPKT, 14 13 BCMASP_STAT_RX_CTRL, 15 14 BCMASP_STAT_RX_CTRL_PER_INTF, 16 15 BCMASP_STAT_SOFT, ··· 32 33 .reg_offset = offset, \ 33 34 } 34 35 35 - #define STAT_BCMASP_RX_EDPKT(str, offset) \ 36 - STAT_BCMASP_OFFSET(str, BCMASP_STAT_RX_EDPKT, offset) 37 36 #define STAT_BCMASP_RX_CTRL(str, offset) \ 38 37 STAT_BCMASP_OFFSET(str, BCMASP_STAT_RX_CTRL, offset) 39 38 #define STAT_BCMASP_RX_CTRL_PER_INTF(str, offset) \ ··· 39 42 40 43 /* Must match the order of struct bcmasp_mib_counters */ 41 44 static const struct bcmasp_stats bcmasp_gstrings_stats[] = { 42 - /* EDPKT counters */ 43 - STAT_BCMASP_RX_EDPKT("RX Time Stamp", ASP_EDPKT_RX_TS_COUNTER), 44 - STAT_BCMASP_RX_EDPKT("RX PKT Count", ASP_EDPKT_RX_PKT_CNT), 45 - STAT_BCMASP_RX_EDPKT("RX PKT Buffered", ASP_EDPKT_HDR_EXTR_CNT), 46 - STAT_BCMASP_RX_EDPKT("RX PKT Pushed to DRAM", ASP_EDPKT_HDR_OUT_CNT), 47 45 /* ASP RX control */ 48 46 STAT_BCMASP_RX_CTRL_PER_INTF("Frames From Unimac", 49 47 ASP_RX_CTRL_UMAC_0_FRAME_COUNT), ··· 62 70 }; 63 71 64 72 #define BCMASP_STATS_LEN ARRAY_SIZE(bcmasp_gstrings_stats) 65 - 66 - static u16 bcmasp_stat_fixup_offset(struct bcmasp_intf *intf, 67 - const struct bcmasp_stats *s) 68 - { 69 - struct bcmasp_priv *priv = intf->parent; 70 - 71 - if (!strcmp("Frames Out(Buffer)", s->stat_string)) 72 - return priv->hw_info->rx_ctrl_fb_out_frame_count; 73 - 74 - if (!strcmp("Frames Out(Filters)", s->stat_string)) 75 - return priv->hw_info->rx_ctrl_fb_filt_out_frame_count; 76 - 77 - if (!strcmp("RX Buffer FIFO Depth", s->stat_string)) 78 - return priv->hw_info->rx_ctrl_fb_rx_fifo_depth; 79 - 80 - return s->reg_offset; 81 - } 82 73 83 74 static int bcmasp_get_sset_count(struct net_device *dev, int string_set) 84 75 { ··· 101 126 char *p; 102 127 103 128 s = &bcmasp_gstrings_stats[i]; 104 - offset = bcmasp_stat_fixup_offset(intf, s); 129 + offset = s->reg_offset; 105 130 switch (s->type) { 106 131 case BCMASP_STAT_SOFT: 107 132 continue; 108 - case BCMASP_STAT_RX_EDPKT: 109 - val = rx_edpkt_core_rl(intf->parent, offset); 110 - break; 111 133 case BCMASP_STAT_RX_CTRL: 112 134 val = rx_ctrl_core_rl(intf->parent, offset); 113 135 break; ··· 187 215 memcpy(intf->sopass, wol->sopass, sizeof(wol->sopass)); 188 216 189 217 mutex_lock(&priv->wol_lock); 190 - priv->enable_wol(intf, !!intf->wolopts); 218 + bcmasp_enable_wol(intf, !!intf->wolopts); 191 219 mutex_unlock(&priv->wol_lock); 192 220 193 221 return 0; ··· 261 289 262 290 memcpy(&cmd->fs, &nfilter->fs, sizeof(nfilter->fs)); 263 291 264 - cmd->data = NUM_NET_FILTERS; 292 + cmd->data = intf->parent->num_net_filters; 265 293 266 294 return 0; 267 295 } ··· 308 336 break; 309 337 case ETHTOOL_GRXCLSRLALL: 310 338 err = bcmasp_netfilt_get_all_active(intf, rule_locs, &cmd->rule_cnt); 311 - cmd->data = NUM_NET_FILTERS; 339 + cmd->data = intf->parent->num_net_filters; 312 340 break; 313 341 default: 314 342 err = -EOPNOTSUPP;

+5 -8

drivers/net/ethernet/broadcom/asp2/bcmasp_intf.c

··· 180 180 case htons(ETH_P_IP): 181 181 header |= PKT_OFFLOAD_HDR_SIZE_2((ip_hdrlen(skb) >> 8) & 0xf); 182 182 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(ip_hdrlen(skb) & 0xff); 183 - epkt |= PKT_OFFLOAD_EPKT_IP(0) | PKT_OFFLOAD_EPKT_CSUM_L2; 183 + epkt |= PKT_OFFLOAD_EPKT_IP(0); 184 184 ip_proto = ip_hdr(skb)->protocol; 185 185 header_cnt += 2; 186 186 break; 187 187 case htons(ETH_P_IPV6): 188 188 header |= PKT_OFFLOAD_HDR_SIZE_2((IP6_HLEN >> 8) & 0xf); 189 189 header2 |= PKT_OFFLOAD_HDR2_SIZE_2(IP6_HLEN & 0xff); 190 - epkt |= PKT_OFFLOAD_EPKT_IP(1) | PKT_OFFLOAD_EPKT_CSUM_L2; 190 + epkt |= PKT_OFFLOAD_EPKT_IP(1); 191 191 ip_proto = ipv6_hdr(skb)->nexthdr; 192 192 header_cnt += 2; 193 193 break; ··· 198 198 switch (ip_proto) { 199 199 case IPPROTO_TCP: 200 200 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(tcp_hdrlen(skb)); 201 - epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L3; 201 + epkt |= PKT_OFFLOAD_EPKT_TP(0) | PKT_OFFLOAD_EPKT_CSUM_L4; 202 202 header_cnt++; 203 203 break; 204 204 case IPPROTO_UDP: 205 205 header2 |= PKT_OFFLOAD_HDR2_SIZE_3(UDP_HLEN); 206 - epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L3; 206 + epkt |= PKT_OFFLOAD_EPKT_TP(1) | PKT_OFFLOAD_EPKT_CSUM_L4; 207 207 header_cnt++; 208 208 break; 209 209 default: ··· 818 818 /* Tx SPB */ 819 819 tx_spb_ctrl_wl(intf, ((intf->channel + 8) << TX_SPB_CTRL_XF_BID_SHIFT), 820 820 TX_SPB_CTRL_XF_CTRL2); 821 - tx_pause_ctrl_wl(intf, (1 << (intf->channel + 8)), TX_PAUSE_MAP_VECTOR); 822 821 tx_spb_top_wl(intf, 0x1e, TX_SPB_TOP_BLKOUT); 823 - tx_spb_top_wl(intf, 0x0, TX_SPB_TOP_SPRE_BW_CTRL); 824 822 825 823 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_READ); 826 824 tx_spb_dma_wq(intf, intf->tx_spb_dma_addr, TX_SPB_DMA_BASE); ··· 1183 1185 { 1184 1186 /* Per port */ 1185 1187 intf->res.umac = priv->base + UMC_OFFSET(intf); 1186 - intf->res.umac2fb = priv->base + (priv->hw_info->umac2fb + 1188 + intf->res.umac2fb = priv->base + (UMAC2FB_OFFSET + priv->rx_ctrl_offset + 1187 1189 (intf->port * 0x4)); 1188 1190 intf->res.rgmii = priv->base + RGMII_OFFSET(intf); 1189 1191 ··· 1198 1200 intf->rx_edpkt_cfg = priv->base + RX_EDPKT_CFG_OFFSET(intf); 1199 1201 } 1200 1202 1201 - #define MAX_IRQ_STR_LEN 64 1202 1203 struct bcmasp_intf *bcmasp_interface_create(struct bcmasp_priv *priv, 1203 1204 struct device_node *ndev_dn, int i) 1204 1205 {

+1 -2

drivers/net/ethernet/broadcom/asp2/bcmasp_intf_defs.h

··· 118 118 #define UMC_PSW_MS 0x624 119 119 #define UMC_PSW_LS 0x628 120 120 121 - #define UMAC2FB_OFFSET_2_1 0x9f044 122 - #define UMAC2FB_OFFSET 0x9f03c 121 + #define UMAC2FB_OFFSET 0x9f044 123 122 #define UMAC2FB_CFG 0x0 124 123 #define UMAC2FB_CFG_OPUT_EN BIT(0) 125 124 #define UMAC2FB_CFG_VLAN_EN BIT(1)

+1 -1

drivers/net/mdio/mdio-bcm-unimac.c

··· 334 334 NULL, unimac_mdio_resume); 335 335 336 336 static const struct of_device_id unimac_mdio_ids[] = { 337 + { .compatible = "brcm,asp-v3.0-mdio", }, 337 338 { .compatible = "brcm,asp-v2.2-mdio", }, 338 339 { .compatible = "brcm,asp-v2.1-mdio", }, 339 - { .compatible = "brcm,asp-v2.0-mdio", }, 340 340 { .compatible = "brcm,bcm6846-mdio", }, 341 341 { .compatible = "brcm,genet-mdio-v5", }, 342 342 { .compatible = "brcm,genet-mdio-v4", },

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