Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
dt-binding: Update oss email address for Coresight documents
Update the OSS email addresses across all Coresight documents, as the
previous addresses have been deprecated.
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250902042143.1010-1-jie.gan@oss.qualcomm.com
authored by
Jie Gan
and committed by
Suzuki K Poulose
7009646d
8f0b4cce
+42
-42
+2
-2
Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
+2
-2
Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
···
1
1
What: /sys/bus/coresight/devices/dummy_source<N>/enable_source
2
2
Date: Dec 2024
3
3
KernelVersion: 6.14
4
-
Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
4
+
Contact: Mao Jinlong <jinlong.mao@oss.qualcomm.com>
5
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Description: (RW) Enable/disable tracing of dummy source. A sink should be activated
6
6
before enabling the source. The path of coresight components linking
7
7
the source to the sink is configured and managed automatically by the
···
10
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What: /sys/bus/coresight/devices/dummy_source<N>/traceid
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Date: Dec 2024
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KernelVersion: 6.14
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Contact: Mao Jinlong <quic_jinlmao@quicinc.com>
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+
Contact: Mao Jinlong <jinlong.mao@oss.qualcomm.com>
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Description: (R) Show the trace ID that will appear in the trace stream
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coming from this trace entity.
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+28
-28
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
+28
-28
Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
···
1
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What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
2
2
Date: January 2023
3
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KernelVersion: 6.2
4
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
4
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
5
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Description:
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(Write) Run integration test for tpdm. Integration test
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will generate test data for tpdm. It can help to make
···
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What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
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Description:
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(Write) Reset the dataset of the tpdm.
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···
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
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Description:
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(RW) Set/Get the trigger type of the DSB for tpdm.
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···
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
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Description:
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(RW) Set/Get the trigger timestamp of the DSB for tpdm.
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···
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
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Description:
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(RW) Set/Get the programming mode of the DSB for tpdm.
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···
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
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Description:
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(RW) Set/Get the index number of the edge detection for the DSB
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subunit TPDM. Since there are at most 256 edge detections, this
···
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
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+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
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Description:
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Write a data to control the edge detection corresponding to
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the index number. Before writing data to this sysfs file,
···
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
89
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
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Description:
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Write a data to mask the edge detection corresponding to the index
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number. Before writing data to this sysfs file, "ctrl_idx" should
···
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
101
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
102
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Description:
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Read a set of the edge control value of the DSB in TPDM.
104
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
108
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
109
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Description:
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Read a set of the edge control mask of the DSB in TPDM.
111
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
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Date: March 2023
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
115
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
116
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Description:
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(RW) Set/Get the value of the trigger pattern for the DSB
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subunit TPDM.
···
120
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
121
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Date: March 2023
122
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KernelVersion: 6.7
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-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
123
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
124
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Description:
125
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(RW) Set/Get the mask of the trigger pattern for the DSB
126
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subunit TPDM.
···
128
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
129
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Date: March 2023
130
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KernelVersion: 6.7
131
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
131
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
132
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Description:
133
133
(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
134
134
135
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
136
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Date: March 2023
137
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KernelVersion: 6.7
138
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
138
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
139
139
Description:
140
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(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
141
141
142
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What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
143
143
Date: March 2023
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KernelVersion: 6.7
145
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
145
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
146
146
Description:
147
147
(Write) Set the pattern timestamp of DSB tpdm. Read
148
148
the pattern timestamp of DSB tpdm.
···
154
154
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
155
155
Date: March 2023
156
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KernelVersion: 6.7
157
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
157
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
158
158
Description:
159
159
(Write) Set the pattern type of DSB tpdm. Read
160
160
the pattern type of DSB tpdm.
···
166
166
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
167
167
Date: March 2023
168
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KernelVersion: 6.7
169
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
169
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
170
170
Description:
171
171
(RW) Set/Get the MSR(mux select register) for the DSB subunit
172
172
TPDM.
···
174
174
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode
175
175
Date: January 2024
176
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KernelVersion: 6.9
177
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
177
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
178
178
Description: (Write) Set the data collection mode of CMB tpdm. Continuous
179
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change creates CMB data set elements on every CMBCLK edge.
180
180
Trace-on-change creates CMB data set elements only when a new
···
188
188
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1]
189
189
Date: January 2024
190
190
KernelVersion: 6.9
191
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
191
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
192
192
Description:
193
193
(RW) Set/Get the value of the trigger pattern for the CMB
194
194
subunit TPDM.
···
196
196
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1]
197
197
Date: January 2024
198
198
KernelVersion: 6.9
199
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
199
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
200
200
Description:
201
201
(RW) Set/Get the mask of the trigger pattern for the CMB
202
202
subunit TPDM.
···
204
204
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1]
205
205
Date: January 2024
206
206
KernelVersion: 6.9
207
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
207
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
208
208
Description:
209
209
(RW) Set/Get the value of the pattern for the CMB subunit TPDM.
210
210
211
211
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1]
212
212
Date: January 2024
213
213
KernelVersion: 6.9
214
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
214
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
215
215
Description:
216
216
(RW) Set/Get the mask of the pattern for the CMB subunit TPDM.
217
217
218
218
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts
219
219
Date: January 2024
220
220
KernelVersion: 6.9
221
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
221
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
222
222
Description:
223
223
(Write) Set the pattern timestamp of CMB tpdm. Read
224
224
the pattern timestamp of CMB tpdm.
···
230
230
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts
231
231
Date: January 2024
232
232
KernelVersion: 6.9
233
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
233
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
234
234
Description:
235
235
(RW) Set/Get the trigger timestamp of the CMB for tpdm.
236
236
···
241
241
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all
242
242
Date: January 2024
243
243
KernelVersion: 6.9
244
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
244
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
245
245
Description:
246
246
(RW) Read or write the status of timestamp upon all interface.
247
247
Only value 0 and 1 can be written to this node. Set this node to 1 to request
···
253
253
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]
254
254
Date: January 2024
255
255
KernelVersion: 6.9
256
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
256
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
257
257
Description:
258
258
(RW) Set/Get the MSR(mux select register) for the CMB subunit
259
259
TPDM.
···
261
261
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane
262
262
Date: Feb 2025
263
263
KernelVersion 6.15
264
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
264
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
265
265
Description:
266
266
(RW) Set/Get which lane participates in the output pattern
267
267
match cross trigger mechanism for the MCMB subunit TPDM.
···
269
269
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select
270
270
Date: Feb 2025
271
271
KernelVersion 6.15
272
-
Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
272
+
Contact: Jinlong Mao <jinlong.mao@oss.qualcomm.com>, Tao Zhang <tao.zhang@oss.qualcomm.com>
273
273
Description:
274
274
(RW) Set/Get the enablement of the individual lane.
275
275
+1
-1
Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
+1
-1
Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
···
31
31
- Mike Leach <mike.leach@linaro.org>
32
32
- Suzuki K Poulose <suzuki.poulose@arm.com>
33
33
- James Clark <james.clark@linaro.org>
34
-
- Mao Jinlong <quic_jinlmao@quicinc.com>
34
+
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
35
35
- Hao Zhang <quic_hazha@quicinc.com>
36
36
37
37
properties:
+1
-1
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
+1
-1
Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
···
30
30
- Mike Leach <mike.leach@linaro.org>
31
31
- Suzuki K Poulose <suzuki.poulose@arm.com>
32
32
- James Clark <james.clark@linaro.org>
33
-
- Mao Jinlong <quic_jinlmao@quicinc.com>
33
+
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
34
34
- Hao Zhang <quic_hazha@quicinc.com>
35
35
36
36
properties:
+3
-3
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+3
-3
Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
···
7
7
title: CoreSight TMC Control Unit
8
8
9
9
maintainers:
10
-
- Yuanfang Zhang <quic_yuanfang@quicinc.com>
11
-
- Mao Jinlong <quic_jinlmao@quicinc.com>
12
-
- Jie Gan <quic_jiegan@quicinc.com>
10
+
- Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>
11
+
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
12
+
- Jie Gan <jie.gan@oss.qualcomm.com>
13
13
14
14
description: |
15
15
The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
+2
-2
Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
+2
-2
Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
···
7
7
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
8
8
9
9
maintainers:
10
-
- Jinlong Mao <quic_jinlmao@quicinc.com>
11
-
- Tao Zhang <quic_taozha@quicinc.com>
10
+
- Jinlong Mao <jinlong.mao@oss.qualcomm.com>
11
+
- Tao Zhang <tao.zhang@oss.qualcomm.com>
12
12
13
13
description:
14
14
Support for ETM trace collection on remote processor using coresight
+1
-1
Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
+1
-1
Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
+2
-2
Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
+2
-2
Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
···
33
33
to sink.
34
34
35
35
maintainers:
36
-
- Mao Jinlong <quic_jinlmao@quicinc.com>
37
-
- Tao Zhang <quic_taozha@quicinc.com>
36
+
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
37
+
- Tao Zhang <tao.zhang@oss.qualcomm.com>
38
38
39
39
# Need a custom select here or 'arm,primecell' will match on lots of nodes
40
40
select:
+2
-2
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
+2
-2
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
···
19
19
sources and send it to a TPDA for packetization, timestamping, and funneling.
20
20
21
21
maintainers:
22
-
- Mao Jinlong <quic_jinlmao@quicinc.com>
23
-
- Tao Zhang <quic_taozha@quicinc.com>
22
+
- Mao Jinlong <jinlong.mao@oss.qualcomm.com>
23
+
- Tao Zhang <tao.zhang@oss.qualcomm.com>
24
24
25
25
# Need a custom select here or 'arm,primecell' will match on lots of nodes
26
26
select: