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linux
ASoC: Add Google Chameleon v3 i2s driver
Add driver for the i2s IP present on Google Chameleon v3
Signed-off-by: Paweł Anikiel <pan@semihalf.com
Link: https://lore.kernel.org/r/20230508113037.137627-2-pan@semihalf.com
Signed-off-by: Mark Brown <broonie@kernel.org
authored by
Paweł Anikiel
and committed by
Mark Brown
70264872
518a1742
+348
+1
sound/soc/Kconfig
+1
sound/soc/Kconfig
+1
sound/soc/Makefile
+1
sound/soc/Makefile
+6
sound/soc/google/Kconfig
+6
sound/soc/google/Kconfig
+2
sound/soc/google/Makefile
+2
sound/soc/google/Makefile
+338
sound/soc/google/chv3-i2s.c
+338
sound/soc/google/chv3-i2s.c
···
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// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <sound/soc.h>
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/*
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* The I2S interface consists of two ring buffers - one for RX and one for
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* TX. A ring buffer has a producer index and a consumer index. Depending
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* on which way the data is flowing, either the software or the hardware
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* writes data and updates the producer index, and the other end reads data
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* and updates the consumer index.
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*
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* The pointer managed by software is updated using the .ack callback
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* (see chv3_dma_ack). This seems to be the only way to reliably obtain
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* the appl_ptr from within the driver and pass it to hardware.
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*
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* Because of the two pointer design, the ring buffer can never be full. With
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* capture this isn't a problem, because the hardware being the producer
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* will wait for the consumer index to move out of the way. With playback,
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* however, this is problematic, because ALSA wants to fill up the buffer
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* completely when waiting for hardware. In the .ack callback, the driver
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* would have to wait for the consumer index to move out of the way by
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* busy-waiting, which would keep stalling the kernel for quite a long time.
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*
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* The workaround to this problem is to "lie" to ALSA that the hw_pointer
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* is one frame behind what it actually is (see chv3_dma_pointer). This
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* way, ALSA will not try to fill up the entire buffer, and all callbacks
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* are wait-free.
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*/
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#define I2S_TX_ENABLE 0x00
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#define I2S_TX_BASE_ADDR 0x04
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#define I2S_TX_BUFFER_SIZE 0x08
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#define I2S_TX_PRODUCER_IDX 0x0c
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#define I2S_TX_CONSUMER_IDX 0x10
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#define I2S_RX_ENABLE 0x14
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#define I2S_RX_BASE_ADDR 0x18
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#define I2S_RX_BUFFER_SIZE 0x1c
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#define I2S_RX_PRODUCER_IDX 0x20
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#define I2S_RX_CONSUMER_IDX 0x24
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#define I2S_SOFT_RESET 0x2c
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#define I2S_SOFT_RESET_RX_BIT 0x1
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#define I2S_SOFT_RESET_TX_BIT 0x2
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#define I2S_RX_IRQ 0x4c
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#define I2S_RX_IRQ_CONST 0x50
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#define I2S_TX_IRQ 0x54
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#define I2S_TX_IRQ_CONST 0x58
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#define I2S_IRQ_MASK 0x8
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#define I2S_IRQ_CLR 0xc
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#define I2S_IRQ_RX_BIT 0x1
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#define I2S_IRQ_TX_BIT 0x2
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#define I2S_MAX_BUFFER_SIZE 0x200000
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struct chv3_i2s_dev {
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struct device *dev;
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void __iomem *iobase;
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void __iomem *iobase_irq;
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struct snd_pcm_substream *rx_substream;
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struct snd_pcm_substream *tx_substream;
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int tx_bytes_to_fetch;
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};
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static struct snd_soc_dai_driver chv3_i2s_dai = {
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.name = "chv3-i2s",
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.capture = {
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.channels_min = 1,
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.channels_max = 128,
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.rates = SNDRV_PCM_RATE_CONTINUOUS,
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.rate_min = 8000,
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.rate_max = 96000,
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.formats = SNDRV_PCM_FMTBIT_S32_LE,
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},
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.playback = {
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.channels_min = 1,
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.channels_max = 128,
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.rates = SNDRV_PCM_RATE_CONTINUOUS,
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.rate_min = 8000,
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.rate_max = 96000,
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.formats = SNDRV_PCM_FMTBIT_S32_LE,
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},
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};
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static const struct snd_pcm_hardware chv3_dma_hw = {
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.info = SNDRV_PCM_INFO_INTERLEAVED |
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SNDRV_PCM_INFO_MMAP |
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SNDRV_PCM_INFO_MMAP_VALID |
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SNDRV_PCM_INFO_BLOCK_TRANSFER,
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.buffer_bytes_max = I2S_MAX_BUFFER_SIZE,
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.period_bytes_min = 64,
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.period_bytes_max = 8192,
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.periods_min = 4,
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.periods_max = 256,
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};
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static inline void chv3_i2s_wr(struct chv3_i2s_dev *i2s, int offset, u32 val)
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{
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writel(val, i2s->iobase + offset);
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}
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static inline u32 chv3_i2s_rd(struct chv3_i2s_dev *i2s, int offset)
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{
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return readl(i2s->iobase + offset);
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}
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static irqreturn_t chv3_i2s_isr(int irq, void *data)
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{
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struct chv3_i2s_dev *i2s = data;
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u32 reg;
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reg = readl(i2s->iobase_irq + I2S_IRQ_CLR);
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if (!reg)
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return IRQ_NONE;
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if (reg & I2S_IRQ_RX_BIT)
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snd_pcm_period_elapsed(i2s->rx_substream);
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if (reg & I2S_IRQ_TX_BIT)
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snd_pcm_period_elapsed(i2s->tx_substream);
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writel(reg, i2s->iobase_irq + I2S_IRQ_CLR);
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return IRQ_HANDLED;
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}
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static int chv3_dma_open(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
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int res;
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snd_soc_set_runtime_hwparams(substream, &chv3_dma_hw);
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res = snd_pcm_hw_constraint_pow2(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
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if (res)
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return res;
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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i2s->rx_substream = substream;
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else
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i2s->tx_substream = substream;
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return 0;
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}
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static int chv3_dma_close(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
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if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
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chv3_i2s_wr(i2s, I2S_RX_ENABLE, 0);
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else
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chv3_i2s_wr(i2s, I2S_TX_ENABLE, 0);
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return 0;
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}
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static int chv3_dma_pcm_construct(struct snd_soc_component *component,
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struct snd_soc_pcm_runtime *rtd)
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{
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struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
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struct snd_pcm_substream *substream;
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int res;
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substream = rtd->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream;
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if (substream) {
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res = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, i2s->dev,
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I2S_MAX_BUFFER_SIZE, &substream->dma_buffer);
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if (res)
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return res;
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}
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substream = rtd->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
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if (substream) {
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res = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, i2s->dev,
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I2S_MAX_BUFFER_SIZE, &substream->dma_buffer);
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if (res)
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return res;
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}
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return 0;
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}
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static int chv3_dma_hw_params(struct snd_soc_component *component,
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struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
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return 0;
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}
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static int chv3_dma_prepare(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
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unsigned int buffer_bytes, period_bytes, period_size;
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buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
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period_bytes = snd_pcm_lib_period_bytes(substream);
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period_size = substream->runtime->period_size;
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if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
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chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_RX_BIT);
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chv3_i2s_wr(i2s, I2S_RX_BASE_ADDR, substream->dma_buffer.addr);
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chv3_i2s_wr(i2s, I2S_RX_BUFFER_SIZE, buffer_bytes);
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chv3_i2s_wr(i2s, I2S_RX_IRQ, (period_size << 8) | 1);
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chv3_i2s_wr(i2s, I2S_RX_ENABLE, 1);
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} else {
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chv3_i2s_wr(i2s, I2S_SOFT_RESET, I2S_SOFT_RESET_TX_BIT);
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chv3_i2s_wr(i2s, I2S_TX_BASE_ADDR, substream->dma_buffer.addr);
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chv3_i2s_wr(i2s, I2S_TX_BUFFER_SIZE, buffer_bytes);
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chv3_i2s_wr(i2s, I2S_TX_IRQ, ((period_bytes / i2s->tx_bytes_to_fetch) << 8) | 1);
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chv3_i2s_wr(i2s, I2S_TX_ENABLE, 1);
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}
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writel(I2S_IRQ_RX_BIT | I2S_IRQ_TX_BIT, i2s->iobase_irq + I2S_IRQ_MASK);
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return 0;
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}
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static snd_pcm_uframes_t chv3_dma_pointer(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
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u32 frame_bytes, buffer_bytes;
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u32 idx_bytes;
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frame_bytes = substream->runtime->frame_bits * 8;
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buffer_bytes = snd_pcm_lib_buffer_bytes(substream);
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if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
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idx_bytes = chv3_i2s_rd(i2s, I2S_RX_PRODUCER_IDX);
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} else {
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idx_bytes = chv3_i2s_rd(i2s, I2S_TX_CONSUMER_IDX);
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/* lag the pointer by one frame */
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idx_bytes = (idx_bytes - frame_bytes) & (buffer_bytes - 1);
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}
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return bytes_to_frames(substream->runtime, idx_bytes);
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}
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static int chv3_dma_ack(struct snd_soc_component *component,
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struct snd_pcm_substream *substream)
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{
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struct snd_pcm_runtime *runtime = substream->runtime;
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struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
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struct chv3_i2s_dev *i2s = snd_soc_dai_get_drvdata(asoc_rtd_to_cpu(rtd, 0));
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unsigned int bytes, idx;
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bytes = frames_to_bytes(runtime, runtime->control->appl_ptr);
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idx = bytes & (snd_pcm_lib_buffer_bytes(substream) - 1);
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if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
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chv3_i2s_wr(i2s, I2S_RX_CONSUMER_IDX, idx);
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else
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chv3_i2s_wr(i2s, I2S_TX_PRODUCER_IDX, idx);
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return 0;
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}
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static const struct snd_soc_component_driver chv3_i2s_comp = {
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.name = "chv3-i2s-comp",
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.open = chv3_dma_open,
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.close = chv3_dma_close,
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.pcm_construct = chv3_dma_pcm_construct,
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.hw_params = chv3_dma_hw_params,
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.prepare = chv3_dma_prepare,
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.pointer = chv3_dma_pointer,
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.ack = chv3_dma_ack,
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};
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static int chv3_i2s_probe(struct platform_device *pdev)
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{
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struct chv3_i2s_dev *i2s;
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int res;
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int irq;
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i2s = devm_kzalloc(&pdev->dev, sizeof(*i2s), GFP_KERNEL);
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if (!i2s)
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return -ENOMEM;
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i2s->iobase = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(i2s->iobase))
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return PTR_ERR(i2s->iobase);
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i2s->iobase_irq = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(i2s->iobase_irq))
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return PTR_ERR(i2s->iobase_irq);
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i2s->tx_bytes_to_fetch = (chv3_i2s_rd(i2s, I2S_TX_IRQ_CONST) >> 8) & 0xffff;
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i2s->dev = &pdev->dev;
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dev_set_drvdata(&pdev->dev, i2s);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return -ENXIO;
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res = devm_request_irq(i2s->dev, irq, chv3_i2s_isr, 0, "chv3-i2s", i2s);
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if (res)
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return res;
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res = devm_snd_soc_register_component(&pdev->dev, &chv3_i2s_comp,
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&chv3_i2s_dai, 1);
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if (res) {
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dev_err(&pdev->dev, "couldn't register component: %d\n", res);
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return res;
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}
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return 0;
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}
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static const struct of_device_id chv3_i2s_of_match[] = {
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{ .compatible = "google,chv3-i2s" },
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{},
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};
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static struct platform_driver chv3_i2s_driver = {
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.probe = chv3_i2s_probe,
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.driver = {
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.name = "chv3-i2s",
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.of_match_table = chv3_i2s_of_match,
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},
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};
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module_platform_driver(chv3_i2s_driver);
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MODULE_AUTHOR("Pawel Anikiel <pan@semihalf.com>");
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MODULE_DESCRIPTION("Chameleon v3 I2S interface");
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MODULE_LICENSE("GPL");