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net: stmmac: rk: remove incorrect _DLY_DISABLE bit definition

The RK3328 GMAC clock delay macros define enable/disable controls for
TX and RX clock delay. While the TX definitions are correct, the
RXCLK_DLY_DISABLE macro incorrectly clears bit 0.

The macros RK3328_GMAC_TXCLK_DLY_DISABLE and
RK3328_GMAC_RXCLK_DLY_DISABLE are not referenced anywhere
in the driver code. Remove them to clean up unused definitions.

No functional change.

Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Link: https://patch.msgid.link/20250826102219.49656-1-alok.a.tiwari@oracle.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Alok Tiwari and committed by
Jakub Kicinski 705609de f63f21e8

-2
-2
drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
··· 556 556 #define RK3328_GMAC_RMII_MODE GRF_BIT(9) 557 557 #define RK3328_GMAC_RMII_MODE_CLR GRF_CLR_BIT(9) 558 558 #define RK3328_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0) 559 - #define RK3328_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0) 560 559 #define RK3328_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1) 561 - #define RK3328_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(0) 562 560 563 561 /* RK3328_GRF_MACPHY_CON1 */ 564 562 #define RK3328_MACPHY_RMII_MODE GRF_BIT(9)