Merge branch 'net-ethernet-mtk_eth_soc-add-basic-support-for-mt7988-soc'

+102 -7

Documentation/devicetree/bindings/net/mediatek,net.yaml

··· 19 19 enum: 20 20 - mediatek,mt2701-eth 21 21 - mediatek,mt7623-eth 22 + - mediatek,mt7621-eth 22 23 - mediatek,mt7622-eth 23 24 - mediatek,mt7629-eth 24 25 - mediatek,mt7981-eth 25 26 - mediatek,mt7986-eth 27 + - mediatek,mt7988-eth 26 28 - ralink,rt5350-eth 27 29 28 30 reg: ··· 34 32 clock-names: true 35 33 36 34 interrupts: 37 - minItems: 3 35 + minItems: 1 38 36 maxItems: 4 39 37 40 38 power-domains: ··· 61 59 description: 62 60 Phandle to the mediatek hifsys controller used to provide various clocks 63 61 and reset to the system. 62 + 63 + mediatek,infracfg: 64 + $ref: /schemas/types.yaml#/definitions/phandle 65 + description: 66 + Phandle to the syscon node that handles the path from GMAC to 67 + PHY variants. 64 68 65 69 mediatek,sgmiisys: 66 70 $ref: /schemas/types.yaml#/definitions/phandle-array ··· 129 121 - const: gp1 130 122 - const: gp2 131 123 124 + mediatek,infracfg: false 125 + 132 126 mediatek,pctl: 133 127 $ref: /schemas/types.yaml#/definitions/phandle 134 128 description: 135 129 Phandle to the syscon node that handles the ports slew rate and 136 130 driver current. 131 + 132 + mediatek,wed: false 133 + 134 + mediatek,wed-pcie: false 135 + 136 + - if: 137 + properties: 138 + compatible: 139 + contains: 140 + enum: 141 + - mediatek,mt7621-eth 142 + then: 143 + properties: 144 + interrupts: 145 + maxItems: 1 146 + 147 + clocks: 148 + minItems: 2 149 + maxItems: 2 150 + 151 + clock-names: 152 + items: 153 + - const: ethif 154 + - const: fe 155 + 156 + mediatek,infracfg: false 137 157 138 158 mediatek,wed: false 139 159 ··· 194 158 - const: sgmii_cdr_fb 195 159 - const: sgmii_ck 196 160 - const: eth2pll 161 + 162 + mediatek,infracfg: false 197 163 198 164 mediatek,sgmiisys: 199 165 minItems: 1 ··· 242 204 - const: sgmii_ck 243 205 - const: eth2pll 244 206 245 - mediatek,infracfg: 246 - $ref: /schemas/types.yaml#/definitions/phandle 247 - description: 248 - Phandle to the syscon node that handles the path from GMAC to 249 - PHY variants. 250 - 251 207 mediatek,sgmiisys: 252 208 minItems: 2 253 209 maxItems: 2 ··· 282 250 - const: netsys0 283 251 - const: netsys1 284 252 253 + mediatek,infracfg: false 254 + 285 255 mediatek,sgmiisys: 286 256 minItems: 2 287 257 maxItems: 2 ··· 319 285 - const: sgmii2_cdr_fb 320 286 - const: netsys0 321 287 - const: netsys1 288 + 289 + mediatek,infracfg: false 290 + 291 + mediatek,sgmiisys: 292 + minItems: 2 293 + maxItems: 2 294 + 295 + - if: 296 + properties: 297 + compatible: 298 + contains: 299 + const: mediatek,mt7988-eth 300 + then: 301 + properties: 302 + interrupts: 303 + minItems: 4 304 + 305 + clocks: 306 + minItems: 34 307 + maxItems: 34 308 + 309 + clock-names: 310 + items: 311 + - const: crypto 312 + - const: fe 313 + - const: gp2 314 + - const: gp1 315 + - const: gp3 316 + - const: ethwarp_wocpu2 317 + - const: ethwarp_wocpu1 318 + - const: ethwarp_wocpu0 319 + - const: esw 320 + - const: netsys0 321 + - const: netsys1 322 + - const: sgmii_tx250m 323 + - const: sgmii_rx250m 324 + - const: sgmii2_tx250m 325 + - const: sgmii2_rx250m 326 + - const: top_usxgmii0_sel 327 + - const: top_usxgmii1_sel 328 + - const: top_sgm0_sel 329 + - const: top_sgm1_sel 330 + - const: top_xfi_phy0_xtal_sel 331 + - const: top_xfi_phy1_xtal_sel 332 + - const: top_eth_gmii_sel 333 + - const: top_eth_refck_50m_sel 334 + - const: top_eth_sys_200m_sel 335 + - const: top_eth_sys_sel 336 + - const: top_eth_xgmii_sel 337 + - const: top_eth_mii_sel 338 + - const: top_netsys_sel 339 + - const: top_netsys_500m_sel 340 + - const: top_netsys_pao_2x_sel 341 + - const: top_netsys_sync_250m_sel 342 + - const: top_netsys_ppefb_250m_sel 343 + - const: top_netsys_warp_sel 344 + - const: wocpu1 345 + - const: wocpu0 346 + - const: xgp1 347 + - const: xgp2 348 + - const: xgp3 322 349 323 350 mediatek,sgmiisys: 324 351 minItems: 2

+19 -17

drivers/net/ethernet/mediatek/mtk_eth_path.c

··· 15 15 struct mtk_eth_muxc { 16 16 const char *name; 17 17 int cap_bit; 18 - int (*set_path)(struct mtk_eth *eth, int path); 18 + int (*set_path)(struct mtk_eth *eth, u64 path); 19 19 }; 20 20 21 - static const char *mtk_eth_path_name(int path) 21 + static const char *mtk_eth_path_name(u64 path) 22 22 { 23 23 switch (path) { 24 24 case MTK_ETH_PATH_GMAC1_RGMII: ··· 40 40 } 41 41 } 42 42 43 - static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, int path) 43 + static int set_mux_gdm1_to_gmac1_esw(struct mtk_eth *eth, u64 path) 44 44 { 45 45 bool updated = true; 46 - u32 val, mask, set; 46 + u32 mask, set, reg; 47 47 48 48 switch (path) { 49 49 case MTK_ETH_PATH_GMAC1_SGMII: ··· 59 59 break; 60 60 } 61 61 62 - if (updated) { 63 - val = mtk_r32(eth, MTK_MAC_MISC); 64 - val = (val & mask) | set; 65 - mtk_w32(eth, val, MTK_MAC_MISC); 66 - } 62 + if (mtk_is_netsys_v3_or_greater(eth)) 63 + reg = MTK_MAC_MISC_V3; 64 + else 65 + reg = MTK_MAC_MISC; 66 + 67 + if (updated) 68 + mtk_m32(eth, mask, set, reg); 67 69 68 70 dev_dbg(eth->dev, "path %s in %s updated = %d\n", 69 71 mtk_eth_path_name(path), __func__, updated); ··· 73 71 return 0; 74 72 } 75 73 76 - static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, int path) 74 + static int set_mux_gmac2_gmac0_to_gephy(struct mtk_eth *eth, u64 path) 77 75 { 78 76 unsigned int val = 0; 79 77 bool updated = true; ··· 96 94 return 0; 97 95 } 98 96 99 - static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, int path) 97 + static int set_mux_u3_gmac2_to_qphy(struct mtk_eth *eth, u64 path) 100 98 { 101 99 unsigned int val = 0, mask = 0, reg = 0; 102 100 bool updated = true; ··· 127 125 return 0; 128 126 } 129 127 130 - static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, int path) 128 + static int set_mux_gmac1_gmac2_to_sgmii_rgmii(struct mtk_eth *eth, u64 path) 131 129 { 132 130 unsigned int val = 0; 133 131 bool updated = true; ··· 165 163 return 0; 166 164 } 167 165 168 - static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, int path) 166 + static int set_mux_gmac12_to_gephy_sgmii(struct mtk_eth *eth, u64 path) 169 167 { 170 168 unsigned int val = 0; 171 169 bool updated = true; ··· 220 218 }, 221 219 }; 222 220 223 - static int mtk_eth_mux_setup(struct mtk_eth *eth, int path) 221 + static int mtk_eth_mux_setup(struct mtk_eth *eth, u64 path) 224 222 { 225 223 int i, err = 0; 226 224 ··· 251 249 252 250 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id) 253 251 { 254 - int path; 252 + u64 path; 255 253 256 254 path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_SGMII : 257 255 MTK_ETH_PATH_GMAC2_SGMII; ··· 262 260 263 261 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id) 264 262 { 265 - int path = 0; 263 + u64 path = 0; 266 264 267 265 if (mac_id == 1) 268 266 path = MTK_ETH_PATH_GMAC2_GEPHY; ··· 276 274 277 275 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id) 278 276 { 279 - int path; 277 + u64 path; 280 278 281 279 path = (mac_id == 0) ? MTK_ETH_PATH_GMAC1_RGMII : 282 280 MTK_ETH_PATH_GMAC2_RGMII;

+310 -90

drivers/net/ethernet/mediatek/mtk_eth_soc.c

··· 152 152 .pse_oq_sta = 0x01a0, 153 153 }; 154 154 155 + static const struct mtk_reg_map mt7988_reg_map = { 156 + .tx_irq_mask = 0x461c, 157 + .tx_irq_status = 0x4618, 158 + .pdma = { 159 + .rx_ptr = 0x6900, 160 + .rx_cnt_cfg = 0x6904, 161 + .pcrx_ptr = 0x6908, 162 + .glo_cfg = 0x6a04, 163 + .rst_idx = 0x6a08, 164 + .delay_irq = 0x6a0c, 165 + .irq_status = 0x6a20, 166 + .irq_mask = 0x6a28, 167 + .adma_rx_dbg0 = 0x6a38, 168 + .int_grp = 0x6a50, 169 + }, 170 + .qdma = { 171 + .qtx_cfg = 0x4400, 172 + .qtx_sch = 0x4404, 173 + .rx_ptr = 0x4500, 174 + .rx_cnt_cfg = 0x4504, 175 + .qcrx_ptr = 0x4508, 176 + .glo_cfg = 0x4604, 177 + .rst_idx = 0x4608, 178 + .delay_irq = 0x460c, 179 + .fc_th = 0x4610, 180 + .int_grp = 0x4620, 181 + .hred = 0x4644, 182 + .ctx_ptr = 0x4700, 183 + .dtx_ptr = 0x4704, 184 + .crx_ptr = 0x4710, 185 + .drx_ptr = 0x4714, 186 + .fq_head = 0x4720, 187 + .fq_tail = 0x4724, 188 + .fq_count = 0x4728, 189 + .fq_blen = 0x472c, 190 + .tx_sch_rate = 0x4798, 191 + }, 192 + .gdm1_cnt = 0x1c00, 193 + .gdma_to_ppe = 0x3333, 194 + .ppe_base = 0x2000, 195 + .wdma_base = { 196 + [0] = 0x4800, 197 + [1] = 0x4c00, 198 + }, 199 + .pse_iq_sta = 0x0180, 200 + .pse_oq_sta = 0x01a0, 201 + }; 202 + 155 203 /* strings used by ethtool */ 156 204 static const struct mtk_ethtool_stats { 157 205 char str[ETH_GSTRING_LEN]; ··· 227 179 }; 228 180 229 181 static const char * const mtk_clks_source_name[] = { 230 - "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "trgpll", 231 - "sgmii_tx250m", "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", 232 - "sgmii2_tx250m", "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", 233 - "sgmii_ck", "eth2pll", "wocpu0", "wocpu1", "netsys0", "netsys1" 182 + "ethif", 183 + "sgmiitop", 184 + "esw", 185 + "gp0", 186 + "gp1", 187 + "gp2", 188 + "gp3", 189 + "xgp1", 190 + "xgp2", 191 + "xgp3", 192 + "crypto", 193 + "fe", 194 + "trgpll", 195 + "sgmii_tx250m", 196 + "sgmii_rx250m", 197 + "sgmii_cdr_ref", 198 + "sgmii_cdr_fb", 199 + "sgmii2_tx250m", 200 + "sgmii2_rx250m", 201 + "sgmii2_cdr_ref", 202 + "sgmii2_cdr_fb", 203 + "sgmii_ck", 204 + "eth2pll", 205 + "wocpu0", 206 + "wocpu1", 207 + "netsys0", 208 + "netsys1", 209 + "ethwarp_wocpu2", 210 + "ethwarp_wocpu1", 211 + "ethwarp_wocpu0", 212 + "top_usxgmii0_sel", 213 + "top_usxgmii1_sel", 214 + "top_sgm0_sel", 215 + "top_sgm1_sel", 216 + "top_xfi_phy0_xtal_sel", 217 + "top_xfi_phy1_xtal_sel", 218 + "top_eth_gmii_sel", 219 + "top_eth_refck_50m_sel", 220 + "top_eth_sys_200m_sel", 221 + "top_eth_sys_sel", 222 + "top_eth_xgmii_sel", 223 + "top_eth_mii_sel", 224 + "top_netsys_sel", 225 + "top_netsys_500m_sel", 226 + "top_netsys_pao_2x_sel", 227 + "top_netsys_sync_250m_sel", 228 + "top_netsys_ppefb_250m_sel", 229 + "top_netsys_warp_sel", 234 230 }; 235 231 236 232 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg) ··· 287 195 return __raw_readl(eth->base + reg); 288 196 } 289 197 290 - static u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg) 198 + u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg) 291 199 { 292 200 u32 val; 293 201 ··· 492 400 dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n"); 493 401 } 494 402 403 + static void mtk_setup_bridge_switch(struct mtk_eth *eth) 404 + { 405 + /* Force Port1 XGMAC Link Up */ 406 + mtk_m32(eth, 0, MTK_XGMAC_FORCE_LINK(MTK_GMAC1_ID), 407 + MTK_XGMAC_STS(MTK_GMAC1_ID)); 408 + 409 + /* Adjust GSW bridge IPG to 11 */ 410 + mtk_m32(eth, GSWTX_IPG_MASK | GSWRX_IPG_MASK, 411 + (GSW_IPG_11 << GSWTX_IPG_SHIFT) | 412 + (GSW_IPG_11 << GSWRX_IPG_SHIFT), 413 + MTK_GSW_CFG); 414 + } 415 + 495 416 static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config, 496 417 phy_interface_t interface) 497 418 { ··· 563 458 if (err) 564 459 goto init_err; 565 460 } 461 + break; 462 + case PHY_INTERFACE_MODE_INTERNAL: 566 463 break; 567 464 default: 568 465 goto err_phy; ··· 635 528 return; 636 529 } 637 530 531 + /* Setup gmac */ 532 + if (mtk_is_netsys_v3_or_greater(eth) && 533 + mac->interface == PHY_INTERFACE_MODE_INTERNAL) { 534 + mtk_w32(mac->hw, MTK_GDMA_XGDM_SEL, MTK_GDMA_EG_CTRL(mac->id)); 535 + mtk_w32(mac->hw, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(mac->id)); 536 + 537 + mtk_setup_bridge_switch(eth); 538 + } 539 + 638 540 return; 639 541 640 542 err_phy: ··· 709 593 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 710 594 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 711 595 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 712 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 596 + if (mtk_is_netsys_v1(eth)) 713 597 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 714 598 715 599 if (IS_ENABLED(CONFIG_SOC_MT7621)) { ··· 856 740 } 857 741 divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); 858 742 743 + /* Configure MDC Turbo Mode */ 744 + if (mtk_is_netsys_v3_or_greater(eth)) 745 + mtk_m32(eth, 0, MISC_MDC_TURBO, MTK_MAC_MISC_V3); 746 + 859 747 /* Configure MDC Divider */ 860 - val = mtk_r32(eth, MTK_PPSC); 861 - val &= ~PPSC_MDC_CFG; 862 - val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO; 863 - mtk_w32(eth, val, MTK_PPSC); 748 + val = FIELD_PREP(PPSC_MDC_CFG, divider); 749 + if (!mtk_is_netsys_v3_or_greater(eth)) 750 + val |= PPSC_MDC_TURBO; 751 + mtk_m32(eth, PPSC_MDC_CFG, val, MTK_PPSC); 864 752 865 753 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider); 866 754 ··· 996 876 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs); 997 877 hw_stats->rx_flow_control_packets += 998 878 mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs); 999 - hw_stats->tx_skip += 1000 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 1001 - hw_stats->tx_collisions += 1002 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 1003 - hw_stats->tx_bytes += 1004 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 1005 - stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 1006 - if (stats) 1007 - hw_stats->tx_bytes += (stats << 32); 1008 - hw_stats->tx_packets += 1009 - mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 879 + 880 + if (mtk_is_netsys_v3_or_greater(eth)) { 881 + hw_stats->tx_skip += 882 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x50 + offs); 883 + hw_stats->tx_collisions += 884 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x54 + offs); 885 + hw_stats->tx_bytes += 886 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x40 + offs); 887 + stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x44 + offs); 888 + if (stats) 889 + hw_stats->tx_bytes += (stats << 32); 890 + hw_stats->tx_packets += 891 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x48 + offs); 892 + } else { 893 + hw_stats->tx_skip += 894 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x28 + offs); 895 + hw_stats->tx_collisions += 896 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x2c + offs); 897 + hw_stats->tx_bytes += 898 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x30 + offs); 899 + stats = mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x34 + offs); 900 + if (stats) 901 + hw_stats->tx_bytes += (stats << 32); 902 + hw_stats->tx_packets += 903 + mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x38 + offs); 904 + } 1010 905 } 1011 906 1012 907 u64_stats_update_end(&hw_stats->syncp); ··· 1031 896 { 1032 897 int i; 1033 898 1034 - for (i = 0; i < MTK_MAC_COUNT; i++) { 899 + for (i = 0; i < MTK_MAX_DEVS; i++) { 1035 900 if (!eth->mac[i] || !eth->mac[i]->hw_stats) 1036 901 continue; 1037 902 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) { ··· 1105 970 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1); 1106 971 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3); 1107 972 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4); 1108 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 973 + if (mtk_is_netsys_v2_or_greater(eth)) { 1109 974 rxd->rxd5 = READ_ONCE(dma_rxd->rxd5); 1110 975 rxd->rxd6 = READ_ONCE(dma_rxd->rxd6); 1111 976 } ··· 1163 1028 1164 1029 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE); 1165 1030 txd->txd4 = 0; 1166 - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 1031 + if (mtk_is_netsys_v2_or_greater(eth)) { 1167 1032 txd->txd5 = 0; 1168 1033 txd->txd6 = 0; 1169 1034 txd->txd7 = 0; ··· 1325 1190 data |= TX_DMA_LS0; 1326 1191 WRITE_ONCE(desc->txd3, data); 1327 1192 1328 - data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */ 1193 + /* set forward port */ 1194 + switch (mac->id) { 1195 + case MTK_GMAC1_ID: 1196 + data = PSE_GDM1_PORT << TX_DMA_FPORT_SHIFT_V2; 1197 + break; 1198 + case MTK_GMAC2_ID: 1199 + data = PSE_GDM2_PORT << TX_DMA_FPORT_SHIFT_V2; 1200 + break; 1201 + case MTK_GMAC3_ID: 1202 + data = PSE_GDM3_PORT << TX_DMA_FPORT_SHIFT_V2; 1203 + break; 1204 + } 1205 + 1329 1206 data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid); 1330 1207 WRITE_ONCE(desc->txd4, data); 1331 1208 ··· 1348 1201 /* tx checksum offload */ 1349 1202 if (info->csum) 1350 1203 data |= TX_DMA_CHKSUM_V2; 1204 + if (mtk_is_netsys_v3_or_greater(eth) && netdev_uses_dsa(dev)) 1205 + data |= TX_DMA_SPTAG_V3; 1351 1206 } 1352 1207 WRITE_ONCE(desc->txd5, data); 1353 1208 ··· 1368 1219 struct mtk_mac *mac = netdev_priv(dev); 1369 1220 struct mtk_eth *eth = mac->hw; 1370 1221 1371 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1222 + if (mtk_is_netsys_v2_or_greater(eth)) 1372 1223 mtk_tx_set_dma_desc_v2(dev, txd, info); 1373 1224 else 1374 1225 mtk_tx_set_dma_desc_v1(dev, txd, info); ··· 1415 1266 mtk_tx_set_dma_desc(dev, itxd, &txd_info); 1416 1267 1417 1268 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0; 1418 - itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1419 - MTK_TX_FLAGS_FPORT1; 1269 + itx_buf->mac_id = mac->id; 1420 1270 setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size, 1421 1271 k++); 1422 1272 ··· 1463 1315 memset(tx_buf, 0, sizeof(*tx_buf)); 1464 1316 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1465 1317 tx_buf->flags |= MTK_TX_FLAGS_PAGE0; 1466 - tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 : 1467 - MTK_TX_FLAGS_FPORT1; 1318 + tx_buf->mac_id = mac->id; 1468 1319 1469 1320 setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr, 1470 1321 txd_info.size, k++); ··· 1548 1401 { 1549 1402 int i; 1550 1403 1551 - for (i = 0; i < MTK_MAC_COUNT; i++) { 1404 + for (i = 0; i < MTK_MAX_DEVS; i++) { 1552 1405 if (!eth->netdev[i]) 1553 1406 continue; 1554 1407 if (netif_queue_stopped(eth->netdev[i])) ··· 1562 1415 { 1563 1416 int i; 1564 1417 1565 - for (i = 0; i < MTK_MAC_COUNT; i++) { 1418 + for (i = 0; i < MTK_MAX_DEVS; i++) { 1566 1419 if (!eth->netdev[i]) 1567 1420 continue; 1568 1421 netif_tx_wake_all_queues(eth->netdev[i]); ··· 1673 1526 1674 1527 static bool mtk_page_pool_enabled(struct mtk_eth *eth) 1675 1528 { 1676 - return MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2); 1529 + return eth->soc->version == 2; 1677 1530 } 1678 1531 1679 1532 static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth, ··· 1765 1618 } 1766 1619 mtk_tx_set_dma_desc(dev, txd, txd_info); 1767 1620 1768 - tx_buf->flags |= !mac->id ? MTK_TX_FLAGS_FPORT0 : MTK_TX_FLAGS_FPORT1; 1621 + tx_buf->mac_id = mac->id; 1769 1622 tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX; 1770 1623 tx_buf->data = (void *)MTK_DMA_DUMMY_DESC; 1771 1624 ··· 2015 1868 break; 2016 1869 2017 1870 /* find out which mac the packet come from. values start at 1 */ 2018 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2019 - mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1; 2020 - else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 2021 - !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) 2022 - mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1871 + if (mtk_is_netsys_v2_or_greater(eth)) { 1872 + u32 val = RX_DMA_GET_SPORT_V2(trxd.rxd5); 2023 1873 2024 - if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT || 1874 + switch (val) { 1875 + case PSE_GDM1_PORT: 1876 + case PSE_GDM2_PORT: 1877 + mac = val - 1; 1878 + break; 1879 + case PSE_GDM3_PORT: 1880 + mac = MTK_GMAC3_ID; 1881 + break; 1882 + default: 1883 + break; 1884 + } 1885 + } else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) && 1886 + !(trxd.rxd4 & RX_DMA_SPECIAL_TAG)) { 1887 + mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1; 1888 + } 1889 + 1890 + if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS || 2025 1891 !eth->netdev[mac])) 2026 1892 goto release_desc; 2027 1893 ··· 2124 1964 skb->dev = netdev; 2125 1965 bytes += skb->len; 2126 1966 2127 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 1967 + if (mtk_is_netsys_v2_or_greater(eth)) { 2128 1968 reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5); 2129 1969 hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY; 2130 1970 if (hash != MTK_RXD5_FOE_ENTRY) ··· 2149 1989 /* When using VLAN untagging in combination with DSA, the 2150 1990 * hardware treats the MTK special tag as a VLAN and untags it. 2151 1991 */ 2152 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) && 2153 - (trxd.rxd2 & RX_DMA_VTAG) && netdev_uses_dsa(netdev)) { 1992 + if (mtk_is_netsys_v1(eth) && (trxd.rxd2 & RX_DMA_VTAG) && 1993 + netdev_uses_dsa(netdev)) { 2154 1994 unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0); 2155 1995 2156 1996 if (port < ARRAY_SIZE(eth->dsa_meta) && ··· 2254 2094 2255 2095 while ((cpu != dma) && budget) { 2256 2096 u32 next_cpu = desc->txd2; 2257 - int mac = 0; 2258 2097 2259 2098 desc = mtk_qdma_phys_to_virt(ring, desc->txd2); 2260 2099 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0) ··· 2261 2102 2262 2103 tx_buf = mtk_desc_to_tx_buf(ring, desc, 2263 2104 eth->soc->txrx.txd_size); 2264 - if (tx_buf->flags & MTK_TX_FLAGS_FPORT1) 2265 - mac = 1; 2266 - 2267 2105 if (!tx_buf->data) 2268 2106 break; 2269 2107 2270 2108 if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) { 2271 2109 if (tx_buf->type == MTK_TYPE_SKB) 2272 - mtk_poll_tx_done(eth, state, mac, tx_buf->data); 2110 + mtk_poll_tx_done(eth, state, tx_buf->mac_id, 2111 + tx_buf->data); 2273 2112 2274 2113 budget--; 2275 2114 } ··· 2457 2300 txd->txd2 = next_ptr; 2458 2301 txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU; 2459 2302 txd->txd4 = 0; 2460 - if (MTK_HAS_CAPS(soc->caps, MTK_NETSYS_V2)) { 2303 + if (mtk_is_netsys_v2_or_greater(eth)) { 2461 2304 txd->txd5 = 0; 2462 2305 txd->txd6 = 0; 2463 2306 txd->txd7 = 0; ··· 2510 2353 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | 2511 2354 FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | 2512 2355 MTK_QTX_SCH_LEAKY_BUCKET_SIZE; 2513 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2356 + if (mtk_is_netsys_v1(eth)) 2514 2357 val |= MTK_QTX_SCH_LEAKY_BUCKET_EN; 2515 2358 mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs); 2516 2359 ofs += MTK_QTX_OFFSET; 2517 2360 } 2518 2361 val = MTK_QDMA_TX_SCH_MAX_WFQ | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); 2519 2362 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate); 2520 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 2363 + if (mtk_is_netsys_v2_or_greater(eth)) 2521 2364 mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4); 2522 2365 } else { 2523 2366 mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0); ··· 2646 2489 2647 2490 rxd->rxd3 = 0; 2648 2491 rxd->rxd4 = 0; 2649 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 2492 + if (mtk_is_netsys_v2_or_greater(eth)) { 2650 2493 rxd->rxd5 = 0; 2651 2494 rxd->rxd6 = 0; 2652 2495 rxd->rxd7 = 0; ··· 3068 2911 const struct mtk_soc_data *soc = eth->soc; 3069 2912 int i; 3070 2913 3071 - for (i = 0; i < MTK_MAC_COUNT; i++) 2914 + for (i = 0; i < MTK_MAX_DEVS; i++) 3072 2915 if (eth->netdev[i]) 3073 2916 netdev_reset_queue(eth->netdev[i]); 3074 2917 if (eth->scratch_ring) { ··· 3194 3037 MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO | 3195 3038 MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE; 3196 3039 3197 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3040 + if (mtk_is_netsys_v2_or_greater(eth)) 3198 3041 val |= MTK_MUTLI_CNT | MTK_RESV_BUF | 3199 3042 MTK_WCOMP_EN | MTK_DMAD_WR_WDONE | 3200 3043 MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN; ··· 3222 3065 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) 3223 3066 return; 3224 3067 3225 - for (i = 0; i < MTK_MAC_COUNT; i++) { 3226 - u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3068 + for (i = 0; i < MTK_MAX_DEVS; i++) { 3069 + u32 val; 3070 + 3071 + if (!eth->netdev[i]) 3072 + continue; 3073 + 3074 + val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i)); 3227 3075 3228 3076 /* default setup the forward port to send frame to PDMA */ 3229 3077 val &= ~0xffff; ··· 3238 3076 3239 3077 val |= config; 3240 3078 3241 - if (eth->netdev[i] && netdev_uses_dsa(eth->netdev[i])) 3079 + if (netdev_uses_dsa(eth->netdev[i])) 3242 3080 val |= MTK_GDMA_SPECIAL_TAG; 3243 3081 3244 3082 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i)); ··· 3345 3183 phylink_start(mac->phylink); 3346 3184 netif_tx_start_all_queues(dev); 3347 3185 3348 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3186 + if (mtk_is_netsys_v2_or_greater(eth)) 3349 3187 return 0; 3350 3188 3351 3189 if (mtk_uses_dsa(dev) && !eth->prog) { ··· 3611 3449 { 3612 3450 u32 val; 3613 3451 3614 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3452 + if (mtk_is_netsys_v2_or_greater(eth)) { 3615 3453 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0); 3616 3454 val = RSTCTRL_PPE0_V2; 3617 3455 } else { ··· 3623 3461 3624 3462 ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val); 3625 3463 3626 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3464 + if (mtk_is_netsys_v2_or_greater(eth)) 3627 3465 regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 3628 3466 0x3ffffff); 3629 3467 } ··· 3649 3487 return; 3650 3488 } 3651 3489 3652 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 3490 + if (mtk_is_netsys_v2_or_greater(eth)) 3653 3491 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2; 3654 3492 else 3655 3493 rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0; ··· 3819 3657 else 3820 3658 mtk_hw_reset(eth); 3821 3659 3822 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3660 + if (mtk_is_netsys_v2_or_greater(eth)) { 3823 3661 /* Set FE to PDMAv2 if necessary */ 3824 3662 val = mtk_r32(eth, MTK_FE_GLO_MISC); 3825 3663 mtk_w32(eth, val | BIT(4), MTK_FE_GLO_MISC); ··· 3840 3678 * up with the more appropriate value when mtk_mac_config call is being 3841 3679 * invoked. 3842 3680 */ 3843 - for (i = 0; i < MTK_MAC_COUNT; i++) { 3681 + for (i = 0; i < MTK_MAX_DEVS; i++) { 3844 3682 struct net_device *dev = eth->netdev[i]; 3845 3683 3846 - mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3847 - if (dev) { 3848 - struct mtk_mac *mac = netdev_priv(dev); 3684 + if (!dev) 3685 + continue; 3849 3686 3850 - mtk_set_mcr_max_rx(mac, dev->mtu + MTK_RX_ETH_HLEN); 3851 - } 3687 + mtk_w32(eth, MAC_MCR_FORCE_LINK_DOWN, MTK_MAC_MCR(i)); 3688 + mtk_set_mcr_max_rx(netdev_priv(dev), 3689 + dev->mtu + MTK_RX_ETH_HLEN); 3852 3690 } 3853 3691 3854 3692 /* Indicates CDM to parse the MTK special tag from CPU ··· 3856 3694 */ 3857 3695 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL); 3858 3696 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL); 3859 - if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3697 + if (mtk_is_netsys_v1(eth)) { 3860 3698 val = mtk_r32(eth, MTK_CDMP_IG_CTRL); 3861 3699 mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL); 3862 3700 ··· 3878 3716 mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4); 3879 3717 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP); 3880 3718 3881 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 3719 + if (mtk_is_netsys_v3_or_greater(eth)) { 3720 + /* PSE should not drop port1, port8 and port9 packets */ 3721 + mtk_w32(eth, 0x00000302, PSE_DROP_CFG); 3722 + 3723 + /* GDM and CDM Threshold */ 3724 + mtk_w32(eth, 0x00000707, MTK_CDMW0_THRES); 3725 + mtk_w32(eth, 0x00000077, MTK_CDMW1_THRES); 3726 + 3727 + /* Disable GDM1 RX CRC stripping */ 3728 + mtk_m32(eth, MTK_GDMA_STRP_CRC, 0, MTK_GDMA_FWD_CFG(0)); 3729 + 3730 + /* PSE GDM3 MIB counter has incorrect hw default values, 3731 + * so the driver ought to read clear the values beforehand 3732 + * in case ethtool retrieve wrong mib values. 3733 + */ 3734 + for (i = 0; i < 0x80; i += 0x4) 3735 + mtk_r32(eth, reg_map->gdm1_cnt + 0x100 + i); 3736 + } else if (!mtk_is_netsys_v1(eth)) { 3882 3737 /* PSE should not drop port8 and port9 packets from WDMA Tx */ 3883 3738 mtk_w32(eth, 0x00000300, PSE_DROP_CFG); 3884 3739 ··· 4045 3866 mtk_prepare_for_reset(eth); 4046 3867 4047 3868 /* stop all devices to make sure that dma is properly shut down */ 4048 - for (i = 0; i < MTK_MAC_COUNT; i++) { 3869 + for (i = 0; i < MTK_MAX_DEVS; i++) { 4049 3870 if (!eth->netdev[i] || !netif_running(eth->netdev[i])) 4050 3871 continue; 4051 3872 ··· 4061 3882 mtk_hw_init(eth, true); 4062 3883 4063 3884 /* restart DMA and enable IRQs */ 4064 - for (i = 0; i < MTK_MAC_COUNT; i++) { 4065 - if (!test_bit(i, &restart)) 3885 + for (i = 0; i < MTK_MAX_DEVS; i++) { 3886 + if (!eth->netdev[i] || !test_bit(i, &restart)) 4066 3887 continue; 4067 3888 4068 3889 if (mtk_open(eth->netdev[i])) { ··· 4089 3910 { 4090 3911 int i; 4091 3912 4092 - for (i = 0; i < MTK_MAC_COUNT; i++) { 3913 + for (i = 0; i < MTK_MAX_DEVS; i++) { 4093 3914 if (!eth->netdev[i]) 4094 3915 continue; 4095 3916 free_netdev(eth->netdev[i]); ··· 4108 3929 { 4109 3930 int i; 4110 3931 4111 - for (i = 0; i < MTK_MAC_COUNT; i++) { 3932 + for (i = 0; i < MTK_MAX_DEVS; i++) { 4112 3933 struct mtk_mac *mac; 4113 3934 if (!eth->netdev[i]) 4114 3935 continue; ··· 4410 4231 } 4411 4232 4412 4233 id = be32_to_cpup(_id); 4413 - if (id >= MTK_MAC_COUNT) { 4234 + if (id >= MTK_MAX_DEVS) { 4414 4235 dev_err(eth->dev, "%d is not a valid mac id\n", id); 4415 4236 return -EINVAL; 4416 4237 } ··· 4458 4279 } 4459 4280 spin_lock_init(&mac->hw_stats->stats_lock); 4460 4281 u64_stats_init(&mac->hw_stats->syncp); 4461 - mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET; 4282 + 4283 + if (mtk_is_netsys_v3_or_greater(eth)) 4284 + mac->hw_stats->reg_offset = id * 0x80; 4285 + else 4286 + mac->hw_stats->reg_offset = id * 0x40; 4462 4287 4463 4288 /* phylink create */ 4464 4289 err = of_get_phy_mode(np, &phy_mode); ··· 4513 4330 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 4514 4331 mac->phylink_config.supported_interfaces); 4515 4332 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 4333 + mac->phylink_config.supported_interfaces); 4334 + } 4335 + 4336 + if (mtk_is_netsys_v3_or_greater(mac->hw) && 4337 + MTK_HAS_CAPS(mac->hw->soc->caps, MTK_ESW_BIT) && 4338 + id == MTK_GMAC1_ID) { 4339 + mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | 4340 + MAC_SYM_PAUSE | 4341 + MAC_10000FD; 4342 + phy_interface_zero(mac->phylink_config.supported_interfaces); 4343 + __set_bit(PHY_INTERFACE_MODE_INTERNAL, 4516 4344 mac->phylink_config.supported_interfaces); 4517 4345 } 4518 4346 ··· 4585 4391 4586 4392 rtnl_lock(); 4587 4393 4588 - for (i = 0; i < MTK_MAC_COUNT; i++) { 4394 + for (i = 0; i < MTK_MAX_DEVS; i++) { 4589 4395 dev = eth->netdev[i]; 4590 4396 4591 4397 if (!dev || !(dev->flags & IFF_UP)) ··· 4715 4521 } 4716 4522 } 4717 4523 4718 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 4524 + if (mtk_is_netsys_v2_or_greater(eth)) { 4719 4525 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 4720 4526 if (!res) { 4721 4527 err = -EINVAL; ··· 4823 4629 } 4824 4630 4825 4631 if (eth->soc->offload_version) { 4826 - u32 num_ppe; 4632 + u32 num_ppe = mtk_is_netsys_v2_or_greater(eth) ? 2 : 1; 4827 4633 4828 - num_ppe = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 4829 4634 num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe); 4830 4635 for (i = 0; i < num_ppe; i++) { 4831 4636 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400; ··· 4891 4698 int i; 4892 4699 4893 4700 /* stop all devices to make sure that dma is properly shut down */ 4894 - for (i = 0; i < MTK_MAC_COUNT; i++) { 4701 + for (i = 0; i < MTK_MAX_DEVS; i++) { 4895 4702 if (!eth->netdev[i]) 4896 4703 continue; 4897 4704 mtk_stop(eth->netdev[i]); ··· 4916 4723 .hw_features = MTK_HW_FEATURES, 4917 4724 .required_clks = MT7623_CLKS_BITMAP, 4918 4725 .required_pctl = true, 4726 + .version = 1, 4919 4727 .txrx = { 4920 4728 .txd_size = sizeof(struct mtk_tx_dma), 4921 4729 .rxd_size = sizeof(struct mtk_rx_dma), ··· 4933 4739 .hw_features = MTK_HW_FEATURES, 4934 4740 .required_clks = MT7621_CLKS_BITMAP, 4935 4741 .required_pctl = false, 4742 + .version = 1, 4936 4743 .offload_version = 1, 4937 4744 .hash_offset = 2, 4938 4745 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, ··· 4954 4759 .hw_features = MTK_HW_FEATURES, 4955 4760 .required_clks = MT7622_CLKS_BITMAP, 4956 4761 .required_pctl = false, 4762 + .version = 1, 4957 4763 .offload_version = 2, 4958 4764 .hash_offset = 2, 4959 4765 .has_accounting = true, ··· 4975 4779 .hw_features = MTK_HW_FEATURES, 4976 4780 .required_clks = MT7623_CLKS_BITMAP, 4977 4781 .required_pctl = true, 4782 + .version = 1, 4978 4783 .offload_version = 1, 4979 4784 .hash_offset = 2, 4980 4785 .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE, ··· 4998 4801 .required_clks = MT7629_CLKS_BITMAP, 4999 4802 .required_pctl = false, 5000 4803 .has_accounting = true, 4804 + .version = 1, 5001 4805 .txrx = { 5002 4806 .txd_size = sizeof(struct mtk_tx_dma), 5003 4807 .rxd_size = sizeof(struct mtk_rx_dma), ··· 5016 4818 .hw_features = MTK_HW_FEATURES, 5017 4819 .required_clks = MT7981_CLKS_BITMAP, 5018 4820 .required_pctl = false, 4821 + .version = 2, 5019 4822 .offload_version = 2, 5020 4823 .hash_offset = 4, 5021 4824 .has_accounting = true, ··· 5038 4839 .hw_features = MTK_HW_FEATURES, 5039 4840 .required_clks = MT7986_CLKS_BITMAP, 5040 4841 .required_pctl = false, 4842 + .version = 2, 5041 4843 .offload_version = 2, 5042 4844 .hash_offset = 4, 5043 4845 .has_accounting = true, 5044 4846 .foe_entry_size = MTK_FOE_ENTRY_V2_SIZE, 4847 + .txrx = { 4848 + .txd_size = sizeof(struct mtk_tx_dma_v2), 4849 + .rxd_size = sizeof(struct mtk_rx_dma_v2), 4850 + .rx_irq_done_mask = MTK_RX_DONE_INT_V2, 4851 + .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, 4852 + .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, 4853 + .dma_len_offset = 8, 4854 + }, 4855 + }; 4856 + 4857 + static const struct mtk_soc_data mt7988_data = { 4858 + .reg_map = &mt7988_reg_map, 4859 + .ana_rgc3 = 0x128, 4860 + .caps = MT7988_CAPS, 4861 + .hw_features = MTK_HW_FEATURES, 4862 + .required_clks = MT7988_CLKS_BITMAP, 4863 + .required_pctl = false, 4864 + .version = 3, 5045 4865 .txrx = { 5046 4866 .txd_size = sizeof(struct mtk_tx_dma_v2), 5047 4867 .rxd_size = sizeof(struct mtk_rx_dma_v2), ··· 5077 4859 .hw_features = MTK_HW_FEATURES_MT7628, 5078 4860 .required_clks = MT7628_CLKS_BITMAP, 5079 4861 .required_pctl = false, 4862 + .version = 1, 5080 4863 .txrx = { 5081 4864 .txd_size = sizeof(struct mtk_tx_dma), 5082 4865 .rxd_size = sizeof(struct mtk_rx_dma), ··· 5089 4870 }; 5090 4871 5091 4872 const struct of_device_id of_mtk_match[] = { 5092 - { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data}, 5093 - { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data}, 5094 - { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data}, 5095 - { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data}, 5096 - { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data}, 5097 - { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data}, 5098 - { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data}, 5099 - { .compatible = "ralink,rt5350-eth", .data = &rt5350_data}, 4873 + { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data }, 4874 + { .compatible = "mediatek,mt7621-eth", .data = &mt7621_data }, 4875 + { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data }, 4876 + { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data }, 4877 + { .compatible = "mediatek,mt7629-eth", .data = &mt7629_data }, 4878 + { .compatible = "mediatek,mt7981-eth", .data = &mt7981_data }, 4879 + { .compatible = "mediatek,mt7986-eth", .data = &mt7986_data }, 4880 + { .compatible = "mediatek,mt7988-eth", .data = &mt7988_data }, 4881 + { .compatible = "ralink,rt5350-eth", .data = &rt5350_data }, 5100 4882 {}, 5101 4883 }; 5102 4884 MODULE_DEVICE_TABLE(of, of_mtk_match);

+226 -101

drivers/net/ethernet/mediatek/mtk_eth_soc.h

··· 33 33 #define MTK_TX_DMA_BUF_LEN_V2 0xffff 34 34 #define MTK_QDMA_RING_SIZE 2048 35 35 #define MTK_DMA_SIZE 512 36 - #define MTK_MAC_COUNT 2 37 36 #define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN) 38 37 #define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN) 39 38 #define MTK_DMA_DUMMY_DESC 0xffffffff ··· 117 118 #define MTK_CDMP_EG_CTRL 0x404 118 119 119 120 /* GDM Exgress Control Register */ 120 - #define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000)) 121 + #define MTK_GDMA_FWD_CFG(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 122 + 0x540 : 0x500 + (_x * 0x1000); }) 121 123 #define MTK_GDMA_SPECIAL_TAG BIT(24) 122 124 #define MTK_GDMA_ICS_EN BIT(22) 123 125 #define MTK_GDMA_TCS_EN BIT(21) 124 126 #define MTK_GDMA_UCS_EN BIT(20) 127 + #define MTK_GDMA_STRP_CRC BIT(16) 125 128 #define MTK_GDMA_TO_PDMA 0x0 126 129 #define MTK_GDMA_DROP_ALL 0x7777 130 + 131 + /* GDM Egress Control Register */ 132 + #define MTK_GDMA_EG_CTRL(x) ({ typeof(x) _x = (x); (_x == MTK_GMAC3_ID) ? \ 133 + 0x544 : 0x504 + (_x * 0x1000); }) 134 + #define MTK_GDMA_XGDM_SEL BIT(31) 127 135 128 136 /* Unicast Filter MAC Address Register - Low */ 129 137 #define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000)) ··· 294 288 /* QDMA Interrupt grouping registers */ 295 289 #define MTK_RLS_DONE_INT BIT(0) 296 290 297 - #define MTK_STAT_OFFSET 0x40 298 - 299 291 /* QDMA TX NUM */ 300 292 #define QID_BITS_V2(x) (((x) & 0x3f) << 16) 301 293 #define MTK_QDMA_GMAC2_QID 8 ··· 305 301 /* QDMA V2 descriptor txd5 */ 306 302 #define TX_DMA_CHKSUM_V2 (0x7 << 28) 307 303 #define TX_DMA_TSO_V2 BIT(31) 304 + 305 + #define TX_DMA_SPTAG_V3 BIT(27) 308 306 309 307 /* QDMA V2 descriptor txd4 */ 310 308 #define TX_DMA_FPORT_SHIFT_V2 8 ··· 395 389 #define PHY_IAC_TIMEOUT HZ 396 390 397 391 #define MTK_MAC_MISC 0x1000c 392 + #define MTK_MAC_MISC_V3 0x10010 398 393 #define MTK_MUX_TO_ESW BIT(0) 394 + #define MISC_MDC_TURBO BIT(4) 395 + 396 + /* XMAC status registers */ 397 + #define MTK_XGMAC_STS(x) (((x) == MTK_GMAC3_ID) ? 0x1001C : 0x1000C) 398 + #define MTK_XGMAC_FORCE_LINK(x) (((x) == MTK_GMAC2_ID) ? BIT(31) : BIT(15)) 399 + #define MTK_USXGMII_PCS_LINK BIT(8) 400 + #define MTK_XGMAC_RX_FC BIT(5) 401 + #define MTK_XGMAC_TX_FC BIT(4) 402 + #define MTK_USXGMII_PCS_MODE GENMASK(3, 1) 403 + #define MTK_XGMAC_LINK_STS BIT(0) 404 + 405 + /* GSW bridge registers */ 406 + #define MTK_GSW_CFG (0x10080) 407 + #define GSWTX_IPG_MASK GENMASK(19, 16) 408 + #define GSWTX_IPG_SHIFT 16 409 + #define GSWRX_IPG_MASK GENMASK(3, 0) 410 + #define GSWRX_IPG_SHIFT 0 411 + #define GSW_IPG_11 11 399 412 400 413 /* Mac control registers */ 401 414 #define MTK_MAC_MCR(x) (0x10100 + (x * 0x100)) ··· 660 635 */ 661 636 MTK_TX_FLAGS_SINGLE0 = 0x01, 662 637 MTK_TX_FLAGS_PAGE0 = 0x02, 663 - 664 - /* MTK_TX_FLAGS_FPORTx allows tracking which port the transmitted 665 - * SKB out instead of looking up through hardware TX descriptor. 666 - */ 667 - MTK_TX_FLAGS_FPORT0 = 0x04, 668 - MTK_TX_FLAGS_FPORT1 = 0x08, 669 638 }; 670 639 671 640 /* This enum allows us to identify how the clock is defined on the array of the ··· 672 653 MTK_CLK_GP0, 673 654 MTK_CLK_GP1, 674 655 MTK_CLK_GP2, 656 + MTK_CLK_GP3, 657 + MTK_CLK_XGP1, 658 + MTK_CLK_XGP2, 659 + MTK_CLK_XGP3, 660 + MTK_CLK_CRYPTO, 675 661 MTK_CLK_FE, 676 662 MTK_CLK_TRGPLL, 677 663 MTK_CLK_SGMII_TX_250M, ··· 693 669 MTK_CLK_WOCPU1, 694 670 MTK_CLK_NETSYS0, 695 671 MTK_CLK_NETSYS1, 672 + MTK_CLK_ETHWARP_WOCPU2, 673 + MTK_CLK_ETHWARP_WOCPU1, 674 + MTK_CLK_ETHWARP_WOCPU0, 675 + MTK_CLK_TOP_USXGMII_SBUS_0_SEL, 676 + MTK_CLK_TOP_USXGMII_SBUS_1_SEL, 677 + MTK_CLK_TOP_SGM_0_SEL, 678 + MTK_CLK_TOP_SGM_1_SEL, 679 + MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL, 680 + MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL, 681 + MTK_CLK_TOP_ETH_GMII_SEL, 682 + MTK_CLK_TOP_ETH_REFCK_50M_SEL, 683 + MTK_CLK_TOP_ETH_SYS_200M_SEL, 684 + MTK_CLK_TOP_ETH_SYS_SEL, 685 + MTK_CLK_TOP_ETH_XGMII_SEL, 686 + MTK_CLK_TOP_ETH_MII_SEL, 687 + MTK_CLK_TOP_NETSYS_SEL, 688 + MTK_CLK_TOP_NETSYS_500M_SEL, 689 + MTK_CLK_TOP_NETSYS_PAO_2X_SEL, 690 + MTK_CLK_TOP_NETSYS_SYNC_250M_SEL, 691 + MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL, 692 + MTK_CLK_TOP_NETSYS_WARP_SEL, 696 693 MTK_CLK_MAX 697 694 }; 698 695 699 - #define MT7623_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 700 - BIT(MTK_CLK_GP1) | BIT(MTK_CLK_GP2) | \ 701 - BIT(MTK_CLK_TRGPLL)) 702 - #define MT7622_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 703 - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 704 - BIT(MTK_CLK_GP2) | \ 705 - BIT(MTK_CLK_SGMII_TX_250M) | \ 706 - BIT(MTK_CLK_SGMII_RX_250M) | \ 707 - BIT(MTK_CLK_SGMII_CDR_REF) | \ 708 - BIT(MTK_CLK_SGMII_CDR_FB) | \ 709 - BIT(MTK_CLK_SGMII_CK) | \ 710 - BIT(MTK_CLK_ETH2PLL)) 696 + #define MT7623_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 697 + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 698 + BIT_ULL(MTK_CLK_TRGPLL)) 699 + #define MT7622_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 700 + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 701 + BIT_ULL(MTK_CLK_GP2) | \ 702 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 703 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 704 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 705 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 706 + BIT_ULL(MTK_CLK_SGMII_CK) | \ 707 + BIT_ULL(MTK_CLK_ETH2PLL)) 711 708 #define MT7621_CLKS_BITMAP (0) 712 709 #define MT7628_CLKS_BITMAP (0) 713 - #define MT7629_CLKS_BITMAP (BIT(MTK_CLK_ETHIF) | BIT(MTK_CLK_ESW) | \ 714 - BIT(MTK_CLK_GP0) | BIT(MTK_CLK_GP1) | \ 715 - BIT(MTK_CLK_GP2) | BIT(MTK_CLK_FE) | \ 716 - BIT(MTK_CLK_SGMII_TX_250M) | \ 717 - BIT(MTK_CLK_SGMII_RX_250M) | \ 718 - BIT(MTK_CLK_SGMII_CDR_REF) | \ 719 - BIT(MTK_CLK_SGMII_CDR_FB) | \ 720 - BIT(MTK_CLK_SGMII2_TX_250M) | \ 721 - BIT(MTK_CLK_SGMII2_RX_250M) | \ 722 - BIT(MTK_CLK_SGMII2_CDR_REF) | \ 723 - BIT(MTK_CLK_SGMII2_CDR_FB) | \ 724 - BIT(MTK_CLK_SGMII_CK) | \ 725 - BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP)) 726 - #define MT7981_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 727 - BIT(MTK_CLK_WOCPU0) | \ 728 - BIT(MTK_CLK_SGMII_TX_250M) | \ 729 - BIT(MTK_CLK_SGMII_RX_250M) | \ 730 - BIT(MTK_CLK_SGMII_CDR_REF) | \ 731 - BIT(MTK_CLK_SGMII_CDR_FB) | \ 732 - BIT(MTK_CLK_SGMII2_TX_250M) | \ 733 - BIT(MTK_CLK_SGMII2_RX_250M) | \ 734 - BIT(MTK_CLK_SGMII2_CDR_REF) | \ 735 - BIT(MTK_CLK_SGMII2_CDR_FB) | \ 736 - BIT(MTK_CLK_SGMII_CK)) 737 - #define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \ 738 - BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \ 739 - BIT(MTK_CLK_SGMII_TX_250M) | \ 740 - BIT(MTK_CLK_SGMII_RX_250M) | \ 741 - BIT(MTK_CLK_SGMII_CDR_REF) | \ 742 - BIT(MTK_CLK_SGMII_CDR_FB) | \ 743 - BIT(MTK_CLK_SGMII2_TX_250M) | \ 744 - BIT(MTK_CLK_SGMII2_RX_250M) | \ 745 - BIT(MTK_CLK_SGMII2_CDR_REF) | \ 746 - BIT(MTK_CLK_SGMII2_CDR_FB)) 710 + #define MT7629_CLKS_BITMAP (BIT_ULL(MTK_CLK_ETHIF) | BIT_ULL(MTK_CLK_ESW) | \ 711 + BIT_ULL(MTK_CLK_GP0) | BIT_ULL(MTK_CLK_GP1) | \ 712 + BIT_ULL(MTK_CLK_GP2) | BIT_ULL(MTK_CLK_FE) | \ 713 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 714 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 715 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 716 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 717 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 718 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 719 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 720 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 721 + BIT_ULL(MTK_CLK_SGMII_CK) | \ 722 + BIT_ULL(MTK_CLK_ETH2PLL) | BIT_ULL(MTK_CLK_SGMIITOP)) 723 + #define MT7981_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 724 + BIT_ULL(MTK_CLK_GP1) | \ 725 + BIT_ULL(MTK_CLK_WOCPU0) | \ 726 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 727 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 728 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 729 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 730 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 731 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 732 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 733 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB) | \ 734 + BIT_ULL(MTK_CLK_SGMII_CK)) 735 + #define MT7986_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_GP2) | \ 736 + BIT_ULL(MTK_CLK_GP1) | \ 737 + BIT_ULL(MTK_CLK_WOCPU1) | BIT_ULL(MTK_CLK_WOCPU0) | \ 738 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 739 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 740 + BIT_ULL(MTK_CLK_SGMII_CDR_REF) | \ 741 + BIT_ULL(MTK_CLK_SGMII_CDR_FB) | \ 742 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 743 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 744 + BIT_ULL(MTK_CLK_SGMII2_CDR_REF) | \ 745 + BIT_ULL(MTK_CLK_SGMII2_CDR_FB)) 746 + #define MT7988_CLKS_BITMAP (BIT_ULL(MTK_CLK_FE) | BIT_ULL(MTK_CLK_ESW) | \ 747 + BIT_ULL(MTK_CLK_GP1) | BIT_ULL(MTK_CLK_GP2) | \ 748 + BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \ 749 + BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \ 750 + BIT_ULL(MTK_CLK_CRYPTO) | \ 751 + BIT_ULL(MTK_CLK_SGMII_TX_250M) | \ 752 + BIT_ULL(MTK_CLK_SGMII_RX_250M) | \ 753 + BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \ 754 + BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \ 755 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \ 756 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \ 757 + BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \ 758 + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \ 759 + BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \ 760 + BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \ 761 + BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \ 762 + BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \ 763 + BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \ 764 + BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \ 765 + BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \ 766 + BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \ 767 + BIT_ULL(MTK_CLK_TOP_ETH_SYS_SEL) | \ 768 + BIT_ULL(MTK_CLK_TOP_ETH_XGMII_SEL) | \ 769 + BIT_ULL(MTK_CLK_TOP_ETH_MII_SEL) | \ 770 + BIT_ULL(MTK_CLK_TOP_NETSYS_SEL) | \ 771 + BIT_ULL(MTK_CLK_TOP_NETSYS_500M_SEL) | \ 772 + BIT_ULL(MTK_CLK_TOP_NETSYS_PAO_2X_SEL) | \ 773 + BIT_ULL(MTK_CLK_TOP_NETSYS_SYNC_250M_SEL) | \ 774 + BIT_ULL(MTK_CLK_TOP_NETSYS_PPEFB_250M_SEL) | \ 775 + BIT_ULL(MTK_CLK_TOP_NETSYS_WARP_SEL)) 747 776 748 777 enum mtk_dev_state { 749 778 MTK_HW_INIT, 750 779 MTK_RESETTING 780 + }; 781 + 782 + /* PSE Port Definition */ 783 + enum mtk_pse_port { 784 + PSE_ADMA_PORT = 0, 785 + PSE_GDM1_PORT, 786 + PSE_GDM2_PORT, 787 + PSE_PPE0_PORT, 788 + PSE_PPE1_PORT, 789 + PSE_QDMA_TX_PORT, 790 + PSE_QDMA_RX_PORT, 791 + PSE_DROP_PORT, 792 + PSE_WDMA0_PORT, 793 + PSE_WDMA1_PORT, 794 + PSE_TDMA_PORT, 795 + PSE_NONE_PORT, 796 + PSE_PPE2_PORT, 797 + PSE_WDMA2_PORT, 798 + PSE_EIP197_PORT, 799 + PSE_GDM3_PORT, 800 + PSE_PORT_MAX 801 + }; 802 + 803 + /* GMAC Identifier */ 804 + enum mtk_gmac_id { 805 + MTK_GMAC1_ID = 0, 806 + MTK_GMAC2_ID, 807 + MTK_GMAC3_ID, 808 + MTK_GMAC_ID_MAX 751 809 }; 752 810 753 811 enum mtk_tx_buf_type { ··· 850 744 enum mtk_tx_buf_type type; 851 745 void *data; 852 746 853 - u32 flags; 747 + u16 mac_id; 748 + u16 flags; 854 749 DEFINE_DMA_UNMAP_ADDR(dma_addr0); 855 750 DEFINE_DMA_UNMAP_LEN(dma_len0); 856 751 DEFINE_DMA_UNMAP_ADDR(dma_addr1); ··· 927 820 MTK_SHARED_INT_BIT, 928 821 MTK_TRGMII_MT7621_CLK_BIT, 929 822 MTK_QDMA_BIT, 930 - MTK_NETSYS_V2_BIT, 931 823 MTK_SOC_MT7628_BIT, 932 824 MTK_RSTCTRL_PPE1_BIT, 933 825 MTK_U3_COPHY_V2_BIT, ··· 949 843 }; 950 844 951 845 /* Supported hardware group on SoCs */ 952 - #define MTK_RGMII BIT(MTK_RGMII_BIT) 953 - #define MTK_TRGMII BIT(MTK_TRGMII_BIT) 954 - #define MTK_SGMII BIT(MTK_SGMII_BIT) 955 - #define MTK_ESW BIT(MTK_ESW_BIT) 956 - #define MTK_GEPHY BIT(MTK_GEPHY_BIT) 957 - #define MTK_MUX BIT(MTK_MUX_BIT) 958 - #define MTK_INFRA BIT(MTK_INFRA_BIT) 959 - #define MTK_SHARED_SGMII BIT(MTK_SHARED_SGMII_BIT) 960 - #define MTK_HWLRO BIT(MTK_HWLRO_BIT) 961 - #define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT) 962 - #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) 963 - #define MTK_QDMA BIT(MTK_QDMA_BIT) 964 - #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) 965 - #define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT) 966 - #define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT) 967 - #define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) 846 + #define MTK_RGMII BIT_ULL(MTK_RGMII_BIT) 847 + #define MTK_TRGMII BIT_ULL(MTK_TRGMII_BIT) 848 + #define MTK_SGMII BIT_ULL(MTK_SGMII_BIT) 849 + #define MTK_ESW BIT_ULL(MTK_ESW_BIT) 850 + #define MTK_GEPHY BIT_ULL(MTK_GEPHY_BIT) 851 + #define MTK_MUX BIT_ULL(MTK_MUX_BIT) 852 + #define MTK_INFRA BIT_ULL(MTK_INFRA_BIT) 853 + #define MTK_SHARED_SGMII BIT_ULL(MTK_SHARED_SGMII_BIT) 854 + #define MTK_HWLRO BIT_ULL(MTK_HWLRO_BIT) 855 + #define MTK_SHARED_INT BIT_ULL(MTK_SHARED_INT_BIT) 856 + #define MTK_TRGMII_MT7621_CLK BIT_ULL(MTK_TRGMII_MT7621_CLK_BIT) 857 + #define MTK_QDMA BIT_ULL(MTK_QDMA_BIT) 858 + #define MTK_SOC_MT7628 BIT_ULL(MTK_SOC_MT7628_BIT) 859 + #define MTK_RSTCTRL_PPE1 BIT_ULL(MTK_RSTCTRL_PPE1_BIT) 860 + #define MTK_U3_COPHY_V2 BIT_ULL(MTK_U3_COPHY_V2_BIT) 968 861 969 862 #define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \ 970 - BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 863 + BIT_ULL(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT) 971 864 #define MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY \ 972 - BIT(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 865 + BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT) 973 866 #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY \ 974 - BIT(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 867 + BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT) 975 868 #define MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII \ 976 - BIT(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 869 + BIT_ULL(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII_BIT) 977 870 #define MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII \ 978 - BIT(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 871 + BIT_ULL(MTK_ETH_MUX_GMAC12_TO_GEPHY_SGMII_BIT) 979 872 980 873 /* Supported path present on SoCs */ 981 - #define MTK_ETH_PATH_GMAC1_RGMII BIT(MTK_ETH_PATH_GMAC1_RGMII_BIT) 982 - #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 983 - #define MTK_ETH_PATH_GMAC1_SGMII BIT(MTK_ETH_PATH_GMAC1_SGMII_BIT) 984 - #define MTK_ETH_PATH_GMAC2_RGMII BIT(MTK_ETH_PATH_GMAC2_RGMII_BIT) 985 - #define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) 986 - #define MTK_ETH_PATH_GMAC2_GEPHY BIT(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 987 - #define MTK_ETH_PATH_GDM1_ESW BIT(MTK_ETH_PATH_GDM1_ESW_BIT) 874 + #define MTK_ETH_PATH_GMAC1_RGMII BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT) 875 + #define MTK_ETH_PATH_GMAC1_TRGMII BIT_ULL(MTK_ETH_PATH_GMAC1_TRGMII_BIT) 876 + #define MTK_ETH_PATH_GMAC1_SGMII BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT) 877 + #define MTK_ETH_PATH_GMAC2_RGMII BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT) 878 + #define MTK_ETH_PATH_GMAC2_SGMII BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT) 879 + #define MTK_ETH_PATH_GMAC2_GEPHY BIT_ULL(MTK_ETH_PATH_GMAC2_GEPHY_BIT) 880 + #define MTK_ETH_PATH_GDM1_ESW BIT_ULL(MTK_ETH_PATH_GDM1_ESW_BIT) 988 881 989 882 #define MTK_GMAC1_RGMII (MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII) 990 883 #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) ··· 1039 934 #define MT7981_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | MTK_GMAC2_GEPHY | \ 1040 935 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1041 936 MTK_MUX_U3_GMAC2_TO_QPHY | MTK_U3_COPHY_V2 | \ 1042 - MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 937 + MTK_RSTCTRL_PPE1) 1043 938 1044 939 #define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \ 1045 940 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \ 1046 - MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1) 941 + MTK_RSTCTRL_PPE1) 942 + 943 + #define MT7988_CAPS (MTK_GDM1_ESW | MTK_QDMA | MTK_RSTCTRL_PPE1) 1047 944 1048 945 struct mtk_tx_dma_desc_info { 1049 946 dma_addr_t addr; ··· 1116 1009 * @required_pctl A bool value to show whether the SoC requires 1117 1010 * the extra setup for those pins used by GMAC. 1118 1011 * @hash_offset Flow table hash offset. 1012 + * @version SoC version. 1119 1013 * @foe_entry_size Foe table entry size. 1120 1014 * @has_accounting Bool indicating support for accounting of 1121 1015 * offloaded flows. ··· 1130 1022 struct mtk_soc_data { 1131 1023 const struct mtk_reg_map *reg_map; 1132 1024 u32 ana_rgc3; 1133 - u32 caps; 1134 - u32 required_clks; 1025 + u64 caps; 1026 + u64 required_clks; 1135 1027 bool required_pctl; 1136 1028 u8 offload_version; 1137 1029 u8 hash_offset; 1030 + u8 version; 1138 1031 u16 foe_entry_size; 1139 1032 netdev_features_t hw_features; 1140 1033 bool has_accounting; ··· 1152 1043 1153 1044 #define MTK_DMA_MONITOR_TIMEOUT msecs_to_jiffies(1000) 1154 1045 1155 - /* currently no SoC has more than 2 macs */ 1156 - #define MTK_MAX_DEVS 2 1046 + /* currently no SoC has more than 3 macs */ 1047 + #define MTK_MAX_DEVS 3 1157 1048 1158 1049 /* struct mtk_eth - This is the main datasructure for holding the state 1159 1050 * of the driver ··· 1292 1183 /* the struct describing the SoC. these are declared in the soc_xyz.c files */ 1293 1184 extern const struct of_device_id of_mtk_match[]; 1294 1185 1186 + static inline bool mtk_is_netsys_v1(struct mtk_eth *eth) 1187 + { 1188 + return eth->soc->version == 1; 1189 + } 1190 + 1191 + static inline bool mtk_is_netsys_v2_or_greater(struct mtk_eth *eth) 1192 + { 1193 + return eth->soc->version > 1; 1194 + } 1195 + 1196 + static inline bool mtk_is_netsys_v3_or_greater(struct mtk_eth *eth) 1197 + { 1198 + return eth->soc->version > 2; 1199 + } 1200 + 1295 1201 static inline struct mtk_foe_entry * 1296 1202 mtk_foe_get_entry(struct mtk_ppe *ppe, u16 hash) 1297 1203 { ··· 1317 1193 1318 1194 static inline u32 mtk_get_ib1_ts_mask(struct mtk_eth *eth) 1319 1195 { 1320 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1196 + if (mtk_is_netsys_v2_or_greater(eth)) 1321 1197 return MTK_FOE_IB1_BIND_TIMESTAMP_V2; 1322 1198 1323 1199 return MTK_FOE_IB1_BIND_TIMESTAMP; ··· 1325 1201 1326 1202 static inline u32 mtk_get_ib1_ppoe_mask(struct mtk_eth *eth) 1327 1203 { 1328 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1204 + if (mtk_is_netsys_v2_or_greater(eth)) 1329 1205 return MTK_FOE_IB1_BIND_PPPOE_V2; 1330 1206 1331 1207 return MTK_FOE_IB1_BIND_PPPOE; ··· 1333 1209 1334 1210 static inline u32 mtk_get_ib1_vlan_tag_mask(struct mtk_eth *eth) 1335 1211 { 1336 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1212 + if (mtk_is_netsys_v2_or_greater(eth)) 1337 1213 return MTK_FOE_IB1_BIND_VLAN_TAG_V2; 1338 1214 1339 1215 return MTK_FOE_IB1_BIND_VLAN_TAG; ··· 1341 1217 1342 1218 static inline u32 mtk_get_ib1_vlan_layer_mask(struct mtk_eth *eth) 1343 1219 { 1344 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1220 + if (mtk_is_netsys_v2_or_greater(eth)) 1345 1221 return MTK_FOE_IB1_BIND_VLAN_LAYER_V2; 1346 1222 1347 1223 return MTK_FOE_IB1_BIND_VLAN_LAYER; ··· 1349 1225 1350 1226 static inline u32 mtk_prep_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1351 1227 { 1352 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1228 + if (mtk_is_netsys_v2_or_greater(eth)) 1353 1229 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1354 1230 1355 1231 return FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, val); ··· 1357 1233 1358 1234 static inline u32 mtk_get_ib1_vlan_layer(struct mtk_eth *eth, u32 val) 1359 1235 { 1360 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1236 + if (mtk_is_netsys_v2_or_greater(eth)) 1361 1237 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER_V2, val); 1362 1238 1363 1239 return FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, val); ··· 1365 1241 1366 1242 static inline u32 mtk_get_ib1_pkt_type_mask(struct mtk_eth *eth) 1367 1243 { 1368 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1244 + if (mtk_is_netsys_v2_or_greater(eth)) 1369 1245 return MTK_FOE_IB1_PACKET_TYPE_V2; 1370 1246 1371 1247 return MTK_FOE_IB1_PACKET_TYPE; ··· 1373 1249 1374 1250 static inline u32 mtk_get_ib1_pkt_type(struct mtk_eth *eth, u32 val) 1375 1251 { 1376 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1252 + if (mtk_is_netsys_v2_or_greater(eth)) 1377 1253 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE_V2, val); 1378 1254 1379 1255 return FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, val); ··· 1381 1257 1382 1258 static inline u32 mtk_get_ib2_multicast_mask(struct mtk_eth *eth) 1383 1259 { 1384 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1260 + if (mtk_is_netsys_v2_or_greater(eth)) 1385 1261 return MTK_FOE_IB2_MULTICAST_V2; 1386 1262 1387 1263 return MTK_FOE_IB2_MULTICAST; ··· 1392 1268 1393 1269 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg); 1394 1270 u32 mtk_r32(struct mtk_eth *eth, unsigned reg); 1271 + u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg); 1395 1272 1396 1273 int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id); 1397 1274 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);

+9 -9

drivers/net/ethernet/mediatek/mtk_ppe.c

··· 208 208 209 209 memset(entry, 0, sizeof(*entry)); 210 210 211 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 211 + if (mtk_is_netsys_v2_or_greater(eth)) { 212 212 val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) | 213 213 FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE_V2, type) | 214 214 FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) | ··· 272 272 u32 *ib2 = mtk_foe_entry_ib2(eth, entry); 273 273 u32 val = *ib2; 274 274 275 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 275 + if (mtk_is_netsys_v2_or_greater(eth)) { 276 276 val &= ~MTK_FOE_IB2_DEST_PORT_V2; 277 277 val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT_V2, port); 278 278 } else { ··· 423 423 struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry); 424 424 u32 *ib2 = mtk_foe_entry_ib2(eth, entry); 425 425 426 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 426 + if (mtk_is_netsys_v2_or_greater(eth)) { 427 427 *ib2 &= ~MTK_FOE_IB2_PORT_MG_V2; 428 428 *ib2 |= FIELD_PREP(MTK_FOE_IB2_RX_IDX, txq) | 429 429 MTK_FOE_IB2_WDMA_WINFO_V2; ··· 447 447 { 448 448 u32 *ib2 = mtk_foe_entry_ib2(eth, entry); 449 449 450 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 450 + if (mtk_is_netsys_v2_or_greater(eth)) { 451 451 *ib2 &= ~MTK_FOE_IB2_QID_V2; 452 452 *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID_V2, queue); 453 453 *ib2 |= MTK_FOE_IB2_PSE_QOS_V2; ··· 603 603 struct mtk_foe_entry *hwe; 604 604 u32 val; 605 605 606 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 606 + if (mtk_is_netsys_v2_or_greater(eth)) { 607 607 entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2; 608 608 entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP_V2, 609 609 timestamp); ··· 619 619 hwe->ib1 = entry->ib1; 620 620 621 621 if (ppe->accounting) { 622 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 622 + if (mtk_is_netsys_v2_or_greater(eth)) 623 623 val = MTK_FOE_IB2_MIB_CNT_V2; 624 624 else 625 625 val = MTK_FOE_IB2_MIB_CNT; ··· 979 979 MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) | 980 980 FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM, 981 981 MTK_PPE_ENTRIES_SHIFT); 982 - if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) 982 + if (mtk_is_netsys_v2_or_greater(ppe->eth)) 983 983 val |= MTK_PPE_TB_CFG_INFO_SEL; 984 984 ppe_w32(ppe, MTK_PPE_TB_CFG, val); 985 985 ··· 995 995 MTK_PPE_FLOW_CFG_IP4_NAPT | 996 996 MTK_PPE_FLOW_CFG_IP4_DSLITE | 997 997 MTK_PPE_FLOW_CFG_IP4_NAT_FRAG; 998 - if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) 998 + if (mtk_is_netsys_v2_or_greater(ppe->eth)) 999 999 val |= MTK_PPE_MD_TOAP_BYP_CRSN0 | 1000 1000 MTK_PPE_MD_TOAP_BYP_CRSN1 | 1001 1001 MTK_PPE_MD_TOAP_BYP_CRSN2 | ··· 1037 1037 1038 1038 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0); 1039 1039 1040 - if (MTK_HAS_CAPS(ppe->eth->soc->caps, MTK_NETSYS_V2)) { 1040 + if (mtk_is_netsys_v2_or_greater(ppe->eth)) { 1041 1041 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777); 1042 1042 ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f); 1043 1043 }

+1 -1

drivers/net/ethernet/mediatek/mtk_ppe_offload.c

··· 193 193 if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) { 194 194 mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue, 195 195 info.bss, info.wcid); 196 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { 196 + if (mtk_is_netsys_v2_or_greater(eth)) { 197 197 switch (info.wdma_idx) { 198 198 case 0: 199 199 pse_port = 8;

+2 -2

drivers/net/ethernet/mediatek/mtk_wed.c

··· 1091 1091 } else { 1092 1092 struct mtk_eth *eth = dev->hw->eth; 1093 1093 1094 - if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) 1094 + if (mtk_is_netsys_v2_or_greater(eth)) 1095 1095 wed_set(dev, MTK_WED_RESET_IDX, 1096 1096 MTK_WED_RESET_IDX_RX_V2); 1097 1097 else ··· 1907 1907 hw->wdma = wdma; 1908 1908 hw->index = index; 1909 1909 hw->irq = irq; 1910 - hw->version = MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ? 2 : 1; 1910 + hw->version = mtk_is_netsys_v1(eth) ? 1 : 2; 1911 1911 1912 1912 if (hw->version == 1) { 1913 1913 hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,

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