Merge branch 'net-stmmac-clean-up-descriptor-handling-part-1'

+2

drivers/net/ethernet/stmicro/stmmac/descs.h

··· 173 173 struct dma_desc basic; 174 174 }; 175 175 176 + #define dma_desc_to_edesc(x) container_of(x, struct dma_edesc, basic) 177 + 176 178 /* Transmit checksum insertion control */ 177 179 #define TX_CIC_FULL 3 /* Include IP header and pseudoheader */ 178 180

+1 -1

drivers/net/ethernet/stmicro/stmmac/dwmac4_descs.c

··· 427 427 extp++; 428 428 } 429 429 } else if (desc_size == sizeof(struct dma_edesc)) { 430 - struct dma_edesc *ep = (struct dma_edesc *)head; 430 + struct dma_edesc *ep = dma_desc_to_edesc(head); 431 431 432 432 for (i = 0; i < size; i++) { 433 433 dma_addr = dma_rx_phy + i * sizeof(*ep);

+3 -5

drivers/net/ethernet/stmicro/stmmac/stmmac.h

··· 47 47 }; 48 48 49 49 struct stmmac_tx_info { 50 + struct xsk_tx_metadata_compl xsk_meta; 50 51 dma_addr_t buf; 51 - bool map_as_page; 52 52 unsigned len; 53 + enum stmmac_txbuf_type buf_type; 54 + bool map_as_page; 53 55 bool last_segment; 54 56 bool is_jumbo; 55 - enum stmmac_txbuf_type buf_type; 56 - struct xsk_tx_metadata_compl xsk_meta; 57 57 }; 58 58 59 59 #define STMMAC_TBS_AVAIL BIT(0) ··· 79 79 unsigned int cur_tx; 80 80 unsigned int dirty_tx; 81 81 dma_addr_t dma_tx_phy; 82 - dma_addr_t tx_tail_addr; 83 82 u32 mss; 84 83 }; 85 84 ··· 130 131 unsigned int buf_alloc_num; 131 132 unsigned int napi_skb_frag_size; 132 133 dma_addr_t dma_rx_phy; 133 - u32 rx_tail_addr; 134 134 unsigned int state_saved; 135 135 struct { 136 136 struct sk_buff *skb;

+190 -266

drivers/net/ethernet/stmicro/stmmac/stmmac_main.c

··· 362 362 priv->dma_conf.dma_tx_size); 363 363 } 364 364 365 + static size_t stmmac_get_tx_desc_size(struct stmmac_priv *priv, 366 + struct stmmac_tx_queue *tx_q) 367 + { 368 + if (priv->extend_desc) 369 + return sizeof(struct dma_extended_desc); 370 + else if (tx_q->tbs & STMMAC_TBS_AVAIL) 371 + return sizeof(struct dma_edesc); 372 + else 373 + return sizeof(struct dma_desc); 374 + } 375 + 376 + static struct dma_desc *stmmac_get_tx_desc(struct stmmac_priv *priv, 377 + struct stmmac_tx_queue *tx_q, 378 + unsigned int index) 379 + { 380 + if (priv->extend_desc) 381 + return &tx_q->dma_etx[index].basic; 382 + else if (tx_q->tbs & STMMAC_TBS_AVAIL) 383 + return &tx_q->dma_entx[index].basic; 384 + else 385 + return &tx_q->dma_tx[index]; 386 + } 387 + 388 + static void stmmac_set_queue_tx_tail_ptr(struct stmmac_priv *priv, 389 + struct stmmac_tx_queue *tx_q, 390 + unsigned int chan, unsigned int index) 391 + { 392 + size_t desc_size; 393 + u32 tx_tail_addr; 394 + 395 + desc_size = stmmac_get_tx_desc_size(priv, tx_q); 396 + 397 + tx_tail_addr = tx_q->dma_tx_phy + index * desc_size; 398 + stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_tail_addr, chan); 399 + } 400 + 401 + static size_t stmmac_get_rx_desc_size(struct stmmac_priv *priv) 402 + { 403 + if (priv->extend_desc) 404 + return sizeof(struct dma_extended_desc); 405 + else 406 + return sizeof(struct dma_desc); 407 + } 408 + 409 + static struct dma_desc *stmmac_get_rx_desc(struct stmmac_priv *priv, 410 + struct stmmac_rx_queue *rx_q, 411 + unsigned int index) 412 + { 413 + if (priv->extend_desc) 414 + return &rx_q->dma_erx[index].basic; 415 + else 416 + return &rx_q->dma_rx[index]; 417 + } 418 + 419 + static void stmmac_set_queue_rx_tail_ptr(struct stmmac_priv *priv, 420 + struct stmmac_rx_queue *rx_q, 421 + unsigned int chan, unsigned int index) 422 + { 423 + /* This only needs to deal with normal descriptors as enhanced 424 + * descriptiors are only supported with dwmac1000 (<v4.0) which 425 + * does not implement .set_rx_tail_ptr 426 + */ 427 + u32 rx_tail_addr = rx_q->dma_rx_phy + index * sizeof(struct dma_desc); 428 + 429 + stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_tail_addr, chan); 430 + } 431 + 432 + static void stmmac_set_queue_rx_buf_size(struct stmmac_priv *priv, 433 + struct stmmac_rx_queue *rx_q, 434 + unsigned int chan) 435 + { 436 + u32 buf_size; 437 + 438 + if (rx_q->xsk_pool && rx_q->buf_alloc_num) 439 + buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 440 + else 441 + buf_size = priv->dma_conf.dma_buf_sz; 442 + 443 + stmmac_set_dma_bfsize(priv, priv->ioaddr, buf_size, chan); 444 + } 445 + 365 446 /** 366 447 * stmmac_rx_dirty - Get RX queue dirty 367 448 * @priv: driver private structure ··· 1502 1421 1503 1422 pr_info("\tRX Queue %u rings\n", queue); 1504 1423 1505 - if (priv->extend_desc) { 1506 - head_rx = (void *)rx_q->dma_erx; 1507 - desc_size = sizeof(struct dma_extended_desc); 1508 - } else { 1509 - head_rx = (void *)rx_q->dma_rx; 1510 - desc_size = sizeof(struct dma_desc); 1511 - } 1424 + head_rx = stmmac_get_rx_desc(priv, rx_q, 0); 1425 + desc_size = stmmac_get_rx_desc_size(priv); 1512 1426 1513 1427 /* Display RX ring */ 1514 1428 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, ··· 1525 1449 1526 1450 pr_info("\tTX Queue %d rings\n", queue); 1527 1451 1528 - if (priv->extend_desc) { 1529 - head_tx = (void *)tx_q->dma_etx; 1530 - desc_size = sizeof(struct dma_extended_desc); 1531 - } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1532 - head_tx = (void *)tx_q->dma_entx; 1533 - desc_size = sizeof(struct dma_edesc); 1534 - } else { 1535 - head_tx = (void *)tx_q->dma_tx; 1536 - desc_size = sizeof(struct dma_desc); 1537 - } 1452 + head_tx = stmmac_get_tx_desc(priv, tx_q, 0); 1453 + desc_size = stmmac_get_tx_desc_size(priv, tx_q); 1538 1454 1539 1455 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1540 1456 tx_q->dma_tx_phy, desc_size); ··· 1582 1514 u32 queue) 1583 1515 { 1584 1516 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1517 + struct dma_desc *desc; 1585 1518 int i; 1586 1519 1587 1520 /* Clear the RX descriptors */ 1588 - for (i = 0; i < dma_conf->dma_rx_size; i++) 1589 - if (priv->extend_desc) 1590 - stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1591 - priv->use_riwt, priv->mode, 1592 - (i == dma_conf->dma_rx_size - 1), 1593 - dma_conf->dma_buf_sz); 1594 - else 1595 - stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1596 - priv->use_riwt, priv->mode, 1597 - (i == dma_conf->dma_rx_size - 1), 1598 - dma_conf->dma_buf_sz); 1521 + for (i = 0; i < dma_conf->dma_rx_size; i++) { 1522 + desc = stmmac_get_rx_desc(priv, rx_q, i); 1523 + 1524 + stmmac_init_rx_desc(priv, desc, priv->use_riwt, priv->mode, 1525 + (i == dma_conf->dma_rx_size - 1), 1526 + dma_conf->dma_buf_sz); 1527 + } 1599 1528 } 1600 1529 1601 1530 /** ··· 1615 1550 int last = (i == (dma_conf->dma_tx_size - 1)); 1616 1551 struct dma_desc *p; 1617 1552 1618 - if (priv->extend_desc) 1619 - p = &tx_q->dma_etx[i].basic; 1620 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1621 - p = &tx_q->dma_entx[i].basic; 1622 - else 1623 - p = &tx_q->dma_tx[i]; 1624 - 1553 + p = stmmac_get_tx_desc(priv, tx_q, i); 1625 1554 stmmac_init_tx_desc(priv, p, priv->mode, last); 1626 1555 } 1627 1556 } ··· 1790 1731 struct dma_desc *p; 1791 1732 int ret; 1792 1733 1793 - if (priv->extend_desc) 1794 - p = &((rx_q->dma_erx + i)->basic); 1795 - else 1796 - p = rx_q->dma_rx + i; 1734 + p = stmmac_get_rx_desc(priv, rx_q, i); 1797 1735 1798 1736 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1799 1737 queue); ··· 1845 1789 dma_addr_t dma_addr; 1846 1790 struct dma_desc *p; 1847 1791 1848 - if (priv->extend_desc) 1849 - p = (struct dma_desc *)(rx_q->dma_erx + i); 1850 - else 1851 - p = rx_q->dma_rx + i; 1792 + p = stmmac_get_rx_desc(priv, rx_q, i); 1852 1793 1853 1794 buf = &rx_q->buf_pool[i]; 1854 1795 ··· 1902 1849 NULL)); 1903 1850 netdev_info(priv->dev, 1904 1851 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1905 - rx_q->queue_index); 1852 + queue); 1906 1853 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1907 1854 } else { 1908 1855 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, ··· 1910 1857 rx_q->page_pool)); 1911 1858 netdev_info(priv->dev, 1912 1859 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1913 - rx_q->queue_index); 1860 + queue); 1914 1861 } 1915 1862 1916 1863 if (rx_q->xsk_pool) { ··· 1978 1925 return ret; 1979 1926 } 1980 1927 1928 + static void stmmac_set_tx_dma_entry(struct stmmac_tx_queue *tx_q, 1929 + unsigned int entry, 1930 + enum stmmac_txbuf_type type, 1931 + dma_addr_t addr, size_t len, 1932 + bool map_as_page) 1933 + { 1934 + tx_q->tx_skbuff_dma[entry].buf = addr; 1935 + tx_q->tx_skbuff_dma[entry].len = len; 1936 + tx_q->tx_skbuff_dma[entry].buf_type = type; 1937 + tx_q->tx_skbuff_dma[entry].map_as_page = map_as_page; 1938 + tx_q->tx_skbuff_dma[entry].last_segment = false; 1939 + tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1940 + } 1941 + 1942 + static void stmmac_set_tx_skb_dma_entry(struct stmmac_tx_queue *tx_q, 1943 + unsigned int entry, dma_addr_t addr, 1944 + size_t len, bool map_as_page) 1945 + { 1946 + stmmac_set_tx_dma_entry(tx_q, entry, STMMAC_TXBUF_T_SKB, addr, len, 1947 + map_as_page); 1948 + } 1949 + 1950 + static void stmmac_set_tx_dma_last_segment(struct stmmac_tx_queue *tx_q, 1951 + unsigned int entry) 1952 + { 1953 + tx_q->tx_skbuff_dma[entry].last_segment = true; 1954 + } 1955 + 1981 1956 /** 1982 1957 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1983 1958 * @priv: driver private structure ··· 2043 1962 for (i = 0; i < dma_conf->dma_tx_size; i++) { 2044 1963 struct dma_desc *p; 2045 1964 2046 - if (priv->extend_desc) 2047 - p = &((tx_q->dma_etx + i)->basic); 2048 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2049 - p = &((tx_q->dma_entx + i)->basic); 2050 - else 2051 - p = tx_q->dma_tx + i; 2052 - 1965 + p = stmmac_get_tx_desc(priv, tx_q, i); 2053 1966 stmmac_clear_desc(priv, p); 1967 + stmmac_set_tx_skb_dma_entry(tx_q, i, 0, 0, false); 2054 1968 2055 - tx_q->tx_skbuff_dma[i].buf = 0; 2056 - tx_q->tx_skbuff_dma[i].map_as_page = false; 2057 - tx_q->tx_skbuff_dma[i].len = 0; 2058 - tx_q->tx_skbuff_dma[i].last_segment = false; 2059 1969 tx_q->tx_skbuff[i] = NULL; 2060 1970 } 2061 1971 ··· 2204 2132 dma_free_tx_skbufs(priv, dma_conf, queue); 2205 2133 2206 2134 if (priv->extend_desc) { 2207 - size = sizeof(struct dma_extended_desc); 2208 2135 addr = tx_q->dma_etx; 2209 2136 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 2210 - size = sizeof(struct dma_edesc); 2211 2137 addr = tx_q->dma_entx; 2212 2138 } else { 2213 - size = sizeof(struct dma_desc); 2214 2139 addr = tx_q->dma_tx; 2215 2140 } 2216 2141 2217 - size *= dma_conf->dma_tx_size; 2142 + size = stmmac_get_tx_desc_size(priv, tx_q) * dma_conf->dma_tx_size; 2218 2143 2219 2144 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 2220 2145 ··· 2310 2241 else 2311 2242 napi_id = ch->rx_napi.napi_id; 2312 2243 2313 - ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2314 - rx_q->queue_index, 2315 - napi_id); 2244 + ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, queue, napi_id); 2316 2245 if (ret) { 2317 2246 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2318 2247 return -EINVAL; ··· 2371 2304 if (!tx_q->tx_skbuff) 2372 2305 return -ENOMEM; 2373 2306 2374 - if (priv->extend_desc) 2375 - size = sizeof(struct dma_extended_desc); 2376 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2377 - size = sizeof(struct dma_edesc); 2378 - else 2379 - size = sizeof(struct dma_desc); 2380 - 2381 - size *= dma_conf->dma_tx_size; 2307 + size = stmmac_get_tx_desc_size(priv, tx_q) * dma_conf->dma_tx_size; 2382 2308 2383 2309 addr = dma_alloc_coherent(priv->device, size, 2384 2310 &tx_q->dma_tx_phy, GFP_KERNEL); ··· 2623 2563 /* configure all channels */ 2624 2564 for (chan = 0; chan < rx_channels_count; chan++) { 2625 2565 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2626 - u32 buf_size; 2627 2566 2628 2567 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2629 2568 2630 2569 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2631 2570 rxfifosz, qmode); 2632 2571 2633 - if (rx_q->xsk_pool) { 2634 - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2635 - stmmac_set_dma_bfsize(priv, priv->ioaddr, 2636 - buf_size, 2637 - chan); 2638 - } else { 2639 - stmmac_set_dma_bfsize(priv, priv->ioaddr, 2640 - priv->dma_conf.dma_buf_sz, 2641 - chan); 2642 - } 2572 + stmmac_set_queue_rx_buf_size(priv, rx_q, chan); 2643 2573 } 2644 2574 2645 2575 for (chan = 0; chan < tx_channels_count; chan++) { ··· 2734 2684 continue; 2735 2685 } 2736 2686 2737 - if (likely(priv->extend_desc)) 2738 - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2739 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2740 - tx_desc = &tx_q->dma_entx[entry].basic; 2741 - else 2742 - tx_desc = tx_q->dma_tx + entry; 2743 - 2687 + tx_desc = stmmac_get_tx_desc(priv, tx_q, entry); 2744 2688 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2745 2689 meta = xsk_buff_get_metadata(pool, xdp_desc.addr); 2746 2690 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2747 - 2748 - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2749 2691 2750 2692 /* To return XDP buffer to XSK pool, we simple call 2751 2693 * xsk_tx_completed(), so we don't need to fill up 2752 2694 * 'buf' and 'xdpf'. 2753 2695 */ 2754 - tx_q->tx_skbuff_dma[entry].buf = 0; 2755 - tx_q->xdpf[entry] = NULL; 2696 + stmmac_set_tx_dma_entry(tx_q, entry, STMMAC_TXBUF_T_XSK_TX, 2697 + 0, xdp_desc.len, false); 2698 + stmmac_set_tx_dma_last_segment(tx_q, entry); 2756 2699 2757 - tx_q->tx_skbuff_dma[entry].map_as_page = false; 2758 - tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2759 - tx_q->tx_skbuff_dma[entry].last_segment = true; 2760 - tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2700 + tx_q->xdpf[entry] = NULL; 2761 2701 2762 2702 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2763 2703 ··· 2861 2821 skb = NULL; 2862 2822 } 2863 2823 2864 - if (priv->extend_desc) 2865 - p = (struct dma_desc *)(tx_q->dma_etx + entry); 2866 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2867 - p = &tx_q->dma_entx[entry].basic; 2868 - else 2869 - p = tx_q->dma_tx + entry; 2870 - 2824 + p = stmmac_get_tx_desc(priv, tx_q, entry); 2871 2825 status = stmmac_tx_status(priv, &priv->xstats, p, priv->ioaddr); 2872 2826 /* Check if the descriptor is owned by the DMA */ 2873 2827 if (unlikely(status & tx_dma_own)) ··· 2916 2882 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2917 2883 } 2918 2884 2885 + /* This looks at tx_q->tx_skbuff_dma[tx_q->dirty_tx].is_jumbo 2886 + * and tx_q->tx_skbuff_dma[tx_q->dirty_tx].last_segment 2887 + */ 2919 2888 stmmac_clean_desc3(priv, tx_q, p); 2920 2889 2921 2890 tx_q->tx_skbuff_dma[entry].last_segment = false; ··· 3311 3274 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 3312 3275 rx_q->dma_rx_phy, chan); 3313 3276 3314 - rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3315 - (rx_q->buf_alloc_num * 3316 - sizeof(struct dma_desc)); 3317 - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 3318 - rx_q->rx_tail_addr, chan); 3277 + stmmac_set_queue_rx_tail_ptr(priv, rx_q, chan, 3278 + rx_q->buf_alloc_num); 3319 3279 } 3320 3280 3321 3281 /* DMA TX Channel Configuration */ ··· 3322 3288 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 3323 3289 tx_q->dma_tx_phy, chan); 3324 3290 3325 - tx_q->tx_tail_addr = tx_q->dma_tx_phy; 3326 - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 3327 - tx_q->tx_tail_addr, chan); 3291 + stmmac_set_queue_tx_tail_ptr(priv, tx_q, chan, 0); 3328 3292 } 3329 3293 3330 3294 return ret; ··· 3338 3306 if (!tx_coal_timer) 3339 3307 return; 3340 3308 3341 - ch = &priv->channel[tx_q->queue_index]; 3309 + ch = &priv->channel[queue]; 3342 3310 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 3343 3311 3344 3312 /* Arm timer only if napi is not already scheduled. ··· 4359 4327 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4360 4328 { 4361 4329 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4362 - int desc_size; 4363 - 4364 - if (likely(priv->extend_desc)) 4365 - desc_size = sizeof(struct dma_extended_desc); 4366 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4367 - desc_size = sizeof(struct dma_edesc); 4368 - else 4369 - desc_size = sizeof(struct dma_desc); 4370 4330 4371 4331 /* The own bit must be the latest setting done when prepare the 4372 4332 * descriptor and then barrier is needed to make sure that ··· 4366 4342 */ 4367 4343 wmb(); 4368 4344 4369 - tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4370 - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4345 + stmmac_set_queue_tx_tail_ptr(priv, tx_q, queue, tx_q->cur_tx); 4371 4346 } 4372 4347 4373 4348 /** ··· 4518 4495 * this DMA buffer right after the DMA engine completely finishes the 4519 4496 * full buffer transmission. 4520 4497 */ 4521 - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4522 - tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_headlen(skb); 4523 - tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = false; 4524 - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4498 + stmmac_set_tx_skb_dma_entry(tx_q, tx_q->cur_tx, des, skb_headlen(skb), 4499 + false); 4525 4500 4526 4501 /* Prepare fragments */ 4527 4502 for (i = 0; i < nfrags; i++) { ··· 4534 4513 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4535 4514 (i == nfrags - 1), queue); 4536 4515 4537 - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4538 - tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4539 - tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4540 - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4516 + stmmac_set_tx_skb_dma_entry(tx_q, tx_q->cur_tx, des, 4517 + skb_frag_size(frag), true); 4541 4518 } 4542 4519 4543 - tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4520 + stmmac_set_tx_dma_last_segment(tx_q, tx_q->cur_tx); 4544 4521 4545 4522 /* Only the last descriptor gets to point to the skb. */ 4546 4523 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4547 - tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4548 4524 4549 4525 /* Manage tx mitigation */ 4550 4526 tx_packets = CIRC_CNT(tx_q->cur_tx + 1, first_tx, ··· 4757 4739 csum_insertion = !csum_insertion; 4758 4740 } 4759 4741 4760 - if (likely(priv->extend_desc)) 4761 - desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4762 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4763 - desc = &tx_q->dma_entx[entry].basic; 4764 - else 4765 - desc = tx_q->dma_tx + entry; 4766 - 4742 + desc = stmmac_get_tx_desc(priv, tx_q, entry); 4767 4743 first = desc; 4768 4744 4769 4745 if (has_vlan) ··· 4782 4770 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4783 4771 WARN_ON(tx_q->tx_skbuff[entry]); 4784 4772 4785 - if (likely(priv->extend_desc)) 4786 - desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4787 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4788 - desc = &tx_q->dma_entx[entry].basic; 4789 - else 4790 - desc = tx_q->dma_tx + entry; 4773 + desc = stmmac_get_tx_desc(priv, tx_q, entry); 4791 4774 4792 4775 des = skb_frag_dma_map(priv->device, frag, 0, len, 4793 4776 DMA_TO_DEVICE); 4794 4777 if (dma_mapping_error(priv->device, des)) 4795 4778 goto dma_map_err; /* should reuse desc w/o issues */ 4796 4779 4797 - tx_q->tx_skbuff_dma[entry].buf = des; 4798 - 4780 + stmmac_set_tx_skb_dma_entry(tx_q, entry, des, len, true); 4799 4781 stmmac_set_desc_addr(priv, desc, des); 4800 - 4801 - tx_q->tx_skbuff_dma[entry].map_as_page = true; 4802 - tx_q->tx_skbuff_dma[entry].len = len; 4803 - tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4804 - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4805 4782 4806 4783 /* Prepare the descriptor and set the own bit too */ 4807 4784 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4808 4785 priv->mode, 1, last_segment, skb->len); 4809 4786 } 4810 4787 4788 + stmmac_set_tx_dma_last_segment(tx_q, entry); 4789 + 4811 4790 /* Only the last descriptor gets to point to the skb. */ 4812 4791 tx_q->tx_skbuff[entry] = skb; 4813 - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4814 4792 4815 4793 /* According to the coalesce parameter the IC bit for the latest 4816 4794 * segment is reset and the timer re-started to clean the tx status. ··· 4823 4821 set_ic = false; 4824 4822 4825 4823 if (set_ic) { 4826 - if (likely(priv->extend_desc)) 4827 - desc = &tx_q->dma_etx[entry].basic; 4828 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4829 - desc = &tx_q->dma_entx[entry].basic; 4830 - else 4831 - desc = &tx_q->dma_tx[entry]; 4832 - 4824 + desc = stmmac_get_tx_desc(priv, tx_q, entry); 4833 4825 tx_q->tx_count_frames = 0; 4834 4826 stmmac_set_tx_ic(priv, desc); 4835 4827 } ··· 4873 4877 if (dma_mapping_error(priv->device, des)) 4874 4878 goto dma_map_err; 4875 4879 4876 - tx_q->tx_skbuff_dma[first_entry].buf = des; 4877 - tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4878 - tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4880 + stmmac_set_tx_skb_dma_entry(tx_q, first_entry, des, nopaged_len, 4881 + false); 4879 4882 4880 4883 stmmac_set_desc_addr(priv, first, des); 4881 4884 4882 - tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4883 - tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4885 + if (last_segment) 4886 + stmmac_set_tx_dma_last_segment(tx_q, first_entry); 4884 4887 4885 4888 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4886 4889 priv->hwts_tx_en)) { ··· 4960 4965 struct dma_desc *p; 4961 4966 bool use_rx_wd; 4962 4967 4963 - if (priv->extend_desc) 4964 - p = (struct dma_desc *)(rx_q->dma_erx + entry); 4965 - else 4966 - p = rx_q->dma_rx + entry; 4968 + p = stmmac_get_rx_desc(priv, rx_q, entry); 4967 4969 4968 4970 if (!buf->page) { 4969 4971 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); ··· 5001 5009 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 5002 5010 } 5003 5011 rx_q->dirty_rx = entry; 5004 - rx_q->rx_tail_addr = rx_q->dma_rx_phy + 5005 - (rx_q->dirty_rx * sizeof(struct dma_desc)); 5006 - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 5012 + stmmac_set_queue_rx_tail_ptr(priv, rx_q, queue, rx_q->dirty_rx); 5007 5013 /* Wake up Rx DMA from the suspend state if required */ 5008 5014 stmmac_enable_dma_reception(priv, priv->ioaddr, queue); 5009 5015 } ··· 5076 5086 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 5077 5087 bool csum = !priv->plat->tx_queues_cfg[queue].coe_unsupported; 5078 5088 unsigned int entry = tx_q->cur_tx; 5089 + enum stmmac_txbuf_type buf_type; 5079 5090 struct dma_desc *tx_desc; 5080 5091 dma_addr_t dma_addr; 5081 5092 bool set_ic; ··· 5091 5100 return STMMAC_XDP_CONSUMED; 5092 5101 } 5093 5102 5094 - if (likely(priv->extend_desc)) 5095 - tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 5096 - else if (tx_q->tbs & STMMAC_TBS_AVAIL) 5097 - tx_desc = &tx_q->dma_entx[entry].basic; 5098 - else 5099 - tx_desc = tx_q->dma_tx + entry; 5100 - 5103 + tx_desc = stmmac_get_tx_desc(priv, tx_q, entry); 5101 5104 if (dma_map) { 5102 5105 dma_addr = dma_map_single(priv->device, xdpf->data, 5103 5106 xdpf->len, DMA_TO_DEVICE); 5104 5107 if (dma_mapping_error(priv->device, dma_addr)) 5105 5108 return STMMAC_XDP_CONSUMED; 5106 5109 5107 - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 5110 + buf_type = STMMAC_TXBUF_T_XDP_NDO; 5108 5111 } else { 5109 5112 struct page *page = virt_to_page(xdpf->data); 5110 5113 ··· 5107 5122 dma_sync_single_for_device(priv->device, dma_addr, 5108 5123 xdpf->len, DMA_BIDIRECTIONAL); 5109 5124 5110 - tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 5125 + buf_type = STMMAC_TXBUF_T_XDP_TX; 5111 5126 } 5112 5127 5113 - tx_q->tx_skbuff_dma[entry].buf = dma_addr; 5114 - tx_q->tx_skbuff_dma[entry].map_as_page = false; 5115 - tx_q->tx_skbuff_dma[entry].len = xdpf->len; 5116 - tx_q->tx_skbuff_dma[entry].last_segment = true; 5117 - tx_q->tx_skbuff_dma[entry].is_jumbo = false; 5128 + stmmac_set_tx_dma_entry(tx_q, entry, buf_type, dma_addr, xdpf->len, 5129 + false); 5130 + stmmac_set_tx_dma_last_segment(tx_q, entry); 5118 5131 5119 5132 tx_q->xdpf[entry] = xdpf; 5120 5133 ··· 5350 5367 } 5351 5368 } 5352 5369 5353 - if (priv->extend_desc) 5354 - rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 5355 - else 5356 - rx_desc = rx_q->dma_rx + entry; 5370 + rx_desc = stmmac_get_rx_desc(priv, rx_q, entry); 5357 5371 5358 5372 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 5359 5373 stmmac_set_desc_addr(priv, rx_desc, dma_addr); ··· 5375 5395 5376 5396 if (rx_desc) { 5377 5397 rx_q->dirty_rx = entry; 5378 - rx_q->rx_tail_addr = rx_q->dma_rx_phy + 5379 - (rx_q->dirty_rx * sizeof(struct dma_desc)); 5380 - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 5398 + stmmac_set_queue_rx_tail_ptr(priv, rx_q, queue, rx_q->dirty_rx); 5381 5399 } 5382 5400 5383 5401 return ret; ··· 5406 5428 int status = 0; 5407 5429 5408 5430 if (netif_msg_rx_status(priv)) { 5409 - void *rx_head; 5431 + void *rx_head = stmmac_get_rx_desc(priv, rx_q, 0); 5410 5432 5411 5433 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5412 - if (priv->extend_desc) { 5413 - rx_head = (void *)rx_q->dma_erx; 5414 - desc_size = sizeof(struct dma_extended_desc); 5415 - } else { 5416 - rx_head = (void *)rx_q->dma_rx; 5417 - desc_size = sizeof(struct dma_desc); 5418 - } 5434 + desc_size = stmmac_get_rx_desc_size(priv); 5419 5435 5420 5436 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5421 5437 rx_q->dma_rx_phy, desc_size); ··· 5445 5473 dirty = 0; 5446 5474 } 5447 5475 5448 - if (priv->extend_desc) 5449 - p = (struct dma_desc *)(rx_q->dma_erx + entry); 5450 - else 5451 - p = rx_q->dma_rx + entry; 5476 + p = stmmac_get_rx_desc(priv, rx_q, entry); 5452 5477 5453 5478 /* read the status of the incoming frame */ 5454 5479 status = stmmac_rx_status(priv, &priv->xstats, p); ··· 5458 5489 priv->dma_conf.dma_rx_size); 5459 5490 next_entry = rx_q->cur_rx; 5460 5491 5461 - if (priv->extend_desc) 5462 - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5463 - else 5464 - np = rx_q->dma_rx + next_entry; 5492 + np = stmmac_get_rx_desc(priv, rx_q, next_entry); 5465 5493 5466 5494 prefetch(np); 5467 5495 ··· 5594 5628 limit = min(priv->dma_conf.dma_rx_size - 1, (unsigned int)limit); 5595 5629 5596 5630 if (netif_msg_rx_status(priv)) { 5597 - void *rx_head; 5631 + void *rx_head = stmmac_get_rx_desc(priv, rx_q, 0); 5598 5632 5599 5633 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5600 - if (priv->extend_desc) { 5601 - rx_head = (void *)rx_q->dma_erx; 5602 - desc_size = sizeof(struct dma_extended_desc); 5603 - } else { 5604 - rx_head = (void *)rx_q->dma_rx; 5605 - desc_size = sizeof(struct dma_desc); 5606 - } 5634 + desc_size = stmmac_get_rx_desc_size(priv); 5607 5635 5608 5636 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5609 5637 rx_q->dma_rx_phy, desc_size); ··· 5630 5670 entry = next_entry; 5631 5671 buf = &rx_q->buf_pool[entry]; 5632 5672 5633 - if (priv->extend_desc) 5634 - p = (struct dma_desc *)(rx_q->dma_erx + entry); 5635 - else 5636 - p = rx_q->dma_rx + entry; 5673 + p = stmmac_get_rx_desc(priv, rx_q, entry); 5637 5674 5638 5675 /* read the status of the incoming frame */ 5639 5676 status = stmmac_rx_status(priv, &priv->xstats, p); ··· 5642 5685 priv->dma_conf.dma_rx_size); 5643 5686 next_entry = rx_q->cur_rx; 5644 5687 5645 - if (priv->extend_desc) 5646 - np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5647 - else 5648 - np = rx_q->dma_rx + next_entry; 5688 + np = stmmac_get_rx_desc(priv, rx_q, next_entry); 5649 5689 5650 5690 prefetch(np); 5651 5691 ··· 6921 6967 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6922 6968 struct stmmac_channel *ch = &priv->channel[queue]; 6923 6969 unsigned long flags; 6924 - u32 buf_size; 6925 6970 int ret; 6926 6971 6927 6972 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); ··· 6940 6987 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6941 6988 6942 6989 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6943 - rx_q->dma_rx_phy, rx_q->queue_index); 6990 + rx_q->dma_rx_phy, queue); 6944 6991 6945 - rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6946 - sizeof(struct dma_desc)); 6947 - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6948 - rx_q->rx_tail_addr, rx_q->queue_index); 6992 + stmmac_set_queue_rx_tail_ptr(priv, rx_q, queue, rx_q->buf_alloc_num); 6949 6993 6950 - if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6951 - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6952 - stmmac_set_dma_bfsize(priv, priv->ioaddr, 6953 - buf_size, 6954 - rx_q->queue_index); 6955 - } else { 6956 - stmmac_set_dma_bfsize(priv, priv->ioaddr, 6957 - priv->dma_conf.dma_buf_sz, 6958 - rx_q->queue_index); 6959 - } 6994 + stmmac_set_queue_rx_buf_size(priv, rx_q, queue); 6960 6995 6961 6996 stmmac_start_rx_dma(priv, queue); 6962 6997 ··· 6990 7049 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6991 7050 6992 7051 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6993 - tx_q->dma_tx_phy, tx_q->queue_index); 7052 + tx_q->dma_tx_phy, queue); 6994 7053 6995 7054 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6996 - stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 7055 + stmmac_enable_tbs(priv, priv->ioaddr, 1, queue); 6997 7056 6998 - tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6999 - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 7000 - tx_q->tx_tail_addr, tx_q->queue_index); 7057 + stmmac_set_queue_tx_tail_ptr(priv, tx_q, queue, 0); 7001 7058 7002 7059 stmmac_start_tx_dma(priv, queue); 7003 7060 ··· 7045 7106 u8 dma_csr_ch = max(rx_cnt, tx_cnt); 7046 7107 struct stmmac_rx_queue *rx_q; 7047 7108 struct stmmac_tx_queue *tx_q; 7048 - u32 buf_size; 7049 7109 bool sph_en; 7050 7110 u8 chan; 7051 7111 int ret; ··· 7081 7143 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 7082 7144 rx_q->dma_rx_phy, chan); 7083 7145 7084 - rx_q->rx_tail_addr = rx_q->dma_rx_phy + 7085 - (rx_q->buf_alloc_num * 7086 - sizeof(struct dma_desc)); 7087 - stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 7088 - rx_q->rx_tail_addr, chan); 7146 + stmmac_set_queue_rx_tail_ptr(priv, rx_q, chan, 7147 + rx_q->buf_alloc_num); 7089 7148 7090 - if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 7091 - buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 7092 - stmmac_set_dma_bfsize(priv, priv->ioaddr, 7093 - buf_size, 7094 - rx_q->queue_index); 7095 - } else { 7096 - stmmac_set_dma_bfsize(priv, priv->ioaddr, 7097 - priv->dma_conf.dma_buf_sz, 7098 - rx_q->queue_index); 7099 - } 7149 + stmmac_set_queue_rx_buf_size(priv, rx_q, chan); 7100 7150 7101 7151 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 7102 7152 } ··· 7096 7170 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 7097 7171 tx_q->dma_tx_phy, chan); 7098 7172 7099 - tx_q->tx_tail_addr = tx_q->dma_tx_phy; 7100 - stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 7101 - tx_q->tx_tail_addr, chan); 7173 + stmmac_set_queue_tx_tail_ptr(priv, tx_q, chan, 0); 7102 7174 7103 7175 hrtimer_setup(&tx_q->txtimer, stmmac_tx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 7104 7176 }

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