Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
drm/amdgpu: Add rlcv firmware for frontdoor loading.
Rlcv is required to be loaded for frontdoor.
1. Add 2 rlcv ucode ids:
AMDGPU_UCODE_RLC_IRAM_1 and AMDGPU_UCODE_RLC_DRAM_1
2. Add rlc_firmware_header_v2_5 for above 2 rlcv headers.
3. Add 2 types in psp_fw_gfx_if interface interacting with asp:
GFX_FW_TYPE_RLX6_UCODE_CORE1 - RLCV IRAM
GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1 - RLCV DRAM BOOT
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
authored by
Feifei Xu
and committed by
Alex Deucher
708b8589
4c7838b5
+96
-1
+8
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+8
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
···
2719
2719
case AMDGPU_UCODE_ID_RLC_DRAM:
2720
2720
*type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2721
2721
break;
2722
+
case AMDGPU_UCODE_ID_RLC_IRAM_1:
2723
+
*type = GFX_FW_TYPE_RLX6_UCODE_CORE1;
2724
+
break;
2725
+
case AMDGPU_UCODE_ID_RLC_DRAM_1:
2726
+
*type = GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1;
2727
+
break;
2722
2728
case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2723
2729
*type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2724
2730
break;
···
2893
2887
amdgpu_ucode_print_gfx_hdr(hdr);
2894
2888
break;
2895
2889
case AMDGPU_UCODE_ID_RLC_G:
2890
+
case AMDGPU_UCODE_ID_RLC_DRAM_1:
2891
+
case AMDGPU_UCODE_ID_RLC_IRAM_1:
2896
2892
hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2897
2893
amdgpu_ucode_print_rlc_hdr(hdr);
2898
2894
break;
+36
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
+36
-1
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.c
···
515
515
}
516
516
}
517
517
518
+
static void amdgpu_gfx_rlc_init_microcode_v2_5(struct amdgpu_device *adev)
519
+
{
520
+
const struct rlc_firmware_header_v2_5 *rlc_hdr;
521
+
struct amdgpu_firmware_info *info;
522
+
523
+
rlc_hdr = (const struct rlc_firmware_header_v2_5 *)adev->gfx.rlc_fw->data;
524
+
adev->gfx.rlc.rlc_1_iram_ucode_size_bytes =
525
+
le32_to_cpu(rlc_hdr->rlc_1_iram_ucode_size_bytes);
526
+
adev->gfx.rlc.rlc_1_iram_ucode = (u8 *)rlc_hdr +
527
+
le32_to_cpu(rlc_hdr->rlc_1_iram_ucode_offset_bytes);
528
+
adev->gfx.rlc.rlc_1_dram_ucode_size_bytes =
529
+
le32_to_cpu(rlc_hdr->rlc_1_dram_ucode_size_bytes);
530
+
adev->gfx.rlc.rlc_1_dram_ucode = (u8 *)rlc_hdr +
531
+
le32_to_cpu(rlc_hdr->rlc_1_dram_ucode_offset_bytes);
532
+
533
+
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
534
+
if (adev->gfx.rlc.rlc_1_iram_ucode_size_bytes) {
535
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_IRAM_1];
536
+
info->ucode_id = AMDGPU_UCODE_ID_RLC_IRAM_1;
537
+
info->fw = adev->gfx.rlc_fw;
538
+
adev->firmware.fw_size +=
539
+
ALIGN(adev->gfx.rlc.rlc_1_iram_ucode_size_bytes, PAGE_SIZE);
540
+
}
541
+
542
+
if (adev->gfx.rlc.rlc_1_dram_ucode_size_bytes) {
543
+
info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_DRAM_1];
544
+
info->ucode_id = AMDGPU_UCODE_ID_RLC_DRAM_1;
545
+
info->fw = adev->gfx.rlc_fw;
546
+
adev->firmware.fw_size +=
547
+
ALIGN(adev->gfx.rlc.rlc_1_dram_ucode_size_bytes, PAGE_SIZE);
548
+
}
549
+
}
550
+
}
551
+
518
552
int amdgpu_gfx_rlc_init_microcode(struct amdgpu_device *adev,
519
553
uint16_t version_major,
520
554
uint16_t version_minor)
···
579
545
amdgpu_gfx_rlc_init_microcode_v2_3(adev);
580
546
if (version_minor == 4)
581
547
amdgpu_gfx_rlc_init_microcode_v2_4(adev);
582
-
548
+
if (version_minor == 5)
549
+
amdgpu_gfx_rlc_init_microcode_v2_5(adev);
583
550
return 0;
584
551
}
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
+4
drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
···
311
311
u32 save_restore_list_srm_size_bytes;
312
312
u32 rlc_iram_ucode_size_bytes;
313
313
u32 rlc_dram_ucode_size_bytes;
314
+
u32 rlc_1_iram_ucode_size_bytes;
315
+
u32 rlc_1_dram_ucode_size_bytes;
314
316
u32 rlcp_ucode_size_bytes;
315
317
u32 rlcv_ucode_size_bytes;
316
318
u32 global_tap_delays_ucode_size_bytes;
···
328
326
u8 *save_restore_list_srm;
329
327
u8 *rlc_iram_ucode;
330
328
u8 *rlc_dram_ucode;
329
+
u8 *rlc_1_iram_ucode;
330
+
u8 *rlc_1_dram_ucode;
331
331
u8 *rlcp_ucode;
332
332
u8 *rlcv_ucode;
333
333
u8 *global_tap_delays_ucode;
+34
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
+34
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.c
···
166
166
container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_3, v2_2);
167
167
const struct rlc_firmware_header_v2_4 *rlc_hdr_v2_4 =
168
168
container_of(rlc_hdr_v2_3, struct rlc_firmware_header_v2_4, v2_3);
169
+
const struct rlc_firmware_header_v2_5 *rlc_hdr_v2_5 =
170
+
container_of(rlc_hdr_v2_2, struct rlc_firmware_header_v2_5, v2_2);
169
171
170
172
switch (version_minor) {
171
173
case 0:
···
288
286
le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_size_bytes));
289
287
DRM_DEBUG("se3_tap_delays_ucode_offset_bytes: %u\n",
290
288
le32_to_cpu(rlc_hdr_v2_4->se3_tap_delays_ucode_offset_bytes));
289
+
break;
290
+
case 5:
291
+
/* rlc_hdr v2_5 */
292
+
DRM_INFO("rlc_iram_ucode_size_bytes: %u\n",
293
+
le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_size_bytes));
294
+
DRM_INFO("rlc_iram_ucode_offset_bytes: %u\n",
295
+
le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_iram_ucode_offset_bytes));
296
+
DRM_INFO("rlc_dram_ucode_size_bytes: %u\n",
297
+
le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_size_bytes));
298
+
DRM_INFO("rlc_dram_ucode_offset_bytes: %u\n",
299
+
le32_to_cpu(rlc_hdr_v2_5->v2_2.rlc_dram_ucode_offset_bytes));
300
+
/* rlc_hdr v2_5 */
301
+
DRM_INFO("rlc_1_iram_ucode_size_bytes: %u\n",
302
+
le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_size_bytes));
303
+
DRM_INFO("rlc_1_iram_ucode_offset_bytes: %u\n",
304
+
le32_to_cpu(rlc_hdr_v2_5->rlc_1_iram_ucode_offset_bytes));
305
+
DRM_INFO("rlc_1_dram_ucode_size_bytes: %u\n",
306
+
le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_size_bytes));
307
+
DRM_INFO("rlc_1_dram_ucode_offset_bytes: %u\n",
308
+
le32_to_cpu(rlc_hdr_v2_5->rlc_1_dram_ucode_offset_bytes));
291
309
break;
292
310
default:
293
311
DRM_ERROR("Unknown RLC v2 ucode: v2.%u\n", version_minor);
···
653
631
return "RLC_IRAM";
654
632
case AMDGPU_UCODE_ID_RLC_DRAM:
655
633
return "RLC_DRAM";
634
+
case AMDGPU_UCODE_ID_RLC_IRAM_1:
635
+
return "RLC_IRAM_1";
636
+
case AMDGPU_UCODE_ID_RLC_DRAM_1:
637
+
return "RLC_DRAM_1";
656
638
case AMDGPU_UCODE_ID_RLC_G:
657
639
return "RLC_G";
658
640
case AMDGPU_UCODE_ID_RLC_P:
···
936
910
case AMDGPU_UCODE_ID_RLC_DRAM:
937
911
ucode->ucode_size = adev->gfx.rlc.rlc_dram_ucode_size_bytes;
938
912
ucode_addr = adev->gfx.rlc.rlc_dram_ucode;
913
+
break;
914
+
case AMDGPU_UCODE_ID_RLC_IRAM_1:
915
+
ucode->ucode_size = adev->gfx.rlc.rlc_1_iram_ucode_size_bytes;
916
+
ucode_addr = adev->gfx.rlc.rlc_1_iram_ucode;
917
+
break;
918
+
case AMDGPU_UCODE_ID_RLC_DRAM_1:
919
+
ucode->ucode_size = adev->gfx.rlc.rlc_1_dram_ucode_size_bytes;
920
+
ucode_addr = adev->gfx.rlc.rlc_1_dram_ucode;
939
921
break;
940
922
case AMDGPU_UCODE_ID_RLC_P:
941
923
ucode->ucode_size = adev->gfx.rlc.rlcp_ucode_size_bytes;
+12
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
+12
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
···
300
300
uint32_t se3_tap_delays_ucode_offset_bytes;
301
301
};
302
302
303
+
/* version_major=2, version_minor=5 */
304
+
struct rlc_firmware_header_v2_5 {
305
+
struct rlc_firmware_header_v2_2 v2_2;
306
+
uint32_t rlc_1_iram_ucode_size_bytes;
307
+
uint32_t rlc_1_iram_ucode_offset_bytes;
308
+
uint32_t rlc_1_dram_ucode_size_bytes;
309
+
uint32_t rlc_1_dram_ucode_offset_bytes;
310
+
};
311
+
303
312
/* version_major=1, version_minor=0 */
304
313
struct sdma_firmware_header_v1_0 {
305
314
struct common_firmware_header header;
···
458
449
struct rlc_firmware_header_v2_2 rlc_v2_2;
459
450
struct rlc_firmware_header_v2_3 rlc_v2_3;
460
451
struct rlc_firmware_header_v2_4 rlc_v2_4;
452
+
struct rlc_firmware_header_v2_5 rlc_v2_5;
461
453
struct sdma_firmware_header_v1_0 sdma;
462
454
struct sdma_firmware_header_v1_1 sdma_v1_1;
463
455
struct sdma_firmware_header_v2_0 sdma_v2_0;
···
522
512
AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
523
513
AMDGPU_UCODE_ID_RLC_IRAM,
524
514
AMDGPU_UCODE_ID_RLC_DRAM,
515
+
AMDGPU_UCODE_ID_RLC_IRAM_1,
516
+
AMDGPU_UCODE_ID_RLC_DRAM_1,
525
517
AMDGPU_UCODE_ID_RLC_P,
526
518
AMDGPU_UCODE_ID_RLC_V,
527
519
AMDGPU_UCODE_ID_RLC_G,
+2
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
+2
drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h
···
299
299
GFX_FW_TYPE_RS64_MEC_P1_STACK = 95, /* RS64 MEC stack P1 SOC21 */
300
300
GFX_FW_TYPE_RS64_MEC_P2_STACK = 96, /* RS64 MEC stack P2 SOC21 */
301
301
GFX_FW_TYPE_RS64_MEC_P3_STACK = 97, /* RS64 MEC stack P3 SOC21 */
302
+
GFX_FW_TYPE_RLX6_UCODE_CORE1 = 98, /* RLCV_IRAM MI */
303
+
GFX_FW_TYPE_RLX6_DRAM_BOOT_CORE1 = 99, /* RLCV DRAM BOOT MI */
302
304
GFX_FW_TYPE_VPEC_FW1 = 100, /* VPEC FW1 To Save VPE */
303
305
GFX_FW_TYPE_VPEC_FW2 = 101, /* VPEC FW2 To Save VPE */
304
306
GFX_FW_TYPE_VPE = 102,