Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
serial: 8250_exar: Kill unneeded ->board_init()
We may reuse ->setup() for the same purpose as it was done before.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: Parker Newman <pnewman@connecttech.com>
Link: https://lore.kernel.org/r/20240503171917.2921250-8-andriy.shevchenko@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
authored by
Andy Shevchenko
and committed by
Greg Kroah-Hartman
709bb045
c5f59747
+81
-90
+81
-90
drivers/tty/serial/8250/8250_exar.c
+81
-90
drivers/tty/serial/8250/8250_exar.c
···
237
237
* struct exar8250_board - board information
238
238
* @num_ports: number of serial ports
239
239
* @reg_shift: describes UART register mapping in PCI memory
240
-
* @board_init: quirk run once at ->probe() stage before setting up ports
241
240
* @setup: quirk run at ->probe() stage for each port
242
241
* @exit: quirk run at ->remove() stage
243
242
*/
244
243
struct exar8250_board {
245
244
unsigned int num_ports;
246
245
unsigned int reg_shift;
247
-
int (*board_init)(struct exar8250 *priv, struct pci_dev *pcidev);
248
246
int (*setup)(struct exar8250 *priv, struct pci_dev *pcidev,
249
247
struct uart_8250_port *port, int idx);
250
248
void (*exit)(struct pci_dev *pcidev);
···
905
907
{
906
908
int ret;
907
909
908
-
if (priv->osc_freq == 0)
909
-
return -EINVAL;
910
-
911
910
port->port.port_id = idx;
912
911
port->port.uartclk = priv->osc_freq;
913
912
···
922
927
return 0;
923
928
}
924
929
930
+
static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcidev)
931
+
{
932
+
int ret;
933
+
u16 cfg_val;
934
+
935
+
// FPGA OSC is fixed to the 33MHz PCI clock
936
+
priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ;
937
+
938
+
// Enable external interrupts in special cfg space register
939
+
ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val);
940
+
if (ret)
941
+
return pcibios_err_to_errno(ret);
942
+
943
+
cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT;
944
+
ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val);
945
+
if (ret)
946
+
return pcibios_err_to_errno(ret);
947
+
948
+
// RS485 gate needs to be enabled; otherwise RTS/CTS will not work
949
+
exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01);
950
+
951
+
return 0;
952
+
}
953
+
925
954
static int cti_port_setup_fpga(struct exar8250 *priv,
926
955
struct pci_dev *pcidev,
927
956
struct uart_8250_port *port,
···
953
934
{
954
935
enum cti_port_type port_type;
955
936
unsigned int offset;
937
+
int ret;
938
+
939
+
if (idx == 0) {
940
+
ret = cti_board_init_fpga(priv, pcidev);
941
+
if (ret)
942
+
return ret;
943
+
}
956
944
957
945
port_type = cti_get_port_type_fpga(priv, pcidev, idx);
958
946
···
979
953
return cti_port_setup_common(priv, pcidev, idx, offset, port);
980
954
}
981
955
956
+
static void cti_board_init_xr17v35x(struct exar8250 *priv, struct pci_dev *pcidev)
957
+
{
958
+
// XR17V35X uses the PCIe clock rather than an oscillator
959
+
priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ;
960
+
}
961
+
982
962
static int cti_port_setup_xr17v35x(struct exar8250 *priv,
983
963
struct pci_dev *pcidev,
984
964
struct uart_8250_port *port,
···
993
961
enum cti_port_type port_type;
994
962
unsigned int offset;
995
963
int ret;
964
+
965
+
if (idx == 0)
966
+
cti_board_init_xr17v35x(priv, pcidev);
996
967
997
968
port_type = cti_get_port_type_xr17v35x(priv, pcidev, idx);
998
969
···
1034
999
return 0;
1035
1000
}
1036
1001
1002
+
static void cti_board_init_xr17v25x(struct exar8250 *priv, struct pci_dev *pcidev)
1003
+
{
1004
+
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17V25X_OSC_FREQ);
1005
+
1006
+
/* enable interrupts on cards that need the "PLX fix" */
1007
+
switch (pcidev->subsystem_device) {
1008
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
1009
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
1010
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
1011
+
cti_plx_int_enable(priv);
1012
+
break;
1013
+
default:
1014
+
break;
1015
+
}
1016
+
}
1017
+
1037
1018
static int cti_port_setup_xr17v25x(struct exar8250 *priv,
1038
1019
struct pci_dev *pcidev,
1039
1020
struct uart_8250_port *port,
···
1058
1007
enum cti_port_type port_type;
1059
1008
unsigned int offset;
1060
1009
int ret;
1010
+
1011
+
if (idx == 0)
1012
+
cti_board_init_xr17v25x(priv, pcidev);
1061
1013
1062
1014
port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
1063
1015
···
1109
1055
return 0;
1110
1056
}
1111
1057
1058
+
static void cti_board_init_xr17c15x(struct exar8250 *priv, struct pci_dev *pcidev)
1059
+
{
1060
+
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17C15X_OSC_FREQ);
1061
+
1062
+
/* enable interrupts on cards that need the "PLX fix" */
1063
+
switch (pcidev->subsystem_device) {
1064
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
1065
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
1066
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
1067
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
1068
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
1069
+
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
1070
+
cti_plx_int_enable(priv);
1071
+
break;
1072
+
default:
1073
+
break;
1074
+
}
1075
+
}
1076
+
1112
1077
static int cti_port_setup_xr17c15x(struct exar8250 *priv,
1113
1078
struct pci_dev *pcidev,
1114
1079
struct uart_8250_port *port,
···
1135
1062
{
1136
1063
enum cti_port_type port_type;
1137
1064
unsigned int offset;
1065
+
1066
+
if (idx == 0)
1067
+
cti_board_init_xr17c15x(priv, pcidev);
1138
1068
1139
1069
port_type = cti_get_port_type_xr17c15x_xr17v25x(priv, pcidev, idx);
1140
1070
···
1170
1094
}
1171
1095
1172
1096
return cti_port_setup_common(priv, pcidev, idx, offset, port);
1173
-
}
1174
-
1175
-
static int cti_board_init_xr17v35x(struct exar8250 *priv,
1176
-
struct pci_dev *pcidev)
1177
-
{
1178
-
// XR17V35X uses the PCIe clock rather than an oscillator
1179
-
priv->osc_freq = CTI_DEFAULT_PCIE_OSC_FREQ;
1180
-
1181
-
return 0;
1182
-
}
1183
-
1184
-
static int cti_board_init_xr17v25x(struct exar8250 *priv, struct pci_dev *pcidev)
1185
-
{
1186
-
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17V25X_OSC_FREQ);
1187
-
1188
-
/* enable interrupts on cards that need the "PLX fix" */
1189
-
switch (pcidev->subsystem_device) {
1190
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_XPRS:
1191
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_A:
1192
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_16_XPRS_B:
1193
-
cti_plx_int_enable(priv);
1194
-
break;
1195
-
default:
1196
-
break;
1197
-
}
1198
-
1199
-
return 0;
1200
-
}
1201
-
1202
-
static int cti_board_init_xr17c15x(struct exar8250 *priv, struct pci_dev *pcidev)
1203
-
{
1204
-
cti_board_init_osc_freq(priv, pcidev, CTI_EE_OFF_XR17C15X_OSC_FREQ);
1205
-
1206
-
/* enable interrupts on cards that need the "PLX fix" */
1207
-
switch (pcidev->subsystem_device) {
1208
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS:
1209
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_A:
1210
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_B:
1211
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_XPRS_OPTO:
1212
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_A:
1213
-
case PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_XPRS_OPTO_B:
1214
-
cti_plx_int_enable(priv);
1215
-
break;
1216
-
default:
1217
-
break;
1218
-
}
1219
-
1220
-
return 0;
1221
-
}
1222
-
1223
-
static int cti_board_init_fpga(struct exar8250 *priv, struct pci_dev *pcidev)
1224
-
{
1225
-
int ret;
1226
-
u16 cfg_val;
1227
-
1228
-
// FPGA OSC is fixed to the 33MHz PCI clock
1229
-
priv->osc_freq = CTI_DEFAULT_FPGA_OSC_FREQ;
1230
-
1231
-
// Enable external interrupts in special cfg space register
1232
-
ret = pci_read_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, &cfg_val);
1233
-
if (ret)
1234
-
return pcibios_err_to_errno(ret);
1235
-
1236
-
cfg_val |= CTI_FPGA_CFG_INT_EN_EXT_BIT;
1237
-
ret = pci_write_config_word(pcidev, CTI_FPGA_CFG_INT_EN_REG, cfg_val);
1238
-
if (ret)
1239
-
return pcibios_err_to_errno(ret);
1240
-
1241
-
// RS485 gate needs to be enabled; otherwise RTS/CTS will not work
1242
-
exar_write_reg(priv, CTI_FPGA_RS485_IO_REG, 0x01);
1243
-
1244
-
return 0;
1245
1097
}
1246
1098
1247
1099
static int
···
1578
1574
if (rc)
1579
1575
return rc;
1580
1576
1581
-
if (board->board_init) {
1582
-
rc = board->board_init(priv, pcidev);
1583
-
if (rc) {
1584
-
dev_err_probe(&pcidev->dev, rc,
1585
-
"failed to init serial board\n");
1586
-
return rc;
1587
-
}
1588
-
}
1589
-
1590
1577
for (i = 0; i < nr_ports && i < maxnr; i++) {
1591
1578
rc = board->setup(priv, pcidev, &uart, i);
1592
1579
if (rc) {
···
1659
1664
};
1660
1665
1661
1666
static const struct exar8250_board pbn_cti_xr17c15x = {
1662
-
.board_init = cti_board_init_xr17c15x,
1663
1667
.setup = cti_port_setup_xr17c15x,
1664
1668
};
1665
1669
1666
1670
static const struct exar8250_board pbn_cti_xr17v25x = {
1667
-
.board_init = cti_board_init_xr17v25x,
1668
1671
.setup = cti_port_setup_xr17v25x,
1669
1672
};
1670
1673
1671
1674
static const struct exar8250_board pbn_cti_xr17v35x = {
1672
-
.board_init = cti_board_init_xr17v35x,
1673
1675
.setup = cti_port_setup_xr17v35x,
1674
1676
};
1675
1677
1676
1678
static const struct exar8250_board pbn_cti_fpga = {
1677
-
.board_init = cti_board_init_fpga,
1678
1679
.setup = cti_port_setup_fpga,
1679
1680
};
1680
1681