Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'renesas-arm-dt-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt
Renesas ARM DT updates for v5.19
- ADC, SDHI, CAN-FD, I2C, QSPI, timer, watchdog, sound, USB, SPI, GPU,
cpufreq, and thermal support for the RZ/V2L SoC, and the RZ/V2L
SMARC EVK development board,
- USB, I2C, Audio, NOR Flash, timer, SPI support for RZ/G2LC SMARC EVK
development board,
- Can-FD support for the R-Car M30W+ and V3U SoCs, and the Falcon
development board,
- I2C and GPIO support for the R-Car S4-8 SoC,
- I2C EEPROM support for the Falcon development board,
- SPI Multi I/O Bus Controller (RPC-IF) support for the R-Car H3,
M3-W(+), M3-N, E3, and D3 SoCs,
- RPC HyperFlash support for the Draak, Ebisu, Salvator-X(S), and ULCB
development boards,
- Initial support (UART, DMAC, pin control, SDHI, eMMC, Ethernet) for
the RZ/G2UL SoC, and the RZ/G2UL SMARC EVK development board,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.19-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (55 commits)
ARM: dts: r9a06g032: Drop "arm,cortex-a7-timer" from timer node
arm64: dts: renesas: r8a779f0: Add GPIO nodes
arm64: dts: renesas: rzg2ul-smarc-som: Enable Ethernet on SMARC platform
arm64: dts: renesas: rzg2ul-smarc-som: Enable eMMC on SMARC platform
arm64: dts: renesas: rzg2ul-smarc: Enable microSD on SMARC platform
arm64: dts: renesas: r9a07g043: Add GbEthernet nodes
arm64: dts: renesas: r9a07g043: Add SDHI nodes
arm64: dts: renesas: rzg2ul-smarc: Add scif0 and audio clk pins
arm64: dts: renesas: r9a07g043: Fillup the pinctrl stub node
arm64: dts: renesas: Add initial device tree for RZ/G2UL Type-1 SMARC EVK
arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC
arm64: dts: renesas: rzg2l-smarc: Move gpios property of vccq_sdhi1 from common dtsi
arm64: dts: renesas: rzg2lc-smarc: Enable RSPI1 on carrier board
arm64: dts: renesas: ulcb: Add RPC HyperFlash device node
arm64: dts: renesas: salvator-common: Add RPC HyperFlash device node
arm64: dts: renesas: ebisu: Add RPC HyperFlash device node
arm64: dts: renesas: draak: Add RPC HyperFlash device node
arm64: dts: renesas: rcar-gen3: Add RPC device nodes
arm64: dts: renesas: rcar-gen4: Add interrupt properties to watchdog nodes
arm64: dts: renesas: rzg2: Add interrupt properties to watchdog nodes
...
Link: https://lore.kernel.org/r/cover.1650638505.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
+2457
-141
+1
arch/arm/boot/dts/r8a7743.dtsi
+1
arch/arm/boot/dts/r8a7743.dtsi
+1
arch/arm/boot/dts/r8a7744.dtsi
+1
arch/arm/boot/dts/r8a7744.dtsi
+1
arch/arm/boot/dts/r8a7745.dtsi
+1
arch/arm/boot/dts/r8a7745.dtsi
+1
arch/arm/boot/dts/r8a77470.dtsi
+1
arch/arm/boot/dts/r8a77470.dtsi
+1
arch/arm/boot/dts/r8a7790.dtsi
+1
arch/arm/boot/dts/r8a7790.dtsi
+1
arch/arm/boot/dts/r8a7791.dtsi
+1
arch/arm/boot/dts/r8a7791.dtsi
+1
arch/arm/boot/dts/r8a7792.dtsi
+1
arch/arm/boot/dts/r8a7792.dtsi
+1
arch/arm/boot/dts/r8a7793.dtsi
+1
arch/arm/boot/dts/r8a7793.dtsi
+1
arch/arm/boot/dts/r8a7794.dtsi
+1
arch/arm/boot/dts/r8a7794.dtsi
+1
-2
arch/arm/boot/dts/r9a06g032.dtsi
+1
-2
arch/arm/boot/dts/r9a06g032.dtsi
+2
arch/arm64/boot/dts/renesas/Makefile
+2
arch/arm64/boot/dts/renesas/Makefile
+58
arch/arm64/boot/dts/renesas/draak.dtsi
+58
arch/arm64/boot/dts/renesas/draak.dtsi
···
541
541
function = "pwm1";
542
542
};
543
543
544
+
rpc_pins: rpc {
545
+
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
546
+
"rpc_int";
547
+
function = "rpc";
548
+
};
549
+
544
550
scif2_pins: scif2 {
545
551
groups = "scif2_data";
546
552
function = "scif2";
···
631
625
frame-master = <&rsnd_for_ak4613>;
632
626
playback = <&ssi3>, <&src5>, <&dvc0>;
633
627
capture = <&ssi4>, <&src6>, <&dvc1>;
628
+
};
629
+
};
630
+
};
631
+
};
632
+
633
+
&rpc {
634
+
pinctrl-0 = <&rpc_pins>;
635
+
pinctrl-names = "default";
636
+
637
+
/* Left disabled. To be enabled by firmware when unlocked. */
638
+
639
+
flash@0 {
640
+
compatible = "cypress,hyperflash", "cfi-flash";
641
+
reg = <0>;
642
+
643
+
partitions {
644
+
compatible = "fixed-partitions";
645
+
#address-cells = <1>;
646
+
#size-cells = <1>;
647
+
648
+
bootparam@0 {
649
+
reg = <0x00000000 0x040000>;
650
+
read-only;
651
+
};
652
+
bl2@40000 {
653
+
reg = <0x00040000 0x140000>;
654
+
read-only;
655
+
};
656
+
cert_header_sa6@180000 {
657
+
reg = <0x00180000 0x040000>;
658
+
read-only;
659
+
};
660
+
bl31@1c0000 {
661
+
reg = <0x001c0000 0x040000>;
662
+
read-only;
663
+
};
664
+
tee@200000 {
665
+
reg = <0x00200000 0x440000>;
666
+
read-only;
667
+
};
668
+
uboot@640000 {
669
+
reg = <0x00640000 0x100000>;
670
+
read-only;
671
+
};
672
+
dtb@740000 {
673
+
reg = <0x00740000 0x080000>;
674
+
};
675
+
kernel@7c0000 {
676
+
reg = <0x007c0000 0x1400000>;
677
+
};
678
+
user@1bc0000 {
679
+
reg = <0x01bc0000 0x2440000>;
634
680
};
635
681
};
636
682
};
+58
arch/arm64/boot/dts/renesas/ebisu.dtsi
+58
arch/arm64/boot/dts/renesas/ebisu.dtsi
···
600
600
function = "pwm5";
601
601
};
602
602
603
+
rpc_pins: rpc {
604
+
groups = "rpc_clk2", "rpc_ctrl", "rpc_data", "rpc_reset",
605
+
"rpc_int";
606
+
function = "rpc";
607
+
};
608
+
603
609
scif2_pins: scif2 {
604
610
groups = "scif2_data_a";
605
611
function = "scif2";
···
715
709
};
716
710
};
717
711
712
+
};
713
+
714
+
&rpc {
715
+
pinctrl-0 = <&rpc_pins>;
716
+
pinctrl-names = "default";
717
+
718
+
/* Left disabled. To be enabled by firmware when unlocked. */
719
+
720
+
flash@0 {
721
+
compatible = "cypress,hyperflash", "cfi-flash";
722
+
reg = <0>;
723
+
724
+
partitions {
725
+
compatible = "fixed-partitions";
726
+
#address-cells = <1>;
727
+
#size-cells = <1>;
728
+
729
+
bootparam@0 {
730
+
reg = <0x00000000 0x040000>;
731
+
read-only;
732
+
};
733
+
bl2@40000 {
734
+
reg = <0x00040000 0x140000>;
735
+
read-only;
736
+
};
737
+
cert_header_sa6@180000 {
738
+
reg = <0x00180000 0x040000>;
739
+
read-only;
740
+
};
741
+
bl31@1c0000 {
742
+
reg = <0x001c0000 0x040000>;
743
+
read-only;
744
+
};
745
+
tee@200000 {
746
+
reg = <0x00200000 0x440000>;
747
+
read-only;
748
+
};
749
+
uboot@640000 {
750
+
reg = <0x00640000 0x100000>;
751
+
read-only;
752
+
};
753
+
dtb@740000 {
754
+
reg = <0x00740000 0x080000>;
755
+
};
756
+
kernel@7c0000 {
757
+
reg = <0x007c0000 0x1400000>;
758
+
};
759
+
user@1bc0000 {
760
+
reg = <0x01bc0000 0x2440000>;
761
+
};
762
+
};
763
+
};
718
764
};
719
765
720
766
&rwdt {
+1
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+1
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+1
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+1
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+1
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+1
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+17
arch/arm64/boot/dts/renesas/r8a77951.dtsi
+17
arch/arm64/boot/dts/renesas/r8a77951.dtsi
···
369
369
rwdt: watchdog@e6020000 {
370
370
compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
371
371
reg = <0 0xe6020000 0 0x0c>;
372
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
372
373
clocks = <&cpg CPG_MOD 402>;
373
374
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
374
375
resets = <&cpg 402>;
···
2729
2728
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2730
2729
resets = <&cpg 311>;
2731
2730
iommus = <&ipmmu_ds1 35>;
2731
+
status = "disabled";
2732
+
};
2733
+
2734
+
rpc: spi@ee200000 {
2735
+
compatible = "renesas,r8a7795-rpc-if",
2736
+
"renesas,rcar-gen3-rpc-if";
2737
+
reg = <0 0xee200000 0 0x200>,
2738
+
<0 0x08000000 0 0x04000000>,
2739
+
<0 0xee208000 0 0x100>;
2740
+
reg-names = "regs", "dirmap", "wbuf";
2741
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2742
+
clocks = <&cpg CPG_MOD 917>;
2743
+
power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
2744
+
resets = <&cpg 917>;
2745
+
#address-cells = <1>;
2746
+
#size-cells = <0>;
2732
2747
status = "disabled";
2733
2748
};
2734
2749
+17
arch/arm64/boot/dts/renesas/r8a77960.dtsi
+17
arch/arm64/boot/dts/renesas/r8a77960.dtsi
···
334
334
compatible = "renesas,r8a7796-wdt",
335
335
"renesas,rcar-gen3-wdt";
336
336
reg = <0 0xe6020000 0 0x0c>;
337
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
337
338
clocks = <&cpg CPG_MOD 402>;
338
339
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
339
340
resets = <&cpg 402>;
···
2529
2528
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2530
2529
resets = <&cpg 311>;
2531
2530
iommus = <&ipmmu_ds1 35>;
2531
+
status = "disabled";
2532
+
};
2533
+
2534
+
rpc: spi@ee200000 {
2535
+
compatible = "renesas,r8a7796-rpc-if",
2536
+
"renesas,rcar-gen3-rpc-if";
2537
+
reg = <0 0xee200000 0 0x200>,
2538
+
<0 0x08000000 0 0x04000000>,
2539
+
<0 0xee208000 0 0x100>;
2540
+
reg-names = "regs", "dirmap", "wbuf";
2541
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2542
+
clocks = <&cpg CPG_MOD 917>;
2543
+
power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
2544
+
resets = <&cpg 917>;
2545
+
#address-cells = <1>;
2546
+
#size-cells = <0>;
2532
2547
status = "disabled";
2533
2548
};
2534
2549
+42
arch/arm64/boot/dts/renesas/r8a77961.dtsi
+42
arch/arm64/boot/dts/renesas/r8a77961.dtsi
···
323
323
compatible = "renesas,r8a77961-wdt",
324
324
"renesas,rcar-gen3-wdt";
325
325
reg = <0 0xe6020000 0 0x0c>;
326
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
326
327
clocks = <&cpg CPG_MOD 402>;
327
328
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
328
329
resets = <&cpg 402>;
···
1221
1220
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1222
1221
resets = <&cpg 915>;
1223
1222
status = "disabled";
1223
+
};
1224
+
1225
+
canfd: can@e66c0000 {
1226
+
compatible = "renesas,r8a77961-canfd",
1227
+
"renesas,rcar-gen3-canfd";
1228
+
reg = <0 0xe66c0000 0 0x8000>;
1229
+
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
1230
+
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1231
+
clocks = <&cpg CPG_MOD 914>,
1232
+
<&cpg CPG_CORE R8A77961_CLK_CANFD>,
1233
+
<&can_clk>;
1234
+
clock-names = "fck", "canfd", "can_clk";
1235
+
assigned-clocks = <&cpg CPG_CORE R8A77961_CLK_CANFD>;
1236
+
assigned-clock-rates = <40000000>;
1237
+
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
1238
+
resets = <&cpg 914>;
1239
+
status = "disabled";
1240
+
1241
+
channel0 {
1242
+
status = "disabled";
1243
+
};
1244
+
1245
+
channel1 {
1246
+
status = "disabled";
1247
+
};
1224
1248
};
1225
1249
1226
1250
pwm0: pwm@e6e30000 {
···
2398
2372
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2399
2373
resets = <&cpg 311>;
2400
2374
iommus = <&ipmmu_ds1 35>;
2375
+
status = "disabled";
2376
+
};
2377
+
2378
+
rpc: spi@ee200000 {
2379
+
compatible = "renesas,r8a77961-rpc-if",
2380
+
"renesas,rcar-gen3-rpc-if";
2381
+
reg = <0 0xee200000 0 0x200>,
2382
+
<0 0x08000000 0 0x04000000>,
2383
+
<0 0xee208000 0 0x100>;
2384
+
reg-names = "regs", "dirmap", "wbuf";
2385
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2386
+
clocks = <&cpg CPG_MOD 917>;
2387
+
power-domains = <&sysc R8A77961_PD_ALWAYS_ON>;
2388
+
resets = <&cpg 917>;
2389
+
#address-cells = <1>;
2390
+
#size-cells = <0>;
2401
2391
status = "disabled";
2402
2392
};
2403
2393
+17
arch/arm64/boot/dts/renesas/r8a77965.dtsi
+17
arch/arm64/boot/dts/renesas/r8a77965.dtsi
···
205
205
compatible = "renesas,r8a77965-wdt",
206
206
"renesas,rcar-gen3-wdt";
207
207
reg = <0 0xe6020000 0 0x0c>;
208
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
208
209
clocks = <&cpg CPG_MOD 402>;
209
210
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
210
211
resets = <&cpg 402>;
···
2376
2375
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2377
2376
resets = <&cpg 311>;
2378
2377
iommus = <&ipmmu_ds1 35>;
2378
+
status = "disabled";
2379
+
};
2380
+
2381
+
rpc: spi@ee200000 {
2382
+
compatible = "renesas,r8a77965-rpc-if",
2383
+
"renesas,rcar-gen3-rpc-if";
2384
+
reg = <0 0xee200000 0 0x200>,
2385
+
<0 0x08000000 0 0x04000000>,
2386
+
<0 0xee208000 0 0x100>;
2387
+
reg-names = "regs", "dirmap", "wbuf";
2388
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2389
+
clocks = <&cpg CPG_MOD 917>;
2390
+
power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
2391
+
resets = <&cpg 917>;
2392
+
#address-cells = <1>;
2393
+
#size-cells = <0>;
2379
2394
status = "disabled";
2380
2395
};
2381
2396
+1
arch/arm64/boot/dts/renesas/r8a77970.dtsi
+1
arch/arm64/boot/dts/renesas/r8a77970.dtsi
+1
arch/arm64/boot/dts/renesas/r8a77980.dtsi
+1
arch/arm64/boot/dts/renesas/r8a77980.dtsi
+17
arch/arm64/boot/dts/renesas/r8a77990.dtsi
+17
arch/arm64/boot/dts/renesas/r8a77990.dtsi
···
171
171
compatible = "renesas,r8a77990-wdt",
172
172
"renesas,rcar-gen3-wdt";
173
173
reg = <0 0xe6020000 0 0x0c>;
174
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
174
175
clocks = <&cpg CPG_MOD 402>;
175
176
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
176
177
resets = <&cpg 402>;
···
1835
1834
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1836
1835
resets = <&cpg 311>;
1837
1836
iommus = <&ipmmu_ds1 35>;
1837
+
status = "disabled";
1838
+
};
1839
+
1840
+
rpc: spi@ee200000 {
1841
+
compatible = "renesas,r8a77990-rpc-if",
1842
+
"renesas,rcar-gen3-rpc-if";
1843
+
reg = <0 0xee200000 0 0x200>,
1844
+
<0 0x08000000 0 0x04000000>,
1845
+
<0 0xee208000 0 0x100>;
1846
+
reg-names = "regs", "dirmap", "wbuf";
1847
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1848
+
clocks = <&cpg CPG_MOD 917>;
1849
+
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
1850
+
resets = <&cpg 917>;
1851
+
#address-cells = <1>;
1852
+
#size-cells = <0>;
1838
1853
status = "disabled";
1839
1854
};
1840
1855
+17
arch/arm64/boot/dts/renesas/r8a77995.dtsi
+17
arch/arm64/boot/dts/renesas/r8a77995.dtsi
···
94
94
compatible = "renesas,r8a77995-wdt",
95
95
"renesas,rcar-gen3-wdt";
96
96
reg = <0 0xe6020000 0 0x0c>;
97
+
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
97
98
clocks = <&cpg CPG_MOD 402>;
98
99
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
99
100
resets = <&cpg 402>;
···
1235
1234
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1236
1235
resets = <&cpg 312>;
1237
1236
iommus = <&ipmmu_ds1 34>;
1237
+
status = "disabled";
1238
+
};
1239
+
1240
+
rpc: spi@ee200000 {
1241
+
compatible = "renesas,r8a77995-rpc-if",
1242
+
"renesas,rcar-gen3-rpc-if";
1243
+
reg = <0 0xee200000 0 0x200>,
1244
+
<0 0x08000000 0 0x04000000>,
1245
+
<0 0xee208000 0 0x100>;
1246
+
reg-names = "regs", "dirmap", "wbuf";
1247
+
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1248
+
clocks = <&cpg CPG_MOD 917>;
1249
+
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
1250
+
resets = <&cpg 917>;
1251
+
#address-cells = <1>;
1252
+
#size-cells = <0>;
1238
1253
status = "disabled";
1239
1254
};
1240
1255
+10
-2
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
+10
-2
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
···
192
192
clock-frequency = <400000>;
193
193
194
194
bridge@2c {
195
+
pinctrl-0 = <&irq0_pins>;
196
+
pinctrl-names = "default";
197
+
195
198
compatible = "ti,sn65dsi86";
196
199
reg = <0x2c>;
197
200
198
201
clocks = <&sn65dsi86_refclk>;
199
202
clock-names = "refclk";
200
203
201
-
interrupt-parent = <&gpio1>;
202
-
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
204
+
interrupt-parent = <&intc_ex>;
205
+
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
203
206
204
207
vccio-supply = <®_1p8v>;
205
208
vpll-supply = <®_1p8v>;
···
272
269
i2c6_pins: i2c6 {
273
270
groups = "i2c6";
274
271
function = "i2c6";
272
+
};
273
+
274
+
irq0_pins: irq0 {
275
+
groups = "intc_ex_irq0";
276
+
function = "intc_ex";
275
277
};
276
278
277
279
keys_pins: keys {
+24
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
+24
arch/arm64/boot/dts/renesas/r8a779a0-falcon.dts
···
37
37
};
38
38
};
39
39
40
+
&canfd {
41
+
pinctrl-0 = <&canfd0_pins>, <&canfd1_pins>;
42
+
pinctrl-names = "default";
43
+
status = "okay";
44
+
45
+
channel0 {
46
+
status = "okay";
47
+
};
48
+
49
+
channel1 {
50
+
status = "okay";
51
+
};
52
+
};
53
+
40
54
&i2c0 {
41
55
eeprom@51 {
42
56
compatible = "rohm,br24g01", "atmel,24c01";
···
78
64
drive-strength = <21>;
79
65
};
80
66
67
+
};
68
+
69
+
canfd0_pins: canfd0 {
70
+
groups = "canfd0_data";
71
+
function = "canfd0";
72
+
};
73
+
74
+
canfd1_pins: canfd1 {
75
+
groups = "canfd1_data";
76
+
function = "canfd1";
81
77
};
82
78
};
+57
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
+57
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
···
24
24
i2c6 = &i2c6;
25
25
};
26
26
27
+
/* External CAN clock - to be overridden by boards that provide it */
28
+
can_clk: can {
29
+
compatible = "fixed-clock";
30
+
#clock-cells = <0>;
31
+
clock-frequency = <0>;
32
+
};
33
+
27
34
cpus {
28
35
#address-cells = <1>;
29
36
#size-cells = <0>;
···
88
81
compatible = "renesas,r8a779a0-wdt",
89
82
"renesas,rcar-gen3-wdt";
90
83
reg = <0 0xe6020000 0 0x0c>;
84
+
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
91
85
clocks = <&cpg CPG_MOD 907>;
92
86
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
93
87
resets = <&cpg 907>;
···
602
594
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
603
595
resets = <&cpg 517>;
604
596
status = "disabled";
597
+
};
598
+
599
+
canfd: can@e6660000 {
600
+
compatible = "renesas,r8a779a0-canfd";
601
+
reg = <0 0xe6660000 0 0x8000>;
602
+
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
603
+
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
604
+
interrupt-names = "ch_int", "g_int";
605
+
clocks = <&cpg CPG_MOD 328>,
606
+
<&cpg CPG_CORE R8A779A0_CLK_CANFD>,
607
+
<&can_clk>;
608
+
clock-names = "fck", "canfd", "can_clk";
609
+
assigned-clocks = <&cpg CPG_CORE R8A779A0_CLK_CANFD>;
610
+
assigned-clock-rates = <80000000>;
611
+
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
612
+
resets = <&cpg 328>;
613
+
status = "disabled";
614
+
615
+
channel0 {
616
+
status = "disabled";
617
+
};
618
+
619
+
channel1 {
620
+
status = "disabled";
621
+
};
622
+
623
+
channel2 {
624
+
status = "disabled";
625
+
};
626
+
627
+
channel3 {
628
+
status = "disabled";
629
+
};
630
+
631
+
channel4 {
632
+
status = "disabled";
633
+
};
634
+
635
+
channel5 {
636
+
status = "disabled";
637
+
};
638
+
639
+
channel6 {
640
+
status = "disabled";
641
+
};
642
+
643
+
channel7 {
644
+
status = "disabled";
645
+
};
605
646
};
606
647
607
648
avb0: ethernet@e6800000 {
+20
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+20
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
···
31
31
clock-frequency = <32768>;
32
32
};
33
33
34
+
&i2c4 {
35
+
pinctrl-0 = <&i2c4_pins>;
36
+
pinctrl-names = "default";
37
+
38
+
status = "okay";
39
+
clock-frequency = <400000>;
40
+
41
+
eeprom@50 {
42
+
compatible = "rohm,br24g01", "atmel,24c01";
43
+
label = "cpu-board";
44
+
reg = <0x50>;
45
+
pagesize = <8>;
46
+
};
47
+
};
48
+
34
49
&pfc {
35
50
pinctrl-0 = <&scif_clk_pins>;
36
51
pinctrl-names = "default";
52
+
53
+
i2c4_pins: i2c4 {
54
+
groups = "i2c4";
55
+
function = "i2c4";
56
+
};
37
57
38
58
scif3_pins: scif3 {
39
59
groups = "scif3_data", "scif3_ctrl";
+15
arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
+15
arch/arm64/boot/dts/renesas/r8a779f0-spider-ethernet.dtsi
···
1
+
// SPDX-License-Identifier: GPL-2.0
2
+
/*
3
+
* Device Tree Source for the Spider Ethernet sub-board
4
+
*
5
+
* Copyright (C) 2021 Renesas Electronics Corp.
6
+
*/
7
+
8
+
&i2c4 {
9
+
eeprom@52 {
10
+
compatible = "rohm,br24g01", "atmel,24c01";
11
+
label = "ethernet-sub-board";
12
+
reg = <0x52>;
13
+
pagesize = <8>;
14
+
};
15
+
};
+10
arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
+10
arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
···
7
7
8
8
/dts-v1/;
9
9
#include "r8a779f0-spider-cpu.dtsi"
10
+
#include "r8a779f0-spider-ethernet.dtsi"
10
11
11
12
/ {
12
13
model = "Renesas Spider CPU and Breakout boards based on r8a779f0";
···
19
18
20
19
chosen {
21
20
stdout-path = "serial0:115200n8";
21
+
};
22
+
};
23
+
24
+
&i2c4 {
25
+
eeprom@51 {
26
+
compatible = "rohm,br24g01", "atmel,24c01";
27
+
label = "breakout-board";
28
+
reg = <0x51>;
29
+
pagesize = <8>;
22
30
};
23
31
};
+163
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+163
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
···
63
63
compatible = "renesas,r8a779f0-wdt",
64
64
"renesas,rcar-gen4-wdt";
65
65
reg = <0 0xe6020000 0 0x0c>;
66
+
interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>;
66
67
clocks = <&cpg CPG_MOD 907>;
67
68
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
68
69
resets = <&cpg 907>;
···
74
73
compatible = "renesas,pfc-r8a779f0";
75
74
reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>,
76
75
<0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>;
76
+
};
77
+
78
+
gpio0: gpio@e6050180 {
79
+
compatible = "renesas,gpio-r8a779f0",
80
+
"renesas,rcar-gen4-gpio";
81
+
reg = <0 0xe6050180 0 0x54>;
82
+
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>;
83
+
clocks = <&cpg CPG_MOD 915>;
84
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
85
+
resets = <&cpg 915>;
86
+
gpio-controller;
87
+
#gpio-cells = <2>;
88
+
gpio-ranges = <&pfc 0 0 21>;
89
+
interrupt-controller;
90
+
#interrupt-cells = <2>;
91
+
};
92
+
93
+
gpio1: gpio@e6050980 {
94
+
compatible = "renesas,gpio-r8a779f0",
95
+
"renesas,rcar-gen4-gpio";
96
+
reg = <0 0xe6050980 0 0x54>;
97
+
interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>;
98
+
clocks = <&cpg CPG_MOD 915>;
99
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
100
+
resets = <&cpg 915>;
101
+
gpio-controller;
102
+
#gpio-cells = <2>;
103
+
gpio-ranges = <&pfc 0 32 25>;
104
+
interrupt-controller;
105
+
#interrupt-cells = <2>;
106
+
};
107
+
108
+
gpio2: gpio@e6051180 {
109
+
compatible = "renesas,gpio-r8a779f0",
110
+
"renesas,rcar-gen4-gpio";
111
+
reg = <0 0xe6051180 0 0x54>;
112
+
interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>;
113
+
clocks = <&cpg CPG_MOD 915>;
114
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
115
+
resets = <&cpg 915>;
116
+
gpio-controller;
117
+
#gpio-cells = <2>;
118
+
gpio-ranges = <&pfc 0 64 17>;
119
+
interrupt-controller;
120
+
#interrupt-cells = <2>;
121
+
};
122
+
123
+
gpio3: gpio@e6051980 {
124
+
compatible = "renesas,gpio-r8a779f0",
125
+
"renesas,rcar-gen4-gpio";
126
+
reg = <0 0xe6051980 0 0x54>;
127
+
interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>;
128
+
clocks = <&cpg CPG_MOD 915>;
129
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
130
+
resets = <&cpg 915>;
131
+
gpio-controller;
132
+
#gpio-cells = <2>;
133
+
gpio-ranges = <&pfc 0 96 19>;
134
+
interrupt-controller;
135
+
#interrupt-cells = <2>;
77
136
};
78
137
79
138
cpg: clock-controller@e6150000 {
···
155
94
compatible = "renesas,r8a779f0-sysc";
156
95
reg = <0 0xe6180000 0 0x4000>;
157
96
#power-domain-cells = <1>;
97
+
};
98
+
99
+
i2c0: i2c@e6500000 {
100
+
compatible = "renesas,i2c-r8a779f0",
101
+
"renesas,rcar-gen4-i2c";
102
+
reg = <0 0xe6500000 0 0x40>;
103
+
interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
104
+
clocks = <&cpg CPG_MOD 518>;
105
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
106
+
resets = <&cpg 518>;
107
+
dmas = <&dmac0 0x91>, <&dmac0 0x90>,
108
+
<&dmac1 0x91>, <&dmac1 0x90>;
109
+
dma-names = "tx", "rx", "tx", "rx";
110
+
i2c-scl-internal-delay-ns = <110>;
111
+
#address-cells = <1>;
112
+
#size-cells = <0>;
113
+
status = "disabled";
114
+
};
115
+
116
+
i2c1: i2c@e6508000 {
117
+
compatible = "renesas,i2c-r8a779f0",
118
+
"renesas,rcar-gen4-i2c";
119
+
reg = <0 0xe6508000 0 0x40>;
120
+
interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
121
+
clocks = <&cpg CPG_MOD 519>;
122
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
123
+
resets = <&cpg 519>;
124
+
dmas = <&dmac0 0x93>, <&dmac0 0x92>,
125
+
<&dmac1 0x93>, <&dmac1 0x92>;
126
+
dma-names = "tx", "rx", "tx", "rx";
127
+
i2c-scl-internal-delay-ns = <110>;
128
+
#address-cells = <1>;
129
+
#size-cells = <0>;
130
+
status = "disabled";
131
+
};
132
+
133
+
i2c2: i2c@e6510000 {
134
+
compatible = "renesas,i2c-r8a779f0",
135
+
"renesas,rcar-gen4-i2c";
136
+
reg = <0 0xe6510000 0 0x40>;
137
+
interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>;
138
+
clocks = <&cpg CPG_MOD 520>;
139
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
140
+
resets = <&cpg 520>;
141
+
dmas = <&dmac0 0x95>, <&dmac0 0x94>,
142
+
<&dmac1 0x95>, <&dmac1 0x94>;
143
+
dma-names = "tx", "rx", "tx", "rx";
144
+
i2c-scl-internal-delay-ns = <110>;
145
+
#address-cells = <1>;
146
+
#size-cells = <0>;
147
+
status = "disabled";
148
+
};
149
+
150
+
i2c3: i2c@e66d0000 {
151
+
compatible = "renesas,i2c-r8a779f0",
152
+
"renesas,rcar-gen4-i2c";
153
+
reg = <0 0xe66d0000 0 0x40>;
154
+
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
155
+
clocks = <&cpg CPG_MOD 521>;
156
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
157
+
resets = <&cpg 521>;
158
+
dmas = <&dmac0 0x97>, <&dmac0 0x96>,
159
+
<&dmac1 0x97>, <&dmac1 0x96>;
160
+
dma-names = "tx", "rx", "tx", "rx";
161
+
i2c-scl-internal-delay-ns = <110>;
162
+
#address-cells = <1>;
163
+
#size-cells = <0>;
164
+
status = "disabled";
165
+
};
166
+
167
+
i2c4: i2c@e66d8000 {
168
+
compatible = "renesas,i2c-r8a779f0",
169
+
"renesas,rcar-gen4-i2c";
170
+
reg = <0 0xe66d8000 0 0x40>;
171
+
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
172
+
clocks = <&cpg CPG_MOD 522>;
173
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
174
+
resets = <&cpg 522>;
175
+
dmas = <&dmac0 0x99>, <&dmac0 0x98>,
176
+
<&dmac1 0x99>, <&dmac1 0x98>;
177
+
dma-names = "tx", "rx", "tx", "rx";
178
+
i2c-scl-internal-delay-ns = <110>;
179
+
#address-cells = <1>;
180
+
#size-cells = <0>;
181
+
status = "disabled";
182
+
};
183
+
184
+
i2c5: i2c@e66e0000 {
185
+
compatible = "renesas,i2c-r8a779f0",
186
+
"renesas,rcar-gen4-i2c";
187
+
reg = <0 0xe66e0000 0 0x40>;
188
+
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
189
+
clocks = <&cpg CPG_MOD 523>;
190
+
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
191
+
resets = <&cpg 523>;
192
+
dmas = <&dmac0 0x9b>, <&dmac0 0x9a>,
193
+
<&dmac1 0x9b>, <&dmac1 0x9a>;
194
+
dma-names = "tx", "rx", "tx", "rx";
195
+
i2c-scl-internal-delay-ns = <110>;
196
+
#address-cells = <1>;
197
+
#size-cells = <0>;
198
+
status = "disabled";
158
199
};
159
200
160
201
scif3: serial@e6c50000 {
+481
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+481
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/G2UL SoC
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <dt-bindings/interrupt-controller/arm-gic.h>
9
+
#include <dt-bindings/clock/r9a07g043-cpg.h>
10
+
11
+
/ {
12
+
compatible = "renesas,r9a07g043";
13
+
#address-cells = <2>;
14
+
#size-cells = <2>;
15
+
16
+
audio_clk1: audio-clk1 {
17
+
compatible = "fixed-clock";
18
+
#clock-cells = <0>;
19
+
/* This value must be overridden by boards that provide it */
20
+
clock-frequency = <0>;
21
+
};
22
+
23
+
audio_clk2: audio-clk2 {
24
+
compatible = "fixed-clock";
25
+
#clock-cells = <0>;
26
+
/* This value must be overridden by boards that provide it */
27
+
clock-frequency = <0>;
28
+
};
29
+
30
+
/* External CAN clock - to be overridden by boards that provide it */
31
+
can_clk: can-clk {
32
+
compatible = "fixed-clock";
33
+
#clock-cells = <0>;
34
+
clock-frequency = <0>;
35
+
};
36
+
37
+
/* clock can be either from exclk or crystal oscillator (XIN/XOUT) */
38
+
extal_clk: extal-clk {
39
+
compatible = "fixed-clock";
40
+
#clock-cells = <0>;
41
+
/* This value must be overridden by the board */
42
+
clock-frequency = <0>;
43
+
};
44
+
45
+
cpus {
46
+
#address-cells = <1>;
47
+
#size-cells = <0>;
48
+
49
+
cpu0: cpu@0 {
50
+
compatible = "arm,cortex-a55";
51
+
reg = <0>;
52
+
device_type = "cpu";
53
+
next-level-cache = <&L3_CA55>;
54
+
enable-method = "psci";
55
+
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
56
+
};
57
+
58
+
L3_CA55: cache-controller-0 {
59
+
compatible = "cache";
60
+
cache-unified;
61
+
cache-size = <0x40000>;
62
+
};
63
+
};
64
+
65
+
psci {
66
+
compatible = "arm,psci-1.0", "arm,psci-0.2";
67
+
method = "smc";
68
+
};
69
+
70
+
soc: soc {
71
+
compatible = "simple-bus";
72
+
interrupt-parent = <&gic>;
73
+
#address-cells = <2>;
74
+
#size-cells = <2>;
75
+
ranges;
76
+
77
+
ssi0: ssi@10049c00 {
78
+
reg = <0 0x10049c00 0 0x400>;
79
+
#sound-dai-cells = <0>;
80
+
/* place holder */
81
+
};
82
+
83
+
spi1: spi@1004b000 {
84
+
reg = <0 0x1004b000 0 0x400>;
85
+
#address-cells = <1>;
86
+
#size-cells = <0>;
87
+
/* place holder */
88
+
};
89
+
90
+
scif0: serial@1004b800 {
91
+
compatible = "renesas,scif-r9a07g043",
92
+
"renesas,scif-r9a07g044";
93
+
reg = <0 0x1004b800 0 0x400>;
94
+
interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
95
+
<GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>,
96
+
<GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
97
+
<GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
98
+
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
99
+
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
100
+
interrupt-names = "eri", "rxi", "txi",
101
+
"bri", "dri", "tei";
102
+
clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>;
103
+
clock-names = "fck";
104
+
power-domains = <&cpg>;
105
+
resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>;
106
+
status = "disabled";
107
+
};
108
+
109
+
scif1: serial@1004bc00 {
110
+
compatible = "renesas,scif-r9a07g043",
111
+
"renesas,scif-r9a07g044";
112
+
reg = <0 0x1004bc00 0 0x400>;
113
+
interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
114
+
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
115
+
<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
116
+
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
117
+
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>,
118
+
<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
119
+
interrupt-names = "eri", "rxi", "txi",
120
+
"bri", "dri", "tei";
121
+
clocks = <&cpg CPG_MOD R9A07G043_SCIF1_CLK_PCK>;
122
+
clock-names = "fck";
123
+
power-domains = <&cpg>;
124
+
resets = <&cpg R9A07G043_SCIF1_RST_SYSTEM_N>;
125
+
status = "disabled";
126
+
};
127
+
128
+
scif2: serial@1004c000 {
129
+
compatible = "renesas,scif-r9a07g043",
130
+
"renesas,scif-r9a07g044";
131
+
reg = <0 0x1004c000 0 0x400>;
132
+
interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>,
133
+
<GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>,
134
+
<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>,
135
+
<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
136
+
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>,
137
+
<GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
138
+
interrupt-names = "eri", "rxi", "txi",
139
+
"bri", "dri", "tei";
140
+
clocks = <&cpg CPG_MOD R9A07G043_SCIF2_CLK_PCK>;
141
+
clock-names = "fck";
142
+
power-domains = <&cpg>;
143
+
resets = <&cpg R9A07G043_SCIF2_RST_SYSTEM_N>;
144
+
status = "disabled";
145
+
};
146
+
147
+
scif3: serial@1004c400 {
148
+
compatible = "renesas,scif-r9a07g043",
149
+
"renesas,scif-r9a07g044";
150
+
reg = <0 0x1004c400 0 0x400>;
151
+
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
152
+
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
153
+
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
154
+
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
155
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
156
+
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
157
+
interrupt-names = "eri", "rxi", "txi",
158
+
"bri", "dri", "tei";
159
+
clocks = <&cpg CPG_MOD R9A07G043_SCIF3_CLK_PCK>;
160
+
clock-names = "fck";
161
+
power-domains = <&cpg>;
162
+
resets = <&cpg R9A07G043_SCIF3_RST_SYSTEM_N>;
163
+
status = "disabled";
164
+
};
165
+
166
+
scif4: serial@1004c800 {
167
+
compatible = "renesas,scif-r9a07g043",
168
+
"renesas,scif-r9a07g044";
169
+
reg = <0 0x1004c800 0 0x400>;
170
+
interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
171
+
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
172
+
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
173
+
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
174
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
175
+
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>;
176
+
interrupt-names = "eri", "rxi", "txi",
177
+
"bri", "dri", "tei";
178
+
clocks = <&cpg CPG_MOD R9A07G043_SCIF4_CLK_PCK>;
179
+
clock-names = "fck";
180
+
power-domains = <&cpg>;
181
+
resets = <&cpg R9A07G043_SCIF4_RST_SYSTEM_N>;
182
+
status = "disabled";
183
+
};
184
+
185
+
sci0: serial@1004d000 {
186
+
compatible = "renesas,r9a07g043-sci", "renesas,sci";
187
+
reg = <0 0x1004d000 0 0x400>;
188
+
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
189
+
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
190
+
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
191
+
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
192
+
interrupt-names = "eri", "rxi", "txi", "tei";
193
+
clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
194
+
clock-names = "fck";
195
+
power-domains = <&cpg>;
196
+
resets = <&cpg R9A07G043_SCI0_RST>;
197
+
status = "disabled";
198
+
};
199
+
200
+
sci1: serial@1004d400 {
201
+
compatible = "renesas,r9a07g043-sci", "renesas,sci";
202
+
reg = <0 0x1004d400 0 0x400>;
203
+
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
204
+
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
205
+
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
206
+
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
207
+
interrupt-names = "eri", "rxi", "txi", "tei";
208
+
clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;
209
+
clock-names = "fck";
210
+
power-domains = <&cpg>;
211
+
resets = <&cpg R9A07G043_SCI1_RST>;
212
+
status = "disabled";
213
+
};
214
+
215
+
canfd: can@10050000 {
216
+
reg = <0 0x10050000 0 0x8000>;
217
+
/* place holder */
218
+
};
219
+
220
+
i2c0: i2c@10058000 {
221
+
#address-cells = <1>;
222
+
#size-cells = <0>;
223
+
reg = <0 0x10058000 0 0x400>;
224
+
/* place holder */
225
+
};
226
+
227
+
i2c1: i2c@10058400 {
228
+
#address-cells = <1>;
229
+
#size-cells = <0>;
230
+
reg = <0 0x10058400 0 0x400>;
231
+
/* place holder */
232
+
};
233
+
234
+
i2c3: i2c@10058c00 {
235
+
#address-cells = <1>;
236
+
#size-cells = <0>;
237
+
reg = <0 0x10058c00 0 0x400>;
238
+
/* place holder */
239
+
};
240
+
241
+
adc: adc@10059000 {
242
+
reg = <0 0x10059000 0 0x400>;
243
+
/* place holder */
244
+
};
245
+
246
+
sbc: spi@10060000 {
247
+
reg = <0 0x10060000 0 0x10000>,
248
+
<0 0x20000000 0 0x10000000>,
249
+
<0 0x10070000 0 0x10000>;
250
+
#address-cells = <1>;
251
+
#size-cells = <0>;
252
+
/* place holder */
253
+
};
254
+
255
+
cpg: clock-controller@11010000 {
256
+
compatible = "renesas,r9a07g043-cpg";
257
+
reg = <0 0x11010000 0 0x10000>;
258
+
clocks = <&extal_clk>;
259
+
clock-names = "extal";
260
+
#clock-cells = <2>;
261
+
#reset-cells = <1>;
262
+
#power-domain-cells = <0>;
263
+
};
264
+
265
+
sysc: system-controller@11020000 {
266
+
compatible = "renesas,r9a07g043-sysc";
267
+
reg = <0 0x11020000 0 0x10000>;
268
+
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
269
+
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
270
+
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
271
+
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
272
+
interrupt-names = "lpm_int", "ca55stbydone_int",
273
+
"cm33stbyr_int", "ca55_deny";
274
+
status = "disabled";
275
+
};
276
+
277
+
pinctrl: pinctrl@11030000 {
278
+
compatible = "renesas,r9a07g043-pinctrl";
279
+
reg = <0 0x11030000 0 0x10000>;
280
+
gpio-controller;
281
+
#gpio-cells = <2>;
282
+
gpio-ranges = <&pinctrl 0 0 152>;
283
+
clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>;
284
+
power-domains = <&cpg>;
285
+
resets = <&cpg R9A07G043_GPIO_RSTN>,
286
+
<&cpg R9A07G043_GPIO_PORT_RESETN>,
287
+
<&cpg R9A07G043_GPIO_SPARE_RESETN>;
288
+
};
289
+
290
+
dmac: dma-controller@11820000 {
291
+
compatible = "renesas,r9a07g043-dmac",
292
+
"renesas,rz-dmac";
293
+
reg = <0 0x11820000 0 0x10000>,
294
+
<0 0x11830000 0 0x10000>;
295
+
interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>,
296
+
<GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
297
+
<GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
298
+
<GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
299
+
<GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
300
+
<GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
301
+
<GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
302
+
<GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
303
+
<GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
304
+
<GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
305
+
<GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
306
+
<GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
307
+
<GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
308
+
<GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
309
+
<GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
310
+
<GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
311
+
<GIC_SPI 140 IRQ_TYPE_EDGE_RISING>;
312
+
interrupt-names = "error",
313
+
"ch0", "ch1", "ch2", "ch3",
314
+
"ch4", "ch5", "ch6", "ch7",
315
+
"ch8", "ch9", "ch10", "ch11",
316
+
"ch12", "ch13", "ch14", "ch15";
317
+
clocks = <&cpg CPG_MOD R9A07G043_DMAC_ACLK>,
318
+
<&cpg CPG_MOD R9A07G043_DMAC_PCLK>;
319
+
power-domains = <&cpg>;
320
+
resets = <&cpg R9A07G043_DMAC_ARESETN>,
321
+
<&cpg R9A07G043_DMAC_RST_ASYNC>;
322
+
#dma-cells = <1>;
323
+
dma-channels = <16>;
324
+
};
325
+
326
+
gic: interrupt-controller@11900000 {
327
+
compatible = "arm,gic-v3";
328
+
#interrupt-cells = <3>;
329
+
#address-cells = <0>;
330
+
interrupt-controller;
331
+
reg = <0x0 0x11900000 0 0x40000>,
332
+
<0x0 0x11940000 0 0x60000>;
333
+
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
334
+
};
335
+
336
+
sdhi0: mmc@11c00000 {
337
+
compatible = "renesas,sdhi-r9a07g043",
338
+
"renesas,rcar-gen3-sdhi";
339
+
reg = <0x0 0x11c00000 0 0x10000>;
340
+
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
341
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
342
+
clocks = <&cpg CPG_MOD R9A07G043_SDHI0_IMCLK>,
343
+
<&cpg CPG_MOD R9A07G043_SDHI0_CLK_HS>,
344
+
<&cpg CPG_MOD R9A07G043_SDHI0_IMCLK2>,
345
+
<&cpg CPG_MOD R9A07G043_SDHI0_ACLK>;
346
+
clock-names = "core", "clkh", "cd", "aclk";
347
+
resets = <&cpg R9A07G043_SDHI0_IXRST>;
348
+
power-domains = <&cpg>;
349
+
status = "disabled";
350
+
};
351
+
352
+
sdhi1: mmc@11c10000 {
353
+
compatible = "renesas,sdhi-r9a07g043",
354
+
"renesas,rcar-gen3-sdhi";
355
+
reg = <0x0 0x11c10000 0 0x10000>;
356
+
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
357
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
358
+
clocks = <&cpg CPG_MOD R9A07G043_SDHI1_IMCLK>,
359
+
<&cpg CPG_MOD R9A07G043_SDHI1_CLK_HS>,
360
+
<&cpg CPG_MOD R9A07G043_SDHI1_IMCLK2>,
361
+
<&cpg CPG_MOD R9A07G043_SDHI1_ACLK>;
362
+
clock-names = "core", "clkh", "cd", "aclk";
363
+
resets = <&cpg R9A07G043_SDHI1_IXRST>;
364
+
power-domains = <&cpg>;
365
+
status = "disabled";
366
+
};
367
+
368
+
eth0: ethernet@11c20000 {
369
+
compatible = "renesas,r9a07g043-gbeth",
370
+
"renesas,rzg2l-gbeth";
371
+
reg = <0 0x11c20000 0 0x10000>;
372
+
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
373
+
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
374
+
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
375
+
interrupt-names = "mux", "fil", "arp_ns";
376
+
phy-mode = "rgmii";
377
+
clocks = <&cpg CPG_MOD R9A07G043_ETH0_CLK_AXI>,
378
+
<&cpg CPG_MOD R9A07G043_ETH0_CLK_CHI>,
379
+
<&cpg CPG_CORE R9A07G043_CLK_HP>;
380
+
clock-names = "axi", "chi", "refclk";
381
+
resets = <&cpg R9A07G043_ETH0_RST_HW_N>;
382
+
power-domains = <&cpg>;
383
+
#address-cells = <1>;
384
+
#size-cells = <0>;
385
+
status = "disabled";
386
+
};
387
+
388
+
eth1: ethernet@11c30000 {
389
+
compatible = "renesas,r9a07g043-gbeth",
390
+
"renesas,rzg2l-gbeth";
391
+
reg = <0 0x11c30000 0 0x10000>;
392
+
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
393
+
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
394
+
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
395
+
interrupt-names = "mux", "fil", "arp_ns";
396
+
phy-mode = "rgmii";
397
+
clocks = <&cpg CPG_MOD R9A07G043_ETH1_CLK_AXI>,
398
+
<&cpg CPG_MOD R9A07G043_ETH1_CLK_CHI>,
399
+
<&cpg CPG_CORE R9A07G043_CLK_HP>;
400
+
clock-names = "axi", "chi", "refclk";
401
+
resets = <&cpg R9A07G043_ETH1_RST_HW_N>;
402
+
power-domains = <&cpg>;
403
+
#address-cells = <1>;
404
+
#size-cells = <0>;
405
+
status = "disabled";
406
+
};
407
+
408
+
phyrst: usbphy-ctrl@11c40000 {
409
+
reg = <0 0x11c40000 0 0x10000>;
410
+
/* place holder */
411
+
};
412
+
413
+
ohci0: usb@11c50000 {
414
+
reg = <0 0x11c50000 0 0x100>;
415
+
/* place holder */
416
+
};
417
+
418
+
ohci1: usb@11c70000 {
419
+
reg = <0 0x11c70000 0 0x100>;
420
+
/* place holder */
421
+
};
422
+
423
+
ehci0: usb@11c50100 {
424
+
reg = <0 0x11c50100 0 0x100>;
425
+
/* place holder */
426
+
};
427
+
428
+
ehci1: usb@11c70100 {
429
+
reg = <0 0x11c70100 0 0x100>;
430
+
/* place holder */
431
+
};
432
+
433
+
usb2_phy0: usb-phy@11c50200 {
434
+
reg = <0 0x11c50200 0 0x700>;
435
+
/* place holder */
436
+
};
437
+
438
+
usb2_phy1: usb-phy@11c70200 {
439
+
reg = <0 0x11c70200 0 0x700>;
440
+
/* place holder */
441
+
};
442
+
443
+
hsusb: usb@11c60000 {
444
+
reg = <0 0x11c60000 0 0x10000>;
445
+
/* place holder */
446
+
};
447
+
448
+
wdt0: watchdog@12800800 {
449
+
reg = <0 0x12800800 0 0x400>;
450
+
/* place holder */
451
+
};
452
+
453
+
wdt2: watchdog@12800400 {
454
+
reg = <0 0x12800400 0 0x400>;
455
+
/* place holder */
456
+
};
457
+
458
+
ostm0: timer@12801000 {
459
+
reg = <0x0 0x12801000 0x0 0x400>;
460
+
/* place holder */
461
+
};
462
+
463
+
ostm1: timer@12801400 {
464
+
reg = <0x0 0x12801400 0x0 0x400>;
465
+
/* place holder */
466
+
};
467
+
468
+
ostm2: timer@12801800 {
469
+
reg = <0x0 0x12801800 0x0 0x400>;
470
+
/* place holder */
471
+
};
472
+
};
473
+
474
+
timer {
475
+
compatible = "arm,armv8-timer";
476
+
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
477
+
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
478
+
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
479
+
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
480
+
};
481
+
};
+97
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
+97
arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/G2UL Type-1 SMARC EVK board
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
/dts-v1/;
9
+
#include "r9a07g043.dtsi"
10
+
#include "rzg2ul-smarc.dtsi"
11
+
12
+
/ {
13
+
model = "Renesas SMARC EVK based on r9a07g043u11";
14
+
compatible = "renesas,smarc-evk", "renesas,r9a07g043u11", "renesas,r9a07g043";
15
+
};
16
+
17
+
&canfd {
18
+
/delete-property/ pinctrl-0;
19
+
/delete-property/ pinctrl-names;
20
+
status = "disabled";
21
+
};
22
+
23
+
&ehci0 {
24
+
/delete-property/ pinctrl-0;
25
+
/delete-property/ pinctrl-names;
26
+
status = "disabled";
27
+
};
28
+
29
+
&ehci1 {
30
+
/delete-property/ pinctrl-0;
31
+
/delete-property/ pinctrl-names;
32
+
status = "disabled";
33
+
};
34
+
35
+
&hsusb {
36
+
/delete-property/ pinctrl-0;
37
+
/delete-property/ pinctrl-names;
38
+
status = "disabled";
39
+
};
40
+
41
+
&i2c0 {
42
+
/delete-property/ pinctrl-0;
43
+
/delete-property/ pinctrl-names;
44
+
status = "disabled";
45
+
};
46
+
47
+
&i2c1 {
48
+
/delete-property/ pinctrl-0;
49
+
/delete-property/ pinctrl-names;
50
+
status = "disabled";
51
+
52
+
wm8978: codec@1a {
53
+
compatible = "wlf,wm8978";
54
+
#sound-dai-cells = <0>;
55
+
reg = <0x1a>;
56
+
};
57
+
};
58
+
59
+
&ohci0 {
60
+
/delete-property/ pinctrl-0;
61
+
/delete-property/ pinctrl-names;
62
+
status = "disabled";
63
+
};
64
+
65
+
&ohci1 {
66
+
/delete-property/ pinctrl-0;
67
+
/delete-property/ pinctrl-names;
68
+
status = "disabled";
69
+
};
70
+
71
+
&phyrst {
72
+
status = "disabled";
73
+
};
74
+
75
+
&spi1 {
76
+
/delete-property/ pinctrl-0;
77
+
/delete-property/ pinctrl-names;
78
+
status = "disabled";
79
+
};
80
+
81
+
&ssi0 {
82
+
/delete-property/ pinctrl-0;
83
+
/delete-property/ pinctrl-names;
84
+
status = "disabled";
85
+
};
86
+
87
+
&usb2_phy0 {
88
+
/delete-property/ pinctrl-0;
89
+
/delete-property/ pinctrl-names;
90
+
status = "disabled";
91
+
};
92
+
93
+
&usb2_phy1 {
94
+
/delete-property/ pinctrl-0;
95
+
/delete-property/ pinctrl-names;
96
+
status = "disabled";
97
+
};
-76
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
-76
arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts
···
13
13
model = "Renesas SMARC EVK based on r9a07g044c2";
14
14
compatible = "renesas,smarc-evk", "renesas,r9a07g044c2", "renesas,r9a07g044";
15
15
};
16
-
17
-
&ehci0 {
18
-
/delete-property/ pinctrl-0;
19
-
/delete-property/ pinctrl-names;
20
-
status = "disabled";
21
-
};
22
-
23
-
&ehci1 {
24
-
/delete-property/ pinctrl-0;
25
-
/delete-property/ pinctrl-names;
26
-
status = "disabled";
27
-
};
28
-
29
-
&hsusb {
30
-
/delete-property/ pinctrl-0;
31
-
/delete-property/ pinctrl-names;
32
-
status = "disabled";
33
-
};
34
-
35
-
&i2c0 {
36
-
/delete-property/ pinctrl-0;
37
-
/delete-property/ pinctrl-names;
38
-
status = "disabled";
39
-
};
40
-
41
-
&i2c1 {
42
-
/delete-property/ pinctrl-0;
43
-
/delete-property/ pinctrl-names;
44
-
status = "disabled";
45
-
};
46
-
47
-
&i2c3 {
48
-
/delete-property/ pinctrl-0;
49
-
/delete-property/ pinctrl-names;
50
-
status = "disabled";
51
-
};
52
-
53
-
&ohci0 {
54
-
/delete-property/ pinctrl-0;
55
-
/delete-property/ pinctrl-names;
56
-
status = "disabled";
57
-
};
58
-
59
-
&ohci1 {
60
-
/delete-property/ pinctrl-0;
61
-
/delete-property/ pinctrl-names;
62
-
status = "disabled";
63
-
};
64
-
65
-
&phyrst {
66
-
status = "disabled";
67
-
};
68
-
69
-
&spi1 {
70
-
/delete-property/ pinctrl-0;
71
-
/delete-property/ pinctrl-names;
72
-
status = "disabled";
73
-
};
74
-
75
-
&ssi0 {
76
-
/delete-property/ pinctrl-0;
77
-
/delete-property/ pinctrl-names;
78
-
status = "disabled";
79
-
};
80
-
81
-
&usb2_phy0 {
82
-
/delete-property/ pinctrl-0;
83
-
/delete-property/ pinctrl-names;
84
-
status = "disabled";
85
-
};
86
-
87
-
&usb2_phy1 {
88
-
/delete-property/ pinctrl-0;
89
-
/delete-property/ pinctrl-names;
90
-
status = "disabled";
91
-
};
+559
-25
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
+559
-25
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
···
42
42
clock-frequency = <0>;
43
43
};
44
44
45
+
cluster0_opp: opp-table-0 {
46
+
compatible = "operating-points-v2";
47
+
opp-shared;
48
+
49
+
opp-150000000 {
50
+
opp-hz = /bits/ 64 <150000000>;
51
+
opp-microvolt = <1100000>;
52
+
clock-latency-ns = <300000>;
53
+
};
54
+
opp-300000000 {
55
+
opp-hz = /bits/ 64 <300000000>;
56
+
opp-microvolt = <1100000>;
57
+
clock-latency-ns = <300000>;
58
+
};
59
+
opp-600000000 {
60
+
opp-hz = /bits/ 64 <600000000>;
61
+
opp-microvolt = <1100000>;
62
+
clock-latency-ns = <300000>;
63
+
};
64
+
opp-1200000000 {
65
+
opp-hz = /bits/ 64 <1200000000>;
66
+
opp-microvolt = <1100000>;
67
+
clock-latency-ns = <300000>;
68
+
opp-suspend;
69
+
};
70
+
};
71
+
45
72
cpus {
46
73
#address-cells = <1>;
47
74
#size-cells = <0>;
···
92
65
next-level-cache = <&L3_CA55>;
93
66
enable-method = "psci";
94
67
clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
68
+
operating-points-v2 = <&cluster0_opp>;
95
69
};
96
70
97
71
cpu1: cpu@100 {
···
102
74
next-level-cache = <&L3_CA55>;
103
75
enable-method = "psci";
104
76
clocks = <&cpg CPG_CORE R9A07G054_CLK_I>;
77
+
operating-points-v2 = <&cluster0_opp>;
105
78
};
106
79
107
80
L3_CA55: cache-controller-0 {
108
81
compatible = "cache";
109
82
cache-unified;
110
83
cache-size = <0x40000>;
84
+
};
85
+
};
86
+
87
+
gpu_opp_table: opp-table-1 {
88
+
compatible = "operating-points-v2";
89
+
90
+
opp-500000000 {
91
+
opp-hz = /bits/ 64 <500000000>;
92
+
opp-microvolt = <1100000>;
93
+
};
94
+
95
+
opp-400000000 {
96
+
opp-hz = /bits/ 64 <400000000>;
97
+
opp-microvolt = <1100000>;
98
+
};
99
+
100
+
opp-250000000 {
101
+
opp-hz = /bits/ 64 <250000000>;
102
+
opp-microvolt = <1100000>;
103
+
};
104
+
105
+
opp-200000000 {
106
+
opp-hz = /bits/ 64 <200000000>;
107
+
opp-microvolt = <1100000>;
108
+
};
109
+
110
+
opp-125000000 {
111
+
opp-hz = /bits/ 64 <125000000>;
112
+
opp-microvolt = <1100000>;
113
+
};
114
+
115
+
opp-100000000 {
116
+
opp-hz = /bits/ 64 <100000000>;
117
+
opp-microvolt = <1100000>;
118
+
};
119
+
120
+
opp-62500000 {
121
+
opp-hz = /bits/ 64 <62500000>;
122
+
opp-microvolt = <1100000>;
123
+
};
124
+
125
+
opp-50000000 {
126
+
opp-hz = /bits/ 64 <50000000>;
127
+
opp-microvolt = <1100000>;
111
128
};
112
129
};
113
130
···
169
96
ranges;
170
97
171
98
ssi0: ssi@10049c00 {
99
+
compatible = "renesas,r9a07g054-ssi",
100
+
"renesas,rz-ssi";
172
101
reg = <0 0x10049c00 0 0x400>;
102
+
interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
103
+
<GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
104
+
<GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
105
+
<GIC_SPI 329 IRQ_TYPE_EDGE_RISING>;
106
+
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
107
+
clocks = <&cpg CPG_MOD R9A07G054_SSI0_PCLK2>,
108
+
<&cpg CPG_MOD R9A07G054_SSI0_PCLK_SFR>,
109
+
<&audio_clk1>, <&audio_clk2>;
110
+
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
111
+
resets = <&cpg R9A07G054_SSI0_RST_M2_REG>;
112
+
dmas = <&dmac 0x2655>, <&dmac 0x2656>;
113
+
dma-names = "tx", "rx";
114
+
power-domains = <&cpg>;
173
115
#sound-dai-cells = <0>;
174
-
/* place holder */
116
+
status = "disabled";
117
+
};
118
+
119
+
ssi1: ssi@1004a000 {
120
+
compatible = "renesas,r9a07g054-ssi",
121
+
"renesas,rz-ssi";
122
+
reg = <0 0x1004a000 0 0x400>;
123
+
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
124
+
<GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
125
+
<GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
126
+
<GIC_SPI 333 IRQ_TYPE_EDGE_RISING>;
127
+
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
128
+
clocks = <&cpg CPG_MOD R9A07G054_SSI1_PCLK2>,
129
+
<&cpg CPG_MOD R9A07G054_SSI1_PCLK_SFR>,
130
+
<&audio_clk1>, <&audio_clk2>;
131
+
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
132
+
resets = <&cpg R9A07G054_SSI1_RST_M2_REG>;
133
+
dmas = <&dmac 0x2659>, <&dmac 0x265a>;
134
+
dma-names = "tx", "rx";
135
+
power-domains = <&cpg>;
136
+
#sound-dai-cells = <0>;
137
+
status = "disabled";
138
+
};
139
+
140
+
ssi2: ssi@1004a400 {
141
+
compatible = "renesas,r9a07g054-ssi",
142
+
"renesas,rz-ssi";
143
+
reg = <0 0x1004a400 0 0x400>;
144
+
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
145
+
<GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
146
+
<GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
147
+
<GIC_SPI 337 IRQ_TYPE_EDGE_RISING>;
148
+
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
149
+
clocks = <&cpg CPG_MOD R9A07G054_SSI2_PCLK2>,
150
+
<&cpg CPG_MOD R9A07G054_SSI2_PCLK_SFR>,
151
+
<&audio_clk1>, <&audio_clk2>;
152
+
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
153
+
resets = <&cpg R9A07G054_SSI2_RST_M2_REG>;
154
+
dmas = <&dmac 0x265f>;
155
+
dma-names = "rt";
156
+
power-domains = <&cpg>;
157
+
#sound-dai-cells = <0>;
158
+
status = "disabled";
159
+
};
160
+
161
+
ssi3: ssi@1004a800 {
162
+
compatible = "renesas,r9a07g054-ssi",
163
+
"renesas,rz-ssi";
164
+
reg = <0 0x1004a800 0 0x400>;
165
+
interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
166
+
<GIC_SPI 339 IRQ_TYPE_EDGE_RISING>,
167
+
<GIC_SPI 340 IRQ_TYPE_EDGE_RISING>,
168
+
<GIC_SPI 341 IRQ_TYPE_EDGE_RISING>;
169
+
interrupt-names = "int_req", "dma_rx", "dma_tx", "dma_rt";
170
+
clocks = <&cpg CPG_MOD R9A07G054_SSI3_PCLK2>,
171
+
<&cpg CPG_MOD R9A07G054_SSI3_PCLK_SFR>,
172
+
<&audio_clk1>, <&audio_clk2>;
173
+
clock-names = "ssi", "ssi_sfr", "audio_clk1", "audio_clk2";
174
+
resets = <&cpg R9A07G054_SSI3_RST_M2_REG>;
175
+
dmas = <&dmac 0x2661>, <&dmac 0x2662>;
176
+
dma-names = "tx", "rx";
177
+
power-domains = <&cpg>;
178
+
#sound-dai-cells = <0>;
179
+
status = "disabled";
180
+
};
181
+
182
+
spi0: spi@1004ac00 {
183
+
compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
184
+
reg = <0 0x1004ac00 0 0x400>;
185
+
interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
186
+
<GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
187
+
<GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
188
+
interrupt-names = "error", "rx", "tx";
189
+
clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
190
+
resets = <&cpg R9A07G054_RSPI0_RST>;
191
+
power-domains = <&cpg>;
192
+
num-cs = <1>;
193
+
#address-cells = <1>;
194
+
#size-cells = <0>;
195
+
status = "disabled";
175
196
};
176
197
177
198
spi1: spi@1004b000 {
199
+
compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
178
200
reg = <0 0x1004b000 0 0x400>;
201
+
interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
202
+
<GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
203
+
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
204
+
interrupt-names = "error", "rx", "tx";
205
+
clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
206
+
resets = <&cpg R9A07G054_RSPI1_RST>;
207
+
power-domains = <&cpg>;
208
+
num-cs = <1>;
179
209
#address-cells = <1>;
180
210
#size-cells = <0>;
181
-
/* place holder */
211
+
status = "disabled";
212
+
};
213
+
214
+
spi2: spi@1004b400 {
215
+
compatible = "renesas,r9a07g054-rspi", "renesas,rspi-rz";
216
+
reg = <0 0x1004b400 0 0x400>;
217
+
interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
218
+
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
219
+
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
220
+
interrupt-names = "error", "rx", "tx";
221
+
clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
222
+
resets = <&cpg R9A07G054_RSPI2_RST>;
223
+
power-domains = <&cpg>;
224
+
num-cs = <1>;
225
+
#address-cells = <1>;
226
+
#size-cells = <0>;
227
+
status = "disabled";
182
228
};
183
229
184
230
scif0: serial@1004b800 {
···
426
234
};
427
235
428
236
canfd: can@10050000 {
237
+
compatible = "renesas,r9a07g054-canfd", "renesas,rzg2l-canfd";
429
238
reg = <0 0x10050000 0 0x8000>;
430
-
/* place holder */
239
+
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>,
240
+
<GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>,
241
+
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
242
+
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
243
+
<GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>,
244
+
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
245
+
<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
246
+
<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>;
247
+
interrupt-names = "g_err", "g_recc",
248
+
"ch0_err", "ch0_rec", "ch0_trx",
249
+
"ch1_err", "ch1_rec", "ch1_trx";
250
+
clocks = <&cpg CPG_MOD R9A07G054_CANFD_PCLK>,
251
+
<&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>,
252
+
<&can_clk>;
253
+
clock-names = "fck", "canfd", "can_clk";
254
+
assigned-clocks = <&cpg CPG_CORE R9A07G054_CLK_P0_DIV2>;
255
+
assigned-clock-rates = <50000000>;
256
+
resets = <&cpg R9A07G054_CANFD_RSTP_N>,
257
+
<&cpg R9A07G054_CANFD_RSTC_N>;
258
+
reset-names = "rstp_n", "rstc_n";
259
+
power-domains = <&cpg>;
260
+
status = "disabled";
261
+
262
+
channel0 {
263
+
status = "disabled";
264
+
};
265
+
channel1 {
266
+
status = "disabled";
267
+
};
431
268
};
432
269
433
270
i2c0: i2c@10058000 {
434
271
#address-cells = <1>;
435
272
#size-cells = <0>;
273
+
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
436
274
reg = <0 0x10058000 0 0x400>;
437
-
/* place holder */
275
+
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
276
+
<GIC_SPI 348 IRQ_TYPE_EDGE_RISING>,
277
+
<GIC_SPI 349 IRQ_TYPE_EDGE_RISING>,
278
+
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
279
+
<GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
280
+
<GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
281
+
<GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
282
+
<GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
283
+
interrupt-names = "tei", "ri", "ti", "spi", "sti",
284
+
"naki", "ali", "tmoi";
285
+
clocks = <&cpg CPG_MOD R9A07G054_I2C0_PCLK>;
286
+
clock-frequency = <100000>;
287
+
resets = <&cpg R9A07G054_I2C0_MRST>;
288
+
power-domains = <&cpg>;
289
+
status = "disabled";
438
290
};
439
291
440
292
i2c1: i2c@10058400 {
441
293
#address-cells = <1>;
442
294
#size-cells = <0>;
295
+
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
443
296
reg = <0 0x10058400 0 0x400>;
444
-
/* place holder */
297
+
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
298
+
<GIC_SPI 356 IRQ_TYPE_EDGE_RISING>,
299
+
<GIC_SPI 357 IRQ_TYPE_EDGE_RISING>,
300
+
<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
301
+
<GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
302
+
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
303
+
<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
304
+
<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>;
305
+
interrupt-names = "tei", "ri", "ti", "spi", "sti",
306
+
"naki", "ali", "tmoi";
307
+
clocks = <&cpg CPG_MOD R9A07G054_I2C1_PCLK>;
308
+
clock-frequency = <100000>;
309
+
resets = <&cpg R9A07G054_I2C1_MRST>;
310
+
power-domains = <&cpg>;
311
+
status = "disabled";
312
+
};
313
+
314
+
i2c2: i2c@10058800 {
315
+
#address-cells = <1>;
316
+
#size-cells = <0>;
317
+
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
318
+
reg = <0 0x10058800 0 0x400>;
319
+
interrupts = <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
320
+
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
321
+
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
322
+
<GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
323
+
<GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
324
+
<GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
325
+
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
326
+
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
327
+
interrupt-names = "tei", "ri", "ti", "spi", "sti",
328
+
"naki", "ali", "tmoi";
329
+
clocks = <&cpg CPG_MOD R9A07G054_I2C2_PCLK>;
330
+
clock-frequency = <100000>;
331
+
resets = <&cpg R9A07G054_I2C2_MRST>;
332
+
power-domains = <&cpg>;
333
+
status = "disabled";
445
334
};
446
335
447
336
i2c3: i2c@10058c00 {
448
337
#address-cells = <1>;
449
338
#size-cells = <0>;
339
+
compatible = "renesas,riic-r9a07g054", "renesas,riic-rz";
450
340
reg = <0 0x10058c00 0 0x400>;
451
-
/* place holder */
341
+
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
342
+
<GIC_SPI 372 IRQ_TYPE_EDGE_RISING>,
343
+
<GIC_SPI 373 IRQ_TYPE_EDGE_RISING>,
344
+
<GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
345
+
<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
346
+
<GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
347
+
<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
348
+
<GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
349
+
interrupt-names = "tei", "ri", "ti", "spi", "sti",
350
+
"naki", "ali", "tmoi";
351
+
clocks = <&cpg CPG_MOD R9A07G054_I2C3_PCLK>;
352
+
clock-frequency = <100000>;
353
+
resets = <&cpg R9A07G054_I2C3_MRST>;
354
+
power-domains = <&cpg>;
355
+
status = "disabled";
452
356
};
453
357
454
358
adc: adc@10059000 {
359
+
compatible = "renesas,r9a07g054-adc", "renesas,rzg2l-adc";
455
360
reg = <0 0x10059000 0 0x400>;
456
-
/* place holder */
361
+
interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
362
+
clocks = <&cpg CPG_MOD R9A07G054_ADC_ADCLK>,
363
+
<&cpg CPG_MOD R9A07G054_ADC_PCLK>;
364
+
clock-names = "adclk", "pclk";
365
+
resets = <&cpg R9A07G054_ADC_PRESETN>,
366
+
<&cpg R9A07G054_ADC_ADRST_N>;
367
+
reset-names = "presetn", "adrst-n";
368
+
power-domains = <&cpg>;
369
+
status = "disabled";
370
+
371
+
#address-cells = <1>;
372
+
#size-cells = <0>;
373
+
374
+
channel@0 {
375
+
reg = <0>;
376
+
};
377
+
channel@1 {
378
+
reg = <1>;
379
+
};
380
+
channel@2 {
381
+
reg = <2>;
382
+
};
383
+
channel@3 {
384
+
reg = <3>;
385
+
};
386
+
channel@4 {
387
+
reg = <4>;
388
+
};
389
+
channel@5 {
390
+
reg = <5>;
391
+
};
392
+
channel@6 {
393
+
reg = <6>;
394
+
};
395
+
channel@7 {
396
+
reg = <7>;
397
+
};
398
+
};
399
+
400
+
tsu: thermal@10059400 {
401
+
compatible = "renesas,r9a07g054-tsu",
402
+
"renesas,rzg2l-tsu";
403
+
reg = <0 0x10059400 0 0x400>;
404
+
clocks = <&cpg CPG_MOD R9A07G054_TSU_PCLK>;
405
+
resets = <&cpg R9A07G054_TSU_PRESETN>;
406
+
power-domains = <&cpg>;
407
+
#thermal-sensor-cells = <1>;
457
408
};
458
409
459
410
sbc: spi@10060000 {
411
+
compatible = "renesas,r9a07g054-rpc-if",
412
+
"renesas,rzg2l-rpc-if";
460
413
reg = <0 0x10060000 0 0x10000>,
461
414
<0 0x20000000 0 0x10000000>,
462
415
<0 0x10070000 0 0x10000>;
416
+
reg-names = "regs", "dirmap", "wbuf";
417
+
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
418
+
clocks = <&cpg CPG_MOD R9A07G054_SPI_CLK2>,
419
+
<&cpg CPG_MOD R9A07G054_SPI_CLK>;
420
+
resets = <&cpg R9A07G054_SPI_RST>;
421
+
power-domains = <&cpg>;
463
422
#address-cells = <1>;
464
423
#size-cells = <0>;
465
-
/* place holder */
424
+
status = "disabled";
466
425
};
467
426
468
427
cpg: clock-controller@11010000 {
···
689
346
};
690
347
691
348
gpu: gpu@11840000 {
349
+
compatible = "renesas,r9a07g054-mali",
350
+
"arm,mali-bifrost";
692
351
reg = <0x0 0x11840000 0x0 0x10000>;
693
-
/* place holder */
352
+
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
353
+
<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
354
+
<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
355
+
<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
356
+
interrupt-names = "job", "mmu", "gpu", "event";
357
+
clocks = <&cpg CPG_MOD R9A07G054_GPU_CLK>,
358
+
<&cpg CPG_MOD R9A07G054_GPU_AXI_CLK>,
359
+
<&cpg CPG_MOD R9A07G054_GPU_ACE_CLK>;
360
+
clock-names = "gpu", "bus", "bus_ace";
361
+
power-domains = <&cpg>;
362
+
resets = <&cpg R9A07G054_GPU_RESETN>,
363
+
<&cpg R9A07G054_GPU_AXI_RESETN>,
364
+
<&cpg R9A07G054_GPU_ACE_RESETN>;
365
+
reset-names = "rst", "axi_rst", "ace_rst";
366
+
operating-points-v2 = <&gpu_opp_table>;
694
367
};
695
368
696
369
gic: interrupt-controller@11900000 {
···
720
361
};
721
362
722
363
sdhi0: mmc@11c00000 {
364
+
compatible = "renesas,sdhi-r9a07g054",
365
+
"renesas,rcar-gen3-sdhi";
723
366
reg = <0x0 0x11c00000 0 0x10000>;
724
-
/* place holder */
367
+
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
368
+
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
369
+
clocks = <&cpg CPG_MOD R9A07G054_SDHI0_IMCLK>,
370
+
<&cpg CPG_MOD R9A07G054_SDHI0_CLK_HS>,
371
+
<&cpg CPG_MOD R9A07G054_SDHI0_IMCLK2>,
372
+
<&cpg CPG_MOD R9A07G054_SDHI0_ACLK>;
373
+
clock-names = "core", "clkh", "cd", "aclk";
374
+
resets = <&cpg R9A07G054_SDHI0_IXRST>;
375
+
power-domains = <&cpg>;
376
+
status = "disabled";
725
377
};
726
378
727
379
sdhi1: mmc@11c10000 {
380
+
compatible = "renesas,sdhi-r9a07g054",
381
+
"renesas,rcar-gen3-sdhi";
728
382
reg = <0x0 0x11c10000 0 0x10000>;
729
-
/* place holder */
383
+
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
384
+
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
385
+
clocks = <&cpg CPG_MOD R9A07G054_SDHI1_IMCLK>,
386
+
<&cpg CPG_MOD R9A07G054_SDHI1_CLK_HS>,
387
+
<&cpg CPG_MOD R9A07G054_SDHI1_IMCLK2>,
388
+
<&cpg CPG_MOD R9A07G054_SDHI1_ACLK>;
389
+
clock-names = "core", "clkh", "cd", "aclk";
390
+
resets = <&cpg R9A07G054_SDHI1_IXRST>;
391
+
power-domains = <&cpg>;
392
+
status = "disabled";
730
393
};
731
394
732
395
eth0: ethernet@11c20000 {
···
792
411
};
793
412
794
413
phyrst: usbphy-ctrl@11c40000 {
414
+
compatible = "renesas,r9a07g054-usbphy-ctrl",
415
+
"renesas,rzg2l-usbphy-ctrl";
795
416
reg = <0 0x11c40000 0 0x10000>;
796
-
/* place holder */
417
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>;
418
+
resets = <&cpg R9A07G054_USB_PRESETN>;
419
+
power-domains = <&cpg>;
420
+
#reset-cells = <1>;
421
+
status = "disabled";
797
422
};
798
423
799
424
ohci0: usb@11c50000 {
425
+
compatible = "generic-ohci";
800
426
reg = <0 0x11c50000 0 0x100>;
801
-
/* place holder */
427
+
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
428
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
429
+
<&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
430
+
resets = <&phyrst 0>,
431
+
<&cpg R9A07G054_USB_U2H0_HRESETN>;
432
+
phys = <&usb2_phy0 1>;
433
+
phy-names = "usb";
434
+
power-domains = <&cpg>;
435
+
status = "disabled";
802
436
};
803
437
804
438
ohci1: usb@11c70000 {
439
+
compatible = "generic-ohci";
805
440
reg = <0 0x11c70000 0 0x100>;
806
-
/* place holder */
441
+
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
442
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
443
+
<&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
444
+
resets = <&phyrst 1>,
445
+
<&cpg R9A07G054_USB_U2H1_HRESETN>;
446
+
phys = <&usb2_phy1 1>;
447
+
phy-names = "usb";
448
+
power-domains = <&cpg>;
449
+
status = "disabled";
807
450
};
808
451
809
452
ehci0: usb@11c50100 {
453
+
compatible = "generic-ehci";
810
454
reg = <0 0x11c50100 0 0x100>;
811
-
/* place holder */
455
+
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
456
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
457
+
<&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
458
+
resets = <&phyrst 0>,
459
+
<&cpg R9A07G054_USB_U2H0_HRESETN>;
460
+
phys = <&usb2_phy0 2>;
461
+
phy-names = "usb";
462
+
companion = <&ohci0>;
463
+
power-domains = <&cpg>;
464
+
status = "disabled";
812
465
};
813
466
814
467
ehci1: usb@11c70100 {
468
+
compatible = "generic-ehci";
815
469
reg = <0 0x11c70100 0 0x100>;
816
-
/* place holder */
470
+
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
471
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
472
+
<&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
473
+
resets = <&phyrst 1>,
474
+
<&cpg R9A07G054_USB_U2H1_HRESETN>;
475
+
phys = <&usb2_phy1 2>;
476
+
phy-names = "usb";
477
+
companion = <&ohci1>;
478
+
power-domains = <&cpg>;
479
+
status = "disabled";
817
480
};
818
481
819
482
usb2_phy0: usb-phy@11c50200 {
483
+
compatible = "renesas,usb2-phy-r9a07g054",
484
+
"renesas,rzg2l-usb2-phy";
820
485
reg = <0 0x11c50200 0 0x700>;
821
-
/* place holder */
486
+
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
487
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
488
+
<&cpg CPG_MOD R9A07G054_USB_U2H0_HCLK>;
489
+
resets = <&phyrst 0>;
490
+
#phy-cells = <1>;
491
+
power-domains = <&cpg>;
492
+
status = "disabled";
822
493
};
823
494
824
495
usb2_phy1: usb-phy@11c70200 {
496
+
compatible = "renesas,usb2-phy-r9a07g054",
497
+
"renesas,rzg2l-usb2-phy";
825
498
reg = <0 0x11c70200 0 0x700>;
826
-
/* place holder */
499
+
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
500
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
501
+
<&cpg CPG_MOD R9A07G054_USB_U2H1_HCLK>;
502
+
resets = <&phyrst 1>;
503
+
#phy-cells = <1>;
504
+
power-domains = <&cpg>;
505
+
status = "disabled";
827
506
};
828
507
829
508
hsusb: usb@11c60000 {
509
+
compatible = "renesas,usbhs-r9a07g054",
510
+
"renesas,rza2-usbhs";
830
511
reg = <0 0x11c60000 0 0x10000>;
831
-
/* place holder */
512
+
interrupts = <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>,
513
+
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
514
+
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
515
+
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
516
+
clocks = <&cpg CPG_MOD R9A07G054_USB_PCLK>,
517
+
<&cpg CPG_MOD R9A07G054_USB_U2P_EXR_CPUCLK>;
518
+
resets = <&phyrst 0>,
519
+
<&cpg R9A07G054_USB_U2P_EXL_SYSRST>;
520
+
renesas,buswait = <7>;
521
+
phys = <&usb2_phy0 3>;
522
+
phy-names = "usb";
523
+
power-domains = <&cpg>;
524
+
status = "disabled";
832
525
};
833
526
834
527
wdt0: watchdog@12800800 {
528
+
compatible = "renesas,r9a07g054-wdt",
529
+
"renesas,rzg2l-wdt";
835
530
reg = <0 0x12800800 0 0x400>;
836
-
/* place holder */
531
+
clocks = <&cpg CPG_MOD R9A07G054_WDT0_PCLK>,
532
+
<&cpg CPG_MOD R9A07G054_WDT0_CLK>;
533
+
clock-names = "pclk", "oscclk";
534
+
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
535
+
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
536
+
interrupt-names = "wdt", "perrout";
537
+
resets = <&cpg R9A07G054_WDT0_PRESETN>;
538
+
power-domains = <&cpg>;
539
+
status = "disabled";
837
540
};
838
541
839
542
wdt1: watchdog@12800c00 {
543
+
compatible = "renesas,r9a07g054-wdt",
544
+
"renesas,rzg2l-wdt";
840
545
reg = <0 0x12800C00 0 0x400>;
841
-
/* place holder */
546
+
clocks = <&cpg CPG_MOD R9A07G054_WDT1_PCLK>,
547
+
<&cpg CPG_MOD R9A07G054_WDT1_CLK>;
548
+
clock-names = "pclk", "oscclk";
549
+
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
550
+
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
551
+
interrupt-names = "wdt", "perrout";
552
+
resets = <&cpg R9A07G054_WDT1_PRESETN>;
553
+
power-domains = <&cpg>;
554
+
status = "disabled";
842
555
};
843
556
844
557
wdt2: watchdog@12800400 {
558
+
compatible = "renesas,r9a07g054-wdt",
559
+
"renesas,rzg2l-wdt";
845
560
reg = <0 0x12800400 0 0x400>;
846
-
/* place holder */
561
+
clocks = <&cpg CPG_MOD R9A07G054_WDT2_PCLK>,
562
+
<&cpg CPG_MOD R9A07G054_WDT2_CLK>;
563
+
clock-names = "pclk", "oscclk";
564
+
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
565
+
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
566
+
interrupt-names = "wdt", "perrout";
567
+
resets = <&cpg R9A07G054_WDT2_PRESETN>;
568
+
power-domains = <&cpg>;
569
+
status = "disabled";
847
570
};
848
571
849
572
ostm0: timer@12801000 {
573
+
compatible = "renesas,r9a07g054-ostm",
574
+
"renesas,ostm";
850
575
reg = <0x0 0x12801000 0x0 0x400>;
851
-
/* place holder */
576
+
interrupts = <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>;
577
+
clocks = <&cpg CPG_MOD R9A07G054_OSTM0_PCLK>;
578
+
resets = <&cpg R9A07G054_OSTM0_PRESETZ>;
579
+
power-domains = <&cpg>;
580
+
status = "disabled";
852
581
};
853
582
854
583
ostm1: timer@12801400 {
584
+
compatible = "renesas,r9a07g054-ostm",
585
+
"renesas,ostm";
855
586
reg = <0x0 0x12801400 0x0 0x400>;
856
-
/* place holder */
587
+
interrupts = <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>;
588
+
clocks = <&cpg CPG_MOD R9A07G054_OSTM1_PCLK>;
589
+
resets = <&cpg R9A07G054_OSTM1_PRESETZ>;
590
+
power-domains = <&cpg>;
591
+
status = "disabled";
857
592
};
858
593
859
594
ostm2: timer@12801800 {
595
+
compatible = "renesas,r9a07g054-ostm",
596
+
"renesas,ostm";
860
597
reg = <0x0 0x12801800 0x0 0x400>;
861
-
/* place holder */
598
+
interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>;
599
+
clocks = <&cpg CPG_MOD R9A07G054_OSTM2_PCLK>;
600
+
resets = <&cpg R9A07G054_OSTM2_PRESETZ>;
601
+
power-domains = <&cpg>;
602
+
status = "disabled";
603
+
};
604
+
};
605
+
606
+
thermal-zones {
607
+
cpu-thermal {
608
+
polling-delay-passive = <250>;
609
+
polling-delay = <1000>;
610
+
thermal-sensors = <&tsu 0>;
611
+
sustainable-power = <717>;
612
+
613
+
cooling-maps {
614
+
map0 {
615
+
trip = <&target>;
616
+
cooling-device = <&cpu0 0 2>;
617
+
contribution = <1024>;
618
+
};
619
+
};
620
+
621
+
trips {
622
+
sensor_crit: sensor-crit {
623
+
temperature = <125000>;
624
+
hysteresis = <1000>;
625
+
type = "critical";
626
+
};
627
+
628
+
target: trip-point {
629
+
temperature = <100000>;
630
+
hysteresis = <1000>;
631
+
type = "passive";
632
+
};
633
+
};
862
634
};
863
635
};
864
636
-8
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
-8
arch/arm64/boot/dts/renesas/r9a07g054l2-smarc.dts
···
16
16
model = "Renesas SMARC EVK based on r9a07g054l2";
17
17
compatible = "renesas,smarc-evk", "renesas,r9a07g054l2", "renesas,r9a07g054";
18
18
};
19
-
20
-
&pinctrl {
21
-
/delete-node/ can0-stb-hog;
22
-
/delete-node/ can1-stb-hog;
23
-
/delete-node/ gpio-sd0-pwr-en-hog;
24
-
/delete-node/ sd0-dev-sel-hog;
25
-
/delete-node/ sd1-pwr-en-hog;
26
-
};
-16
arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
-16
arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi
···
26
26
serial0 = &scif0;
27
27
i2c0 = &i2c0;
28
28
i2c1 = &i2c1;
29
-
i2c3 = &i2c3;
30
29
};
31
30
32
31
chosen {
···
74
75
regulator-name = "SDHI1 VccQ";
75
76
regulator-min-microvolt = <1800000>;
76
77
regulator-max-microvolt = <3300000>;
77
-
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
78
78
gpios-states = <1>;
79
79
states = <3300000 1>, <1800000 0>;
80
80
};
···
127
129
pinctrl-names = "default";
128
130
129
131
status = "okay";
130
-
};
131
-
132
-
&i2c3 {
133
-
pinctrl-0 = <&i2c3_pins>;
134
-
pinctrl-names = "default";
135
-
clock-frequency = <400000>;
136
-
137
-
status = "okay";
138
-
139
-
wm8978: codec@1a {
140
-
compatible = "wlf,wm8978";
141
-
#sound-dai-cells = <0>;
142
-
reg = <0x1a>;
143
-
};
144
132
};
145
133
146
134
&ohci0 {
+19
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
+19
arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi
···
14
14
/ {
15
15
aliases {
16
16
serial1 = &scif2;
17
+
i2c3 = &i2c3;
18
+
};
19
+
};
20
+
21
+
&i2c3 {
22
+
pinctrl-0 = <&i2c3_pins>;
23
+
pinctrl-names = "default";
24
+
clock-frequency = <400000>;
25
+
26
+
status = "okay";
27
+
28
+
wm8978: codec@1a {
29
+
compatible = "wlf,wm8978";
30
+
#sound-dai-cells = <0>;
31
+
reg = <0x1a>;
17
32
};
18
33
};
19
34
···
48
33
status = "okay";
49
34
};
50
35
#endif
36
+
37
+
&vccq_sdhi1 {
38
+
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
39
+
};
+52
-12
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
+52
-12
arch/arm64/boot/dts/renesas/rzg2lc-smarc-pinfunction.dtsi
···
12
12
pinctrl-0 = <&sound_clk_pins>;
13
13
pinctrl-names = "default";
14
14
15
-
scif0_pins: scif0 {
16
-
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
17
-
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
18
-
};
19
-
20
15
#if SW_SCIF_CAN
21
16
/* SW8 should be at position 2->1 */
22
17
can1_pins: can1 {
···
19
24
<RZG2L_PORT_PINMUX(40, 1, 3)>; /* RxD */
20
25
};
21
26
#endif
22
-
23
-
scif1_pins: scif1 {
24
-
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
25
-
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
26
-
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
27
-
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
28
-
};
29
27
30
28
#if SW_RSPI_CAN
31
29
/* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
···
34
46
<RZG2L_PORT_PINMUX(44, 1, 3)>; /* RxD */
35
47
};
36
48
#endif
49
+
50
+
i2c0_pins: i2c0 {
51
+
pins = "RIIC0_SDA", "RIIC0_SCL";
52
+
input-enable;
53
+
};
54
+
55
+
i2c1_pins: i2c1 {
56
+
pins = "RIIC1_SDA", "RIIC1_SCL";
57
+
input-enable;
58
+
};
59
+
60
+
i2c2_pins: i2c2 {
61
+
pinmux = <RZG2L_PORT_PINMUX(42, 3, 1)>, /* SDA */
62
+
<RZG2L_PORT_PINMUX(42, 4, 1)>; /* SCL */
63
+
};
64
+
65
+
scif0_pins: scif0 {
66
+
pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* TxD */
67
+
<RZG2L_PORT_PINMUX(38, 1, 1)>; /* RxD */
68
+
};
69
+
70
+
scif1_pins: scif1 {
71
+
pinmux = <RZG2L_PORT_PINMUX(40, 0, 1)>, /* TxD */
72
+
<RZG2L_PORT_PINMUX(40, 1, 1)>, /* RxD */
73
+
<RZG2L_PORT_PINMUX(41, 0, 1)>, /* CTS# */
74
+
<RZG2L_PORT_PINMUX(41, 1, 1)>; /* RTS# */
75
+
};
37
76
38
77
sd1-pwr-en-hog {
39
78
gpio-hog;
···
104
89
sound_clk_pins: sound_clk {
105
90
pins = "AUDIO_CLK1", "AUDIO_CLK2";
106
91
input-enable;
92
+
};
93
+
94
+
spi1_pins: spi1 {
95
+
pinmux = <RZG2L_PORT_PINMUX(44, 0, 1)>, /* CK */
96
+
<RZG2L_PORT_PINMUX(44, 1, 1)>, /* MOSI */
97
+
<RZG2L_PORT_PINMUX(44, 2, 1)>, /* MISO */
98
+
<RZG2L_PORT_PINMUX(44, 3, 1)>; /* SSL */
99
+
};
100
+
101
+
ssi0_pins: ssi0 {
102
+
pinmux = <RZG2L_PORT_PINMUX(45, 0, 1)>, /* BCK */
103
+
<RZG2L_PORT_PINMUX(45, 1, 1)>, /* RCK */
104
+
<RZG2L_PORT_PINMUX(45, 2, 1)>, /* TXD */
105
+
<RZG2L_PORT_PINMUX(45, 3, 1)>; /* RXD */
106
+
};
107
+
108
+
usb0_pins: usb0 {
109
+
pinmux = <RZG2L_PORT_PINMUX(4, 0, 1)>, /* VBUS */
110
+
<RZG2L_PORT_PINMUX(5, 0, 1)>, /* OVC */
111
+
<RZG2L_PORT_PINMUX(5, 1, 1)>; /* OTG_ID */
112
+
};
113
+
114
+
usb1_pins: usb1 {
115
+
pinmux = <RZG2L_PORT_PINMUX(42, 0, 1)>, /* VBUS */
116
+
<RZG2L_PORT_PINMUX(42, 1, 1)>; /* OVC */
107
117
};
108
118
};
109
119
+61
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
+61
arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi
···
41
41
regulator-always-on;
42
42
};
43
43
44
+
reg_1p1v: regulator-vdd-core {
45
+
compatible = "regulator-fixed";
46
+
regulator-name = "fixed-1.1V";
47
+
regulator-min-microvolt = <1100000>;
48
+
regulator-max-microvolt = <1100000>;
49
+
regulator-boot-on;
50
+
regulator-always-on;
51
+
};
52
+
44
53
vccq_sdhi0: regulator-vccq-sdhi0 {
45
54
compatible = "regulator-gpio";
46
55
···
93
84
clock-frequency = <24000000>;
94
85
};
95
86
87
+
&gpu {
88
+
mali-supply = <®_1p1v>;
89
+
};
90
+
91
+
&ostm1 {
92
+
status = "okay";
93
+
};
94
+
95
+
&ostm2 {
96
+
status = "okay";
97
+
};
98
+
96
99
&pinctrl {
97
100
eth0_pins: eth0 {
98
101
pinmux = <RZG2L_PORT_PINMUX(28, 1, 1)>, /* ET0_LINKSTA */
···
129
108
gpios = <RZG2L_GPIO(18, 1) GPIO_ACTIVE_HIGH>;
130
109
output-high;
131
110
line-name = "gpio_sd0_pwr_en";
111
+
};
112
+
113
+
qspi0_pins: qspi0 {
114
+
qspi0-data {
115
+
pins = "QSPI0_IO0", "QSPI0_IO1", "QSPI0_IO2", "QSPI0_IO3";
116
+
power-source = <1800>;
117
+
};
118
+
119
+
qspi0-ctrl {
120
+
pins = "QSPI0_SPCLK", "QSPI0_SSL", "QSPI_RESET#";
121
+
power-source = <1800>;
122
+
};
132
123
};
133
124
134
125
/*
···
204
171
205
172
sd0_mux_uhs {
206
173
pinmux = <RZG2L_PORT_PINMUX(18, 0, 1)>; /* SD0_CD */
174
+
};
175
+
};
176
+
};
177
+
178
+
&sbc {
179
+
pinctrl-0 = <&qspi0_pins>;
180
+
pinctrl-names = "default";
181
+
status = "okay";
182
+
183
+
flash@0 {
184
+
compatible = "micron,mt25qu512a", "jedec,spi-nor";
185
+
reg = <0>;
186
+
m25p,fast-read;
187
+
spi-max-frequency = <50000000>;
188
+
spi-rx-bus-width = <4>;
189
+
190
+
partitions {
191
+
compatible = "fixed-partitions";
192
+
#address-cells = <1>;
193
+
#size-cells = <1>;
194
+
195
+
boot@0 {
196
+
reg = <0x00000000 0x2000000>;
197
+
read-only;
198
+
};
199
+
user@2000000 {
200
+
reg = <0x2000000 0x2000000>;
201
+
};
207
202
};
208
203
};
209
204
};
+27
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
+27
arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi
···
43
43
/ {
44
44
aliases {
45
45
serial1 = &scif1;
46
+
i2c2 = &i2c2;
46
47
};
47
48
};
48
49
···
59
58
status = "disabled";
60
59
};
61
60
#endif
61
+
62
+
&i2c2 {
63
+
pinctrl-0 = <&i2c2_pins>;
64
+
pinctrl-names = "default";
65
+
clock-frequency = <400000>;
66
+
67
+
status = "okay";
68
+
69
+
wm8978: codec@1a {
70
+
compatible = "wlf,wm8978";
71
+
#sound-dai-cells = <0>;
72
+
reg = <0x1a>;
73
+
};
74
+
};
62
75
63
76
/*
64
77
* To enable SCIF1 (SER0) on PMOD1 (CN7), On connector board
···
90
75
status = "okay";
91
76
};
92
77
#endif
78
+
79
+
#if (SW_RSPI_CAN)
80
+
&spi1 {
81
+
/delete-property/ pinctrl-0;
82
+
/delete-property/ pinctrl-names;
83
+
status = "disabled";
84
+
};
85
+
#endif
86
+
87
+
&vccq_sdhi1 {
88
+
gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>;
89
+
};
+63
arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
+63
arch/arm64/boot/dts/renesas/rzg2ul-smarc-pinfunction.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/G2UL SMARC pincontrol parts
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <dt-bindings/gpio/gpio.h>
9
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
+
11
+
&pinctrl {
12
+
pinctrl-0 = <&sound_clk_pins>;
13
+
pinctrl-names = "default";
14
+
15
+
scif0_pins: scif0 {
16
+
pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
17
+
<RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */
18
+
};
19
+
20
+
sd1-pwr-en-hog {
21
+
gpio-hog;
22
+
gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_HIGH>;
23
+
output-high;
24
+
line-name = "sd1_pwr_en";
25
+
};
26
+
27
+
sdhi1_pins: sd1 {
28
+
sd1_data {
29
+
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
30
+
power-source = <3300>;
31
+
};
32
+
33
+
sd1_ctrl {
34
+
pins = "SD1_CLK", "SD1_CMD";
35
+
power-source = <3300>;
36
+
};
37
+
38
+
sd1_mux {
39
+
pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
40
+
};
41
+
};
42
+
43
+
sdhi1_pins_uhs: sd1_uhs {
44
+
sd1_data_uhs {
45
+
pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
46
+
power-source = <1800>;
47
+
};
48
+
49
+
sd1_ctrl_uhs {
50
+
pins = "SD1_CLK", "SD1_CMD";
51
+
power-source = <1800>;
52
+
};
53
+
54
+
sd1_mux_uhs {
55
+
pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
56
+
};
57
+
};
58
+
59
+
sound_clk_pins: sound_clk {
60
+
pins = "AUDIO_CLK1", "AUDIO_CLK2";
61
+
input-enable;
62
+
};
63
+
};
+233
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
+233
arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/G2UL SMARC SOM common parts
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
#include <dt-bindings/gpio/gpio.h>
9
+
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
+
11
+
/ {
12
+
aliases {
13
+
ethernet0 = ð0;
14
+
ethernet1 = ð1;
15
+
};
16
+
17
+
chosen {
18
+
bootargs = "ignore_loglevel rw root=/dev/nfs ip=on";
19
+
};
20
+
21
+
memory@48000000 {
22
+
device_type = "memory";
23
+
/* first 128MB is reserved for secure area. */
24
+
reg = <0x0 0x48000000 0x0 0x38000000>;
25
+
};
26
+
27
+
reg_1p8v: regulator0 {
28
+
compatible = "regulator-fixed";
29
+
regulator-name = "fixed-1.8V";
30
+
regulator-min-microvolt = <1800000>;
31
+
regulator-max-microvolt = <1800000>;
32
+
regulator-boot-on;
33
+
regulator-always-on;
34
+
};
35
+
36
+
reg_3p3v: regulator1 {
37
+
compatible = "regulator-fixed";
38
+
regulator-name = "fixed-3.3V";
39
+
regulator-min-microvolt = <3300000>;
40
+
regulator-max-microvolt = <3300000>;
41
+
regulator-boot-on;
42
+
regulator-always-on;
43
+
};
44
+
45
+
#if !(SW_SW0_DEV_SEL)
46
+
vccq_sdhi0: regulator-vccq-sdhi0 {
47
+
compatible = "regulator-gpio";
48
+
49
+
regulator-name = "SDHI0 VccQ";
50
+
regulator-min-microvolt = <1800000>;
51
+
regulator-max-microvolt = <3300000>;
52
+
states = <3300000 1>, <1800000 0>;
53
+
regulator-boot-on;
54
+
gpios = <&pinctrl RZG2L_GPIO(6, 2) GPIO_ACTIVE_HIGH>;
55
+
regulator-always-on;
56
+
};
57
+
#endif
58
+
};
59
+
60
+
#if (!SW_ET0_EN_N)
61
+
ð0 {
62
+
pinctrl-0 = <ð0_pins>;
63
+
pinctrl-names = "default";
64
+
phy-handle = <&phy0>;
65
+
phy-mode = "rgmii-id";
66
+
status = "okay";
67
+
68
+
phy0: ethernet-phy@7 {
69
+
compatible = "ethernet-phy-id0022.1640",
70
+
"ethernet-phy-ieee802.3-c22";
71
+
reg = <7>;
72
+
rxc-skew-psec = <2400>;
73
+
txc-skew-psec = <2400>;
74
+
rxdv-skew-psec = <0>;
75
+
txdv-skew-psec = <0>;
76
+
rxd0-skew-psec = <0>;
77
+
rxd1-skew-psec = <0>;
78
+
rxd2-skew-psec = <0>;
79
+
rxd3-skew-psec = <0>;
80
+
txd0-skew-psec = <0>;
81
+
txd1-skew-psec = <0>;
82
+
txd2-skew-psec = <0>;
83
+
txd3-skew-psec = <0>;
84
+
};
85
+
};
86
+
#endif
87
+
88
+
ð1 {
89
+
pinctrl-0 = <ð1_pins>;
90
+
pinctrl-names = "default";
91
+
phy-handle = <&phy1>;
92
+
phy-mode = "rgmii-id";
93
+
status = "okay";
94
+
95
+
phy1: ethernet-phy@7 {
96
+
compatible = "ethernet-phy-id0022.1640",
97
+
"ethernet-phy-ieee802.3-c22";
98
+
reg = <7>;
99
+
rxc-skew-psec = <2400>;
100
+
txc-skew-psec = <2400>;
101
+
rxdv-skew-psec = <0>;
102
+
txdv-skew-psec = <0>;
103
+
rxd0-skew-psec = <0>;
104
+
rxd1-skew-psec = <0>;
105
+
rxd2-skew-psec = <0>;
106
+
rxd3-skew-psec = <0>;
107
+
txd0-skew-psec = <0>;
108
+
txd1-skew-psec = <0>;
109
+
txd2-skew-psec = <0>;
110
+
txd3-skew-psec = <0>;
111
+
};
112
+
};
113
+
114
+
&extal_clk {
115
+
clock-frequency = <24000000>;
116
+
};
117
+
118
+
&pinctrl {
119
+
eth0_pins: eth0 {
120
+
pinmux = <RZG2L_PORT_PINMUX(4, 5, 1)>, /* ET0_LINKSTA */
121
+
<RZG2L_PORT_PINMUX(4, 3, 1)>, /* ET0_MDC */
122
+
<RZG2L_PORT_PINMUX(4, 4, 1)>, /* ET0_MDIO */
123
+
<RZG2L_PORT_PINMUX(1, 0, 1)>, /* ET0_TXC */
124
+
<RZG2L_PORT_PINMUX(1, 1, 1)>, /* ET0_TX_CTL */
125
+
<RZG2L_PORT_PINMUX(1, 2, 1)>, /* ET0_TXD0 */
126
+
<RZG2L_PORT_PINMUX(1, 3, 1)>, /* ET0_TXD1 */
127
+
<RZG2L_PORT_PINMUX(1, 4, 1)>, /* ET0_TXD2 */
128
+
<RZG2L_PORT_PINMUX(2, 0, 1)>, /* ET0_TXD3 */
129
+
<RZG2L_PORT_PINMUX(3, 0, 1)>, /* ET0_RXC */
130
+
<RZG2L_PORT_PINMUX(3, 1, 1)>, /* ET0_RX_CTL */
131
+
<RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
132
+
<RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
133
+
<RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
134
+
<RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
135
+
};
136
+
137
+
eth1_pins: eth1 {
138
+
pinmux = <RZG2L_PORT_PINMUX(10, 4, 1)>, /* ET1_LINKSTA */
139
+
<RZG2L_PORT_PINMUX(10, 2, 1)>, /* ET1_MDC */
140
+
<RZG2L_PORT_PINMUX(10, 3, 1)>, /* ET1_MDIO */
141
+
<RZG2L_PORT_PINMUX(7, 0, 1)>, /* ET1_TXC */
142
+
<RZG2L_PORT_PINMUX(7, 1, 1)>, /* ET1_TX_CTL */
143
+
<RZG2L_PORT_PINMUX(7, 2, 1)>, /* ET1_TXD0 */
144
+
<RZG2L_PORT_PINMUX(7, 3, 1)>, /* ET1_TXD1 */
145
+
<RZG2L_PORT_PINMUX(7, 4, 1)>, /* ET1_TXD2 */
146
+
<RZG2L_PORT_PINMUX(8, 0, 1)>, /* ET1_TXD3 */
147
+
<RZG2L_PORT_PINMUX(8, 4, 1)>, /* ET1_RXC */
148
+
<RZG2L_PORT_PINMUX(9, 0, 1)>, /* ET1_RX_CTL */
149
+
<RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
150
+
<RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
151
+
<RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
152
+
<RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
153
+
};
154
+
155
+
sdhi0_emmc_pins: sd0emmc {
156
+
sd0_emmc_data {
157
+
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3",
158
+
"SD0_DATA4", "SD0_DATA5", "SD0_DATA6", "SD0_DATA7";
159
+
power-source = <1800>;
160
+
};
161
+
162
+
sd0_emmc_ctrl {
163
+
pins = "SD0_CLK", "SD0_CMD";
164
+
power-source = <1800>;
165
+
};
166
+
167
+
sd0_emmc_rst {
168
+
pins = "SD0_RST#";
169
+
power-source = <1800>;
170
+
};
171
+
};
172
+
173
+
sdhi0_pins: sd0 {
174
+
sd0_data {
175
+
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
176
+
power-source = <3300>;
177
+
};
178
+
179
+
sd0_ctrl {
180
+
pins = "SD0_CLK", "SD0_CMD";
181
+
power-source = <3300>;
182
+
};
183
+
184
+
sd0_mux {
185
+
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
186
+
};
187
+
};
188
+
189
+
sdhi0_pins_uhs: sd0_uhs {
190
+
sd0_data_uhs {
191
+
pins = "SD0_DATA0", "SD0_DATA1", "SD0_DATA2", "SD0_DATA3";
192
+
power-source = <1800>;
193
+
};
194
+
195
+
sd0_ctrl_uhs {
196
+
pins = "SD0_CLK", "SD0_CMD";
197
+
power-source = <1800>;
198
+
};
199
+
200
+
sd0_mux_uhs {
201
+
pinmux = <RZG2L_PORT_PINMUX(0, 0, 1)>; /* SD0_CD */
202
+
};
203
+
};
204
+
};
205
+
206
+
#if (SW_SW0_DEV_SEL)
207
+
&sdhi0 {
208
+
pinctrl-0 = <&sdhi0_emmc_pins>;
209
+
pinctrl-1 = <&sdhi0_emmc_pins>;
210
+
pinctrl-names = "default", "state_uhs";
211
+
212
+
vmmc-supply = <®_3p3v>;
213
+
vqmmc-supply = <®_1p8v>;
214
+
bus-width = <8>;
215
+
mmc-hs200-1_8v;
216
+
non-removable;
217
+
fixed-emmc-driver-type = <1>;
218
+
status = "okay";
219
+
};
220
+
#else
221
+
&sdhi0 {
222
+
pinctrl-0 = <&sdhi0_pins>;
223
+
pinctrl-1 = <&sdhi0_pins_uhs>;
224
+
pinctrl-names = "default", "state_uhs";
225
+
226
+
vmmc-supply = <®_3p3v>;
227
+
vqmmc-supply = <&vccq_sdhi0>;
228
+
bus-width = <4>;
229
+
sd-uhs-sdr50;
230
+
sd-uhs-sdr104;
231
+
status = "okay";
232
+
};
233
+
#endif
+24
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
+24
arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi
···
1
+
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
/*
3
+
* Device Tree Source for the RZ/G2UL Type-1 SMARC EVK parts
4
+
*
5
+
* Copyright (C) 2022 Renesas Electronics Corp.
6
+
*/
7
+
8
+
/*
9
+
* DIP-Switch SW1 setting
10
+
* 1 : High; 0: Low
11
+
* SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC)
12
+
* SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1)
13
+
* Please change below macros according to SW1 setting
14
+
*/
15
+
#define SW_SW0_DEV_SEL 1
16
+
#define SW_ET0_EN_N 1
17
+
18
+
#include "rzg2ul-smarc-som.dtsi"
19
+
#include "rzg2ul-smarc-pinfunction.dtsi"
20
+
#include "rz-smarc-common.dtsi"
21
+
22
+
&vccq_sdhi1 {
23
+
gpios = <&pinctrl RZG2L_GPIO(6, 1) GPIO_ACTIVE_HIGH>;
24
+
};
+49
arch/arm64/boot/dts/renesas/salvator-common.dtsi
+49
arch/arm64/boot/dts/renesas/salvator-common.dtsi
···
866
866
};
867
867
};
868
868
869
+
&rpc {
870
+
/* Left disabled. To be enabled by firmware when unlocked. */
871
+
872
+
flash@0 {
873
+
compatible = "cypress,hyperflash", "cfi-flash";
874
+
reg = <0>;
875
+
876
+
partitions {
877
+
compatible = "fixed-partitions";
878
+
#address-cells = <1>;
879
+
#size-cells = <1>;
880
+
881
+
bootparam@0 {
882
+
reg = <0x00000000 0x040000>;
883
+
read-only;
884
+
};
885
+
bl2@40000 {
886
+
reg = <0x00040000 0x140000>;
887
+
read-only;
888
+
};
889
+
cert_header_sa6@180000 {
890
+
reg = <0x00180000 0x040000>;
891
+
read-only;
892
+
};
893
+
bl31@1c0000 {
894
+
reg = <0x001c0000 0x040000>;
895
+
read-only;
896
+
};
897
+
tee@200000 {
898
+
reg = <0x00200000 0x440000>;
899
+
read-only;
900
+
};
901
+
uboot@640000 {
902
+
reg = <0x00640000 0x100000>;
903
+
read-only;
904
+
};
905
+
dtb@740000 {
906
+
reg = <0x00740000 0x080000>;
907
+
};
908
+
kernel@7c0000 {
909
+
reg = <0x007c0000 0x1400000>;
910
+
};
911
+
user@1bc0000 {
912
+
reg = <0x01bc0000 0x2440000>;
913
+
};
914
+
};
915
+
};
916
+
};
917
+
869
918
&rwdt {
870
919
timeout-sec = <60>;
871
920
status = "okay";
+49
arch/arm64/boot/dts/renesas/ulcb.dtsi
+49
arch/arm64/boot/dts/renesas/ulcb.dtsi
···
426
426
};
427
427
};
428
428
429
+
&rpc {
430
+
/* Left disabled. To be enabled by firmware when unlocked. */
431
+
432
+
flash@0 {
433
+
compatible = "cypress,hyperflash", "cfi-flash";
434
+
reg = <0>;
435
+
436
+
partitions {
437
+
compatible = "fixed-partitions";
438
+
#address-cells = <1>;
439
+
#size-cells = <1>;
440
+
441
+
bootparam@0 {
442
+
reg = <0x00000000 0x040000>;
443
+
read-only;
444
+
};
445
+
bl2@40000 {
446
+
reg = <0x00040000 0x140000>;
447
+
read-only;
448
+
};
449
+
cert_header_sa6@180000 {
450
+
reg = <0x00180000 0x040000>;
451
+
read-only;
452
+
};
453
+
bl31@1c0000 {
454
+
reg = <0x001c0000 0x040000>;
455
+
read-only;
456
+
};
457
+
tee@200000 {
458
+
reg = <0x00200000 0x440000>;
459
+
read-only;
460
+
};
461
+
uboot@640000 {
462
+
reg = <0x00640000 0x100000>;
463
+
read-only;
464
+
};
465
+
dtb@740000 {
466
+
reg = <0x00740000 0x080000>;
467
+
};
468
+
kernel@7c0000 {
469
+
reg = <0x007c0000 0x1400000>;
470
+
};
471
+
user@1bc0000 {
472
+
reg = <0x01bc0000 0x2440000>;
473
+
};
474
+
};
475
+
};
476
+
};
477
+
429
478
&rwdt {
430
479
timeout-sec = <60>;
431
480
status = "okay";
+184
include/dt-bindings/clock/r9a07g043-cpg.h
+184
include/dt-bindings/clock/r9a07g043-cpg.h
···
1
+
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2
+
*
3
+
* Copyright (C) 2022 Renesas Electronics Corp.
4
+
*/
5
+
#ifndef __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
6
+
#define __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__
7
+
8
+
#include <dt-bindings/clock/renesas-cpg-mssr.h>
9
+
10
+
/* R9A07G043 CPG Core Clocks */
11
+
#define R9A07G043_CLK_I 0
12
+
#define R9A07G043_CLK_I2 1
13
+
#define R9A07G043_CLK_S0 2
14
+
#define R9A07G043_CLK_SPI0 3
15
+
#define R9A07G043_CLK_SPI1 4
16
+
#define R9A07G043_CLK_SD0 5
17
+
#define R9A07G043_CLK_SD1 6
18
+
#define R9A07G043_CLK_M0 7
19
+
#define R9A07G043_CLK_M2 8
20
+
#define R9A07G043_CLK_M3 9
21
+
#define R9A07G043_CLK_HP 10
22
+
#define R9A07G043_CLK_TSU 11
23
+
#define R9A07G043_CLK_ZT 12
24
+
#define R9A07G043_CLK_P0 13
25
+
#define R9A07G043_CLK_P1 14
26
+
#define R9A07G043_CLK_P2 15
27
+
#define R9A07G043_CLK_AT 16
28
+
#define R9A07G043_OSCCLK 17
29
+
#define R9A07G043_CLK_P0_DIV2 18
30
+
31
+
/* R9A07G043 Module Clocks */
32
+
#define R9A07G043_CA55_SCLK 0 /* RZ/G2UL Only */
33
+
#define R9A07G043_CA55_PCLK 1 /* RZ/G2UL Only */
34
+
#define R9A07G043_CA55_ATCLK 2 /* RZ/G2UL Only */
35
+
#define R9A07G043_CA55_GICCLK 3 /* RZ/G2UL Only */
36
+
#define R9A07G043_CA55_PERICLK 4 /* RZ/G2UL Only */
37
+
#define R9A07G043_CA55_ACLK 5 /* RZ/G2UL Only */
38
+
#define R9A07G043_CA55_TSCLK 6 /* RZ/G2UL Only */
39
+
#define R9A07G043_GIC600_GICCLK 7 /* RZ/G2UL Only */
40
+
#define R9A07G043_IA55_CLK 8 /* RZ/G2UL Only */
41
+
#define R9A07G043_IA55_PCLK 9 /* RZ/G2UL Only */
42
+
#define R9A07G043_MHU_PCLK 10 /* RZ/G2UL Only */
43
+
#define R9A07G043_SYC_CNT_CLK 11
44
+
#define R9A07G043_DMAC_ACLK 12
45
+
#define R9A07G043_DMAC_PCLK 13
46
+
#define R9A07G043_OSTM0_PCLK 14
47
+
#define R9A07G043_OSTM1_PCLK 15
48
+
#define R9A07G043_OSTM2_PCLK 16
49
+
#define R9A07G043_MTU_X_MCK_MTU3 17
50
+
#define R9A07G043_POE3_CLKM_POE 18
51
+
#define R9A07G043_WDT0_PCLK 19
52
+
#define R9A07G043_WDT0_CLK 20
53
+
#define R9A07G043_WDT2_PCLK 21 /* RZ/G2UL Only */
54
+
#define R9A07G043_WDT2_CLK 22 /* RZ/G2UL Only */
55
+
#define R9A07G043_SPI_CLK2 23
56
+
#define R9A07G043_SPI_CLK 24
57
+
#define R9A07G043_SDHI0_IMCLK 25
58
+
#define R9A07G043_SDHI0_IMCLK2 26
59
+
#define R9A07G043_SDHI0_CLK_HS 27
60
+
#define R9A07G043_SDHI0_ACLK 28
61
+
#define R9A07G043_SDHI1_IMCLK 29
62
+
#define R9A07G043_SDHI1_IMCLK2 30
63
+
#define R9A07G043_SDHI1_CLK_HS 31
64
+
#define R9A07G043_SDHI1_ACLK 32
65
+
#define R9A07G043_ISU_ACLK 33 /* RZ/G2UL Only */
66
+
#define R9A07G043_ISU_PCLK 34 /* RZ/G2UL Only */
67
+
#define R9A07G043_CRU_SYSCLK 35 /* RZ/G2UL Only */
68
+
#define R9A07G043_CRU_VCLK 36 /* RZ/G2UL Only */
69
+
#define R9A07G043_CRU_PCLK 37 /* RZ/G2UL Only */
70
+
#define R9A07G043_CRU_ACLK 38 /* RZ/G2UL Only */
71
+
#define R9A07G043_LCDC_CLK_A 39 /* RZ/G2UL Only */
72
+
#define R9A07G043_LCDC_CLK_P 40 /* RZ/G2UL Only */
73
+
#define R9A07G043_LCDC_CLK_D 41 /* RZ/G2UL Only */
74
+
#define R9A07G043_SSI0_PCLK2 42
75
+
#define R9A07G043_SSI0_PCLK_SFR 43
76
+
#define R9A07G043_SSI1_PCLK2 44
77
+
#define R9A07G043_SSI1_PCLK_SFR 45
78
+
#define R9A07G043_SSI2_PCLK2 46
79
+
#define R9A07G043_SSI2_PCLK_SFR 47
80
+
#define R9A07G043_SSI3_PCLK2 48
81
+
#define R9A07G043_SSI3_PCLK_SFR 49
82
+
#define R9A07G043_SRC_CLKP 50 /* RZ/G2UL Only */
83
+
#define R9A07G043_USB_U2H0_HCLK 51
84
+
#define R9A07G043_USB_U2H1_HCLK 52
85
+
#define R9A07G043_USB_U2P_EXR_CPUCLK 53
86
+
#define R9A07G043_USB_PCLK 54
87
+
#define R9A07G043_ETH0_CLK_AXI 55
88
+
#define R9A07G043_ETH0_CLK_CHI 56
89
+
#define R9A07G043_ETH1_CLK_AXI 57
90
+
#define R9A07G043_ETH1_CLK_CHI 58
91
+
#define R9A07G043_I2C0_PCLK 59
92
+
#define R9A07G043_I2C1_PCLK 60
93
+
#define R9A07G043_I2C2_PCLK 61
94
+
#define R9A07G043_I2C3_PCLK 62
95
+
#define R9A07G043_SCIF0_CLK_PCK 63
96
+
#define R9A07G043_SCIF1_CLK_PCK 64
97
+
#define R9A07G043_SCIF2_CLK_PCK 65
98
+
#define R9A07G043_SCIF3_CLK_PCK 66
99
+
#define R9A07G043_SCIF4_CLK_PCK 67
100
+
#define R9A07G043_SCI0_CLKP 68
101
+
#define R9A07G043_SCI1_CLKP 69
102
+
#define R9A07G043_IRDA_CLKP 70
103
+
#define R9A07G043_RSPI0_CLKB 71
104
+
#define R9A07G043_RSPI1_CLKB 72
105
+
#define R9A07G043_RSPI2_CLKB 73
106
+
#define R9A07G043_CANFD_PCLK 74
107
+
#define R9A07G043_GPIO_HCLK 75
108
+
#define R9A07G043_ADC_ADCLK 76
109
+
#define R9A07G043_ADC_PCLK 77
110
+
#define R9A07G043_TSU_PCLK 78
111
+
112
+
/* R9A07G043 Resets */
113
+
#define R9A07G043_CA55_RST_1_0 0 /* RZ/G2UL Only */
114
+
#define R9A07G043_CA55_RST_1_1 1 /* RZ/G2UL Only */
115
+
#define R9A07G043_CA55_RST_3_0 2 /* RZ/G2UL Only */
116
+
#define R9A07G043_CA55_RST_3_1 3 /* RZ/G2UL Only */
117
+
#define R9A07G043_CA55_RST_4 4 /* RZ/G2UL Only */
118
+
#define R9A07G043_CA55_RST_5 5 /* RZ/G2UL Only */
119
+
#define R9A07G043_CA55_RST_6 6 /* RZ/G2UL Only */
120
+
#define R9A07G043_CA55_RST_7 7 /* RZ/G2UL Only */
121
+
#define R9A07G043_CA55_RST_8 8 /* RZ/G2UL Only */
122
+
#define R9A07G043_CA55_RST_9 9 /* RZ/G2UL Only */
123
+
#define R9A07G043_CA55_RST_10 10 /* RZ/G2UL Only */
124
+
#define R9A07G043_CA55_RST_11 11 /* RZ/G2UL Only */
125
+
#define R9A07G043_CA55_RST_12 12 /* RZ/G2UL Only */
126
+
#define R9A07G043_GIC600_GICRESET_N 13 /* RZ/G2UL Only */
127
+
#define R9A07G043_GIC600_DBG_GICRESET_N 14 /* RZ/G2UL Only */
128
+
#define R9A07G043_IA55_RESETN 15 /* RZ/G2UL Only */
129
+
#define R9A07G043_MHU_RESETN 16 /* RZ/G2UL Only */
130
+
#define R9A07G043_DMAC_ARESETN 17
131
+
#define R9A07G043_DMAC_RST_ASYNC 18
132
+
#define R9A07G043_SYC_RESETN 19
133
+
#define R9A07G043_OSTM0_PRESETZ 20
134
+
#define R9A07G043_OSTM1_PRESETZ 21
135
+
#define R9A07G043_OSTM2_PRESETZ 22
136
+
#define R9A07G043_MTU_X_PRESET_MTU3 23
137
+
#define R9A07G043_POE3_RST_M_REG 24
138
+
#define R9A07G043_WDT0_PRESETN 25
139
+
#define R9A07G043_WDT2_PRESETN 26 /* RZ/G2UL Only */
140
+
#define R9A07G043_SPI_RST 27
141
+
#define R9A07G043_SDHI0_IXRST 28
142
+
#define R9A07G043_SDHI1_IXRST 29
143
+
#define R9A07G043_ISU_ARESETN 30 /* RZ/G2UL Only */
144
+
#define R9A07G043_ISU_PRESETN 31 /* RZ/G2UL Only */
145
+
#define R9A07G043_CRU_CMN_RSTB 32 /* RZ/G2UL Only */
146
+
#define R9A07G043_CRU_PRESETN 33 /* RZ/G2UL Only */
147
+
#define R9A07G043_CRU_ARESETN 34 /* RZ/G2UL Only */
148
+
#define R9A07G043_LCDC_RESET_N 35 /* RZ/G2UL Only */
149
+
#define R9A07G043_SSI0_RST_M2_REG 36
150
+
#define R9A07G043_SSI1_RST_M2_REG 37
151
+
#define R9A07G043_SSI2_RST_M2_REG 38
152
+
#define R9A07G043_SSI3_RST_M2_REG 39
153
+
#define R9A07G043_SRC_RST 40 /* RZ/G2UL Only */
154
+
#define R9A07G043_USB_U2H0_HRESETN 41
155
+
#define R9A07G043_USB_U2H1_HRESETN 42
156
+
#define R9A07G043_USB_U2P_EXL_SYSRST 43
157
+
#define R9A07G043_USB_PRESETN 44
158
+
#define R9A07G043_ETH0_RST_HW_N 45
159
+
#define R9A07G043_ETH1_RST_HW_N 46
160
+
#define R9A07G043_I2C0_MRST 47
161
+
#define R9A07G043_I2C1_MRST 48
162
+
#define R9A07G043_I2C2_MRST 49
163
+
#define R9A07G043_I2C3_MRST 50
164
+
#define R9A07G043_SCIF0_RST_SYSTEM_N 51
165
+
#define R9A07G043_SCIF1_RST_SYSTEM_N 52
166
+
#define R9A07G043_SCIF2_RST_SYSTEM_N 53
167
+
#define R9A07G043_SCIF3_RST_SYSTEM_N 54
168
+
#define R9A07G043_SCIF4_RST_SYSTEM_N 55
169
+
#define R9A07G043_SCI0_RST 56
170
+
#define R9A07G043_SCI1_RST 57
171
+
#define R9A07G043_IRDA_RST 58
172
+
#define R9A07G043_RSPI0_RST 59
173
+
#define R9A07G043_RSPI1_RST 60
174
+
#define R9A07G043_RSPI2_RST 61
175
+
#define R9A07G043_CANFD_RSTP_N 62
176
+
#define R9A07G043_CANFD_RSTC_N 63
177
+
#define R9A07G043_GPIO_RSTN 64
178
+
#define R9A07G043_GPIO_PORT_RESETN 65
179
+
#define R9A07G043_GPIO_SPARE_RESETN 66
180
+
#define R9A07G043_ADC_PRESETN 67
181
+
#define R9A07G043_ADC_ADRST_N 68
182
+
#define R9A07G043_TSU_PRESETN 69
183
+
184
+
#endif /* __DT_BINDINGS_CLOCK_R9A07G043_CPG_H__ */