Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'powerpc-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux
Pull powerpc updates from Michael Ellerman:
- Add support for building the kernel using PC-relative addressing on
Power10.
- Allow HV KVM guests on Power10 to use prefixed instructions.
- Unify support for the P2020 CPU (85xx) into a single machine
description.
- Always build the 64-bit kernel with 128-bit long double.
- Drop support for several obsolete 2000's era development boards as
identified by Paul Gortmaker.
- A series fixing VFIO on Power since some generic changes.
- Various other small features and fixes.
Thanks to Alexey Kardashevskiy, Andrew Donnellan, Benjamin Gray, Bo Liu,
Christophe Leroy, Dan Carpenter, David Binderman, Ira Weiny, Joel
Stanley, Kajol Jain, Kautuk Consul, Liang He, Luis Chamberlain, Masahiro
Yamada, Michael Neuling, Nathan Chancellor, Nathan Lynch, Nicholas
Miehlbradt, Nicholas Piggin, Nick Desaulniers, Nysal Jan K.A, Pali
Rohár, Paul Gortmaker, Paul Mackerras, Petr Vaněk, Randy Dunlap, Rob
Herring, Sachin Sant, Sean Christopherson, Segher Boessenkool, and
Timothy Pearson.
* tag 'powerpc-6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux: (156 commits)
powerpc/64s: Disable pcrel code model on Clang
powerpc: Fix merge conflict between pcrel and copy_thread changes
powerpc/configs/powernv: Add IGB=y
powerpc/configs/64s: Drop JFS Filesystem
powerpc/configs/64s: Use EXT4 to mount EXT2 filesystems
powerpc/configs: Make pseries_defconfig an alias for ppc64le_guest
powerpc/configs: Make pseries_le an alias for ppc64le_guest
powerpc/configs: Incorporate generic kvm_guest.config into guest configs
powerpc/configs: Add IBMVETH=y and IBMVNIC=y to guest configs
powerpc/configs/64s: Enable Device Mapper options
powerpc/configs/64s: Enable PSTORE
powerpc/configs/64s: Enable VLAN support
powerpc/configs/64s: Enable BLK_DEV_NVME
powerpc/configs/64s: Drop REISERFS
powerpc/configs/64s: Use SHA512 for module signatures
powerpc/configs/64s: Enable IO_STRICT_DEVMEM
powerpc/configs/64s: Enable SCHEDSTATS
powerpc/configs/64s: Enable DEBUG_VM & other options
powerpc/configs/64s: Enable EMULATED_STATS
powerpc/configs/64s: Enable KUNIT and most tests
...
+2689
-9528
+5
MAINTAINERS
+5
MAINTAINERS
···
9900
9900
F: drivers/crypto/vmx/ppc-xlate.pl
9901
9901
F: drivers/crypto/vmx/vmx.c
9902
9902
9903
+
IBM Power VFIO Support
9904
+
M: Timothy Pearson <tpearson@raptorengineering.com>
9905
+
S: Supported
9906
+
F: drivers/vfio/vfio_iommu_spapr_tce.c
9907
+
9903
9908
IBM ServeRAID RAID DRIVER
9904
9909
S: Orphan
9905
9910
F: drivers/scsi/ips.*
+14
-6
arch/powerpc/Kconfig
+14
-6
arch/powerpc/Kconfig
···
4
4
config CC_HAS_ELFV2
5
5
def_bool PPC64 && $(cc-option, -mabi=elfv2)
6
6
7
+
config CC_HAS_PREFIXED
8
+
def_bool PPC64 && $(cc-option, -mcpu=power10 -mprefixed)
9
+
10
+
config CC_HAS_PCREL
11
+
# Clang has a bug (https://github.com/llvm/llvm-project/issues/62372)
12
+
# where pcrel code is not generated if -msoft-float, -mno-altivec, or
13
+
# -mno-vsx options are also given. Without these options, fp/vec
14
+
# instructions are generated from regular kernel code. So Clang can't
15
+
# do pcrel yet.
16
+
def_bool PPC64 && CC_IS_GCC && $(cc-option, -mcpu=power10 -mpcrel)
17
+
7
18
config 32BIT
8
19
bool
9
20
default y if PPC32
···
169
158
select ARCH_USE_CMPXCHG_LOCKREF if PPC64
170
159
select ARCH_USE_MEMTEST
171
160
select ARCH_USE_QUEUED_RWLOCKS if PPC_QUEUED_SPINLOCKS
161
+
select ARCH_WANT_DEFAULT_BPF_JIT
172
162
select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
173
163
select ARCH_WANT_IPC_PARSE_VERSION
174
164
select ARCH_WANT_IRQS_OFF_ACTIVATE_MM
···
213
201
select HAVE_ARCH_KCSAN if PPC_BOOK3S_64
214
202
select HAVE_ARCH_KFENCE if ARCH_SUPPORTS_DEBUG_PAGEALLOC
215
203
select HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET
204
+
select HAVE_ARCH_WITHIN_STACK_FRAMES
216
205
select HAVE_ARCH_KGDB
217
206
select HAVE_ARCH_MMAP_RND_BITS
218
207
select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
···
304
291
#
305
292
# Please keep this list sorted alphabetically.
306
293
#
307
-
308
-
config PPC_LONG_DOUBLE_128
309
-
depends on PPC64 && ALTIVEC
310
-
def_bool $(success,test "$(shell,echo __LONG_DOUBLE_128__ | $(CC) -E -P -)" = 1)
311
294
312
295
config PPC_BARRIER_NOSPEC
313
296
bool
···
627
618
bool "Build big-endian kernel using ELF ABI V2 (EXPERIMENTAL)"
628
619
depends on PPC64 && CPU_BIG_ENDIAN
629
620
depends on CC_HAS_ELFV2
630
-
depends on LD_IS_BFD && LD_VERSION >= 22400
631
-
default n
621
+
depends on LD_VERSION >= 22400 || LLD_VERSION >= 150000
632
622
help
633
623
This builds the kernel image using the "Power Architecture 64-Bit ELF
634
624
V2 ABI Specification", which has a reduced stack overhead and faster
+61
-44
arch/powerpc/Makefile
+61
-44
arch/powerpc/Makefile
···
107
107
LDFLAGS_vmlinux := $(LDFLAGS_vmlinux-y)
108
108
109
109
ifdef CONFIG_PPC64
110
+
ifndef CONFIG_PPC_KERNEL_PCREL
110
111
ifeq ($(call cc-option-yn,-mcmodel=medium),y)
111
112
# -mcmodel=medium breaks modules because it uses 32bit offsets from
112
113
# the TOC pointer to create pointers where possible. Pointers into the
···
122
121
export NO_MINIMAL_TOC := -mno-minimal-toc
123
122
endif
124
123
endif
124
+
endif
125
125
126
126
CFLAGS-$(CONFIG_PPC64) := $(call cc-option,-mtraceback=no)
127
-
ifndef CONFIG_CC_IS_CLANG
128
127
ifdef CONFIG_PPC64_ELF_ABI_V2
129
128
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2,$(call cc-option,-mcall-aixdesc))
130
-
AFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv2)
131
129
else
130
+
ifndef CONFIG_CC_IS_CLANG
132
131
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv1)
133
132
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcall-aixdesc)
134
-
AFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mabi=elfv1)
135
133
endif
136
134
endif
137
135
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mcmodel=medium,$(call cc-option,-mminimal-toc))
138
136
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mno-pointers-to-nested-functions)
137
+
CFLAGS-$(CONFIG_PPC64) += $(call cc-option,-mlong-double-128)
139
138
140
139
# Clang unconditionally reserves r2 on ppc32 and does not support the flag
141
140
# https://bugs.llvm.org/show_bug.cgi?id=39555
···
182
181
endif
183
182
184
183
# No prefix or pcrel
184
+
ifdef CONFIG_PPC_KERNEL_PREFIXED
185
+
KBUILD_CFLAGS += $(call cc-option,-mprefixed)
186
+
else
185
187
KBUILD_CFLAGS += $(call cc-option,-mno-prefixed)
188
+
endif
189
+
ifdef CONFIG_PPC_KERNEL_PCREL
190
+
KBUILD_CFLAGS += $(call cc-option,-mpcrel)
191
+
else
186
192
KBUILD_CFLAGS += $(call cc-option,-mno-pcrel)
193
+
endif
187
194
188
195
# No AltiVec or VSX or MMA instructions when building kernel
189
196
KBUILD_CFLAGS += $(call cc-option,-mno-altivec)
···
247
238
$(Q)$(MAKE) $(build)=$(boot) $(patsubst %,$(boot)/%,$@)
248
239
249
240
include $(srctree)/scripts/Makefile.defconf
250
-
PHONY += pseries_le_defconfig
251
-
pseries_le_defconfig:
252
-
$(call merge_into_defconfig,pseries_defconfig,le)
253
241
254
-
PHONY += ppc64le_defconfig
242
+
generated_configs += ppc64le_defconfig
255
243
ppc64le_defconfig:
256
244
$(call merge_into_defconfig,ppc64_defconfig,le)
257
245
258
-
PHONY += ppc64le_guest_defconfig
246
+
generated_configs += ppc64le_guest_defconfig
259
247
ppc64le_guest_defconfig:
260
-
$(call merge_into_defconfig,ppc64_defconfig,le guest)
248
+
$(call merge_into_defconfig,ppc64_defconfig,le guest kvm_guest)
261
249
262
-
PHONY += ppc64_guest_defconfig
250
+
generated_configs += ppc64_guest_defconfig
263
251
ppc64_guest_defconfig:
264
-
$(call merge_into_defconfig,ppc64_defconfig,be guest)
252
+
$(call merge_into_defconfig,ppc64_defconfig,be guest kvm_guest)
265
253
266
-
PHONY += powernv_be_defconfig
254
+
generated_configs += pseries_le_defconfig
255
+
pseries_le_defconfig: ppc64le_guest_defconfig
256
+
257
+
generated_configs += pseries_defconfig
258
+
pseries_defconfig: ppc64le_guest_defconfig
259
+
260
+
generated_configs += powernv_be_defconfig
267
261
powernv_be_defconfig:
268
262
$(call merge_into_defconfig,powernv_defconfig,be)
269
263
270
-
PHONY += mpc85xx_defconfig
264
+
generated_configs += mpc85xx_defconfig
271
265
mpc85xx_defconfig:
272
266
$(call merge_into_defconfig,mpc85xx_base.config,\
273
267
85xx-32bit 85xx-hw fsl-emb-nonhw)
274
268
275
-
PHONY += mpc85xx_smp_defconfig
269
+
generated_configs += mpc85xx_smp_defconfig
276
270
mpc85xx_smp_defconfig:
277
271
$(call merge_into_defconfig,mpc85xx_base.config,\
278
272
85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw)
279
273
280
-
PHONY += corenet32_smp_defconfig
274
+
generated_configs += corenet32_smp_defconfig
281
275
corenet32_smp_defconfig:
282
276
$(call merge_into_defconfig,corenet_base.config,\
283
277
85xx-32bit 85xx-smp 85xx-hw fsl-emb-nonhw dpaa)
284
278
285
-
PHONY += corenet64_smp_defconfig
279
+
generated_configs += corenet64_smp_defconfig
286
280
corenet64_smp_defconfig:
287
281
$(call merge_into_defconfig,corenet_base.config,\
288
282
85xx-64bit 85xx-smp altivec 85xx-hw fsl-emb-nonhw dpaa)
289
283
290
-
PHONY += mpc86xx_defconfig
284
+
generated_configs += mpc86xx_defconfig
291
285
mpc86xx_defconfig:
292
286
$(call merge_into_defconfig,mpc86xx_base.config,\
293
287
86xx-hw fsl-emb-nonhw)
294
288
295
-
PHONY += mpc86xx_smp_defconfig
289
+
generated_configs += mpc86xx_smp_defconfig
296
290
mpc86xx_smp_defconfig:
297
291
$(call merge_into_defconfig,mpc86xx_base.config,\
298
292
86xx-smp 86xx-hw fsl-emb-nonhw)
299
293
300
-
PHONY += ppc32_allmodconfig
294
+
generated_configs += ppc32_allmodconfig
301
295
ppc32_allmodconfig:
302
296
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/book3s_32.config \
303
297
-f $(srctree)/Makefile allmodconfig
304
298
305
-
PHONY += ppc_defconfig
299
+
generated_configs += ppc_defconfig
306
300
ppc_defconfig:
307
301
$(call merge_into_defconfig,book3s_32.config,)
308
302
309
-
PHONY += ppc64le_allmodconfig
303
+
generated_configs += ppc64le_allmodconfig
310
304
ppc64le_allmodconfig:
311
305
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/le.config \
312
306
-f $(srctree)/Makefile allmodconfig
313
307
314
-
PHONY += ppc64le_allnoconfig
308
+
generated_configs += ppc64le_allnoconfig
315
309
ppc64le_allnoconfig:
316
310
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/ppc64le.config \
317
311
-f $(srctree)/Makefile allnoconfig
318
312
319
-
PHONY += ppc64_book3e_allmodconfig
313
+
generated_configs += ppc64_book3e_allmodconfig
320
314
ppc64_book3e_allmodconfig:
321
315
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/85xx-64bit.config \
322
316
-f $(srctree)/Makefile allmodconfig
323
317
324
-
PHONY += ppc32_randconfig
318
+
generated_configs += ppc32_randconfig
325
319
ppc32_randconfig:
326
320
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/32-bit.config \
327
321
-f $(srctree)/Makefile randconfig
328
322
329
-
PHONY += ppc64_randconfig
323
+
generated_configs += ppc64_randconfig
330
324
ppc64_randconfig:
331
325
$(Q)$(MAKE) KCONFIG_ALLCONFIG=$(srctree)/arch/powerpc/configs/64-bit.config \
332
326
-f $(srctree)/Makefile randconfig
333
327
328
+
PHONY += $(generated_configs)
329
+
334
330
define archhelp
335
-
@echo '* zImage - Build default images selected by kernel config'
336
-
@echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
337
-
@echo ' uImage - U-Boot native image format'
338
-
@echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
339
-
@echo ' versions which do not support device trees'
340
-
@echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
341
-
@echo ' simpleImage.<dt> - Firmware independent image.'
342
-
@echo ' treeImage.<dt> - Support for older IBM 4xx firmware (not U-Boot)'
343
-
@echo ' install - Install kernel using'
344
-
@echo ' (your) ~/bin/$(INSTALLKERNEL) or'
345
-
@echo ' (distribution) /sbin/$(INSTALLKERNEL) or'
346
-
@echo ' install to $$(INSTALL_PATH) and run lilo'
347
-
@echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
348
-
@echo ''
349
-
@echo ' Targets with <dt> embed a device tree blob inside the image'
350
-
@echo ' These targets support board with firmware that does not'
351
-
@echo ' support passing a device tree directly. Replace <dt> with the'
352
-
@echo ' name of a dts file from the arch/$(ARCH)/boot/dts/ directory'
353
-
@echo ' (minus the .dts extension).'
331
+
echo '* zImage - Build default images selected by kernel config'
332
+
echo ' zImage.* - Compressed kernel image (arch/$(ARCH)/boot/zImage.*)'
333
+
echo ' uImage - U-Boot native image format'
334
+
echo ' cuImage.<dt> - Backwards compatible U-Boot image for older'
335
+
echo ' versions which do not support device trees'
336
+
echo ' dtbImage.<dt> - zImage with an embedded device tree blob'
337
+
echo ' simpleImage.<dt> - Firmware independent image.'
338
+
echo ' treeImage.<dt> - Support for older IBM 4xx firmware (not U-Boot)'
339
+
echo ' install - Install kernel using'
340
+
echo ' (your) ~/bin/$(INSTALLKERNEL) or'
341
+
echo ' (distribution) /sbin/$(INSTALLKERNEL) or'
342
+
echo ' install to $$(INSTALL_PATH) and run lilo'
343
+
echo ' *_defconfig - Select default config from arch/$(ARCH)/configs'
344
+
echo ''
345
+
echo ' Targets with <dt> embed a device tree blob inside the image'
346
+
echo ' These targets support board with firmware that does not'
347
+
echo ' support passing a device tree directly. Replace <dt> with the'
348
+
echo ' name of a dts file from the arch/$(ARCH)/boot/dts/ directory'
349
+
echo ' (minus the .dts extension).'
350
+
echo
351
+
$(foreach cfg,$(generated_configs),
352
+
printf " %-27s - Build for %s\\n" $(cfg) $(subst _defconfig,,$(cfg));)
354
353
endef
355
354
356
355
PHONY += install
+6
-10
arch/powerpc/boot/Makefile
+6
-10
arch/powerpc/boot/Makefile
···
34
34
35
35
BOOTCFLAGS := -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs \
36
36
-fno-strict-aliasing -O2 -msoft-float -mno-altivec -mno-vsx \
37
+
$(call cc-option,-mno-prefixed) $(call cc-option,-mno-pcrel) \
38
+
$(call cc-option,-mno-mma) \
37
39
$(call cc-option,-mno-spe) $(call cc-option,-mspe=no) \
38
40
-pipe -fomit-frame-pointer -fno-builtin -fPIC -nostdinc \
39
41
$(LINUXINCLUDE)
40
42
41
43
ifdef CONFIG_PPC64_BOOT_WRAPPER
42
44
BOOTCFLAGS += -m64
45
+
ifdef CONFIG_PPC64_ELF_ABI_V2
46
+
BOOTCFLAGS += $(call cc-option,-mabi=elfv2)
47
+
endif
43
48
else
44
49
BOOTCFLAGS += -m32
45
50
endif
···
65
60
BOOTCFLAGS += -mbig-endian
66
61
else
67
62
BOOTCFLAGS += -mlittle-endian
68
-
endif
69
-
ifdef CONFIG_PPC64_ELF_ABI_V2
70
-
BOOTCFLAGS += $(call cc-option,-mabi=elfv2)
71
63
endif
72
64
73
65
BOOTAFLAGS := -D__ASSEMBLY__ $(BOOTCFLAGS) -nostdinc
···
166
164
src-plat-$(CONFIG_PPC_82xx) += cuboot-pq2.c fixed-head.S ep8248e.c cuboot-824x.c
167
165
src-plat-$(CONFIG_PPC_83xx) += cuboot-83xx.c fixed-head.S redboot-83xx.c
168
166
src-plat-$(CONFIG_FSL_SOC_BOOKE) += cuboot-85xx.c cuboot-85xx-cpm2.c
169
-
src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c cuboot-mpc7448hpc2.c \
167
+
src-plat-$(CONFIG_EMBEDDED6xx) += cuboot-pq2.c \
170
168
gamecube-head.S gamecube.c \
171
169
wii-head.S wii.c holly.c \
172
170
fixed-head.S mvme5100.c
···
329
327
image-$(CONFIG_PPC_MEDIA5200) += cuImage.media5200
330
328
331
329
# Board ports in arch/powerpc/platform/82xx/Kconfig
332
-
image-$(CONFIG_MPC8272_ADS) += cuImage.mpc8272ads
333
-
image-$(CONFIG_PQ2FADS) += cuImage.pq2fads
334
330
image-$(CONFIG_EP8248E) += dtbImage.ep8248e
335
331
336
332
# Board ports in arch/powerpc/platform/83xx/Kconfig
337
-
image-$(CONFIG_MPC832x_MDS) += cuImage.mpc832x_mds
338
333
image-$(CONFIG_MPC832x_RDB) += cuImage.mpc832x_rdb
339
334
image-$(CONFIG_MPC834x_ITX) += cuImage.mpc8349emitx \
340
335
cuImage.mpc8349emitxgp
341
-
image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
342
-
image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
343
336
image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
344
337
345
338
# Board ports in arch/powerpc/platform/85xx/Kconfig
···
358
361
359
362
# Board ports in arch/powerpc/platform/embedded6xx/Kconfig
360
363
image-$(CONFIG_STORCENTER) += cuImage.storcenter
361
-
image-$(CONFIG_MPC7448HPC2) += cuImage.mpc7448hpc2
362
364
image-$(CONFIG_GAMECUBE) += dtbImage.gamecube
363
365
image-$(CONFIG_WII) += dtbImage.wii
364
366
image-$(CONFIG_MVME5100) += dtbImage.mvme5100
+2
-2
arch/powerpc/boot/crt0.S
+2
-2
arch/powerpc/boot/crt0.S
···
51
51
_zimage_start_lib:
52
52
/* Work out the offset between the address we were linked at
53
53
and the address where we're running. */
54
-
bl .+4
54
+
bcl 20,31,.+4
55
55
p_base: mflr r10 /* r10 now points to runtime addr of p_base */
56
56
#ifndef __powerpc64__
57
57
/* grab the link address of the dynamic section in r11 */
···
274
274
mtsrr1 r10
275
275
276
276
/* Load FW address, set LR to label 1, and jump to FW */
277
-
bl 0f
277
+
bcl 20,31,0f
278
278
0: mflr r10
279
279
addi r11,r10,(1f-0b)
280
280
mtlr r11
-43
arch/powerpc/boot/cuboot-mpc7448hpc2.c
-43
arch/powerpc/boot/cuboot-mpc7448hpc2.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
4
-
*
5
-
* Author: Roy Zang <tie-fei.zang@freescale.com>
6
-
*
7
-
* Description:
8
-
* Old U-boot compatibility for mpc7448hpc2 board
9
-
* Based on the code of Scott Wood <scottwood@freescale.com>
10
-
* for 83xx and 85xx.
11
-
*/
12
-
13
-
#include "ops.h"
14
-
#include "stdio.h"
15
-
#include "cuboot.h"
16
-
17
-
#define TARGET_HAS_ETH1
18
-
#include "ppcboot.h"
19
-
20
-
static bd_t bd;
21
-
extern char _dtb_start[], _dtb_end[];
22
-
23
-
static void platform_fixups(void)
24
-
{
25
-
void *tsi;
26
-
27
-
dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
28
-
dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
29
-
dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
30
-
tsi = find_node_by_devtype(NULL, "tsi-bridge");
31
-
if (tsi)
32
-
setprop(tsi, "bus-frequency", &bd.bi_busfreq,
33
-
sizeof(bd.bi_busfreq));
34
-
}
35
-
36
-
void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
37
-
unsigned long r6, unsigned long r7)
38
-
{
39
-
CUBOOT_INIT();
40
-
fdt_init(_dtb_start);
41
-
serial_console_init();
42
-
platform_ops.fixups = platform_fixups;
43
-
}
-394
arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
-394
arch/powerpc/boot/dts/fsl/mpc8641_hpcn.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8641 HPCN Device Tree Source
4
-
*
5
-
* Copyright 2006 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/include/ "mpc8641si-pre.dtsi"
9
-
10
-
/ {
11
-
model = "MPC8641HPCN";
12
-
compatible = "fsl,mpc8641hpcn";
13
-
14
-
memory {
15
-
device_type = "memory";
16
-
reg = <0x00000000 0x40000000>; // 1G at 0x0
17
-
};
18
-
19
-
lbc: localbus@ffe05000 {
20
-
reg = <0xffe05000 0x1000>;
21
-
22
-
ranges = <0 0 0xef800000 0x00800000
23
-
2 0 0xffdf8000 0x00008000
24
-
3 0 0xffdf0000 0x00008000>;
25
-
26
-
flash@0,0 {
27
-
compatible = "cfi-flash";
28
-
reg = <0 0 0x00800000>;
29
-
bank-width = <2>;
30
-
device-width = <2>;
31
-
#address-cells = <1>;
32
-
#size-cells = <1>;
33
-
partition@0 {
34
-
label = "kernel";
35
-
reg = <0x00000000 0x00300000>;
36
-
};
37
-
partition@300000 {
38
-
label = "firmware b";
39
-
reg = <0x00300000 0x00100000>;
40
-
read-only;
41
-
};
42
-
partition@400000 {
43
-
label = "fs";
44
-
reg = <0x00400000 0x00300000>;
45
-
};
46
-
partition@700000 {
47
-
label = "firmware a";
48
-
reg = <0x00700000 0x00100000>;
49
-
read-only;
50
-
};
51
-
};
52
-
};
53
-
54
-
soc: soc8641@ffe00000 {
55
-
ranges = <0x00000000 0xffe00000 0x00100000>;
56
-
57
-
enet0: ethernet@24000 {
58
-
tbi-handle = <&tbi0>;
59
-
phy-handle = <&phy0>;
60
-
phy-connection-type = "rgmii-id";
61
-
};
62
-
63
-
mdio@24520 {
64
-
phy0: ethernet-phy@0 {
65
-
interrupts = <10 1 0 0>;
66
-
reg = <0>;
67
-
};
68
-
phy1: ethernet-phy@1 {
69
-
interrupts = <10 1 0 0>;
70
-
reg = <1>;
71
-
};
72
-
phy2: ethernet-phy@2 {
73
-
interrupts = <10 1 0 0>;
74
-
reg = <2>;
75
-
};
76
-
phy3: ethernet-phy@3 {
77
-
interrupts = <10 1 0 0>;
78
-
reg = <3>;
79
-
};
80
-
tbi0: tbi-phy@11 {
81
-
reg = <0x11>;
82
-
device_type = "tbi-phy";
83
-
};
84
-
};
85
-
86
-
enet1: ethernet@25000 {
87
-
tbi-handle = <&tbi1>;
88
-
phy-handle = <&phy1>;
89
-
phy-connection-type = "rgmii-id";
90
-
};
91
-
92
-
mdio@25520 {
93
-
tbi1: tbi-phy@11 {
94
-
reg = <0x11>;
95
-
device_type = "tbi-phy";
96
-
};
97
-
};
98
-
99
-
enet2: ethernet@26000 {
100
-
tbi-handle = <&tbi2>;
101
-
phy-handle = <&phy2>;
102
-
phy-connection-type = "rgmii-id";
103
-
};
104
-
105
-
mdio@26520 {
106
-
tbi2: tbi-phy@11 {
107
-
reg = <0x11>;
108
-
device_type = "tbi-phy";
109
-
};
110
-
};
111
-
112
-
enet3: ethernet@27000 {
113
-
tbi-handle = <&tbi3>;
114
-
phy-handle = <&phy3>;
115
-
phy-connection-type = "rgmii-id";
116
-
};
117
-
118
-
mdio@27520 {
119
-
tbi3: tbi-phy@11 {
120
-
reg = <0x11>;
121
-
device_type = "tbi-phy";
122
-
};
123
-
};
124
-
125
-
rmu: rmu@d3000 {
126
-
#address-cells = <1>;
127
-
#size-cells = <1>;
128
-
compatible = "fsl,srio-rmu";
129
-
reg = <0xd3000 0x500>;
130
-
ranges = <0x0 0xd3000 0x500>;
131
-
132
-
message-unit@0 {
133
-
compatible = "fsl,srio-msg-unit";
134
-
reg = <0x0 0x100>;
135
-
interrupts = <
136
-
53 2 0 0 /* msg1_tx_irq */
137
-
54 2 0 0>;/* msg1_rx_irq */
138
-
};
139
-
message-unit@100 {
140
-
compatible = "fsl,srio-msg-unit";
141
-
reg = <0x100 0x100>;
142
-
interrupts = <
143
-
55 2 0 0 /* msg2_tx_irq */
144
-
56 2 0 0>;/* msg2_rx_irq */
145
-
};
146
-
doorbell-unit@400 {
147
-
compatible = "fsl,srio-dbell-unit";
148
-
reg = <0x400 0x80>;
149
-
interrupts = <
150
-
49 2 0 0 /* bell_outb_irq */
151
-
50 2 0 0>;/* bell_inb_irq */
152
-
};
153
-
port-write-unit@4e0 {
154
-
compatible = "fsl,srio-port-write-unit";
155
-
reg = <0x4e0 0x20>;
156
-
interrupts = <48 2 0 0>;
157
-
};
158
-
};
159
-
};
160
-
161
-
pci0: pcie@ffe08000 {
162
-
reg = <0xffe08000 0x1000>;
163
-
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
164
-
0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
165
-
interrupt-map-mask = <0xff00 0 0 7>;
166
-
interrupt-map = <
167
-
/* IDSEL 0x11 func 0 - PCI slot 1 */
168
-
0x8800 0 0 1 &mpic 2 1 0 0
169
-
0x8800 0 0 2 &mpic 3 1 0 0
170
-
0x8800 0 0 3 &mpic 4 1 0 0
171
-
0x8800 0 0 4 &mpic 1 1 0 0
172
-
173
-
/* IDSEL 0x11 func 1 - PCI slot 1 */
174
-
0x8900 0 0 1 &mpic 2 1 0 0
175
-
0x8900 0 0 2 &mpic 3 1 0 0
176
-
0x8900 0 0 3 &mpic 4 1 0 0
177
-
0x8900 0 0 4 &mpic 1 1 0 0
178
-
179
-
/* IDSEL 0x11 func 2 - PCI slot 1 */
180
-
0x8a00 0 0 1 &mpic 2 1 0 0
181
-
0x8a00 0 0 2 &mpic 3 1 0 0
182
-
0x8a00 0 0 3 &mpic 4 1 0 0
183
-
0x8a00 0 0 4 &mpic 1 1 0 0
184
-
185
-
/* IDSEL 0x11 func 3 - PCI slot 1 */
186
-
0x8b00 0 0 1 &mpic 2 1 0 0
187
-
0x8b00 0 0 2 &mpic 3 1 0 0
188
-
0x8b00 0 0 3 &mpic 4 1 0 0
189
-
0x8b00 0 0 4 &mpic 1 1 0 0
190
-
191
-
/* IDSEL 0x11 func 4 - PCI slot 1 */
192
-
0x8c00 0 0 1 &mpic 2 1 0 0
193
-
0x8c00 0 0 2 &mpic 3 1 0 0
194
-
0x8c00 0 0 3 &mpic 4 1 0 0
195
-
0x8c00 0 0 4 &mpic 1 1 0 0
196
-
197
-
/* IDSEL 0x11 func 5 - PCI slot 1 */
198
-
0x8d00 0 0 1 &mpic 2 1 0 0
199
-
0x8d00 0 0 2 &mpic 3 1 0 0
200
-
0x8d00 0 0 3 &mpic 4 1 0 0
201
-
0x8d00 0 0 4 &mpic 1 1 0 0
202
-
203
-
/* IDSEL 0x11 func 6 - PCI slot 1 */
204
-
0x8e00 0 0 1 &mpic 2 1 0 0
205
-
0x8e00 0 0 2 &mpic 3 1 0 0
206
-
0x8e00 0 0 3 &mpic 4 1 0 0
207
-
0x8e00 0 0 4 &mpic 1 1 0 0
208
-
209
-
/* IDSEL 0x11 func 7 - PCI slot 1 */
210
-
0x8f00 0 0 1 &mpic 2 1 0 0
211
-
0x8f00 0 0 2 &mpic 3 1 0 0
212
-
0x8f00 0 0 3 &mpic 4 1 0 0
213
-
0x8f00 0 0 4 &mpic 1 1 0 0
214
-
215
-
/* IDSEL 0x12 func 0 - PCI slot 2 */
216
-
0x9000 0 0 1 &mpic 3 1 0 0
217
-
0x9000 0 0 2 &mpic 4 1 0 0
218
-
0x9000 0 0 3 &mpic 1 1 0 0
219
-
0x9000 0 0 4 &mpic 2 1 0 0
220
-
221
-
/* IDSEL 0x12 func 1 - PCI slot 2 */
222
-
0x9100 0 0 1 &mpic 3 1 0 0
223
-
0x9100 0 0 2 &mpic 4 1 0 0
224
-
0x9100 0 0 3 &mpic 1 1 0 0
225
-
0x9100 0 0 4 &mpic 2 1 0 0
226
-
227
-
/* IDSEL 0x12 func 2 - PCI slot 2 */
228
-
0x9200 0 0 1 &mpic 3 1 0 0
229
-
0x9200 0 0 2 &mpic 4 1 0 0
230
-
0x9200 0 0 3 &mpic 1 1 0 0
231
-
0x9200 0 0 4 &mpic 2 1 0 0
232
-
233
-
/* IDSEL 0x12 func 3 - PCI slot 2 */
234
-
0x9300 0 0 1 &mpic 3 1 0 0
235
-
0x9300 0 0 2 &mpic 4 1 0 0
236
-
0x9300 0 0 3 &mpic 1 1 0 0
237
-
0x9300 0 0 4 &mpic 2 1 0 0
238
-
239
-
/* IDSEL 0x12 func 4 - PCI slot 2 */
240
-
0x9400 0 0 1 &mpic 3 1 0 0
241
-
0x9400 0 0 2 &mpic 4 1 0 0
242
-
0x9400 0 0 3 &mpic 1 1 0 0
243
-
0x9400 0 0 4 &mpic 2 1 0 0
244
-
245
-
/* IDSEL 0x12 func 5 - PCI slot 2 */
246
-
0x9500 0 0 1 &mpic 3 1 0 0
247
-
0x9500 0 0 2 &mpic 4 1 0 0
248
-
0x9500 0 0 3 &mpic 1 1 0 0
249
-
0x9500 0 0 4 &mpic 2 1 0 0
250
-
251
-
/* IDSEL 0x12 func 6 - PCI slot 2 */
252
-
0x9600 0 0 1 &mpic 3 1 0 0
253
-
0x9600 0 0 2 &mpic 4 1 0 0
254
-
0x9600 0 0 3 &mpic 1 1 0 0
255
-
0x9600 0 0 4 &mpic 2 1 0 0
256
-
257
-
/* IDSEL 0x12 func 7 - PCI slot 2 */
258
-
0x9700 0 0 1 &mpic 3 1 0 0
259
-
0x9700 0 0 2 &mpic 4 1 0 0
260
-
0x9700 0 0 3 &mpic 1 1 0 0
261
-
0x9700 0 0 4 &mpic 2 1 0 0
262
-
263
-
// IDSEL 0x1c USB
264
-
0xe000 0 0 1 &i8259 12 2
265
-
0xe100 0 0 2 &i8259 9 2
266
-
0xe200 0 0 3 &i8259 10 2
267
-
0xe300 0 0 4 &i8259 11 2
268
-
269
-
// IDSEL 0x1d Audio
270
-
0xe800 0 0 1 &i8259 6 2
271
-
272
-
// IDSEL 0x1e Legacy
273
-
0xf000 0 0 1 &i8259 7 2
274
-
0xf100 0 0 1 &i8259 7 2
275
-
276
-
// IDSEL 0x1f IDE/SATA
277
-
0xf800 0 0 1 &i8259 14 2
278
-
0xf900 0 0 1 &i8259 5 2
279
-
>;
280
-
281
-
pcie@0 {
282
-
ranges = <0x02000000 0x0 0x80000000
283
-
0x02000000 0x0 0x80000000
284
-
0x0 0x20000000
285
-
286
-
0x01000000 0x0 0x00000000
287
-
0x01000000 0x0 0x00000000
288
-
0x0 0x00010000>;
289
-
uli1575@0 {
290
-
reg = <0 0 0 0 0>;
291
-
#size-cells = <2>;
292
-
#address-cells = <3>;
293
-
ranges = <0x02000000 0x0 0x80000000
294
-
0x02000000 0x0 0x80000000
295
-
0x0 0x20000000
296
-
0x01000000 0x0 0x00000000
297
-
0x01000000 0x0 0x00000000
298
-
0x0 0x00010000>;
299
-
isa@1e {
300
-
device_type = "isa";
301
-
#size-cells = <1>;
302
-
#address-cells = <2>;
303
-
reg = <0xf000 0 0 0 0>;
304
-
ranges = <1 0 0x01000000 0 0
305
-
0x00001000>;
306
-
interrupt-parent = <&i8259>;
307
-
308
-
i8259: interrupt-controller@20 {
309
-
reg = <1 0x20 2
310
-
1 0xa0 2
311
-
1 0x4d0 2>;
312
-
interrupt-controller;
313
-
device_type = "interrupt-controller";
314
-
#address-cells = <0>;
315
-
#interrupt-cells = <2>;
316
-
compatible = "chrp,iic";
317
-
interrupts = <9 2 0 0>;
318
-
};
319
-
320
-
i8042@60 {
321
-
#size-cells = <0>;
322
-
#address-cells = <1>;
323
-
reg = <1 0x60 1 1 0x64 1>;
324
-
interrupts = <1 3 12 3>;
325
-
interrupt-parent = <&i8259>;
326
-
327
-
keyboard@0 {
328
-
reg = <0>;
329
-
compatible = "pnpPNP,303";
330
-
};
331
-
332
-
mouse@1 {
333
-
reg = <1>;
334
-
compatible = "pnpPNP,f03";
335
-
};
336
-
};
337
-
338
-
rtc@70 {
339
-
compatible =
340
-
"pnpPNP,b00";
341
-
reg = <1 0x70 2>;
342
-
};
343
-
344
-
gpio@400 {
345
-
reg = <1 0x400 0x80>;
346
-
};
347
-
};
348
-
};
349
-
};
350
-
351
-
};
352
-
353
-
pci1: pcie@ffe09000 {
354
-
reg = <0xffe09000 0x1000>;
355
-
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
356
-
0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
357
-
358
-
pcie@0 {
359
-
ranges = <0x02000000 0x0 0xa0000000
360
-
0x02000000 0x0 0xa0000000
361
-
0x0 0x20000000
362
-
363
-
0x01000000 0x0 0x00000000
364
-
0x01000000 0x0 0x00000000
365
-
0x0 0x00010000>;
366
-
};
367
-
};
368
-
/*
369
-
* Only one of Rapid IO or PCI can be present due to HW limitations and
370
-
* due to the fact that the 2 now share address space in the new memory
371
-
* map. The most likely case is that we have PCI, so comment out the
372
-
* rapidio node. Leave it here for reference.
373
-
374
-
rapidio@ffec0000 {
375
-
reg = <0xffec0000 0x11000>;
376
-
compatible = "fsl,srio";
377
-
interrupts = <48 2 0 0>;
378
-
#address-cells = <2>;
379
-
#size-cells = <2>;
380
-
fsl,srio-rmu-handle = <&rmu>;
381
-
ranges;
382
-
383
-
port1 {
384
-
#address-cells = <2>;
385
-
#size-cells = <2>;
386
-
cell-index = <1>;
387
-
ranges = <0 0 0x80000000 0 0x20000000>;
388
-
};
389
-
};
390
-
*/
391
-
392
-
};
393
-
394
-
/include/ "mpc8641si-post.dtsi"
-337
arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
-337
arch/powerpc/boot/dts/fsl/mpc8641_hpcn_36b.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8641 HPCN Device Tree Source
4
-
*
5
-
* Copyright 2008-2009 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/include/ "mpc8641si-pre.dtsi"
9
-
10
-
/ {
11
-
model = "MPC8641HPCN";
12
-
compatible = "fsl,mpc8641hpcn";
13
-
#address-cells = <2>;
14
-
#size-cells = <2>;
15
-
16
-
memory {
17
-
device_type = "memory";
18
-
reg = <0x0 0x00000000 0x0 0x40000000>; // 1G at 0x0
19
-
};
20
-
21
-
lbc: localbus@fffe05000 {
22
-
reg = <0x0f 0xffe05000 0x0 0x1000>;
23
-
24
-
ranges = <0 0 0xf 0xef800000 0x00800000
25
-
2 0 0xf 0xffdf8000 0x00008000
26
-
3 0 0xf 0xffdf0000 0x00008000>;
27
-
28
-
flash@0,0 {
29
-
compatible = "cfi-flash";
30
-
reg = <0 0 0x00800000>;
31
-
bank-width = <2>;
32
-
device-width = <2>;
33
-
#address-cells = <1>;
34
-
#size-cells = <1>;
35
-
partition@0 {
36
-
label = "kernel";
37
-
reg = <0x00000000 0x00300000>;
38
-
};
39
-
partition@300000 {
40
-
label = "firmware b";
41
-
reg = <0x00300000 0x00100000>;
42
-
read-only;
43
-
};
44
-
partition@400000 {
45
-
label = "fs";
46
-
reg = <0x00400000 0x00300000>;
47
-
};
48
-
partition@700000 {
49
-
label = "firmware a";
50
-
reg = <0x00700000 0x00100000>;
51
-
read-only;
52
-
};
53
-
};
54
-
};
55
-
56
-
soc: soc8641@fffe00000 {
57
-
ranges = <0x00000000 0x0f 0xffe00000 0x00100000>;
58
-
59
-
enet0: ethernet@24000 {
60
-
tbi-handle = <&tbi0>;
61
-
phy-handle = <&phy0>;
62
-
phy-connection-type = "rgmii-id";
63
-
};
64
-
65
-
mdio@24520 {
66
-
phy0: ethernet-phy@0 {
67
-
interrupts = <10 1 0 0>;
68
-
reg = <0>;
69
-
};
70
-
phy1: ethernet-phy@1 {
71
-
interrupts = <10 1 0 0>;
72
-
reg = <1>;
73
-
};
74
-
phy2: ethernet-phy@2 {
75
-
interrupts = <10 1 0 0>;
76
-
reg = <2>;
77
-
};
78
-
phy3: ethernet-phy@3 {
79
-
interrupts = <10 1 0 0>;
80
-
reg = <3>;
81
-
};
82
-
tbi0: tbi-phy@11 {
83
-
reg = <0x11>;
84
-
device_type = "tbi-phy";
85
-
};
86
-
};
87
-
88
-
enet1: ethernet@25000 {
89
-
tbi-handle = <&tbi1>;
90
-
phy-handle = <&phy1>;
91
-
phy-connection-type = "rgmii-id";
92
-
};
93
-
94
-
mdio@25520 {
95
-
tbi1: tbi-phy@11 {
96
-
reg = <0x11>;
97
-
device_type = "tbi-phy";
98
-
};
99
-
};
100
-
101
-
enet2: ethernet@26000 {
102
-
tbi-handle = <&tbi2>;
103
-
phy-handle = <&phy2>;
104
-
phy-connection-type = "rgmii-id";
105
-
};
106
-
107
-
mdio@26520 {
108
-
tbi2: tbi-phy@11 {
109
-
reg = <0x11>;
110
-
device_type = "tbi-phy";
111
-
};
112
-
};
113
-
114
-
enet3: ethernet@27000 {
115
-
tbi-handle = <&tbi3>;
116
-
phy-handle = <&phy3>;
117
-
phy-connection-type = "rgmii-id";
118
-
};
119
-
120
-
mdio@27520 {
121
-
tbi3: tbi-phy@11 {
122
-
reg = <0x11>;
123
-
device_type = "tbi-phy";
124
-
};
125
-
};
126
-
};
127
-
128
-
pci0: pcie@fffe08000 {
129
-
reg = <0x0f 0xffe08000 0x0 0x1000>;
130
-
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x00000000 0x0 0x20000000
131
-
0x01000000 0x0 0x00000000 0x0f 0xffc00000 0x0 0x00010000>;
132
-
interrupt-map-mask = <0xff00 0 0 7>;
133
-
interrupt-map = <
134
-
/* IDSEL 0x11 func 0 - PCI slot 1 */
135
-
0x8800 0 0 1 &mpic 2 1 0 0
136
-
0x8800 0 0 2 &mpic 3 1 0 0
137
-
0x8800 0 0 3 &mpic 4 1 0 0
138
-
0x8800 0 0 4 &mpic 1 1 0 0
139
-
140
-
/* IDSEL 0x11 func 1 - PCI slot 1 */
141
-
0x8900 0 0 1 &mpic 2 1 0 0
142
-
0x8900 0 0 2 &mpic 3 1 0 0
143
-
0x8900 0 0 3 &mpic 4 1 0 0
144
-
0x8900 0 0 4 &mpic 1 1 0 0
145
-
146
-
/* IDSEL 0x11 func 2 - PCI slot 1 */
147
-
0x8a00 0 0 1 &mpic 2 1 0 0
148
-
0x8a00 0 0 2 &mpic 3 1 0 0
149
-
0x8a00 0 0 3 &mpic 4 1 0 0
150
-
0x8a00 0 0 4 &mpic 1 1 0 0
151
-
152
-
/* IDSEL 0x11 func 3 - PCI slot 1 */
153
-
0x8b00 0 0 1 &mpic 2 1 0 0
154
-
0x8b00 0 0 2 &mpic 3 1 0 0
155
-
0x8b00 0 0 3 &mpic 4 1 0 0
156
-
0x8b00 0 0 4 &mpic 1 1 0 0
157
-
158
-
/* IDSEL 0x11 func 4 - PCI slot 1 */
159
-
0x8c00 0 0 1 &mpic 2 1 0 0
160
-
0x8c00 0 0 2 &mpic 3 1 0 0
161
-
0x8c00 0 0 3 &mpic 4 1 0 0
162
-
0x8c00 0 0 4 &mpic 1 1 0 0
163
-
164
-
/* IDSEL 0x11 func 5 - PCI slot 1 */
165
-
0x8d00 0 0 1 &mpic 2 1 0 0
166
-
0x8d00 0 0 2 &mpic 3 1 0 0
167
-
0x8d00 0 0 3 &mpic 4 1 0 0
168
-
0x8d00 0 0 4 &mpic 1 1 0 0
169
-
170
-
/* IDSEL 0x11 func 6 - PCI slot 1 */
171
-
0x8e00 0 0 1 &mpic 2 1 0 0
172
-
0x8e00 0 0 2 &mpic 3 1 0 0
173
-
0x8e00 0 0 3 &mpic 4 1 0 0
174
-
0x8e00 0 0 4 &mpic 1 1 0 0
175
-
176
-
/* IDSEL 0x11 func 7 - PCI slot 1 */
177
-
0x8f00 0 0 1 &mpic 2 1 0 0
178
-
0x8f00 0 0 2 &mpic 3 1 0 0
179
-
0x8f00 0 0 3 &mpic 4 1 0 0
180
-
0x8f00 0 0 4 &mpic 1 1 0 0
181
-
182
-
/* IDSEL 0x12 func 0 - PCI slot 2 */
183
-
0x9000 0 0 1 &mpic 3 1 0 0
184
-
0x9000 0 0 2 &mpic 4 1 0 0
185
-
0x9000 0 0 3 &mpic 1 1 0 0
186
-
0x9000 0 0 4 &mpic 2 1 0 0
187
-
188
-
/* IDSEL 0x12 func 1 - PCI slot 2 */
189
-
0x9100 0 0 1 &mpic 3 1 0 0
190
-
0x9100 0 0 2 &mpic 4 1 0 0
191
-
0x9100 0 0 3 &mpic 1 1 0 0
192
-
0x9100 0 0 4 &mpic 2 1 0 0
193
-
194
-
/* IDSEL 0x12 func 2 - PCI slot 2 */
195
-
0x9200 0 0 1 &mpic 3 1 0 0
196
-
0x9200 0 0 2 &mpic 4 1 0 0
197
-
0x9200 0 0 3 &mpic 1 1 0 0
198
-
0x9200 0 0 4 &mpic 2 1 0 0
199
-
200
-
/* IDSEL 0x12 func 3 - PCI slot 2 */
201
-
0x9300 0 0 1 &mpic 3 1 0 0
202
-
0x9300 0 0 2 &mpic 4 1 0 0
203
-
0x9300 0 0 3 &mpic 1 1 0 0
204
-
0x9300 0 0 4 &mpic 2 1 0 0
205
-
206
-
/* IDSEL 0x12 func 4 - PCI slot 2 */
207
-
0x9400 0 0 1 &mpic 3 1 0 0
208
-
0x9400 0 0 2 &mpic 4 1 0 0
209
-
0x9400 0 0 3 &mpic 1 1 0 0
210
-
0x9400 0 0 4 &mpic 2 1 0 0
211
-
212
-
/* IDSEL 0x12 func 5 - PCI slot 2 */
213
-
0x9500 0 0 1 &mpic 3 1 0 0
214
-
0x9500 0 0 2 &mpic 4 1 0 0
215
-
0x9500 0 0 3 &mpic 1 1 0 0
216
-
0x9500 0 0 4 &mpic 2 1 0 0
217
-
218
-
/* IDSEL 0x12 func 6 - PCI slot 2 */
219
-
0x9600 0 0 1 &mpic 3 1 0 0
220
-
0x9600 0 0 2 &mpic 4 1 0 0
221
-
0x9600 0 0 3 &mpic 1 1 0 0
222
-
0x9600 0 0 4 &mpic 2 1 0 0
223
-
224
-
/* IDSEL 0x12 func 7 - PCI slot 2 */
225
-
0x9700 0 0 1 &mpic 3 1 0 0
226
-
0x9700 0 0 2 &mpic 4 1 0 0
227
-
0x9700 0 0 3 &mpic 1 1 0 0
228
-
0x9700 0 0 4 &mpic 2 1 0 0
229
-
230
-
// IDSEL 0x1c USB
231
-
0xe000 0 0 1 &i8259 12 2
232
-
0xe100 0 0 2 &i8259 9 2
233
-
0xe200 0 0 3 &i8259 10 2
234
-
0xe300 0 0 4 &i8259 11 2
235
-
236
-
// IDSEL 0x1d Audio
237
-
0xe800 0 0 1 &i8259 6 2
238
-
239
-
// IDSEL 0x1e Legacy
240
-
0xf000 0 0 1 &i8259 7 2
241
-
0xf100 0 0 1 &i8259 7 2
242
-
243
-
// IDSEL 0x1f IDE/SATA
244
-
0xf800 0 0 1 &i8259 14 2
245
-
0xf900 0 0 1 &i8259 5 2
246
-
>;
247
-
248
-
pcie@0 {
249
-
ranges = <0x02000000 0x0 0xe0000000
250
-
0x02000000 0x0 0xe0000000
251
-
0x0 0x20000000
252
-
253
-
0x01000000 0x0 0x00000000
254
-
0x01000000 0x0 0x00000000
255
-
0x0 0x00010000>;
256
-
uli1575@0 {
257
-
reg = <0 0 0 0 0>;
258
-
#size-cells = <2>;
259
-
#address-cells = <3>;
260
-
ranges = <0x02000000 0x0 0xe0000000
261
-
0x02000000 0x0 0xe0000000
262
-
0x0 0x20000000
263
-
0x01000000 0x0 0x00000000
264
-
0x01000000 0x0 0x00000000
265
-
0x0 0x00010000>;
266
-
isa@1e {
267
-
device_type = "isa";
268
-
#size-cells = <1>;
269
-
#address-cells = <2>;
270
-
reg = <0xf000 0 0 0 0>;
271
-
ranges = <1 0 0x01000000 0 0
272
-
0x00001000>;
273
-
interrupt-parent = <&i8259>;
274
-
275
-
i8259: interrupt-controller@20 {
276
-
reg = <1 0x20 2
277
-
1 0xa0 2
278
-
1 0x4d0 2>;
279
-
interrupt-controller;
280
-
device_type = "interrupt-controller";
281
-
#address-cells = <0>;
282
-
#interrupt-cells = <2>;
283
-
compatible = "chrp,iic";
284
-
interrupts = <9 2 0 0>;
285
-
};
286
-
287
-
i8042@60 {
288
-
#size-cells = <0>;
289
-
#address-cells = <1>;
290
-
reg = <1 0x60 1 1 0x64 1>;
291
-
interrupts = <1 3 12 3>;
292
-
interrupt-parent = <&i8259>;
293
-
294
-
keyboard@0 {
295
-
reg = <0>;
296
-
compatible = "pnpPNP,303";
297
-
};
298
-
299
-
mouse@1 {
300
-
reg = <1>;
301
-
compatible = "pnpPNP,f03";
302
-
};
303
-
};
304
-
305
-
rtc@70 {
306
-
compatible =
307
-
"pnpPNP,b00";
308
-
reg = <1 0x70 2>;
309
-
};
310
-
311
-
gpio@400 {
312
-
reg = <1 0x400 0x80>;
313
-
};
314
-
};
315
-
};
316
-
};
317
-
318
-
};
319
-
320
-
pci1: pcie@fffe09000 {
321
-
reg = <0x0f 0xffe09000 0x0 0x1000>;
322
-
ranges = <0x02000000 0x0 0xe0000000 0x0c 0x20000000 0x0 0x20000000
323
-
0x01000000 0x0 0x00000000 0x0f 0xffc10000 0x0 0x00010000>;
324
-
325
-
pcie@0 {
326
-
ranges = <0x02000000 0x0 0xe0000000
327
-
0x02000000 0x0 0xe0000000
328
-
0x0 0x20000000
329
-
330
-
0x01000000 0x0 0x00000000
331
-
0x01000000 0x0 0x00000000
332
-
0x0 0x00010000>;
333
-
};
334
-
};
335
-
};
336
-
337
-
/include/ "mpc8641si-post.dtsi"
-192
arch/powerpc/boot/dts/mpc7448hpc2.dts
-192
arch/powerpc/boot/dts/mpc7448hpc2.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC7448HPC2 (Taiga) board Device Tree Source
4
-
*
5
-
* Copyright 2006, 2008 Freescale Semiconductor Inc.
6
-
* 2006 Roy Zang <Roy Zang at freescale.com>.
7
-
*/
8
-
9
-
/dts-v1/;
10
-
11
-
/ {
12
-
model = "mpc7448hpc2";
13
-
compatible = "mpc74xx";
14
-
#address-cells = <1>;
15
-
#size-cells = <1>;
16
-
17
-
aliases {
18
-
ethernet0 = &enet0;
19
-
ethernet1 = &enet1;
20
-
21
-
serial0 = &serial0;
22
-
serial1 = &serial1;
23
-
24
-
pci0 = &pci0;
25
-
};
26
-
27
-
cpus {
28
-
#address-cells = <1>;
29
-
#size-cells =<0>;
30
-
31
-
PowerPC,7448@0 {
32
-
device_type = "cpu";
33
-
reg = <0x0>;
34
-
d-cache-line-size = <32>; // 32 bytes
35
-
i-cache-line-size = <32>; // 32 bytes
36
-
d-cache-size = <0x8000>; // L1, 32K bytes
37
-
i-cache-size = <0x8000>; // L1, 32K bytes
38
-
timebase-frequency = <0>; // 33 MHz, from uboot
39
-
clock-frequency = <0>; // From U-Boot
40
-
bus-frequency = <0>; // From U-Boot
41
-
};
42
-
};
43
-
44
-
memory {
45
-
device_type = "memory";
46
-
reg = <0x0 0x20000000 // DDR2 512M at 0
47
-
>;
48
-
};
49
-
50
-
tsi108@c0000000 {
51
-
#address-cells = <1>;
52
-
#size-cells = <1>;
53
-
device_type = "tsi-bridge";
54
-
ranges = <0x0 0xc0000000 0x10000>;
55
-
reg = <0xc0000000 0x10000>;
56
-
bus-frequency = <0>;
57
-
58
-
i2c@7000 {
59
-
interrupt-parent = <&mpic>;
60
-
interrupts = <14 0>;
61
-
reg = <0x7000 0x400>;
62
-
device_type = "i2c";
63
-
compatible = "tsi108-i2c";
64
-
};
65
-
66
-
MDIO: mdio@6000 {
67
-
compatible = "tsi108-mdio";
68
-
reg = <0x6000 0x50>;
69
-
#address-cells = <1>;
70
-
#size-cells = <0>;
71
-
72
-
phy8: ethernet-phy@8 {
73
-
interrupt-parent = <&mpic>;
74
-
interrupts = <2 1>;
75
-
reg = <0x8>;
76
-
};
77
-
78
-
phy9: ethernet-phy@9 {
79
-
interrupt-parent = <&mpic>;
80
-
interrupts = <2 1>;
81
-
reg = <0x9>;
82
-
};
83
-
84
-
};
85
-
86
-
enet0: ethernet@6200 {
87
-
linux,network-index = <0>;
88
-
#size-cells = <0>;
89
-
device_type = "network";
90
-
compatible = "tsi108-ethernet";
91
-
reg = <0x6000 0x200>;
92
-
address = [ 00 06 D2 00 00 01 ];
93
-
interrupts = <16 2>;
94
-
interrupt-parent = <&mpic>;
95
-
mdio-handle = <&MDIO>;
96
-
phy-handle = <&phy8>;
97
-
};
98
-
99
-
enet1: ethernet@6600 {
100
-
linux,network-index = <1>;
101
-
#address-cells = <1>;
102
-
#size-cells = <0>;
103
-
device_type = "network";
104
-
compatible = "tsi108-ethernet";
105
-
reg = <0x6400 0x200>;
106
-
address = [ 00 06 D2 00 00 02 ];
107
-
interrupts = <17 2>;
108
-
interrupt-parent = <&mpic>;
109
-
mdio-handle = <&MDIO>;
110
-
phy-handle = <&phy9>;
111
-
};
112
-
113
-
serial0: serial@7808 {
114
-
device_type = "serial";
115
-
compatible = "ns16550";
116
-
reg = <0x7808 0x200>;
117
-
clock-frequency = <1064000000>;
118
-
interrupts = <12 0>;
119
-
interrupt-parent = <&mpic>;
120
-
};
121
-
122
-
serial1: serial@7c08 {
123
-
device_type = "serial";
124
-
compatible = "ns16550";
125
-
reg = <0x7c08 0x200>;
126
-
clock-frequency = <1064000000>;
127
-
interrupts = <13 0>;
128
-
interrupt-parent = <&mpic>;
129
-
};
130
-
131
-
mpic: pic@7400 {
132
-
interrupt-controller;
133
-
#address-cells = <0>;
134
-
#interrupt-cells = <2>;
135
-
reg = <0x7400 0x400>;
136
-
compatible = "chrp,open-pic";
137
-
device_type = "open-pic";
138
-
};
139
-
pci0: pci@1000 {
140
-
compatible = "tsi108-pci";
141
-
device_type = "pci";
142
-
#interrupt-cells = <1>;
143
-
#size-cells = <2>;
144
-
#address-cells = <3>;
145
-
reg = <0x1000 0x1000>;
146
-
bus-range = <0 0>;
147
-
ranges = <0x2000000 0x0 0xe0000000 0xe0000000 0x0 0x1a000000
148
-
0x1000000 0x0 0x0 0xfa000000 0x0 0x10000>;
149
-
clock-frequency = <133333332>;
150
-
interrupt-parent = <&mpic>;
151
-
interrupts = <23 2>;
152
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
153
-
interrupt-map = <
154
-
155
-
/* IDSEL 0x11 */
156
-
0x800 0x0 0x0 0x1 &RT0 0x24 0x0
157
-
0x800 0x0 0x0 0x2 &RT0 0x25 0x0
158
-
0x800 0x0 0x0 0x3 &RT0 0x26 0x0
159
-
0x800 0x0 0x0 0x4 &RT0 0x27 0x0
160
-
161
-
/* IDSEL 0x12 */
162
-
0x1000 0x0 0x0 0x1 &RT0 0x25 0x0
163
-
0x1000 0x0 0x0 0x2 &RT0 0x26 0x0
164
-
0x1000 0x0 0x0 0x3 &RT0 0x27 0x0
165
-
0x1000 0x0 0x0 0x4 &RT0 0x24 0x0
166
-
167
-
/* IDSEL 0x13 */
168
-
0x1800 0x0 0x0 0x1 &RT0 0x26 0x0
169
-
0x1800 0x0 0x0 0x2 &RT0 0x27 0x0
170
-
0x1800 0x0 0x0 0x3 &RT0 0x24 0x0
171
-
0x1800 0x0 0x0 0x4 &RT0 0x25 0x0
172
-
173
-
/* IDSEL 0x14 */
174
-
0x2000 0x0 0x0 0x1 &RT0 0x27 0x0
175
-
0x2000 0x0 0x0 0x2 &RT0 0x24 0x0
176
-
0x2000 0x0 0x0 0x3 &RT0 0x25 0x0
177
-
0x2000 0x0 0x0 0x4 &RT0 0x26 0x0
178
-
>;
179
-
180
-
RT0: router@1180 {
181
-
clock-frequency = <0>;
182
-
interrupt-controller;
183
-
device_type = "pic-router";
184
-
#address-cells = <0>;
185
-
#interrupt-cells = <2>;
186
-
big-endian;
187
-
interrupts = <23 2>;
188
-
interrupt-parent = <&mpic>;
189
-
};
190
-
};
191
-
};
192
-
};
-263
arch/powerpc/boot/dts/mpc8272ads.dts
-263
arch/powerpc/boot/dts/mpc8272ads.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8272 ADS Device Tree Source
4
-
*
5
-
* Copyright 2005,2008 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
/ {
11
-
model = "MPC8272ADS";
12
-
compatible = "fsl,mpc8272ads";
13
-
#address-cells = <1>;
14
-
#size-cells = <1>;
15
-
16
-
aliases {
17
-
ethernet0 = ð0;
18
-
ethernet1 = ð1;
19
-
serial0 = &scc1;
20
-
serial1 = &scc4;
21
-
};
22
-
23
-
cpus {
24
-
#address-cells = <1>;
25
-
#size-cells = <0>;
26
-
27
-
PowerPC,8272@0 {
28
-
device_type = "cpu";
29
-
reg = <0x0>;
30
-
d-cache-line-size = <32>;
31
-
i-cache-line-size = <32>;
32
-
d-cache-size = <16384>;
33
-
i-cache-size = <16384>;
34
-
timebase-frequency = <0>;
35
-
bus-frequency = <0>;
36
-
clock-frequency = <0>;
37
-
};
38
-
};
39
-
40
-
memory {
41
-
device_type = "memory";
42
-
reg = <0x0 0x0>;
43
-
};
44
-
45
-
localbus@f0010100 {
46
-
compatible = "fsl,mpc8272-localbus",
47
-
"fsl,pq2-localbus";
48
-
#address-cells = <2>;
49
-
#size-cells = <1>;
50
-
reg = <0xf0010100 0x40>;
51
-
52
-
ranges = <0x0 0x0 0xff800000 0x00800000
53
-
0x1 0x0 0xf4500000 0x8000
54
-
0x3 0x0 0xf8200000 0x8000>;
55
-
56
-
flash@0,0 {
57
-
compatible = "jedec-flash";
58
-
reg = <0x0 0x0 0x00800000>;
59
-
bank-width = <4>;
60
-
device-width = <1>;
61
-
};
62
-
63
-
board-control@1,0 {
64
-
reg = <0x1 0x0 0x20>;
65
-
compatible = "fsl,mpc8272ads-bcsr";
66
-
};
67
-
68
-
PCI_PIC: interrupt-controller@3,0 {
69
-
compatible = "fsl,mpc8272ads-pci-pic",
70
-
"fsl,pq2ads-pci-pic";
71
-
#interrupt-cells = <1>;
72
-
interrupt-controller;
73
-
reg = <0x3 0x0 0x8>;
74
-
interrupt-parent = <&PIC>;
75
-
interrupts = <20 8>;
76
-
};
77
-
};
78
-
79
-
80
-
pci@f0010800 {
81
-
device_type = "pci";
82
-
reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
83
-
compatible = "fsl,mpc8272-pci", "fsl,pq2-pci";
84
-
#interrupt-cells = <1>;
85
-
#size-cells = <2>;
86
-
#address-cells = <3>;
87
-
clock-frequency = <66666666>;
88
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
89
-
interrupt-map = <
90
-
/* IDSEL 0x16 */
91
-
0xb000 0x0 0x0 0x1 &PCI_PIC 0
92
-
0xb000 0x0 0x0 0x2 &PCI_PIC 1
93
-
0xb000 0x0 0x0 0x3 &PCI_PIC 2
94
-
0xb000 0x0 0x0 0x4 &PCI_PIC 3
95
-
96
-
/* IDSEL 0x17 */
97
-
0xb800 0x0 0x0 0x1 &PCI_PIC 4
98
-
0xb800 0x0 0x0 0x2 &PCI_PIC 5
99
-
0xb800 0x0 0x0 0x3 &PCI_PIC 6
100
-
0xb800 0x0 0x0 0x4 &PCI_PIC 7
101
-
102
-
/* IDSEL 0x18 */
103
-
0xc000 0x0 0x0 0x1 &PCI_PIC 8
104
-
0xc000 0x0 0x0 0x2 &PCI_PIC 9
105
-
0xc000 0x0 0x0 0x3 &PCI_PIC 10
106
-
0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
107
-
108
-
interrupt-parent = <&PIC>;
109
-
interrupts = <18 8>;
110
-
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
111
-
0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
112
-
0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
113
-
};
114
-
115
-
soc@f0000000 {
116
-
#address-cells = <1>;
117
-
#size-cells = <1>;
118
-
device_type = "soc";
119
-
compatible = "fsl,mpc8272", "fsl,pq2-soc";
120
-
ranges = <0x0 0xf0000000 0x53000>;
121
-
122
-
// Temporary -- will go away once kernel uses ranges for get_immrbase().
123
-
reg = <0xf0000000 0x53000>;
124
-
125
-
cpm@119c0 {
126
-
#address-cells = <1>;
127
-
#size-cells = <1>;
128
-
compatible = "fsl,mpc8272-cpm", "fsl,cpm2";
129
-
reg = <0x119c0 0x30>;
130
-
ranges;
131
-
132
-
muram@0 {
133
-
#address-cells = <1>;
134
-
#size-cells = <1>;
135
-
ranges = <0x0 0x0 0x10000>;
136
-
137
-
data@0 {
138
-
compatible = "fsl,cpm-muram-data";
139
-
reg = <0x0 0x2000 0x9800 0x800>;
140
-
};
141
-
};
142
-
143
-
brg@119f0 {
144
-
compatible = "fsl,mpc8272-brg",
145
-
"fsl,cpm2-brg",
146
-
"fsl,cpm-brg";
147
-
reg = <0x119f0 0x10 0x115f0 0x10>;
148
-
};
149
-
150
-
scc1: serial@11a00 {
151
-
device_type = "serial";
152
-
compatible = "fsl,mpc8272-scc-uart",
153
-
"fsl,cpm2-scc-uart";
154
-
reg = <0x11a00 0x20 0x8000 0x100>;
155
-
interrupts = <40 8>;
156
-
interrupt-parent = <&PIC>;
157
-
fsl,cpm-brg = <1>;
158
-
fsl,cpm-command = <0x800000>;
159
-
};
160
-
161
-
scc4: serial@11a60 {
162
-
device_type = "serial";
163
-
compatible = "fsl,mpc8272-scc-uart",
164
-
"fsl,cpm2-scc-uart";
165
-
reg = <0x11a60 0x20 0x8300 0x100>;
166
-
interrupts = <43 8>;
167
-
interrupt-parent = <&PIC>;
168
-
fsl,cpm-brg = <4>;
169
-
fsl,cpm-command = <0xce00000>;
170
-
};
171
-
172
-
usb@11b60 {
173
-
compatible = "fsl,mpc8272-cpm-usb";
174
-
reg = <0x11b60 0x40 0x8b00 0x100>;
175
-
interrupts = <11 8>;
176
-
interrupt-parent = <&PIC>;
177
-
mode = "peripheral";
178
-
};
179
-
180
-
mdio@10d40 {
181
-
compatible = "fsl,mpc8272ads-mdio-bitbang",
182
-
"fsl,mpc8272-mdio-bitbang",
183
-
"fsl,cpm2-mdio-bitbang";
184
-
reg = <0x10d40 0x14>;
185
-
#address-cells = <1>;
186
-
#size-cells = <0>;
187
-
fsl,mdio-pin = <18>;
188
-
fsl,mdc-pin = <19>;
189
-
190
-
PHY0: ethernet-phy@0 {
191
-
interrupt-parent = <&PIC>;
192
-
interrupts = <23 8>;
193
-
reg = <0x0>;
194
-
};
195
-
196
-
PHY1: ethernet-phy@1 {
197
-
interrupt-parent = <&PIC>;
198
-
interrupts = <23 8>;
199
-
reg = <0x3>;
200
-
};
201
-
};
202
-
203
-
eth0: ethernet@11300 {
204
-
device_type = "network";
205
-
compatible = "fsl,mpc8272-fcc-enet",
206
-
"fsl,cpm2-fcc-enet";
207
-
reg = <0x11300 0x20 0x8400 0x100 0x11390 0x1>;
208
-
local-mac-address = [ 00 00 00 00 00 00 ];
209
-
interrupts = <32 8>;
210
-
interrupt-parent = <&PIC>;
211
-
phy-handle = <&PHY0>;
212
-
linux,network-index = <0>;
213
-
fsl,cpm-command = <0x12000300>;
214
-
};
215
-
216
-
eth1: ethernet@11320 {
217
-
device_type = "network";
218
-
compatible = "fsl,mpc8272-fcc-enet",
219
-
"fsl,cpm2-fcc-enet";
220
-
reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
221
-
local-mac-address = [ 00 00 00 00 00 00 ];
222
-
interrupts = <33 8>;
223
-
interrupt-parent = <&PIC>;
224
-
phy-handle = <&PHY1>;
225
-
linux,network-index = <1>;
226
-
fsl,cpm-command = <0x16200300>;
227
-
};
228
-
229
-
i2c@11860 {
230
-
compatible = "fsl,mpc8272-i2c",
231
-
"fsl,cpm2-i2c";
232
-
reg = <0x11860 0x20 0x8afc 0x2>;
233
-
interrupts = <1 8>;
234
-
interrupt-parent = <&PIC>;
235
-
fsl,cpm-command = <0x29600000>;
236
-
#address-cells = <1>;
237
-
#size-cells = <0>;
238
-
};
239
-
};
240
-
241
-
PIC: interrupt-controller@10c00 {
242
-
#interrupt-cells = <2>;
243
-
interrupt-controller;
244
-
reg = <0x10c00 0x80>;
245
-
compatible = "fsl,mpc8272-pic", "fsl,cpm2-pic";
246
-
};
247
-
248
-
crypto@30000 {
249
-
compatible = "fsl,sec1.0";
250
-
reg = <0x40000 0x13000>;
251
-
interrupts = <47 0x8>;
252
-
interrupt-parent = <&PIC>;
253
-
fsl,num-channels = <4>;
254
-
fsl,channel-fifo-len = <24>;
255
-
fsl,exec-units-mask = <0x7e>;
256
-
fsl,descriptor-types-mask = <0x1010415>;
257
-
};
258
-
};
259
-
260
-
chosen {
261
-
stdout-path = "/soc/cpm/serial@11a00";
262
-
};
263
-
};
-436
arch/powerpc/boot/dts/mpc832x_mds.dts
-436
arch/powerpc/boot/dts/mpc832x_mds.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8323E EMDS Device Tree Source
4
-
*
5
-
* Copyright 2006 Freescale Semiconductor Inc.
6
-
*
7
-
8
-
* To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
9
-
* this:
10
-
*
11
-
* 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
12
-
* 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
13
-
* next to the serial ports.
14
-
* 3) Solder a wire from U61-22 to P19K-22.
15
-
*
16
-
* Note that there's a typo in the schematic. The board labels the last column
17
-
* of pins "P19K", but in the schematic, that column is called "P19J". So if
18
-
* you're going by the schematic, the pin is called "P19J-K22".
19
-
*/
20
-
21
-
/dts-v1/;
22
-
23
-
/ {
24
-
model = "MPC8323EMDS";
25
-
compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
26
-
#address-cells = <1>;
27
-
#size-cells = <1>;
28
-
29
-
aliases {
30
-
ethernet0 = &enet0;
31
-
ethernet1 = &enet1;
32
-
serial0 = &serial0;
33
-
serial1 = &serial1;
34
-
pci0 = &pci0;
35
-
};
36
-
37
-
cpus {
38
-
#address-cells = <1>;
39
-
#size-cells = <0>;
40
-
41
-
PowerPC,8323@0 {
42
-
device_type = "cpu";
43
-
reg = <0x0>;
44
-
d-cache-line-size = <32>; // 32 bytes
45
-
i-cache-line-size = <32>; // 32 bytes
46
-
d-cache-size = <16384>; // L1, 16K
47
-
i-cache-size = <16384>; // L1, 16K
48
-
timebase-frequency = <0>;
49
-
bus-frequency = <0>;
50
-
clock-frequency = <0>;
51
-
};
52
-
};
53
-
54
-
memory {
55
-
device_type = "memory";
56
-
reg = <0x00000000 0x08000000>;
57
-
};
58
-
59
-
bcsr@f8000000 {
60
-
compatible = "fsl,mpc8323mds-bcsr";
61
-
reg = <0xf8000000 0x8000>;
62
-
};
63
-
64
-
soc8323@e0000000 {
65
-
#address-cells = <1>;
66
-
#size-cells = <1>;
67
-
device_type = "soc";
68
-
compatible = "simple-bus";
69
-
ranges = <0x0 0xe0000000 0x00100000>;
70
-
reg = <0xe0000000 0x00000200>;
71
-
bus-frequency = <132000000>;
72
-
73
-
wdt@200 {
74
-
device_type = "watchdog";
75
-
compatible = "mpc83xx_wdt";
76
-
reg = <0x200 0x100>;
77
-
};
78
-
79
-
pmc: power@b00 {
80
-
compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
81
-
reg = <0xb00 0x100 0xa00 0x100>;
82
-
interrupts = <80 0x8>;
83
-
interrupt-parent = <&ipic>;
84
-
};
85
-
86
-
i2c@3000 {
87
-
#address-cells = <1>;
88
-
#size-cells = <0>;
89
-
cell-index = <0>;
90
-
compatible = "fsl-i2c";
91
-
reg = <0x3000 0x100>;
92
-
interrupts = <14 0x8>;
93
-
interrupt-parent = <&ipic>;
94
-
dfsrr;
95
-
96
-
rtc@68 {
97
-
compatible = "dallas,ds1374";
98
-
reg = <0x68>;
99
-
};
100
-
};
101
-
102
-
serial0: serial@4500 {
103
-
cell-index = <0>;
104
-
device_type = "serial";
105
-
compatible = "fsl,ns16550", "ns16550";
106
-
reg = <0x4500 0x100>;
107
-
clock-frequency = <0>;
108
-
interrupts = <9 0x8>;
109
-
interrupt-parent = <&ipic>;
110
-
};
111
-
112
-
serial1: serial@4600 {
113
-
cell-index = <1>;
114
-
device_type = "serial";
115
-
compatible = "fsl,ns16550", "ns16550";
116
-
reg = <0x4600 0x100>;
117
-
clock-frequency = <0>;
118
-
interrupts = <10 0x8>;
119
-
interrupt-parent = <&ipic>;
120
-
};
121
-
122
-
dma@82a8 {
123
-
#address-cells = <1>;
124
-
#size-cells = <1>;
125
-
compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
126
-
reg = <0x82a8 4>;
127
-
ranges = <0 0x8100 0x1a8>;
128
-
interrupt-parent = <&ipic>;
129
-
interrupts = <71 8>;
130
-
cell-index = <0>;
131
-
dma-channel@0 {
132
-
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
133
-
reg = <0 0x80>;
134
-
cell-index = <0>;
135
-
interrupt-parent = <&ipic>;
136
-
interrupts = <71 8>;
137
-
};
138
-
dma-channel@80 {
139
-
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
140
-
reg = <0x80 0x80>;
141
-
cell-index = <1>;
142
-
interrupt-parent = <&ipic>;
143
-
interrupts = <71 8>;
144
-
};
145
-
dma-channel@100 {
146
-
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
147
-
reg = <0x100 0x80>;
148
-
cell-index = <2>;
149
-
interrupt-parent = <&ipic>;
150
-
interrupts = <71 8>;
151
-
};
152
-
dma-channel@180 {
153
-
compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
154
-
reg = <0x180 0x28>;
155
-
cell-index = <3>;
156
-
interrupt-parent = <&ipic>;
157
-
interrupts = <71 8>;
158
-
};
159
-
};
160
-
161
-
crypto@30000 {
162
-
compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
163
-
reg = <0x30000 0x10000>;
164
-
interrupts = <11 0x8>;
165
-
interrupt-parent = <&ipic>;
166
-
fsl,num-channels = <1>;
167
-
fsl,channel-fifo-len = <24>;
168
-
fsl,exec-units-mask = <0x4c>;
169
-
fsl,descriptor-types-mask = <0x0122003f>;
170
-
sleep = <&pmc 0x03000000>;
171
-
};
172
-
173
-
ipic: pic@700 {
174
-
interrupt-controller;
175
-
#address-cells = <0>;
176
-
#interrupt-cells = <2>;
177
-
reg = <0x700 0x100>;
178
-
device_type = "ipic";
179
-
};
180
-
181
-
par_io@1400 {
182
-
reg = <0x1400 0x100>;
183
-
device_type = "par_io";
184
-
num-ports = <7>;
185
-
186
-
pio3: ucc_pin@3 {
187
-
pio-map = <
188
-
/* port pin dir open_drain assignment has_irq */
189
-
3 4 3 0 2 0 /* MDIO */
190
-
3 5 1 0 2 0 /* MDC */
191
-
0 13 2 0 1 0 /* RX_CLK (CLK9) */
192
-
3 24 2 0 1 0 /* TX_CLK (CLK10) */
193
-
1 0 1 0 1 0 /* TxD0 */
194
-
1 1 1 0 1 0 /* TxD1 */
195
-
1 2 1 0 1 0 /* TxD2 */
196
-
1 3 1 0 1 0 /* TxD3 */
197
-
1 4 2 0 1 0 /* RxD0 */
198
-
1 5 2 0 1 0 /* RxD1 */
199
-
1 6 2 0 1 0 /* RxD2 */
200
-
1 7 2 0 1 0 /* RxD3 */
201
-
1 8 2 0 1 0 /* RX_ER */
202
-
1 9 1 0 1 0 /* TX_ER */
203
-
1 10 2 0 1 0 /* RX_DV */
204
-
1 11 2 0 1 0 /* COL */
205
-
1 12 1 0 1 0 /* TX_EN */
206
-
1 13 2 0 1 0>; /* CRS */
207
-
};
208
-
pio4: ucc_pin@4 {
209
-
pio-map = <
210
-
/* port pin dir open_drain assignment has_irq */
211
-
3 31 2 0 1 0 /* RX_CLK (CLK7) */
212
-
3 6 2 0 1 0 /* TX_CLK (CLK8) */
213
-
1 18 1 0 1 0 /* TxD0 */
214
-
1 19 1 0 1 0 /* TxD1 */
215
-
1 20 1 0 1 0 /* TxD2 */
216
-
1 21 1 0 1 0 /* TxD3 */
217
-
1 22 2 0 1 0 /* RxD0 */
218
-
1 23 2 0 1 0 /* RxD1 */
219
-
1 24 2 0 1 0 /* RxD2 */
220
-
1 25 2 0 1 0 /* RxD3 */
221
-
1 26 2 0 1 0 /* RX_ER */
222
-
1 27 1 0 1 0 /* TX_ER */
223
-
1 28 2 0 1 0 /* RX_DV */
224
-
1 29 2 0 1 0 /* COL */
225
-
1 30 1 0 1 0 /* TX_EN */
226
-
1 31 2 0 1 0>; /* CRS */
227
-
};
228
-
pio5: ucc_pin@5 {
229
-
pio-map = <
230
-
/*
231
-
* open has
232
-
* port pin dir drain sel irq
233
-
*/
234
-
2 0 1 0 2 0 /* TxD5 */
235
-
2 8 2 0 2 0 /* RxD5 */
236
-
237
-
2 29 2 0 0 0 /* CTS5 */
238
-
2 31 1 0 2 0 /* RTS5 */
239
-
240
-
2 24 2 0 0 0 /* CD */
241
-
242
-
>;
243
-
};
244
-
245
-
};
246
-
};
247
-
248
-
qe@e0100000 {
249
-
#address-cells = <1>;
250
-
#size-cells = <1>;
251
-
device_type = "qe";
252
-
compatible = "fsl,qe";
253
-
ranges = <0x0 0xe0100000 0x00100000>;
254
-
reg = <0xe0100000 0x480>;
255
-
brg-frequency = <0>;
256
-
bus-frequency = <198000000>;
257
-
fsl,qe-num-riscs = <1>;
258
-
fsl,qe-num-snums = <28>;
259
-
260
-
muram@10000 {
261
-
#address-cells = <1>;
262
-
#size-cells = <1>;
263
-
compatible = "fsl,qe-muram", "fsl,cpm-muram";
264
-
ranges = <0x0 0x00010000 0x00004000>;
265
-
266
-
data-only@0 {
267
-
compatible = "fsl,qe-muram-data",
268
-
"fsl,cpm-muram-data";
269
-
reg = <0x0 0x4000>;
270
-
};
271
-
};
272
-
273
-
spi@4c0 {
274
-
cell-index = <0>;
275
-
compatible = "fsl,spi";
276
-
reg = <0x4c0 0x40>;
277
-
interrupts = <2>;
278
-
interrupt-parent = <&qeic>;
279
-
mode = "cpu";
280
-
};
281
-
282
-
spi@500 {
283
-
cell-index = <1>;
284
-
compatible = "fsl,spi";
285
-
reg = <0x500 0x40>;
286
-
interrupts = <1>;
287
-
interrupt-parent = <&qeic>;
288
-
mode = "cpu";
289
-
};
290
-
291
-
usb@6c0 {
292
-
compatible = "qe_udc";
293
-
reg = <0x6c0 0x40 0x8b00 0x100>;
294
-
interrupts = <11>;
295
-
interrupt-parent = <&qeic>;
296
-
mode = "slave";
297
-
};
298
-
299
-
enet0: ucc@2200 {
300
-
device_type = "network";
301
-
compatible = "ucc_geth";
302
-
cell-index = <3>;
303
-
reg = <0x2200 0x200>;
304
-
interrupts = <34>;
305
-
interrupt-parent = <&qeic>;
306
-
local-mac-address = [ 00 00 00 00 00 00 ];
307
-
rx-clock-name = "clk9";
308
-
tx-clock-name = "clk10";
309
-
phy-handle = <&phy3>;
310
-
pio-handle = <&pio3>;
311
-
};
312
-
313
-
enet1: ucc@3200 {
314
-
device_type = "network";
315
-
compatible = "ucc_geth";
316
-
cell-index = <4>;
317
-
reg = <0x3200 0x200>;
318
-
interrupts = <35>;
319
-
interrupt-parent = <&qeic>;
320
-
local-mac-address = [ 00 00 00 00 00 00 ];
321
-
rx-clock-name = "clk7";
322
-
tx-clock-name = "clk8";
323
-
phy-handle = <&phy4>;
324
-
pio-handle = <&pio4>;
325
-
};
326
-
327
-
ucc@2400 {
328
-
device_type = "serial";
329
-
compatible = "ucc_uart";
330
-
cell-index = <5>; /* The UCC number, 1-7*/
331
-
port-number = <0>; /* Which ttyQEx device */
332
-
soft-uart; /* We need Soft-UART */
333
-
reg = <0x2400 0x200>;
334
-
interrupts = <40>; /* From Table 18-12 */
335
-
interrupt-parent = < &qeic >;
336
-
/*
337
-
* For Soft-UART, we need to set TX to 1X, which
338
-
* means specifying separate clock sources.
339
-
*/
340
-
rx-clock-name = "brg5";
341
-
tx-clock-name = "brg6";
342
-
pio-handle = < &pio5 >;
343
-
};
344
-
345
-
346
-
mdio@2320 {
347
-
#address-cells = <1>;
348
-
#size-cells = <0>;
349
-
reg = <0x2320 0x18>;
350
-
compatible = "fsl,ucc-mdio";
351
-
352
-
phy3: ethernet-phy@3 {
353
-
interrupt-parent = <&ipic>;
354
-
interrupts = <17 0x8>;
355
-
reg = <0x3>;
356
-
};
357
-
phy4: ethernet-phy@4 {
358
-
interrupt-parent = <&ipic>;
359
-
interrupts = <18 0x8>;
360
-
reg = <0x4>;
361
-
};
362
-
};
363
-
364
-
qeic: interrupt-controller@80 {
365
-
interrupt-controller;
366
-
compatible = "fsl,qe-ic";
367
-
#address-cells = <0>;
368
-
#interrupt-cells = <1>;
369
-
reg = <0x80 0x80>;
370
-
big-endian;
371
-
interrupts = <32 0x8 33 0x8>; //high:32 low:33
372
-
interrupt-parent = <&ipic>;
373
-
};
374
-
};
375
-
376
-
pci0: pci@e0008500 {
377
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
378
-
interrupt-map = <
379
-
/* IDSEL 0x11 AD17 */
380
-
0x8800 0x0 0x0 0x1 &ipic 20 0x8
381
-
0x8800 0x0 0x0 0x2 &ipic 21 0x8
382
-
0x8800 0x0 0x0 0x3 &ipic 22 0x8
383
-
0x8800 0x0 0x0 0x4 &ipic 23 0x8
384
-
385
-
/* IDSEL 0x12 AD18 */
386
-
0x9000 0x0 0x0 0x1 &ipic 22 0x8
387
-
0x9000 0x0 0x0 0x2 &ipic 23 0x8
388
-
0x9000 0x0 0x0 0x3 &ipic 20 0x8
389
-
0x9000 0x0 0x0 0x4 &ipic 21 0x8
390
-
391
-
/* IDSEL 0x13 AD19 */
392
-
0x9800 0x0 0x0 0x1 &ipic 23 0x8
393
-
0x9800 0x0 0x0 0x2 &ipic 20 0x8
394
-
0x9800 0x0 0x0 0x3 &ipic 21 0x8
395
-
0x9800 0x0 0x0 0x4 &ipic 22 0x8
396
-
397
-
/* IDSEL 0x15 AD21*/
398
-
0xa800 0x0 0x0 0x1 &ipic 20 0x8
399
-
0xa800 0x0 0x0 0x2 &ipic 21 0x8
400
-
0xa800 0x0 0x0 0x3 &ipic 22 0x8
401
-
0xa800 0x0 0x0 0x4 &ipic 23 0x8
402
-
403
-
/* IDSEL 0x16 AD22*/
404
-
0xb000 0x0 0x0 0x1 &ipic 23 0x8
405
-
0xb000 0x0 0x0 0x2 &ipic 20 0x8
406
-
0xb000 0x0 0x0 0x3 &ipic 21 0x8
407
-
0xb000 0x0 0x0 0x4 &ipic 22 0x8
408
-
409
-
/* IDSEL 0x17 AD23*/
410
-
0xb800 0x0 0x0 0x1 &ipic 22 0x8
411
-
0xb800 0x0 0x0 0x2 &ipic 23 0x8
412
-
0xb800 0x0 0x0 0x3 &ipic 20 0x8
413
-
0xb800 0x0 0x0 0x4 &ipic 21 0x8
414
-
415
-
/* IDSEL 0x18 AD24*/
416
-
0xc000 0x0 0x0 0x1 &ipic 21 0x8
417
-
0xc000 0x0 0x0 0x2 &ipic 22 0x8
418
-
0xc000 0x0 0x0 0x3 &ipic 23 0x8
419
-
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
420
-
interrupt-parent = <&ipic>;
421
-
interrupts = <66 0x8>;
422
-
bus-range = <0x0 0x0>;
423
-
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
424
-
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
425
-
0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
426
-
clock-frequency = <0>;
427
-
#interrupt-cells = <1>;
428
-
#size-cells = <2>;
429
-
#address-cells = <3>;
430
-
reg = <0xe0008500 0x100 /* internal registers */
431
-
0xe0008300 0x8>; /* config space access registers */
432
-
compatible = "fsl,mpc8349-pci";
433
-
device_type = "pci";
434
-
sleep = <&pmc 0x00010000>;
435
-
};
436
-
};
-403
arch/powerpc/boot/dts/mpc834x_mds.dts
-403
arch/powerpc/boot/dts/mpc834x_mds.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8349E MDS Device Tree Source
4
-
*
5
-
* Copyright 2005, 2006 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
/ {
11
-
model = "MPC8349EMDS";
12
-
compatible = "MPC8349EMDS", "MPC834xMDS", "MPC83xxMDS";
13
-
#address-cells = <1>;
14
-
#size-cells = <1>;
15
-
16
-
aliases {
17
-
ethernet0 = &enet0;
18
-
ethernet1 = &enet1;
19
-
serial0 = &serial0;
20
-
serial1 = &serial1;
21
-
pci0 = &pci0;
22
-
pci1 = &pci1;
23
-
};
24
-
25
-
cpus {
26
-
#address-cells = <1>;
27
-
#size-cells = <0>;
28
-
29
-
PowerPC,8349@0 {
30
-
device_type = "cpu";
31
-
reg = <0x0>;
32
-
d-cache-line-size = <32>;
33
-
i-cache-line-size = <32>;
34
-
d-cache-size = <32768>;
35
-
i-cache-size = <32768>;
36
-
timebase-frequency = <0>; // from bootloader
37
-
bus-frequency = <0>; // from bootloader
38
-
clock-frequency = <0>; // from bootloader
39
-
};
40
-
};
41
-
42
-
memory {
43
-
device_type = "memory";
44
-
reg = <0x00000000 0x10000000>; // 256MB at 0
45
-
};
46
-
47
-
bcsr@e2400000 {
48
-
compatible = "fsl,mpc8349mds-bcsr";
49
-
reg = <0xe2400000 0x8000>;
50
-
};
51
-
52
-
soc8349@e0000000 {
53
-
#address-cells = <1>;
54
-
#size-cells = <1>;
55
-
device_type = "soc";
56
-
compatible = "simple-bus";
57
-
ranges = <0x0 0xe0000000 0x00100000>;
58
-
reg = <0xe0000000 0x00000200>;
59
-
bus-frequency = <0>;
60
-
61
-
wdt@200 {
62
-
device_type = "watchdog";
63
-
compatible = "mpc83xx_wdt";
64
-
reg = <0x200 0x100>;
65
-
};
66
-
67
-
i2c@3000 {
68
-
#address-cells = <1>;
69
-
#size-cells = <0>;
70
-
cell-index = <0>;
71
-
compatible = "fsl-i2c";
72
-
reg = <0x3000 0x100>;
73
-
interrupts = <14 0x8>;
74
-
interrupt-parent = <&ipic>;
75
-
dfsrr;
76
-
77
-
rtc@68 {
78
-
compatible = "dallas,ds1374";
79
-
reg = <0x68>;
80
-
};
81
-
};
82
-
83
-
i2c@3100 {
84
-
#address-cells = <1>;
85
-
#size-cells = <0>;
86
-
cell-index = <1>;
87
-
compatible = "fsl-i2c";
88
-
reg = <0x3100 0x100>;
89
-
interrupts = <15 0x8>;
90
-
interrupt-parent = <&ipic>;
91
-
dfsrr;
92
-
};
93
-
94
-
spi@7000 {
95
-
cell-index = <0>;
96
-
compatible = "fsl,spi";
97
-
reg = <0x7000 0x1000>;
98
-
interrupts = <16 0x8>;
99
-
interrupt-parent = <&ipic>;
100
-
mode = "cpu";
101
-
};
102
-
103
-
dma@82a8 {
104
-
#address-cells = <1>;
105
-
#size-cells = <1>;
106
-
compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
107
-
reg = <0x82a8 4>;
108
-
ranges = <0 0x8100 0x1a8>;
109
-
interrupt-parent = <&ipic>;
110
-
interrupts = <71 8>;
111
-
cell-index = <0>;
112
-
dma-channel@0 {
113
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
114
-
reg = <0 0x80>;
115
-
cell-index = <0>;
116
-
interrupt-parent = <&ipic>;
117
-
interrupts = <71 8>;
118
-
};
119
-
dma-channel@80 {
120
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
121
-
reg = <0x80 0x80>;
122
-
cell-index = <1>;
123
-
interrupt-parent = <&ipic>;
124
-
interrupts = <71 8>;
125
-
};
126
-
dma-channel@100 {
127
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
128
-
reg = <0x100 0x80>;
129
-
cell-index = <2>;
130
-
interrupt-parent = <&ipic>;
131
-
interrupts = <71 8>;
132
-
};
133
-
dma-channel@180 {
134
-
compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
135
-
reg = <0x180 0x28>;
136
-
cell-index = <3>;
137
-
interrupt-parent = <&ipic>;
138
-
interrupts = <71 8>;
139
-
};
140
-
};
141
-
142
-
/* phy type (ULPI or SERIAL) are only types supported for MPH */
143
-
/* port = 0 or 1 */
144
-
usb@22000 {
145
-
compatible = "fsl-usb2-mph";
146
-
reg = <0x22000 0x1000>;
147
-
#address-cells = <1>;
148
-
#size-cells = <0>;
149
-
interrupt-parent = <&ipic>;
150
-
interrupts = <39 0x8>;
151
-
phy_type = "ulpi";
152
-
port0;
153
-
};
154
-
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
155
-
usb@23000 {
156
-
compatible = "fsl-usb2-dr";
157
-
reg = <0x23000 0x1000>;
158
-
#address-cells = <1>;
159
-
#size-cells = <0>;
160
-
interrupt-parent = <&ipic>;
161
-
interrupts = <38 0x8>;
162
-
dr_mode = "otg";
163
-
phy_type = "ulpi";
164
-
};
165
-
166
-
enet0: ethernet@24000 {
167
-
#address-cells = <1>;
168
-
#size-cells = <1>;
169
-
cell-index = <0>;
170
-
device_type = "network";
171
-
model = "TSEC";
172
-
compatible = "gianfar";
173
-
reg = <0x24000 0x1000>;
174
-
ranges = <0x0 0x24000 0x1000>;
175
-
local-mac-address = [ 00 00 00 00 00 00 ];
176
-
interrupts = <32 0x8 33 0x8 34 0x8>;
177
-
interrupt-parent = <&ipic>;
178
-
tbi-handle = <&tbi0>;
179
-
phy-handle = <&phy0>;
180
-
linux,network-index = <0>;
181
-
182
-
mdio@520 {
183
-
#address-cells = <1>;
184
-
#size-cells = <0>;
185
-
compatible = "fsl,gianfar-mdio";
186
-
reg = <0x520 0x20>;
187
-
188
-
phy0: ethernet-phy@0 {
189
-
interrupt-parent = <&ipic>;
190
-
interrupts = <17 0x8>;
191
-
reg = <0x0>;
192
-
};
193
-
194
-
phy1: ethernet-phy@1 {
195
-
interrupt-parent = <&ipic>;
196
-
interrupts = <18 0x8>;
197
-
reg = <0x1>;
198
-
};
199
-
200
-
tbi0: tbi-phy@11 {
201
-
reg = <0x11>;
202
-
device_type = "tbi-phy";
203
-
};
204
-
};
205
-
};
206
-
207
-
enet1: ethernet@25000 {
208
-
#address-cells = <1>;
209
-
#size-cells = <1>;
210
-
cell-index = <1>;
211
-
device_type = "network";
212
-
model = "TSEC";
213
-
compatible = "gianfar";
214
-
reg = <0x25000 0x1000>;
215
-
ranges = <0x0 0x25000 0x1000>;
216
-
local-mac-address = [ 00 00 00 00 00 00 ];
217
-
interrupts = <35 0x8 36 0x8 37 0x8>;
218
-
interrupt-parent = <&ipic>;
219
-
tbi-handle = <&tbi1>;
220
-
phy-handle = <&phy1>;
221
-
linux,network-index = <1>;
222
-
223
-
mdio@520 {
224
-
#address-cells = <1>;
225
-
#size-cells = <0>;
226
-
compatible = "fsl,gianfar-tbi";
227
-
reg = <0x520 0x20>;
228
-
229
-
tbi1: tbi-phy@11 {
230
-
reg = <0x11>;
231
-
device_type = "tbi-phy";
232
-
};
233
-
};
234
-
};
235
-
236
-
serial0: serial@4500 {
237
-
cell-index = <0>;
238
-
device_type = "serial";
239
-
compatible = "fsl,ns16550", "ns16550";
240
-
reg = <0x4500 0x100>;
241
-
clock-frequency = <0>;
242
-
interrupts = <9 0x8>;
243
-
interrupt-parent = <&ipic>;
244
-
};
245
-
246
-
serial1: serial@4600 {
247
-
cell-index = <1>;
248
-
device_type = "serial";
249
-
compatible = "fsl,ns16550", "ns16550";
250
-
reg = <0x4600 0x100>;
251
-
clock-frequency = <0>;
252
-
interrupts = <10 0x8>;
253
-
interrupt-parent = <&ipic>;
254
-
};
255
-
256
-
crypto@30000 {
257
-
compatible = "fsl,sec2.0";
258
-
reg = <0x30000 0x10000>;
259
-
interrupts = <11 0x8>;
260
-
interrupt-parent = <&ipic>;
261
-
fsl,num-channels = <4>;
262
-
fsl,channel-fifo-len = <24>;
263
-
fsl,exec-units-mask = <0x7e>;
264
-
fsl,descriptor-types-mask = <0x01010ebf>;
265
-
};
266
-
267
-
/* IPIC
268
-
* interrupts cell = <intr #, sense>
269
-
* sense values match linux IORESOURCE_IRQ_* defines:
270
-
* sense == 8: Level, low assertion
271
-
* sense == 2: Edge, high-to-low change
272
-
*/
273
-
ipic: pic@700 {
274
-
interrupt-controller;
275
-
#address-cells = <0>;
276
-
#interrupt-cells = <2>;
277
-
reg = <0x700 0x100>;
278
-
device_type = "ipic";
279
-
};
280
-
};
281
-
282
-
pci0: pci@e0008500 {
283
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
284
-
interrupt-map = <
285
-
286
-
/* IDSEL 0x11 */
287
-
0x8800 0x0 0x0 0x1 &ipic 20 0x8
288
-
0x8800 0x0 0x0 0x2 &ipic 21 0x8
289
-
0x8800 0x0 0x0 0x3 &ipic 22 0x8
290
-
0x8800 0x0 0x0 0x4 &ipic 23 0x8
291
-
292
-
/* IDSEL 0x12 */
293
-
0x9000 0x0 0x0 0x1 &ipic 22 0x8
294
-
0x9000 0x0 0x0 0x2 &ipic 23 0x8
295
-
0x9000 0x0 0x0 0x3 &ipic 20 0x8
296
-
0x9000 0x0 0x0 0x4 &ipic 21 0x8
297
-
298
-
/* IDSEL 0x13 */
299
-
0x9800 0x0 0x0 0x1 &ipic 23 0x8
300
-
0x9800 0x0 0x0 0x2 &ipic 20 0x8
301
-
0x9800 0x0 0x0 0x3 &ipic 21 0x8
302
-
0x9800 0x0 0x0 0x4 &ipic 22 0x8
303
-
304
-
/* IDSEL 0x15 */
305
-
0xa800 0x0 0x0 0x1 &ipic 20 0x8
306
-
0xa800 0x0 0x0 0x2 &ipic 21 0x8
307
-
0xa800 0x0 0x0 0x3 &ipic 22 0x8
308
-
0xa800 0x0 0x0 0x4 &ipic 23 0x8
309
-
310
-
/* IDSEL 0x16 */
311
-
0xb000 0x0 0x0 0x1 &ipic 23 0x8
312
-
0xb000 0x0 0x0 0x2 &ipic 20 0x8
313
-
0xb000 0x0 0x0 0x3 &ipic 21 0x8
314
-
0xb000 0x0 0x0 0x4 &ipic 22 0x8
315
-
316
-
/* IDSEL 0x17 */
317
-
0xb800 0x0 0x0 0x1 &ipic 22 0x8
318
-
0xb800 0x0 0x0 0x2 &ipic 23 0x8
319
-
0xb800 0x0 0x0 0x3 &ipic 20 0x8
320
-
0xb800 0x0 0x0 0x4 &ipic 21 0x8
321
-
322
-
/* IDSEL 0x18 */
323
-
0xc000 0x0 0x0 0x1 &ipic 21 0x8
324
-
0xc000 0x0 0x0 0x2 &ipic 22 0x8
325
-
0xc000 0x0 0x0 0x3 &ipic 23 0x8
326
-
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
327
-
interrupt-parent = <&ipic>;
328
-
interrupts = <66 0x8>;
329
-
bus-range = <0 0>;
330
-
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
331
-
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
332
-
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
333
-
clock-frequency = <66666666>;
334
-
#interrupt-cells = <1>;
335
-
#size-cells = <2>;
336
-
#address-cells = <3>;
337
-
reg = <0xe0008500 0x100 /* internal registers */
338
-
0xe0008300 0x8>; /* config space access registers */
339
-
compatible = "fsl,mpc8349-pci";
340
-
device_type = "pci";
341
-
};
342
-
343
-
pci1: pci@e0008600 {
344
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
345
-
interrupt-map = <
346
-
347
-
/* IDSEL 0x11 */
348
-
0x8800 0x0 0x0 0x1 &ipic 20 0x8
349
-
0x8800 0x0 0x0 0x2 &ipic 21 0x8
350
-
0x8800 0x0 0x0 0x3 &ipic 22 0x8
351
-
0x8800 0x0 0x0 0x4 &ipic 23 0x8
352
-
353
-
/* IDSEL 0x12 */
354
-
0x9000 0x0 0x0 0x1 &ipic 22 0x8
355
-
0x9000 0x0 0x0 0x2 &ipic 23 0x8
356
-
0x9000 0x0 0x0 0x3 &ipic 20 0x8
357
-
0x9000 0x0 0x0 0x4 &ipic 21 0x8
358
-
359
-
/* IDSEL 0x13 */
360
-
0x9800 0x0 0x0 0x1 &ipic 23 0x8
361
-
0x9800 0x0 0x0 0x2 &ipic 20 0x8
362
-
0x9800 0x0 0x0 0x3 &ipic 21 0x8
363
-
0x9800 0x0 0x0 0x4 &ipic 22 0x8
364
-
365
-
/* IDSEL 0x15 */
366
-
0xa800 0x0 0x0 0x1 &ipic 20 0x8
367
-
0xa800 0x0 0x0 0x2 &ipic 21 0x8
368
-
0xa800 0x0 0x0 0x3 &ipic 22 0x8
369
-
0xa800 0x0 0x0 0x4 &ipic 23 0x8
370
-
371
-
/* IDSEL 0x16 */
372
-
0xb000 0x0 0x0 0x1 &ipic 23 0x8
373
-
0xb000 0x0 0x0 0x2 &ipic 20 0x8
374
-
0xb000 0x0 0x0 0x3 &ipic 21 0x8
375
-
0xb000 0x0 0x0 0x4 &ipic 22 0x8
376
-
377
-
/* IDSEL 0x17 */
378
-
0xb800 0x0 0x0 0x1 &ipic 22 0x8
379
-
0xb800 0x0 0x0 0x2 &ipic 23 0x8
380
-
0xb800 0x0 0x0 0x3 &ipic 20 0x8
381
-
0xb800 0x0 0x0 0x4 &ipic 21 0x8
382
-
383
-
/* IDSEL 0x18 */
384
-
0xc000 0x0 0x0 0x1 &ipic 21 0x8
385
-
0xc000 0x0 0x0 0x2 &ipic 22 0x8
386
-
0xc000 0x0 0x0 0x3 &ipic 23 0x8
387
-
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
388
-
interrupt-parent = <&ipic>;
389
-
interrupts = <67 0x8>;
390
-
bus-range = <0 0>;
391
-
ranges = <0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000
392
-
0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
393
-
0x01000000 0x0 0x00000000 0xe2100000 0x0 0x00100000>;
394
-
clock-frequency = <66666666>;
395
-
#interrupt-cells = <1>;
396
-
#size-cells = <2>;
397
-
#address-cells = <3>;
398
-
reg = <0xe0008600 0x100 /* internal registers */
399
-
0xe0008380 0x8>; /* config space access registers */
400
-
compatible = "fsl,mpc8349-pci";
401
-
device_type = "pci";
402
-
};
403
-
};
-481
arch/powerpc/boot/dts/mpc836x_mds.dts
-481
arch/powerpc/boot/dts/mpc836x_mds.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8360E EMDS Device Tree Source
4
-
*
5
-
* Copyright 2006 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
9
-
/*
10
-
/memreserve/ 00000000 1000000;
11
-
*/
12
-
13
-
/dts-v1/;
14
-
15
-
/ {
16
-
model = "MPC8360MDS";
17
-
compatible = "MPC8360EMDS", "MPC836xMDS", "MPC83xxMDS";
18
-
#address-cells = <1>;
19
-
#size-cells = <1>;
20
-
21
-
aliases {
22
-
ethernet0 = &enet0;
23
-
ethernet1 = &enet1;
24
-
serial0 = &serial0;
25
-
serial1 = &serial1;
26
-
pci0 = &pci0;
27
-
};
28
-
29
-
cpus {
30
-
#address-cells = <1>;
31
-
#size-cells = <0>;
32
-
33
-
PowerPC,8360@0 {
34
-
device_type = "cpu";
35
-
reg = <0x0>;
36
-
d-cache-line-size = <32>; // 32 bytes
37
-
i-cache-line-size = <32>; // 32 bytes
38
-
d-cache-size = <32768>; // L1, 32K
39
-
i-cache-size = <32768>; // L1, 32K
40
-
timebase-frequency = <66000000>;
41
-
bus-frequency = <264000000>;
42
-
clock-frequency = <528000000>;
43
-
};
44
-
};
45
-
46
-
memory {
47
-
device_type = "memory";
48
-
reg = <0x00000000 0x10000000>;
49
-
};
50
-
51
-
localbus@e0005000 {
52
-
#address-cells = <2>;
53
-
#size-cells = <1>;
54
-
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
55
-
"simple-bus";
56
-
reg = <0xe0005000 0xd8>;
57
-
ranges = <0 0 0xfe000000 0x02000000
58
-
1 0 0xf8000000 0x00008000>;
59
-
60
-
flash@0,0 {
61
-
compatible = "cfi-flash";
62
-
reg = <0 0 0x2000000>;
63
-
bank-width = <2>;
64
-
device-width = <1>;
65
-
};
66
-
67
-
bcsr@1,0 {
68
-
#address-cells = <1>;
69
-
#size-cells = <1>;
70
-
compatible = "fsl,mpc8360mds-bcsr";
71
-
reg = <1 0 0x8000>;
72
-
ranges = <0 1 0 0x8000>;
73
-
74
-
bcsr13: gpio-controller@d {
75
-
#gpio-cells = <2>;
76
-
compatible = "fsl,mpc8360mds-bcsr-gpio";
77
-
reg = <0xd 1>;
78
-
gpio-controller;
79
-
};
80
-
};
81
-
};
82
-
83
-
soc8360@e0000000 {
84
-
#address-cells = <1>;
85
-
#size-cells = <1>;
86
-
device_type = "soc";
87
-
compatible = "simple-bus";
88
-
ranges = <0x0 0xe0000000 0x00100000>;
89
-
reg = <0xe0000000 0x00000200>;
90
-
bus-frequency = <264000000>;
91
-
92
-
wdt@200 {
93
-
device_type = "watchdog";
94
-
compatible = "mpc83xx_wdt";
95
-
reg = <0x200 0x100>;
96
-
};
97
-
98
-
pmc: power@b00 {
99
-
compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
100
-
reg = <0xb00 0x100 0xa00 0x100>;
101
-
interrupts = <80 0x8>;
102
-
interrupt-parent = <&ipic>;
103
-
};
104
-
105
-
i2c@3000 {
106
-
#address-cells = <1>;
107
-
#size-cells = <0>;
108
-
cell-index = <0>;
109
-
compatible = "fsl-i2c";
110
-
reg = <0x3000 0x100>;
111
-
interrupts = <14 0x8>;
112
-
interrupt-parent = <&ipic>;
113
-
dfsrr;
114
-
115
-
rtc@68 {
116
-
compatible = "dallas,ds1374";
117
-
reg = <0x68>;
118
-
};
119
-
};
120
-
121
-
i2c@3100 {
122
-
#address-cells = <1>;
123
-
#size-cells = <0>;
124
-
cell-index = <1>;
125
-
compatible = "fsl-i2c";
126
-
reg = <0x3100 0x100>;
127
-
interrupts = <15 0x8>;
128
-
interrupt-parent = <&ipic>;
129
-
dfsrr;
130
-
};
131
-
132
-
serial0: serial@4500 {
133
-
cell-index = <0>;
134
-
device_type = "serial";
135
-
compatible = "fsl,ns16550", "ns16550";
136
-
reg = <0x4500 0x100>;
137
-
clock-frequency = <264000000>;
138
-
interrupts = <9 0x8>;
139
-
interrupt-parent = <&ipic>;
140
-
};
141
-
142
-
serial1: serial@4600 {
143
-
cell-index = <1>;
144
-
device_type = "serial";
145
-
compatible = "fsl,ns16550", "ns16550";
146
-
reg = <0x4600 0x100>;
147
-
clock-frequency = <264000000>;
148
-
interrupts = <10 0x8>;
149
-
interrupt-parent = <&ipic>;
150
-
};
151
-
152
-
dma@82a8 {
153
-
#address-cells = <1>;
154
-
#size-cells = <1>;
155
-
compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
156
-
reg = <0x82a8 4>;
157
-
ranges = <0 0x8100 0x1a8>;
158
-
interrupt-parent = <&ipic>;
159
-
interrupts = <71 8>;
160
-
cell-index = <0>;
161
-
dma-channel@0 {
162
-
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
163
-
reg = <0 0x80>;
164
-
cell-index = <0>;
165
-
interrupt-parent = <&ipic>;
166
-
interrupts = <71 8>;
167
-
};
168
-
dma-channel@80 {
169
-
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
170
-
reg = <0x80 0x80>;
171
-
cell-index = <1>;
172
-
interrupt-parent = <&ipic>;
173
-
interrupts = <71 8>;
174
-
};
175
-
dma-channel@100 {
176
-
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
177
-
reg = <0x100 0x80>;
178
-
cell-index = <2>;
179
-
interrupt-parent = <&ipic>;
180
-
interrupts = <71 8>;
181
-
};
182
-
dma-channel@180 {
183
-
compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
184
-
reg = <0x180 0x28>;
185
-
cell-index = <3>;
186
-
interrupt-parent = <&ipic>;
187
-
interrupts = <71 8>;
188
-
};
189
-
};
190
-
191
-
crypto@30000 {
192
-
compatible = "fsl,sec2.0";
193
-
reg = <0x30000 0x10000>;
194
-
interrupts = <11 0x8>;
195
-
interrupt-parent = <&ipic>;
196
-
fsl,num-channels = <4>;
197
-
fsl,channel-fifo-len = <24>;
198
-
fsl,exec-units-mask = <0x7e>;
199
-
fsl,descriptor-types-mask = <0x01010ebf>;
200
-
sleep = <&pmc 0x03000000>;
201
-
};
202
-
203
-
ipic: pic@700 {
204
-
interrupt-controller;
205
-
#address-cells = <0>;
206
-
#interrupt-cells = <2>;
207
-
reg = <0x700 0x100>;
208
-
device_type = "ipic";
209
-
};
210
-
211
-
par_io@1400 {
212
-
#address-cells = <1>;
213
-
#size-cells = <1>;
214
-
reg = <0x1400 0x100>;
215
-
ranges = <0 0x1400 0x100>;
216
-
device_type = "par_io";
217
-
num-ports = <7>;
218
-
219
-
qe_pio_b: gpio-controller@18 {
220
-
#gpio-cells = <2>;
221
-
compatible = "fsl,mpc8360-qe-pario-bank",
222
-
"fsl,mpc8323-qe-pario-bank";
223
-
reg = <0x18 0x18>;
224
-
gpio-controller;
225
-
};
226
-
227
-
pio1: ucc_pin@1 {
228
-
pio-map = <
229
-
/* port pin dir open_drain assignment has_irq */
230
-
0 3 1 0 1 0 /* TxD0 */
231
-
0 4 1 0 1 0 /* TxD1 */
232
-
0 5 1 0 1 0 /* TxD2 */
233
-
0 6 1 0 1 0 /* TxD3 */
234
-
1 6 1 0 3 0 /* TxD4 */
235
-
1 7 1 0 1 0 /* TxD5 */
236
-
1 9 1 0 2 0 /* TxD6 */
237
-
1 10 1 0 2 0 /* TxD7 */
238
-
0 9 2 0 1 0 /* RxD0 */
239
-
0 10 2 0 1 0 /* RxD1 */
240
-
0 11 2 0 1 0 /* RxD2 */
241
-
0 12 2 0 1 0 /* RxD3 */
242
-
0 13 2 0 1 0 /* RxD4 */
243
-
1 1 2 0 2 0 /* RxD5 */
244
-
1 0 2 0 2 0 /* RxD6 */
245
-
1 4 2 0 2 0 /* RxD7 */
246
-
0 7 1 0 1 0 /* TX_EN */
247
-
0 8 1 0 1 0 /* TX_ER */
248
-
0 15 2 0 1 0 /* RX_DV */
249
-
0 16 2 0 1 0 /* RX_ER */
250
-
0 0 2 0 1 0 /* RX_CLK */
251
-
2 9 1 0 3 0 /* GTX_CLK - CLK10 */
252
-
2 8 2 0 1 0>; /* GTX125 - CLK9 */
253
-
};
254
-
pio2: ucc_pin@2 {
255
-
pio-map = <
256
-
/* port pin dir open_drain assignment has_irq */
257
-
0 17 1 0 1 0 /* TxD0 */
258
-
0 18 1 0 1 0 /* TxD1 */
259
-
0 19 1 0 1 0 /* TxD2 */
260
-
0 20 1 0 1 0 /* TxD3 */
261
-
1 2 1 0 1 0 /* TxD4 */
262
-
1 3 1 0 2 0 /* TxD5 */
263
-
1 5 1 0 3 0 /* TxD6 */
264
-
1 8 1 0 3 0 /* TxD7 */
265
-
0 23 2 0 1 0 /* RxD0 */
266
-
0 24 2 0 1 0 /* RxD1 */
267
-
0 25 2 0 1 0 /* RxD2 */
268
-
0 26 2 0 1 0 /* RxD3 */
269
-
0 27 2 0 1 0 /* RxD4 */
270
-
1 12 2 0 2 0 /* RxD5 */
271
-
1 13 2 0 3 0 /* RxD6 */
272
-
1 11 2 0 2 0 /* RxD7 */
273
-
0 21 1 0 1 0 /* TX_EN */
274
-
0 22 1 0 1 0 /* TX_ER */
275
-
0 29 2 0 1 0 /* RX_DV */
276
-
0 30 2 0 1 0 /* RX_ER */
277
-
0 31 2 0 1 0 /* RX_CLK */
278
-
2 2 1 0 2 0 /* GTX_CLK - CLK10 */
279
-
2 3 2 0 1 0 /* GTX125 - CLK4 */
280
-
0 1 3 0 2 0 /* MDIO */
281
-
0 2 1 0 1 0>; /* MDC */
282
-
};
283
-
284
-
};
285
-
};
286
-
287
-
qe@e0100000 {
288
-
#address-cells = <1>;
289
-
#size-cells = <1>;
290
-
device_type = "qe";
291
-
compatible = "fsl,qe";
292
-
ranges = <0x0 0xe0100000 0x00100000>;
293
-
reg = <0xe0100000 0x480>;
294
-
brg-frequency = <0>;
295
-
bus-frequency = <396000000>;
296
-
fsl,qe-num-riscs = <2>;
297
-
fsl,qe-num-snums = <28>;
298
-
299
-
muram@10000 {
300
-
#address-cells = <1>;
301
-
#size-cells = <1>;
302
-
compatible = "fsl,qe-muram", "fsl,cpm-muram";
303
-
ranges = <0x0 0x00010000 0x0000c000>;
304
-
305
-
data-only@0 {
306
-
compatible = "fsl,qe-muram-data",
307
-
"fsl,cpm-muram-data";
308
-
reg = <0x0 0xc000>;
309
-
};
310
-
};
311
-
312
-
timer@440 {
313
-
compatible = "fsl,mpc8360-qe-gtm",
314
-
"fsl,qe-gtm", "fsl,gtm";
315
-
reg = <0x440 0x40>;
316
-
clock-frequency = <132000000>;
317
-
interrupts = <12 13 14 15>;
318
-
interrupt-parent = <&qeic>;
319
-
};
320
-
321
-
spi@4c0 {
322
-
cell-index = <0>;
323
-
compatible = "fsl,spi";
324
-
reg = <0x4c0 0x40>;
325
-
interrupts = <2>;
326
-
interrupt-parent = <&qeic>;
327
-
mode = "cpu";
328
-
};
329
-
330
-
spi@500 {
331
-
cell-index = <1>;
332
-
compatible = "fsl,spi";
333
-
reg = <0x500 0x40>;
334
-
interrupts = <1>;
335
-
interrupt-parent = <&qeic>;
336
-
mode = "cpu";
337
-
};
338
-
339
-
usb@6c0 {
340
-
compatible = "fsl,mpc8360-qe-usb",
341
-
"fsl,mpc8323-qe-usb";
342
-
reg = <0x6c0 0x40 0x8b00 0x100>;
343
-
interrupts = <11>;
344
-
interrupt-parent = <&qeic>;
345
-
fsl,fullspeed-clock = "clk21";
346
-
fsl,lowspeed-clock = "brg9";
347
-
gpios = <&qe_pio_b 2 0 /* USBOE */
348
-
&qe_pio_b 3 0 /* USBTP */
349
-
&qe_pio_b 8 0 /* USBTN */
350
-
&qe_pio_b 9 0 /* USBRP */
351
-
&qe_pio_b 11 0 /* USBRN */
352
-
&bcsr13 5 0 /* SPEED */
353
-
&bcsr13 4 1>; /* POWER */
354
-
};
355
-
356
-
enet0: ucc@2000 {
357
-
device_type = "network";
358
-
compatible = "ucc_geth";
359
-
cell-index = <1>;
360
-
reg = <0x2000 0x200>;
361
-
interrupts = <32>;
362
-
interrupt-parent = <&qeic>;
363
-
local-mac-address = [ 00 00 00 00 00 00 ];
364
-
rx-clock-name = "none";
365
-
tx-clock-name = "clk9";
366
-
phy-handle = <&phy0>;
367
-
phy-connection-type = "rgmii-id";
368
-
pio-handle = <&pio1>;
369
-
};
370
-
371
-
enet1: ucc@3000 {
372
-
device_type = "network";
373
-
compatible = "ucc_geth";
374
-
cell-index = <2>;
375
-
reg = <0x3000 0x200>;
376
-
interrupts = <33>;
377
-
interrupt-parent = <&qeic>;
378
-
local-mac-address = [ 00 00 00 00 00 00 ];
379
-
rx-clock-name = "none";
380
-
tx-clock-name = "clk4";
381
-
phy-handle = <&phy1>;
382
-
phy-connection-type = "rgmii-id";
383
-
pio-handle = <&pio2>;
384
-
};
385
-
386
-
mdio@2120 {
387
-
#address-cells = <1>;
388
-
#size-cells = <0>;
389
-
reg = <0x2120 0x18>;
390
-
compatible = "fsl,ucc-mdio";
391
-
392
-
phy0: ethernet-phy@0 {
393
-
interrupt-parent = <&ipic>;
394
-
interrupts = <17 0x8>;
395
-
reg = <0x0>;
396
-
};
397
-
phy1: ethernet-phy@1 {
398
-
interrupt-parent = <&ipic>;
399
-
interrupts = <18 0x8>;
400
-
reg = <0x1>;
401
-
};
402
-
tbi-phy@2 {
403
-
device_type = "tbi-phy";
404
-
reg = <0x2>;
405
-
};
406
-
};
407
-
408
-
qeic: interrupt-controller@80 {
409
-
interrupt-controller;
410
-
compatible = "fsl,qe-ic";
411
-
#address-cells = <0>;
412
-
#interrupt-cells = <1>;
413
-
reg = <0x80 0x80>;
414
-
big-endian;
415
-
interrupts = <32 0x8 33 0x8>; // high:32 low:33
416
-
interrupt-parent = <&ipic>;
417
-
};
418
-
};
419
-
420
-
pci0: pci@e0008500 {
421
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
422
-
interrupt-map = <
423
-
424
-
/* IDSEL 0x11 AD17 */
425
-
0x8800 0x0 0x0 0x1 &ipic 20 0x8
426
-
0x8800 0x0 0x0 0x2 &ipic 21 0x8
427
-
0x8800 0x0 0x0 0x3 &ipic 22 0x8
428
-
0x8800 0x0 0x0 0x4 &ipic 23 0x8
429
-
430
-
/* IDSEL 0x12 AD18 */
431
-
0x9000 0x0 0x0 0x1 &ipic 22 0x8
432
-
0x9000 0x0 0x0 0x2 &ipic 23 0x8
433
-
0x9000 0x0 0x0 0x3 &ipic 20 0x8
434
-
0x9000 0x0 0x0 0x4 &ipic 21 0x8
435
-
436
-
/* IDSEL 0x13 AD19 */
437
-
0x9800 0x0 0x0 0x1 &ipic 23 0x8
438
-
0x9800 0x0 0x0 0x2 &ipic 20 0x8
439
-
0x9800 0x0 0x0 0x3 &ipic 21 0x8
440
-
0x9800 0x0 0x0 0x4 &ipic 22 0x8
441
-
442
-
/* IDSEL 0x15 AD21*/
443
-
0xa800 0x0 0x0 0x1 &ipic 20 0x8
444
-
0xa800 0x0 0x0 0x2 &ipic 21 0x8
445
-
0xa800 0x0 0x0 0x3 &ipic 22 0x8
446
-
0xa800 0x0 0x0 0x4 &ipic 23 0x8
447
-
448
-
/* IDSEL 0x16 AD22*/
449
-
0xb000 0x0 0x0 0x1 &ipic 23 0x8
450
-
0xb000 0x0 0x0 0x2 &ipic 20 0x8
451
-
0xb000 0x0 0x0 0x3 &ipic 21 0x8
452
-
0xb000 0x0 0x0 0x4 &ipic 22 0x8
453
-
454
-
/* IDSEL 0x17 AD23*/
455
-
0xb800 0x0 0x0 0x1 &ipic 22 0x8
456
-
0xb800 0x0 0x0 0x2 &ipic 23 0x8
457
-
0xb800 0x0 0x0 0x3 &ipic 20 0x8
458
-
0xb800 0x0 0x0 0x4 &ipic 21 0x8
459
-
460
-
/* IDSEL 0x18 AD24*/
461
-
0xc000 0x0 0x0 0x1 &ipic 21 0x8
462
-
0xc000 0x0 0x0 0x2 &ipic 22 0x8
463
-
0xc000 0x0 0x0 0x3 &ipic 23 0x8
464
-
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
465
-
interrupt-parent = <&ipic>;
466
-
interrupts = <66 0x8>;
467
-
bus-range = <0 0>;
468
-
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
469
-
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
470
-
0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
471
-
clock-frequency = <66666666>;
472
-
#interrupt-cells = <1>;
473
-
#size-cells = <2>;
474
-
#address-cells = <3>;
475
-
reg = <0xe0008500 0x100 /* internal registers */
476
-
0xe0008300 0x8>; /* config space access registers */
477
-
compatible = "fsl,mpc8349-pci";
478
-
device_type = "pci";
479
-
sleep = <&pmc 0x00010000>;
480
-
};
481
-
};
-505
arch/powerpc/boot/dts/mpc8377_mds.dts
-505
arch/powerpc/boot/dts/mpc8377_mds.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8377E MDS Device Tree Source
4
-
*
5
-
* Copyright 2007 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
/ {
11
-
model = "fsl,mpc8377emds";
12
-
compatible = "fsl,mpc8377emds","fsl,mpc837xmds";
13
-
#address-cells = <1>;
14
-
#size-cells = <1>;
15
-
16
-
aliases {
17
-
ethernet0 = &enet0;
18
-
ethernet1 = &enet1;
19
-
serial0 = &serial0;
20
-
serial1 = &serial1;
21
-
pci0 = &pci0;
22
-
pci1 = &pci1;
23
-
pci2 = &pci2;
24
-
};
25
-
26
-
cpus {
27
-
#address-cells = <1>;
28
-
#size-cells = <0>;
29
-
30
-
PowerPC,8377@0 {
31
-
device_type = "cpu";
32
-
reg = <0x0>;
33
-
d-cache-line-size = <32>;
34
-
i-cache-line-size = <32>;
35
-
d-cache-size = <32768>;
36
-
i-cache-size = <32768>;
37
-
timebase-frequency = <0>;
38
-
bus-frequency = <0>;
39
-
clock-frequency = <0>;
40
-
};
41
-
};
42
-
43
-
memory {
44
-
device_type = "memory";
45
-
reg = <0x00000000 0x20000000>; // 512MB at 0
46
-
};
47
-
48
-
localbus@e0005000 {
49
-
#address-cells = <2>;
50
-
#size-cells = <1>;
51
-
compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
52
-
reg = <0xe0005000 0x1000>;
53
-
interrupts = <77 0x8>;
54
-
interrupt-parent = <&ipic>;
55
-
56
-
// booting from NOR flash
57
-
ranges = <0 0x0 0xfe000000 0x02000000
58
-
1 0x0 0xf8000000 0x00008000
59
-
3 0x0 0xe0600000 0x00008000>;
60
-
61
-
flash@0,0 {
62
-
#address-cells = <1>;
63
-
#size-cells = <1>;
64
-
compatible = "cfi-flash";
65
-
reg = <0 0x0 0x2000000>;
66
-
bank-width = <2>;
67
-
device-width = <1>;
68
-
69
-
u-boot@0 {
70
-
reg = <0x0 0x100000>;
71
-
read-only;
72
-
};
73
-
74
-
fs@100000 {
75
-
reg = <0x100000 0x800000>;
76
-
};
77
-
78
-
kernel@1d00000 {
79
-
reg = <0x1d00000 0x200000>;
80
-
};
81
-
82
-
dtb@1f00000 {
83
-
reg = <0x1f00000 0x100000>;
84
-
};
85
-
};
86
-
87
-
bcsr@1,0 {
88
-
reg = <1 0x0 0x8000>;
89
-
compatible = "fsl,mpc837xmds-bcsr";
90
-
};
91
-
92
-
nand@3,0 {
93
-
#address-cells = <1>;
94
-
#size-cells = <1>;
95
-
compatible = "fsl,mpc8377-fcm-nand",
96
-
"fsl,elbc-fcm-nand";
97
-
reg = <3 0x0 0x8000>;
98
-
99
-
u-boot@0 {
100
-
reg = <0x0 0x100000>;
101
-
read-only;
102
-
};
103
-
104
-
kernel@100000 {
105
-
reg = <0x100000 0x300000>;
106
-
};
107
-
108
-
fs@400000 {
109
-
reg = <0x400000 0x1c00000>;
110
-
};
111
-
};
112
-
};
113
-
114
-
soc@e0000000 {
115
-
#address-cells = <1>;
116
-
#size-cells = <1>;
117
-
device_type = "soc";
118
-
compatible = "simple-bus";
119
-
ranges = <0x0 0xe0000000 0x00100000>;
120
-
reg = <0xe0000000 0x00000200>;
121
-
bus-frequency = <0>;
122
-
123
-
wdt@200 {
124
-
compatible = "mpc83xx_wdt";
125
-
reg = <0x200 0x100>;
126
-
};
127
-
128
-
sleep-nexus {
129
-
#address-cells = <1>;
130
-
#size-cells = <1>;
131
-
compatible = "simple-bus";
132
-
sleep = <&pmc 0x0c000000>;
133
-
ranges;
134
-
135
-
i2c@3000 {
136
-
#address-cells = <1>;
137
-
#size-cells = <0>;
138
-
cell-index = <0>;
139
-
compatible = "fsl-i2c";
140
-
reg = <0x3000 0x100>;
141
-
interrupts = <14 0x8>;
142
-
interrupt-parent = <&ipic>;
143
-
dfsrr;
144
-
145
-
rtc@68 {
146
-
compatible = "dallas,ds1374";
147
-
reg = <0x68>;
148
-
interrupts = <19 0x8>;
149
-
interrupt-parent = <&ipic>;
150
-
};
151
-
};
152
-
153
-
sdhci@2e000 {
154
-
compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
155
-
reg = <0x2e000 0x1000>;
156
-
interrupts = <42 0x8>;
157
-
interrupt-parent = <&ipic>;
158
-
sdhci,wp-inverted;
159
-
/* Filled in by U-Boot */
160
-
clock-frequency = <0>;
161
-
};
162
-
};
163
-
164
-
i2c@3100 {
165
-
#address-cells = <1>;
166
-
#size-cells = <0>;
167
-
cell-index = <1>;
168
-
compatible = "fsl-i2c";
169
-
reg = <0x3100 0x100>;
170
-
interrupts = <15 0x8>;
171
-
interrupt-parent = <&ipic>;
172
-
dfsrr;
173
-
};
174
-
175
-
spi@7000 {
176
-
cell-index = <0>;
177
-
compatible = "fsl,spi";
178
-
reg = <0x7000 0x1000>;
179
-
interrupts = <16 0x8>;
180
-
interrupt-parent = <&ipic>;
181
-
mode = "cpu";
182
-
};
183
-
184
-
usb@23000 {
185
-
compatible = "fsl-usb2-dr";
186
-
reg = <0x23000 0x1000>;
187
-
#address-cells = <1>;
188
-
#size-cells = <0>;
189
-
interrupt-parent = <&ipic>;
190
-
interrupts = <38 0x8>;
191
-
dr_mode = "host";
192
-
phy_type = "ulpi";
193
-
sleep = <&pmc 0x00c00000>;
194
-
};
195
-
196
-
enet0: ethernet@24000 {
197
-
#address-cells = <1>;
198
-
#size-cells = <1>;
199
-
cell-index = <0>;
200
-
device_type = "network";
201
-
model = "eTSEC";
202
-
compatible = "gianfar";
203
-
reg = <0x24000 0x1000>;
204
-
ranges = <0x0 0x24000 0x1000>;
205
-
local-mac-address = [ 00 00 00 00 00 00 ];
206
-
interrupts = <32 0x8 33 0x8 34 0x8>;
207
-
phy-connection-type = "mii";
208
-
interrupt-parent = <&ipic>;
209
-
tbi-handle = <&tbi0>;
210
-
phy-handle = <&phy2>;
211
-
sleep = <&pmc 0xc0000000>;
212
-
fsl,magic-packet;
213
-
214
-
mdio@520 {
215
-
#address-cells = <1>;
216
-
#size-cells = <0>;
217
-
compatible = "fsl,gianfar-mdio";
218
-
reg = <0x520 0x20>;
219
-
220
-
phy2: ethernet-phy@2 {
221
-
interrupt-parent = <&ipic>;
222
-
interrupts = <17 0x8>;
223
-
reg = <0x2>;
224
-
};
225
-
226
-
phy3: ethernet-phy@3 {
227
-
interrupt-parent = <&ipic>;
228
-
interrupts = <18 0x8>;
229
-
reg = <0x3>;
230
-
};
231
-
232
-
tbi0: tbi-phy@11 {
233
-
reg = <0x11>;
234
-
device_type = "tbi-phy";
235
-
};
236
-
};
237
-
};
238
-
239
-
enet1: ethernet@25000 {
240
-
#address-cells = <1>;
241
-
#size-cells = <1>;
242
-
cell-index = <1>;
243
-
device_type = "network";
244
-
model = "eTSEC";
245
-
compatible = "gianfar";
246
-
reg = <0x25000 0x1000>;
247
-
ranges = <0x0 0x25000 0x1000>;
248
-
local-mac-address = [ 00 00 00 00 00 00 ];
249
-
interrupts = <35 0x8 36 0x8 37 0x8>;
250
-
phy-connection-type = "mii";
251
-
interrupt-parent = <&ipic>;
252
-
tbi-handle = <&tbi1>;
253
-
phy-handle = <&phy3>;
254
-
sleep = <&pmc 0x30000000>;
255
-
fsl,magic-packet;
256
-
257
-
mdio@520 {
258
-
#address-cells = <1>;
259
-
#size-cells = <0>;
260
-
compatible = "fsl,gianfar-tbi";
261
-
reg = <0x520 0x20>;
262
-
263
-
tbi1: tbi-phy@11 {
264
-
reg = <0x11>;
265
-
device_type = "tbi-phy";
266
-
};
267
-
};
268
-
};
269
-
270
-
serial0: serial@4500 {
271
-
cell-index = <0>;
272
-
device_type = "serial";
273
-
compatible = "fsl,ns16550", "ns16550";
274
-
reg = <0x4500 0x100>;
275
-
clock-frequency = <0>;
276
-
interrupts = <9 0x8>;
277
-
interrupt-parent = <&ipic>;
278
-
};
279
-
280
-
serial1: serial@4600 {
281
-
cell-index = <1>;
282
-
device_type = "serial";
283
-
compatible = "fsl,ns16550", "ns16550";
284
-
reg = <0x4600 0x100>;
285
-
clock-frequency = <0>;
286
-
interrupts = <10 0x8>;
287
-
interrupt-parent = <&ipic>;
288
-
};
289
-
290
-
dma@82a8 {
291
-
#address-cells = <1>;
292
-
#size-cells = <1>;
293
-
compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
294
-
reg = <0x82a8 4>;
295
-
ranges = <0 0x8100 0x1a8>;
296
-
interrupt-parent = <&ipic>;
297
-
interrupts = <0x47 8>;
298
-
cell-index = <0>;
299
-
dma-channel@0 {
300
-
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
301
-
reg = <0 0x80>;
302
-
cell-index = <0>;
303
-
interrupt-parent = <&ipic>;
304
-
interrupts = <0x47 8>;
305
-
};
306
-
dma-channel@80 {
307
-
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
308
-
reg = <0x80 0x80>;
309
-
cell-index = <1>;
310
-
interrupt-parent = <&ipic>;
311
-
interrupts = <0x47 8>;
312
-
};
313
-
dma-channel@100 {
314
-
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
315
-
reg = <0x100 0x80>;
316
-
cell-index = <2>;
317
-
interrupt-parent = <&ipic>;
318
-
interrupts = <0x47 8>;
319
-
};
320
-
dma-channel@180 {
321
-
compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
322
-
reg = <0x180 0x28>;
323
-
cell-index = <3>;
324
-
interrupt-parent = <&ipic>;
325
-
interrupts = <0x47 8>;
326
-
};
327
-
};
328
-
329
-
crypto@30000 {
330
-
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
331
-
"fsl,sec2.1", "fsl,sec2.0";
332
-
reg = <0x30000 0x10000>;
333
-
interrupts = <11 0x8>;
334
-
interrupt-parent = <&ipic>;
335
-
fsl,num-channels = <4>;
336
-
fsl,channel-fifo-len = <24>;
337
-
fsl,exec-units-mask = <0x9fe>;
338
-
fsl,descriptor-types-mask = <0x3ab0ebf>;
339
-
sleep = <&pmc 0x03000000>;
340
-
};
341
-
342
-
sata@18000 {
343
-
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
344
-
reg = <0x18000 0x1000>;
345
-
interrupts = <44 0x8>;
346
-
interrupt-parent = <&ipic>;
347
-
sleep = <&pmc 0x000000c0>;
348
-
};
349
-
350
-
sata@19000 {
351
-
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
352
-
reg = <0x19000 0x1000>;
353
-
interrupts = <45 0x8>;
354
-
interrupt-parent = <&ipic>;
355
-
sleep = <&pmc 0x00000030>;
356
-
};
357
-
358
-
/* IPIC
359
-
* interrupts cell = <intr #, sense>
360
-
* sense values match linux IORESOURCE_IRQ_* defines:
361
-
* sense == 8: Level, low assertion
362
-
* sense == 2: Edge, high-to-low change
363
-
*/
364
-
ipic: pic@700 {
365
-
compatible = "fsl,ipic";
366
-
interrupt-controller;
367
-
#address-cells = <0>;
368
-
#interrupt-cells = <2>;
369
-
reg = <0x700 0x100>;
370
-
};
371
-
372
-
pmc: power@b00 {
373
-
compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
374
-
reg = <0xb00 0x100 0xa00 0x100>;
375
-
interrupts = <80 0x8>;
376
-
interrupt-parent = <&ipic>;
377
-
};
378
-
};
379
-
380
-
pci0: pci@e0008500 {
381
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
382
-
interrupt-map = <
383
-
384
-
/* IDSEL 0x11 */
385
-
0x8800 0x0 0x0 0x1 &ipic 20 0x8
386
-
0x8800 0x0 0x0 0x2 &ipic 21 0x8
387
-
0x8800 0x0 0x0 0x3 &ipic 22 0x8
388
-
0x8800 0x0 0x0 0x4 &ipic 23 0x8
389
-
390
-
/* IDSEL 0x12 */
391
-
0x9000 0x0 0x0 0x1 &ipic 22 0x8
392
-
0x9000 0x0 0x0 0x2 &ipic 23 0x8
393
-
0x9000 0x0 0x0 0x3 &ipic 20 0x8
394
-
0x9000 0x0 0x0 0x4 &ipic 21 0x8
395
-
396
-
/* IDSEL 0x13 */
397
-
0x9800 0x0 0x0 0x1 &ipic 23 0x8
398
-
0x9800 0x0 0x0 0x2 &ipic 20 0x8
399
-
0x9800 0x0 0x0 0x3 &ipic 21 0x8
400
-
0x9800 0x0 0x0 0x4 &ipic 22 0x8
401
-
402
-
/* IDSEL 0x15 */
403
-
0xa800 0x0 0x0 0x1 &ipic 20 0x8
404
-
0xa800 0x0 0x0 0x2 &ipic 21 0x8
405
-
0xa800 0x0 0x0 0x3 &ipic 22 0x8
406
-
0xa800 0x0 0x0 0x4 &ipic 23 0x8
407
-
408
-
/* IDSEL 0x16 */
409
-
0xb000 0x0 0x0 0x1 &ipic 23 0x8
410
-
0xb000 0x0 0x0 0x2 &ipic 20 0x8
411
-
0xb000 0x0 0x0 0x3 &ipic 21 0x8
412
-
0xb000 0x0 0x0 0x4 &ipic 22 0x8
413
-
414
-
/* IDSEL 0x17 */
415
-
0xb800 0x0 0x0 0x1 &ipic 22 0x8
416
-
0xb800 0x0 0x0 0x2 &ipic 23 0x8
417
-
0xb800 0x0 0x0 0x3 &ipic 20 0x8
418
-
0xb800 0x0 0x0 0x4 &ipic 21 0x8
419
-
420
-
/* IDSEL 0x18 */
421
-
0xc000 0x0 0x0 0x1 &ipic 21 0x8
422
-
0xc000 0x0 0x0 0x2 &ipic 22 0x8
423
-
0xc000 0x0 0x0 0x3 &ipic 23 0x8
424
-
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
425
-
interrupt-parent = <&ipic>;
426
-
interrupts = <66 0x8>;
427
-
bus-range = <0x0 0x0>;
428
-
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
429
-
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
430
-
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
431
-
sleep = <&pmc 0x00010000>;
432
-
clock-frequency = <0>;
433
-
#interrupt-cells = <1>;
434
-
#size-cells = <2>;
435
-
#address-cells = <3>;
436
-
reg = <0xe0008500 0x100 /* internal registers */
437
-
0xe0008300 0x8>; /* config space access registers */
438
-
compatible = "fsl,mpc8349-pci";
439
-
device_type = "pci";
440
-
};
441
-
442
-
pci1: pcie@e0009000 {
443
-
#address-cells = <3>;
444
-
#size-cells = <2>;
445
-
#interrupt-cells = <1>;
446
-
device_type = "pci";
447
-
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
448
-
reg = <0xe0009000 0x00001000>;
449
-
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
450
-
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
451
-
bus-range = <0 255>;
452
-
interrupt-map-mask = <0xf800 0 0 7>;
453
-
interrupt-map = <0 0 0 1 &ipic 1 8
454
-
0 0 0 2 &ipic 1 8
455
-
0 0 0 3 &ipic 1 8
456
-
0 0 0 4 &ipic 1 8>;
457
-
sleep = <&pmc 0x00300000>;
458
-
clock-frequency = <0>;
459
-
460
-
pcie@0 {
461
-
#address-cells = <3>;
462
-
#size-cells = <2>;
463
-
device_type = "pci";
464
-
reg = <0 0 0 0 0>;
465
-
ranges = <0x02000000 0 0xa8000000
466
-
0x02000000 0 0xa8000000
467
-
0 0x10000000
468
-
0x01000000 0 0x00000000
469
-
0x01000000 0 0x00000000
470
-
0 0x00800000>;
471
-
};
472
-
};
473
-
474
-
pci2: pcie@e000a000 {
475
-
#address-cells = <3>;
476
-
#size-cells = <2>;
477
-
#interrupt-cells = <1>;
478
-
device_type = "pci";
479
-
compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
480
-
reg = <0xe000a000 0x00001000>;
481
-
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
482
-
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
483
-
bus-range = <0 255>;
484
-
interrupt-map-mask = <0xf800 0 0 7>;
485
-
interrupt-map = <0 0 0 1 &ipic 2 8
486
-
0 0 0 2 &ipic 2 8
487
-
0 0 0 3 &ipic 2 8
488
-
0 0 0 4 &ipic 2 8>;
489
-
sleep = <&pmc 0x000c0000>;
490
-
clock-frequency = <0>;
491
-
492
-
pcie@0 {
493
-
#address-cells = <3>;
494
-
#size-cells = <2>;
495
-
device_type = "pci";
496
-
reg = <0 0 0 0 0>;
497
-
ranges = <0x02000000 0 0xc8000000
498
-
0x02000000 0 0xc8000000
499
-
0 0x10000000
500
-
0x01000000 0 0x00000000
501
-
0x01000000 0 0x00000000
502
-
0 0x00800000>;
503
-
};
504
-
};
505
-
};
-489
arch/powerpc/boot/dts/mpc8378_mds.dts
-489
arch/powerpc/boot/dts/mpc8378_mds.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8378E MDS Device Tree Source
4
-
*
5
-
* Copyright 2007 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
/ {
11
-
model = "fsl,mpc8378emds";
12
-
compatible = "fsl,mpc8378emds","fsl,mpc837xmds";
13
-
#address-cells = <1>;
14
-
#size-cells = <1>;
15
-
16
-
aliases {
17
-
ethernet0 = &enet0;
18
-
ethernet1 = &enet1;
19
-
serial0 = &serial0;
20
-
serial1 = &serial1;
21
-
pci0 = &pci0;
22
-
pci1 = &pci1;
23
-
pci2 = &pci2;
24
-
};
25
-
26
-
cpus {
27
-
#address-cells = <1>;
28
-
#size-cells = <0>;
29
-
30
-
PowerPC,8378@0 {
31
-
device_type = "cpu";
32
-
reg = <0x0>;
33
-
d-cache-line-size = <32>;
34
-
i-cache-line-size = <32>;
35
-
d-cache-size = <32768>;
36
-
i-cache-size = <32768>;
37
-
timebase-frequency = <0>;
38
-
bus-frequency = <0>;
39
-
clock-frequency = <0>;
40
-
};
41
-
};
42
-
43
-
memory {
44
-
device_type = "memory";
45
-
reg = <0x00000000 0x20000000>; // 512MB at 0
46
-
};
47
-
48
-
localbus@e0005000 {
49
-
#address-cells = <2>;
50
-
#size-cells = <1>;
51
-
compatible = "fsl,mpc8378-elbc", "fsl,elbc", "simple-bus";
52
-
reg = <0xe0005000 0x1000>;
53
-
interrupts = <77 0x8>;
54
-
interrupt-parent = <&ipic>;
55
-
56
-
// booting from NOR flash
57
-
ranges = <0 0x0 0xfe000000 0x02000000
58
-
1 0x0 0xf8000000 0x00008000
59
-
3 0x0 0xe0600000 0x00008000>;
60
-
61
-
flash@0,0 {
62
-
#address-cells = <1>;
63
-
#size-cells = <1>;
64
-
compatible = "cfi-flash";
65
-
reg = <0 0x0 0x2000000>;
66
-
bank-width = <2>;
67
-
device-width = <1>;
68
-
69
-
u-boot@0 {
70
-
reg = <0x0 0x100000>;
71
-
read-only;
72
-
};
73
-
74
-
fs@100000 {
75
-
reg = <0x100000 0x800000>;
76
-
};
77
-
78
-
kernel@1d00000 {
79
-
reg = <0x1d00000 0x200000>;
80
-
};
81
-
82
-
dtb@1f00000 {
83
-
reg = <0x1f00000 0x100000>;
84
-
};
85
-
};
86
-
87
-
bcsr@1,0 {
88
-
reg = <1 0x0 0x8000>;
89
-
compatible = "fsl,mpc837xmds-bcsr";
90
-
};
91
-
92
-
nand@3,0 {
93
-
#address-cells = <1>;
94
-
#size-cells = <1>;
95
-
compatible = "fsl,mpc8378-fcm-nand",
96
-
"fsl,elbc-fcm-nand";
97
-
reg = <3 0x0 0x8000>;
98
-
99
-
u-boot@0 {
100
-
reg = <0x0 0x100000>;
101
-
read-only;
102
-
};
103
-
104
-
kernel@100000 {
105
-
reg = <0x100000 0x300000>;
106
-
};
107
-
108
-
fs@400000 {
109
-
reg = <0x400000 0x1c00000>;
110
-
};
111
-
};
112
-
};
113
-
114
-
soc@e0000000 {
115
-
#address-cells = <1>;
116
-
#size-cells = <1>;
117
-
device_type = "soc";
118
-
compatible = "simple-bus";
119
-
ranges = <0x0 0xe0000000 0x00100000>;
120
-
reg = <0xe0000000 0x00000200>;
121
-
bus-frequency = <0>;
122
-
123
-
wdt@200 {
124
-
compatible = "mpc83xx_wdt";
125
-
reg = <0x200 0x100>;
126
-
};
127
-
128
-
sleep-nexus {
129
-
#address-cells = <1>;
130
-
#size-cells = <1>;
131
-
compatible = "simple-bus";
132
-
sleep = <&pmc 0x0c000000>;
133
-
ranges;
134
-
135
-
i2c@3000 {
136
-
#address-cells = <1>;
137
-
#size-cells = <0>;
138
-
cell-index = <0>;
139
-
compatible = "fsl-i2c";
140
-
reg = <0x3000 0x100>;
141
-
interrupts = <14 0x8>;
142
-
interrupt-parent = <&ipic>;
143
-
dfsrr;
144
-
145
-
rtc@68 {
146
-
compatible = "dallas,ds1374";
147
-
reg = <0x68>;
148
-
interrupts = <19 0x8>;
149
-
interrupt-parent = <&ipic>;
150
-
};
151
-
};
152
-
153
-
sdhci@2e000 {
154
-
compatible = "fsl,mpc8378-esdhc", "fsl,esdhc";
155
-
reg = <0x2e000 0x1000>;
156
-
interrupts = <42 0x8>;
157
-
interrupt-parent = <&ipic>;
158
-
sdhci,wp-inverted;
159
-
/* Filled in by U-Boot */
160
-
clock-frequency = <0>;
161
-
};
162
-
};
163
-
164
-
i2c@3100 {
165
-
#address-cells = <1>;
166
-
#size-cells = <0>;
167
-
cell-index = <1>;
168
-
compatible = "fsl-i2c";
169
-
reg = <0x3100 0x100>;
170
-
interrupts = <15 0x8>;
171
-
interrupt-parent = <&ipic>;
172
-
dfsrr;
173
-
};
174
-
175
-
spi@7000 {
176
-
cell-index = <0>;
177
-
compatible = "fsl,spi";
178
-
reg = <0x7000 0x1000>;
179
-
interrupts = <16 0x8>;
180
-
interrupt-parent = <&ipic>;
181
-
mode = "cpu";
182
-
};
183
-
184
-
dma@82a8 {
185
-
#address-cells = <1>;
186
-
#size-cells = <1>;
187
-
compatible = "fsl,mpc8378-dma", "fsl,elo-dma";
188
-
reg = <0x82a8 4>;
189
-
ranges = <0 0x8100 0x1a8>;
190
-
interrupt-parent = <&ipic>;
191
-
interrupts = <71 8>;
192
-
cell-index = <0>;
193
-
dma-channel@0 {
194
-
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
195
-
reg = <0 0x80>;
196
-
cell-index = <0>;
197
-
interrupt-parent = <&ipic>;
198
-
interrupts = <71 8>;
199
-
};
200
-
dma-channel@80 {
201
-
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
202
-
reg = <0x80 0x80>;
203
-
cell-index = <1>;
204
-
interrupt-parent = <&ipic>;
205
-
interrupts = <71 8>;
206
-
};
207
-
dma-channel@100 {
208
-
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
209
-
reg = <0x100 0x80>;
210
-
cell-index = <2>;
211
-
interrupt-parent = <&ipic>;
212
-
interrupts = <71 8>;
213
-
};
214
-
dma-channel@180 {
215
-
compatible = "fsl,mpc8378-dma-channel", "fsl,elo-dma-channel";
216
-
reg = <0x180 0x28>;
217
-
cell-index = <3>;
218
-
interrupt-parent = <&ipic>;
219
-
interrupts = <71 8>;
220
-
};
221
-
};
222
-
223
-
usb@23000 {
224
-
compatible = "fsl-usb2-dr";
225
-
reg = <0x23000 0x1000>;
226
-
#address-cells = <1>;
227
-
#size-cells = <0>;
228
-
interrupt-parent = <&ipic>;
229
-
interrupts = <38 0x8>;
230
-
dr_mode = "host";
231
-
phy_type = "ulpi";
232
-
sleep = <&pmc 0x00c00000>;
233
-
};
234
-
235
-
enet0: ethernet@24000 {
236
-
#address-cells = <1>;
237
-
#size-cells = <1>;
238
-
cell-index = <0>;
239
-
device_type = "network";
240
-
model = "eTSEC";
241
-
compatible = "gianfar";
242
-
reg = <0x24000 0x1000>;
243
-
ranges = <0x0 0x24000 0x1000>;
244
-
local-mac-address = [ 00 00 00 00 00 00 ];
245
-
interrupts = <32 0x8 33 0x8 34 0x8>;
246
-
phy-connection-type = "mii";
247
-
interrupt-parent = <&ipic>;
248
-
tbi-handle = <&tbi0>;
249
-
phy-handle = <&phy2>;
250
-
sleep = <&pmc 0xc0000000>;
251
-
fsl,magic-packet;
252
-
253
-
mdio@520 {
254
-
#address-cells = <1>;
255
-
#size-cells = <0>;
256
-
compatible = "fsl,gianfar-mdio";
257
-
reg = <0x520 0x20>;
258
-
259
-
phy2: ethernet-phy@2 {
260
-
interrupt-parent = <&ipic>;
261
-
interrupts = <17 0x8>;
262
-
reg = <0x2>;
263
-
};
264
-
265
-
phy3: ethernet-phy@3 {
266
-
interrupt-parent = <&ipic>;
267
-
interrupts = <18 0x8>;
268
-
reg = <0x3>;
269
-
};
270
-
271
-
tbi0: tbi-phy@11 {
272
-
reg = <0x11>;
273
-
device_type = "tbi-phy";
274
-
};
275
-
};
276
-
};
277
-
278
-
enet1: ethernet@25000 {
279
-
#address-cells = <1>;
280
-
#size-cells = <1>;
281
-
cell-index = <1>;
282
-
device_type = "network";
283
-
model = "eTSEC";
284
-
compatible = "gianfar";
285
-
reg = <0x25000 0x1000>;
286
-
ranges = <0x0 0x25000 0x1000>;
287
-
local-mac-address = [ 00 00 00 00 00 00 ];
288
-
interrupts = <35 0x8 36 0x8 37 0x8>;
289
-
phy-connection-type = "mii";
290
-
interrupt-parent = <&ipic>;
291
-
tbi-handle = <&tbi1>;
292
-
phy-handle = <&phy3>;
293
-
sleep = <&pmc 0x30000000>;
294
-
fsl,magic-packet;
295
-
296
-
mdio@520 {
297
-
#address-cells = <1>;
298
-
#size-cells = <0>;
299
-
compatible = "fsl,gianfar-tbi";
300
-
reg = <0x520 0x20>;
301
-
302
-
tbi1: tbi-phy@11 {
303
-
reg = <0x11>;
304
-
device_type = "tbi-phy";
305
-
};
306
-
};
307
-
};
308
-
309
-
serial0: serial@4500 {
310
-
cell-index = <0>;
311
-
device_type = "serial";
312
-
compatible = "fsl,ns16550", "ns16550";
313
-
reg = <0x4500 0x100>;
314
-
clock-frequency = <0>;
315
-
interrupts = <9 0x8>;
316
-
interrupt-parent = <&ipic>;
317
-
};
318
-
319
-
serial1: serial@4600 {
320
-
cell-index = <1>;
321
-
device_type = "serial";
322
-
compatible = "fsl,ns16550", "ns16550";
323
-
reg = <0x4600 0x100>;
324
-
clock-frequency = <0>;
325
-
interrupts = <10 0x8>;
326
-
interrupt-parent = <&ipic>;
327
-
};
328
-
329
-
crypto@30000 {
330
-
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
331
-
"fsl,sec2.1", "fsl,sec2.0";
332
-
reg = <0x30000 0x10000>;
333
-
interrupts = <11 0x8>;
334
-
interrupt-parent = <&ipic>;
335
-
fsl,num-channels = <4>;
336
-
fsl,channel-fifo-len = <24>;
337
-
fsl,exec-units-mask = <0x9fe>;
338
-
fsl,descriptor-types-mask = <0x3ab0ebf>;
339
-
sleep = <&pmc 0x03000000>;
340
-
};
341
-
342
-
/* IPIC
343
-
* interrupts cell = <intr #, sense>
344
-
* sense values match linux IORESOURCE_IRQ_* defines:
345
-
* sense == 8: Level, low assertion
346
-
* sense == 2: Edge, high-to-low change
347
-
*/
348
-
ipic: pic@700 {
349
-
compatible = "fsl,ipic";
350
-
interrupt-controller;
351
-
#address-cells = <0>;
352
-
#interrupt-cells = <2>;
353
-
reg = <0x700 0x100>;
354
-
};
355
-
356
-
pmc: power@b00 {
357
-
compatible = "fsl,mpc8378-pmc", "fsl,mpc8349-pmc";
358
-
reg = <0xb00 0x100 0xa00 0x100>;
359
-
interrupts = <80 0x8>;
360
-
interrupt-parent = <&ipic>;
361
-
};
362
-
};
363
-
364
-
pci0: pci@e0008500 {
365
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
366
-
interrupt-map = <
367
-
368
-
/* IDSEL 0x11 */
369
-
0x8800 0x0 0x0 0x1 &ipic 20 0x8
370
-
0x8800 0x0 0x0 0x2 &ipic 21 0x8
371
-
0x8800 0x0 0x0 0x3 &ipic 22 0x8
372
-
0x8800 0x0 0x0 0x4 &ipic 23 0x8
373
-
374
-
/* IDSEL 0x12 */
375
-
0x9000 0x0 0x0 0x1 &ipic 22 0x8
376
-
0x9000 0x0 0x0 0x2 &ipic 23 0x8
377
-
0x9000 0x0 0x0 0x3 &ipic 20 0x8
378
-
0x9000 0x0 0x0 0x4 &ipic 21 0x8
379
-
380
-
/* IDSEL 0x13 */
381
-
0x9800 0x0 0x0 0x1 &ipic 23 0x8
382
-
0x9800 0x0 0x0 0x2 &ipic 20 0x8
383
-
0x9800 0x0 0x0 0x3 &ipic 21 0x8
384
-
0x9800 0x0 0x0 0x4 &ipic 22 0x8
385
-
386
-
/* IDSEL 0x15 */
387
-
0xa800 0x0 0x0 0x1 &ipic 20 0x8
388
-
0xa800 0x0 0x0 0x2 &ipic 21 0x8
389
-
0xa800 0x0 0x0 0x3 &ipic 22 0x8
390
-
0xa800 0x0 0x0 0x4 &ipic 23 0x8
391
-
392
-
/* IDSEL 0x16 */
393
-
0xb000 0x0 0x0 0x1 &ipic 23 0x8
394
-
0xb000 0x0 0x0 0x2 &ipic 20 0x8
395
-
0xb000 0x0 0x0 0x3 &ipic 21 0x8
396
-
0xb000 0x0 0x0 0x4 &ipic 22 0x8
397
-
398
-
/* IDSEL 0x17 */
399
-
0xb800 0x0 0x0 0x1 &ipic 22 0x8
400
-
0xb800 0x0 0x0 0x2 &ipic 23 0x8
401
-
0xb800 0x0 0x0 0x3 &ipic 20 0x8
402
-
0xb800 0x0 0x0 0x4 &ipic 21 0x8
403
-
404
-
/* IDSEL 0x18 */
405
-
0xc000 0x0 0x0 0x1 &ipic 21 0x8
406
-
0xc000 0x0 0x0 0x2 &ipic 22 0x8
407
-
0xc000 0x0 0x0 0x3 &ipic 23 0x8
408
-
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
409
-
interrupt-parent = <&ipic>;
410
-
interrupts = <66 0x8>;
411
-
bus-range = <0x0 0x0>;
412
-
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
413
-
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
414
-
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
415
-
clock-frequency = <0>;
416
-
sleep = <&pmc 0x00010000>;
417
-
#interrupt-cells = <1>;
418
-
#size-cells = <2>;
419
-
#address-cells = <3>;
420
-
reg = <0xe0008500 0x100 /* internal registers */
421
-
0xe0008300 0x8>; /* config space access registers */
422
-
compatible = "fsl,mpc8349-pci";
423
-
device_type = "pci";
424
-
};
425
-
426
-
pci1: pcie@e0009000 {
427
-
#address-cells = <3>;
428
-
#size-cells = <2>;
429
-
#interrupt-cells = <1>;
430
-
device_type = "pci";
431
-
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
432
-
reg = <0xe0009000 0x00001000>;
433
-
ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
434
-
0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
435
-
bus-range = <0 255>;
436
-
interrupt-map-mask = <0xf800 0 0 7>;
437
-
interrupt-map = <0 0 0 1 &ipic 1 8
438
-
0 0 0 2 &ipic 1 8
439
-
0 0 0 3 &ipic 1 8
440
-
0 0 0 4 &ipic 1 8>;
441
-
sleep = <&pmc 0x00300000>;
442
-
clock-frequency = <0>;
443
-
444
-
pcie@0 {
445
-
#address-cells = <3>;
446
-
#size-cells = <2>;
447
-
device_type = "pci";
448
-
reg = <0 0 0 0 0>;
449
-
ranges = <0x02000000 0 0xa8000000
450
-
0x02000000 0 0xa8000000
451
-
0 0x10000000
452
-
0x01000000 0 0x00000000
453
-
0x01000000 0 0x00000000
454
-
0 0x00800000>;
455
-
};
456
-
};
457
-
458
-
pci2: pcie@e000a000 {
459
-
#address-cells = <3>;
460
-
#size-cells = <2>;
461
-
#interrupt-cells = <1>;
462
-
device_type = "pci";
463
-
compatible = "fsl,mpc8378-pcie", "fsl,mpc8314-pcie";
464
-
reg = <0xe000a000 0x00001000>;
465
-
ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
466
-
0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
467
-
bus-range = <0 255>;
468
-
interrupt-map-mask = <0xf800 0 0 7>;
469
-
interrupt-map = <0 0 0 1 &ipic 2 8
470
-
0 0 0 2 &ipic 2 8
471
-
0 0 0 3 &ipic 2 8
472
-
0 0 0 4 &ipic 2 8>;
473
-
sleep = <&pmc 0x000c0000>;
474
-
clock-frequency = <0>;
475
-
476
-
pcie@0 {
477
-
#address-cells = <3>;
478
-
#size-cells = <2>;
479
-
device_type = "pci";
480
-
reg = <0 0 0 0 0>;
481
-
ranges = <0x02000000 0 0xc8000000
482
-
0x02000000 0 0xc8000000
483
-
0 0x10000000
484
-
0x01000000 0 0x00000000
485
-
0x01000000 0 0x00000000
486
-
0 0x00800000>;
487
-
};
488
-
};
489
-
};
-455
arch/powerpc/boot/dts/mpc8379_mds.dts
-455
arch/powerpc/boot/dts/mpc8379_mds.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8379E MDS Device Tree Source
4
-
*
5
-
* Copyright 2007 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
/ {
11
-
model = "fsl,mpc8379emds";
12
-
compatible = "fsl,mpc8379emds","fsl,mpc837xmds";
13
-
#address-cells = <1>;
14
-
#size-cells = <1>;
15
-
16
-
aliases {
17
-
ethernet0 = &enet0;
18
-
ethernet1 = &enet1;
19
-
serial0 = &serial0;
20
-
serial1 = &serial1;
21
-
pci0 = &pci0;
22
-
};
23
-
24
-
cpus {
25
-
#address-cells = <1>;
26
-
#size-cells = <0>;
27
-
28
-
PowerPC,8379@0 {
29
-
device_type = "cpu";
30
-
reg = <0x0>;
31
-
d-cache-line-size = <32>;
32
-
i-cache-line-size = <32>;
33
-
d-cache-size = <32768>;
34
-
i-cache-size = <32768>;
35
-
timebase-frequency = <0>;
36
-
bus-frequency = <0>;
37
-
clock-frequency = <0>;
38
-
};
39
-
};
40
-
41
-
memory {
42
-
device_type = "memory";
43
-
reg = <0x00000000 0x20000000>; // 512MB at 0
44
-
};
45
-
46
-
localbus@e0005000 {
47
-
#address-cells = <2>;
48
-
#size-cells = <1>;
49
-
compatible = "fsl,mpc8379-elbc", "fsl,elbc", "simple-bus";
50
-
reg = <0xe0005000 0x1000>;
51
-
interrupts = <77 0x8>;
52
-
interrupt-parent = <&ipic>;
53
-
54
-
// booting from NOR flash
55
-
ranges = <0 0x0 0xfe000000 0x02000000
56
-
1 0x0 0xf8000000 0x00008000
57
-
3 0x0 0xe0600000 0x00008000>;
58
-
59
-
flash@0,0 {
60
-
#address-cells = <1>;
61
-
#size-cells = <1>;
62
-
compatible = "cfi-flash";
63
-
reg = <0 0x0 0x2000000>;
64
-
bank-width = <2>;
65
-
device-width = <1>;
66
-
67
-
u-boot@0 {
68
-
reg = <0x0 0x100000>;
69
-
read-only;
70
-
};
71
-
72
-
fs@100000 {
73
-
reg = <0x100000 0x800000>;
74
-
};
75
-
76
-
kernel@1d00000 {
77
-
reg = <0x1d00000 0x200000>;
78
-
};
79
-
80
-
dtb@1f00000 {
81
-
reg = <0x1f00000 0x100000>;
82
-
};
83
-
};
84
-
85
-
bcsr@1,0 {
86
-
reg = <1 0x0 0x8000>;
87
-
compatible = "fsl,mpc837xmds-bcsr";
88
-
};
89
-
90
-
nand@3,0 {
91
-
#address-cells = <1>;
92
-
#size-cells = <1>;
93
-
compatible = "fsl,mpc8379-fcm-nand",
94
-
"fsl,elbc-fcm-nand";
95
-
reg = <3 0x0 0x8000>;
96
-
97
-
u-boot@0 {
98
-
reg = <0x0 0x100000>;
99
-
read-only;
100
-
};
101
-
102
-
kernel@100000 {
103
-
reg = <0x100000 0x300000>;
104
-
};
105
-
106
-
fs@400000 {
107
-
reg = <0x400000 0x1c00000>;
108
-
};
109
-
};
110
-
};
111
-
112
-
soc@e0000000 {
113
-
#address-cells = <1>;
114
-
#size-cells = <1>;
115
-
device_type = "soc";
116
-
compatible = "simple-bus";
117
-
ranges = <0x0 0xe0000000 0x00100000>;
118
-
reg = <0xe0000000 0x00000200>;
119
-
bus-frequency = <0>;
120
-
121
-
wdt@200 {
122
-
compatible = "mpc83xx_wdt";
123
-
reg = <0x200 0x100>;
124
-
};
125
-
126
-
sleep-nexus {
127
-
#address-cells = <1>;
128
-
#size-cells = <1>;
129
-
compatible = "simple-bus";
130
-
sleep = <&pmc 0x0c000000>;
131
-
ranges;
132
-
133
-
i2c@3000 {
134
-
#address-cells = <1>;
135
-
#size-cells = <0>;
136
-
cell-index = <0>;
137
-
compatible = "fsl-i2c";
138
-
reg = <0x3000 0x100>;
139
-
interrupts = <14 0x8>;
140
-
interrupt-parent = <&ipic>;
141
-
dfsrr;
142
-
143
-
rtc@68 {
144
-
compatible = "dallas,ds1374";
145
-
reg = <0x68>;
146
-
interrupts = <19 0x8>;
147
-
interrupt-parent = <&ipic>;
148
-
};
149
-
};
150
-
151
-
sdhci@2e000 {
152
-
compatible = "fsl,mpc8379-esdhc", "fsl,esdhc";
153
-
reg = <0x2e000 0x1000>;
154
-
interrupts = <42 0x8>;
155
-
interrupt-parent = <&ipic>;
156
-
sdhci,wp-inverted;
157
-
/* Filled in by U-Boot */
158
-
clock-frequency = <0>;
159
-
};
160
-
};
161
-
162
-
i2c@3100 {
163
-
#address-cells = <1>;
164
-
#size-cells = <0>;
165
-
cell-index = <1>;
166
-
compatible = "fsl-i2c";
167
-
reg = <0x3100 0x100>;
168
-
interrupts = <15 0x8>;
169
-
interrupt-parent = <&ipic>;
170
-
dfsrr;
171
-
};
172
-
173
-
spi@7000 {
174
-
cell-index = <0>;
175
-
compatible = "fsl,spi";
176
-
reg = <0x7000 0x1000>;
177
-
interrupts = <16 0x8>;
178
-
interrupt-parent = <&ipic>;
179
-
mode = "cpu";
180
-
};
181
-
182
-
dma@82a8 {
183
-
#address-cells = <1>;
184
-
#size-cells = <1>;
185
-
compatible = "fsl,mpc8379-dma", "fsl,elo-dma";
186
-
reg = <0x82a8 4>;
187
-
ranges = <0 0x8100 0x1a8>;
188
-
interrupt-parent = <&ipic>;
189
-
interrupts = <71 8>;
190
-
cell-index = <0>;
191
-
dma-channel@0 {
192
-
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
193
-
reg = <0 0x80>;
194
-
cell-index = <0>;
195
-
interrupt-parent = <&ipic>;
196
-
interrupts = <71 8>;
197
-
};
198
-
dma-channel@80 {
199
-
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
200
-
reg = <0x80 0x80>;
201
-
cell-index = <1>;
202
-
interrupt-parent = <&ipic>;
203
-
interrupts = <71 8>;
204
-
};
205
-
dma-channel@100 {
206
-
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
207
-
reg = <0x100 0x80>;
208
-
cell-index = <2>;
209
-
interrupt-parent = <&ipic>;
210
-
interrupts = <71 8>;
211
-
};
212
-
dma-channel@180 {
213
-
compatible = "fsl,mpc8379-dma-channel", "fsl,elo-dma-channel";
214
-
reg = <0x180 0x28>;
215
-
cell-index = <3>;
216
-
interrupt-parent = <&ipic>;
217
-
interrupts = <71 8>;
218
-
};
219
-
};
220
-
221
-
usb@23000 {
222
-
compatible = "fsl-usb2-dr";
223
-
reg = <0x23000 0x1000>;
224
-
#address-cells = <1>;
225
-
#size-cells = <0>;
226
-
interrupt-parent = <&ipic>;
227
-
interrupts = <38 0x8>;
228
-
dr_mode = "host";
229
-
phy_type = "ulpi";
230
-
sleep = <&pmc 0x00c00000>;
231
-
};
232
-
233
-
enet0: ethernet@24000 {
234
-
#address-cells = <1>;
235
-
#size-cells = <1>;
236
-
cell-index = <0>;
237
-
device_type = "network";
238
-
model = "eTSEC";
239
-
compatible = "gianfar";
240
-
reg = <0x24000 0x1000>;
241
-
ranges = <0x0 0x24000 0x1000>;
242
-
local-mac-address = [ 00 00 00 00 00 00 ];
243
-
interrupts = <32 0x8 33 0x8 34 0x8>;
244
-
phy-connection-type = "mii";
245
-
interrupt-parent = <&ipic>;
246
-
tbi-handle = <&tbi0>;
247
-
phy-handle = <&phy2>;
248
-
sleep = <&pmc 0xc0000000>;
249
-
fsl,magic-packet;
250
-
251
-
mdio@520 {
252
-
#address-cells = <1>;
253
-
#size-cells = <0>;
254
-
compatible = "fsl,gianfar-mdio";
255
-
reg = <0x520 0x20>;
256
-
257
-
phy2: ethernet-phy@2 {
258
-
interrupt-parent = <&ipic>;
259
-
interrupts = <17 0x8>;
260
-
reg = <0x2>;
261
-
};
262
-
263
-
phy3: ethernet-phy@3 {
264
-
interrupt-parent = <&ipic>;
265
-
interrupts = <18 0x8>;
266
-
reg = <0x3>;
267
-
};
268
-
269
-
tbi0: tbi-phy@11 {
270
-
reg = <0x11>;
271
-
device_type = "tbi-phy";
272
-
};
273
-
};
274
-
};
275
-
276
-
enet1: ethernet@25000 {
277
-
#address-cells = <1>;
278
-
#size-cells = <1>;
279
-
cell-index = <1>;
280
-
device_type = "network";
281
-
model = "eTSEC";
282
-
compatible = "gianfar";
283
-
reg = <0x25000 0x1000>;
284
-
ranges = <0x0 0x25000 0x1000>;
285
-
local-mac-address = [ 00 00 00 00 00 00 ];
286
-
interrupts = <35 0x8 36 0x8 37 0x8>;
287
-
phy-connection-type = "mii";
288
-
interrupt-parent = <&ipic>;
289
-
tbi-handle = <&tbi1>;
290
-
phy-handle = <&phy3>;
291
-
sleep = <&pmc 0x30000000>;
292
-
fsl,magic-packet;
293
-
294
-
mdio@520 {
295
-
#address-cells = <1>;
296
-
#size-cells = <0>;
297
-
compatible = "fsl,gianfar-tbi";
298
-
reg = <0x520 0x20>;
299
-
300
-
tbi1: tbi-phy@11 {
301
-
reg = <0x11>;
302
-
device_type = "tbi-phy";
303
-
};
304
-
};
305
-
};
306
-
307
-
serial0: serial@4500 {
308
-
cell-index = <0>;
309
-
device_type = "serial";
310
-
compatible = "fsl,ns16550", "ns16550";
311
-
reg = <0x4500 0x100>;
312
-
clock-frequency = <0>;
313
-
interrupts = <9 0x8>;
314
-
interrupt-parent = <&ipic>;
315
-
};
316
-
317
-
serial1: serial@4600 {
318
-
cell-index = <1>;
319
-
device_type = "serial";
320
-
compatible = "fsl,ns16550", "ns16550";
321
-
reg = <0x4600 0x100>;
322
-
clock-frequency = <0>;
323
-
interrupts = <10 0x8>;
324
-
interrupt-parent = <&ipic>;
325
-
};
326
-
327
-
crypto@30000 {
328
-
compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
329
-
"fsl,sec2.1", "fsl,sec2.0";
330
-
reg = <0x30000 0x10000>;
331
-
interrupts = <11 0x8>;
332
-
interrupt-parent = <&ipic>;
333
-
fsl,num-channels = <4>;
334
-
fsl,channel-fifo-len = <24>;
335
-
fsl,exec-units-mask = <0x9fe>;
336
-
fsl,descriptor-types-mask = <0x3ab0ebf>;
337
-
sleep = <&pmc 0x03000000>;
338
-
};
339
-
340
-
sata@18000 {
341
-
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
342
-
reg = <0x18000 0x1000>;
343
-
interrupts = <44 0x8>;
344
-
interrupt-parent = <&ipic>;
345
-
sleep = <&pmc 0x000000c0>;
346
-
};
347
-
348
-
sata@19000 {
349
-
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
350
-
reg = <0x19000 0x1000>;
351
-
interrupts = <45 0x8>;
352
-
interrupt-parent = <&ipic>;
353
-
sleep = <&pmc 0x00000030>;
354
-
};
355
-
356
-
sata@1a000 {
357
-
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
358
-
reg = <0x1a000 0x1000>;
359
-
interrupts = <46 0x8>;
360
-
interrupt-parent = <&ipic>;
361
-
sleep = <&pmc 0x0000000c>;
362
-
};
363
-
364
-
sata@1b000 {
365
-
compatible = "fsl,mpc8379-sata", "fsl,pq-sata";
366
-
reg = <0x1b000 0x1000>;
367
-
interrupts = <47 0x8>;
368
-
interrupt-parent = <&ipic>;
369
-
sleep = <&pmc 0x00000003>;
370
-
};
371
-
372
-
/* IPIC
373
-
* interrupts cell = <intr #, sense>
374
-
* sense values match linux IORESOURCE_IRQ_* defines:
375
-
* sense == 8: Level, low assertion
376
-
* sense == 2: Edge, high-to-low change
377
-
*/
378
-
ipic: pic@700 {
379
-
compatible = "fsl,ipic";
380
-
interrupt-controller;
381
-
#address-cells = <0>;
382
-
#interrupt-cells = <2>;
383
-
reg = <0x700 0x100>;
384
-
};
385
-
386
-
pmc: power@b00 {
387
-
compatible = "fsl,mpc8379-pmc", "fsl,mpc8349-pmc";
388
-
reg = <0xb00 0x100 0xa00 0x100>;
389
-
interrupts = <80 0x8>;
390
-
interrupt-parent = <&ipic>;
391
-
};
392
-
};
393
-
394
-
pci0: pci@e0008500 {
395
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
396
-
interrupt-map = <
397
-
398
-
/* IDSEL 0x11 */
399
-
0x8800 0x0 0x0 0x1 &ipic 20 0x8
400
-
0x8800 0x0 0x0 0x2 &ipic 21 0x8
401
-
0x8800 0x0 0x0 0x3 &ipic 22 0x8
402
-
0x8800 0x0 0x0 0x4 &ipic 23 0x8
403
-
404
-
/* IDSEL 0x12 */
405
-
0x9000 0x0 0x0 0x1 &ipic 22 0x8
406
-
0x9000 0x0 0x0 0x2 &ipic 23 0x8
407
-
0x9000 0x0 0x0 0x3 &ipic 20 0x8
408
-
0x9000 0x0 0x0 0x4 &ipic 21 0x8
409
-
410
-
/* IDSEL 0x13 */
411
-
0x9800 0x0 0x0 0x1 &ipic 23 0x8
412
-
0x9800 0x0 0x0 0x2 &ipic 20 0x8
413
-
0x9800 0x0 0x0 0x3 &ipic 21 0x8
414
-
0x9800 0x0 0x0 0x4 &ipic 22 0x8
415
-
416
-
/* IDSEL 0x15 */
417
-
0xa800 0x0 0x0 0x1 &ipic 20 0x8
418
-
0xa800 0x0 0x0 0x2 &ipic 21 0x8
419
-
0xa800 0x0 0x0 0x3 &ipic 22 0x8
420
-
0xa800 0x0 0x0 0x4 &ipic 23 0x8
421
-
422
-
/* IDSEL 0x16 */
423
-
0xb000 0x0 0x0 0x1 &ipic 23 0x8
424
-
0xb000 0x0 0x0 0x2 &ipic 20 0x8
425
-
0xb000 0x0 0x0 0x3 &ipic 21 0x8
426
-
0xb000 0x0 0x0 0x4 &ipic 22 0x8
427
-
428
-
/* IDSEL 0x17 */
429
-
0xb800 0x0 0x0 0x1 &ipic 22 0x8
430
-
0xb800 0x0 0x0 0x2 &ipic 23 0x8
431
-
0xb800 0x0 0x0 0x3 &ipic 20 0x8
432
-
0xb800 0x0 0x0 0x4 &ipic 21 0x8
433
-
434
-
/* IDSEL 0x18 */
435
-
0xc000 0x0 0x0 0x1 &ipic 21 0x8
436
-
0xc000 0x0 0x0 0x2 &ipic 22 0x8
437
-
0xc000 0x0 0x0 0x3 &ipic 23 0x8
438
-
0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
439
-
interrupt-parent = <&ipic>;
440
-
interrupts = <66 0x8>;
441
-
bus-range = <0x0 0x0>;
442
-
ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
443
-
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
444
-
0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
445
-
sleep = <&pmc 0x00010000>;
446
-
clock-frequency = <0>;
447
-
#interrupt-cells = <1>;
448
-
#size-cells = <2>;
449
-
#address-cells = <3>;
450
-
reg = <0xe0008500 0x100 /* internal registers */
451
-
0xe0008300 0x8>; /* config space access registers */
452
-
compatible = "fsl,mpc8349-pci";
453
-
device_type = "pci";
454
-
};
455
-
};
-503
arch/powerpc/boot/dts/mpc8610_hpcd.dts
-503
arch/powerpc/boot/dts/mpc8610_hpcd.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* MPC8610 HPCD Device Tree Source
4
-
*
5
-
* Copyright 2007-2008 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
/ {
11
-
model = "MPC8610HPCD";
12
-
compatible = "fsl,MPC8610HPCD";
13
-
#address-cells = <1>;
14
-
#size-cells = <1>;
15
-
16
-
aliases {
17
-
serial0 = &serial0;
18
-
serial1 = &serial1;
19
-
pci0 = &pci0;
20
-
pci1 = &pci1;
21
-
pci2 = &pci2;
22
-
};
23
-
24
-
cpus {
25
-
#address-cells = <1>;
26
-
#size-cells = <0>;
27
-
28
-
PowerPC,8610@0 {
29
-
device_type = "cpu";
30
-
reg = <0>;
31
-
d-cache-line-size = <32>;
32
-
i-cache-line-size = <32>;
33
-
d-cache-size = <32768>; // L1
34
-
i-cache-size = <32768>; // L1
35
-
sleep = <&pmc 0x00008000 0 // core
36
-
&pmc 0x00004000 0>; // timebase
37
-
timebase-frequency = <0>; // From uboot
38
-
bus-frequency = <0>; // From uboot
39
-
clock-frequency = <0>; // From uboot
40
-
};
41
-
};
42
-
43
-
memory {
44
-
device_type = "memory";
45
-
reg = <0x00000000 0x20000000>; // 512M at 0x0
46
-
};
47
-
48
-
localbus@e0005000 {
49
-
#address-cells = <2>;
50
-
#size-cells = <1>;
51
-
compatible = "fsl,mpc8610-elbc", "fsl,elbc", "simple-bus";
52
-
reg = <0xe0005000 0x1000>;
53
-
interrupts = <19 2>;
54
-
interrupt-parent = <&mpic>;
55
-
ranges = <0 0 0xf8000000 0x08000000
56
-
1 0 0xf0000000 0x08000000
57
-
2 0 0xe8400000 0x00008000
58
-
4 0 0xe8440000 0x00008000
59
-
5 0 0xe8480000 0x00008000
60
-
6 0 0xe84c0000 0x00008000
61
-
3 0 0xe8000000 0x00000020>;
62
-
sleep = <&pmc 0x08000000 0>;
63
-
64
-
flash@0,0 {
65
-
compatible = "cfi-flash";
66
-
reg = <0 0 0x8000000>;
67
-
bank-width = <2>;
68
-
device-width = <1>;
69
-
};
70
-
71
-
flash@1,0 {
72
-
compatible = "cfi-flash";
73
-
reg = <1 0 0x8000000>;
74
-
bank-width = <2>;
75
-
device-width = <1>;
76
-
};
77
-
78
-
flash@2,0 {
79
-
compatible = "fsl,mpc8610-fcm-nand",
80
-
"fsl,elbc-fcm-nand";
81
-
reg = <2 0 0x8000>;
82
-
};
83
-
84
-
flash@4,0 {
85
-
compatible = "fsl,mpc8610-fcm-nand",
86
-
"fsl,elbc-fcm-nand";
87
-
reg = <4 0 0x8000>;
88
-
};
89
-
90
-
flash@5,0 {
91
-
compatible = "fsl,mpc8610-fcm-nand",
92
-
"fsl,elbc-fcm-nand";
93
-
reg = <5 0 0x8000>;
94
-
};
95
-
96
-
flash@6,0 {
97
-
compatible = "fsl,mpc8610-fcm-nand",
98
-
"fsl,elbc-fcm-nand";
99
-
reg = <6 0 0x8000>;
100
-
};
101
-
102
-
board-control@3,0 {
103
-
#address-cells = <1>;
104
-
#size-cells = <1>;
105
-
compatible = "fsl,fpga-pixis";
106
-
reg = <3 0 0x20>;
107
-
ranges = <0 3 0 0x20>;
108
-
interrupt-parent = <&mpic>;
109
-
interrupts = <8 8>;
110
-
111
-
sdcsr_pio: gpio-controller@a {
112
-
#gpio-cells = <2>;
113
-
compatible = "fsl,fpga-pixis-gpio-bank";
114
-
reg = <0xa 1>;
115
-
gpio-controller;
116
-
};
117
-
};
118
-
};
119
-
120
-
soc@e0000000 {
121
-
#address-cells = <1>;
122
-
#size-cells = <1>;
123
-
#interrupt-cells = <2>;
124
-
device_type = "soc";
125
-
compatible = "fsl,mpc8610-immr", "simple-bus";
126
-
ranges = <0x0 0xe0000000 0x00100000>;
127
-
bus-frequency = <0>;
128
-
129
-
mcm-law@0 {
130
-
compatible = "fsl,mcm-law";
131
-
reg = <0x0 0x1000>;
132
-
fsl,num-laws = <10>;
133
-
};
134
-
135
-
mcm@1000 {
136
-
compatible = "fsl,mpc8610-mcm", "fsl,mcm";
137
-
reg = <0x1000 0x1000>;
138
-
interrupts = <17 2>;
139
-
interrupt-parent = <&mpic>;
140
-
};
141
-
142
-
i2c@3000 {
143
-
#address-cells = <1>;
144
-
#size-cells = <0>;
145
-
cell-index = <0>;
146
-
compatible = "fsl-i2c";
147
-
reg = <0x3000 0x100>;
148
-
interrupts = <43 2>;
149
-
interrupt-parent = <&mpic>;
150
-
dfsrr;
151
-
152
-
cs4270:codec@4f {
153
-
compatible = "cirrus,cs4270";
154
-
reg = <0x4f>;
155
-
/* MCLK source is a stand-alone oscillator */
156
-
clock-frequency = <12288000>;
157
-
};
158
-
};
159
-
160
-
i2c@3100 {
161
-
#address-cells = <1>;
162
-
#size-cells = <0>;
163
-
cell-index = <1>;
164
-
compatible = "fsl-i2c";
165
-
reg = <0x3100 0x100>;
166
-
interrupts = <43 2>;
167
-
interrupt-parent = <&mpic>;
168
-
sleep = <&pmc 0x00000004 0>;
169
-
dfsrr;
170
-
};
171
-
172
-
serial0: serial@4500 {
173
-
cell-index = <0>;
174
-
device_type = "serial";
175
-
compatible = "fsl,ns16550", "ns16550";
176
-
reg = <0x4500 0x100>;
177
-
clock-frequency = <0>;
178
-
interrupts = <42 2>;
179
-
interrupt-parent = <&mpic>;
180
-
sleep = <&pmc 0x00000002 0>;
181
-
};
182
-
183
-
serial1: serial@4600 {
184
-
cell-index = <1>;
185
-
device_type = "serial";
186
-
compatible = "fsl,ns16550", "ns16550";
187
-
reg = <0x4600 0x100>;
188
-
clock-frequency = <0>;
189
-
interrupts = <42 2>;
190
-
interrupt-parent = <&mpic>;
191
-
sleep = <&pmc 0x00000008 0>;
192
-
};
193
-
194
-
spi@7000 {
195
-
#address-cells = <1>;
196
-
#size-cells = <0>;
197
-
compatible = "fsl,mpc8610-spi", "fsl,spi";
198
-
reg = <0x7000 0x40>;
199
-
cell-index = <0>;
200
-
interrupts = <59 2>;
201
-
interrupt-parent = <&mpic>;
202
-
mode = "cpu";
203
-
cs-gpios = <&sdcsr_pio 7 0>;
204
-
sleep = <&pmc 0x00000800 0>;
205
-
206
-
mmc-slot@0 {
207
-
compatible = "fsl,mpc8610hpcd-mmc-slot",
208
-
"mmc-spi-slot";
209
-
reg = <0>;
210
-
gpios = <&sdcsr_pio 0 1 /* nCD */
211
-
&sdcsr_pio 1 0>; /* WP */
212
-
voltage-ranges = <3300 3300>;
213
-
spi-max-frequency = <50000000>;
214
-
};
215
-
};
216
-
217
-
display@2c000 {
218
-
compatible = "fsl,diu";
219
-
reg = <0x2c000 100>;
220
-
interrupts = <72 2>;
221
-
interrupt-parent = <&mpic>;
222
-
sleep = <&pmc 0x04000000 0>;
223
-
};
224
-
225
-
mpic: interrupt-controller@40000 {
226
-
interrupt-controller;
227
-
#address-cells = <0>;
228
-
#interrupt-cells = <2>;
229
-
reg = <0x40000 0x40000>;
230
-
compatible = "chrp,open-pic";
231
-
device_type = "open-pic";
232
-
};
233
-
234
-
msi@41600 {
235
-
compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
236
-
reg = <0x41600 0x80>;
237
-
msi-available-ranges = <0 0x100>;
238
-
interrupts = <
239
-
0xe0 0
240
-
0xe1 0
241
-
0xe2 0
242
-
0xe3 0
243
-
0xe4 0
244
-
0xe5 0
245
-
0xe6 0
246
-
0xe7 0>;
247
-
interrupt-parent = <&mpic>;
248
-
};
249
-
250
-
global-utilities@e0000 {
251
-
#address-cells = <1>;
252
-
#size-cells = <1>;
253
-
compatible = "fsl,mpc8610-guts";
254
-
reg = <0xe0000 0x1000>;
255
-
ranges = <0 0xe0000 0x1000>;
256
-
fsl,has-rstcr;
257
-
258
-
pmc: power@70 {
259
-
compatible = "fsl,mpc8610-pmc",
260
-
"fsl,mpc8641d-pmc";
261
-
reg = <0x70 0x20>;
262
-
};
263
-
};
264
-
265
-
wdt@e4000 {
266
-
compatible = "fsl,mpc8610-wdt";
267
-
reg = <0xe4000 0x100>;
268
-
};
269
-
270
-
ssi@16000 {
271
-
compatible = "fsl,mpc8610-ssi";
272
-
cell-index = <0>;
273
-
reg = <0x16000 0x100>;
274
-
interrupt-parent = <&mpic>;
275
-
interrupts = <62 2>;
276
-
fsl,mode = "i2s-slave";
277
-
codec-handle = <&cs4270>;
278
-
fsl,playback-dma = <&dma00>;
279
-
fsl,capture-dma = <&dma01>;
280
-
fsl,fifo-depth = <8>;
281
-
sleep = <&pmc 0 0x08000000>;
282
-
};
283
-
284
-
ssi@16100 {
285
-
compatible = "fsl,mpc8610-ssi";
286
-
status = "disabled";
287
-
cell-index = <1>;
288
-
reg = <0x16100 0x100>;
289
-
interrupt-parent = <&mpic>;
290
-
interrupts = <63 2>;
291
-
fsl,fifo-depth = <8>;
292
-
sleep = <&pmc 0 0x04000000>;
293
-
};
294
-
295
-
dma@21300 {
296
-
#address-cells = <1>;
297
-
#size-cells = <1>;
298
-
compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
299
-
cell-index = <0>;
300
-
reg = <0x21300 0x4>; /* DMA general status register */
301
-
ranges = <0x0 0x21100 0x200>;
302
-
sleep = <&pmc 0x00000400 0>;
303
-
304
-
dma00: dma-channel@0 {
305
-
compatible = "fsl,mpc8610-dma-channel",
306
-
"fsl,ssi-dma-channel";
307
-
cell-index = <0>;
308
-
reg = <0x0 0x80>;
309
-
interrupt-parent = <&mpic>;
310
-
interrupts = <20 2>;
311
-
};
312
-
dma01: dma-channel@1 {
313
-
compatible = "fsl,mpc8610-dma-channel",
314
-
"fsl,ssi-dma-channel";
315
-
cell-index = <1>;
316
-
reg = <0x80 0x80>;
317
-
interrupt-parent = <&mpic>;
318
-
interrupts = <21 2>;
319
-
};
320
-
dma-channel@2 {
321
-
compatible = "fsl,mpc8610-dma-channel",
322
-
"fsl,eloplus-dma-channel";
323
-
cell-index = <2>;
324
-
reg = <0x100 0x80>;
325
-
interrupt-parent = <&mpic>;
326
-
interrupts = <22 2>;
327
-
};
328
-
dma-channel@3 {
329
-
compatible = "fsl,mpc8610-dma-channel",
330
-
"fsl,eloplus-dma-channel";
331
-
cell-index = <3>;
332
-
reg = <0x180 0x80>;
333
-
interrupt-parent = <&mpic>;
334
-
interrupts = <23 2>;
335
-
};
336
-
};
337
-
338
-
dma@c300 {
339
-
#address-cells = <1>;
340
-
#size-cells = <1>;
341
-
compatible = "fsl,mpc8610-dma", "fsl,eloplus-dma";
342
-
cell-index = <1>;
343
-
reg = <0xc300 0x4>; /* DMA general status register */
344
-
ranges = <0x0 0xc100 0x200>;
345
-
sleep = <&pmc 0x00000200 0>;
346
-
347
-
dma-channel@0 {
348
-
compatible = "fsl,mpc8610-dma-channel",
349
-
"fsl,eloplus-dma-channel";
350
-
cell-index = <0>;
351
-
reg = <0x0 0x80>;
352
-
interrupt-parent = <&mpic>;
353
-
interrupts = <76 2>;
354
-
};
355
-
dma-channel@1 {
356
-
compatible = "fsl,mpc8610-dma-channel",
357
-
"fsl,eloplus-dma-channel";
358
-
cell-index = <1>;
359
-
reg = <0x80 0x80>;
360
-
interrupt-parent = <&mpic>;
361
-
interrupts = <77 2>;
362
-
};
363
-
dma-channel@2 {
364
-
compatible = "fsl,mpc8610-dma-channel",
365
-
"fsl,eloplus-dma-channel";
366
-
cell-index = <2>;
367
-
reg = <0x100 0x80>;
368
-
interrupt-parent = <&mpic>;
369
-
interrupts = <78 2>;
370
-
};
371
-
dma-channel@3 {
372
-
compatible = "fsl,mpc8610-dma-channel",
373
-
"fsl,eloplus-dma-channel";
374
-
cell-index = <3>;
375
-
reg = <0x180 0x80>;
376
-
interrupt-parent = <&mpic>;
377
-
interrupts = <79 2>;
378
-
};
379
-
};
380
-
381
-
};
382
-
383
-
pci0: pci@e0008000 {
384
-
compatible = "fsl,mpc8610-pci";
385
-
device_type = "pci";
386
-
#interrupt-cells = <1>;
387
-
#size-cells = <2>;
388
-
#address-cells = <3>;
389
-
reg = <0xe0008000 0x1000>;
390
-
bus-range = <0 0>;
391
-
ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
392
-
0x01000000 0x0 0x00000000 0xe1000000 0x0 0x00100000>;
393
-
sleep = <&pmc 0x80000000 0>;
394
-
clock-frequency = <33333333>;
395
-
interrupt-parent = <&mpic>;
396
-
interrupts = <24 2>;
397
-
interrupt-map-mask = <0xf800 0 0 7>;
398
-
interrupt-map = <
399
-
/* IDSEL 0x11 */
400
-
0x8800 0 0 1 &mpic 4 1
401
-
0x8800 0 0 2 &mpic 5 1
402
-
0x8800 0 0 3 &mpic 6 1
403
-
0x8800 0 0 4 &mpic 7 1
404
-
405
-
/* IDSEL 0x12 */
406
-
0x9000 0 0 1 &mpic 5 1
407
-
0x9000 0 0 2 &mpic 6 1
408
-
0x9000 0 0 3 &mpic 7 1
409
-
0x9000 0 0 4 &mpic 4 1
410
-
>;
411
-
};
412
-
413
-
pci1: pcie@e000a000 {
414
-
compatible = "fsl,mpc8641-pcie";
415
-
device_type = "pci";
416
-
#interrupt-cells = <1>;
417
-
#size-cells = <2>;
418
-
#address-cells = <3>;
419
-
reg = <0xe000a000 0x1000>;
420
-
bus-range = <1 3>;
421
-
ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
422
-
0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
423
-
sleep = <&pmc 0x40000000 0>;
424
-
clock-frequency = <33333333>;
425
-
interrupt-parent = <&mpic>;
426
-
interrupts = <26 2>;
427
-
interrupt-map-mask = <0xf800 0 0 7>;
428
-
429
-
interrupt-map = <
430
-
/* IDSEL 0x1b */
431
-
0xd800 0 0 1 &mpic 2 1
432
-
433
-
/* IDSEL 0x1c*/
434
-
0xe000 0 0 1 &mpic 1 1
435
-
0xe000 0 0 2 &mpic 1 1
436
-
0xe000 0 0 3 &mpic 1 1
437
-
0xe000 0 0 4 &mpic 1 1
438
-
439
-
/* IDSEL 0x1f */
440
-
0xf800 0 0 1 &mpic 3 2
441
-
0xf800 0 0 2 &mpic 0 1
442
-
>;
443
-
444
-
pcie@0 {
445
-
reg = <0 0 0 0 0>;
446
-
#size-cells = <2>;
447
-
#address-cells = <3>;
448
-
device_type = "pci";
449
-
ranges = <0x02000000 0x0 0xa0000000
450
-
0x02000000 0x0 0xa0000000
451
-
0x0 0x10000000
452
-
0x01000000 0x0 0x00000000
453
-
0x01000000 0x0 0x00000000
454
-
0x0 0x00100000>;
455
-
uli1575@0 {
456
-
reg = <0 0 0 0 0>;
457
-
#size-cells = <2>;
458
-
#address-cells = <3>;
459
-
ranges = <0x02000000 0x0 0xa0000000
460
-
0x02000000 0x0 0xa0000000
461
-
0x0 0x10000000
462
-
0x01000000 0x0 0x00000000
463
-
0x01000000 0x0 0x00000000
464
-
0x0 0x00100000>;
465
-
466
-
isa@1e {
467
-
device_type = "isa";
468
-
#size-cells = <1>;
469
-
#address-cells = <2>;
470
-
reg = <0xf000 0 0 0 0>;
471
-
ranges = <1 0 0x01000000 0 0
472
-
0x00001000>;
473
-
474
-
rtc@70 {
475
-
compatible = "pnpPNP,b00";
476
-
reg = <1 0x70 2>;
477
-
};
478
-
};
479
-
};
480
-
};
481
-
};
482
-
483
-
pci2: pcie@e0009000 {
484
-
#address-cells = <3>;
485
-
#size-cells = <2>;
486
-
#interrupt-cells = <1>;
487
-
device_type = "pci";
488
-
compatible = "fsl,mpc8641-pcie";
489
-
reg = <0xe0009000 0x00001000>;
490
-
ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
491
-
0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;
492
-
bus-range = <0 255>;
493
-
interrupt-map-mask = <0xf800 0 0 7>;
494
-
interrupt-map = <0x0000 0 0 1 &mpic 4 1
495
-
0x0000 0 0 2 &mpic 5 1
496
-
0x0000 0 0 3 &mpic 6 1
497
-
0x0000 0 0 4 &mpic 7 1>;
498
-
interrupt-parent = <&mpic>;
499
-
interrupts = <25 2>;
500
-
sleep = <&pmc 0x20000000 0>;
501
-
clock-frequency = <33333333>;
502
-
};
503
-
};
-243
arch/powerpc/boot/dts/pq2fads.dts
-243
arch/powerpc/boot/dts/pq2fads.dts
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* Device Tree for the PQ2FADS-ZU board with an MPC8280 chip.
4
-
*
5
-
* Copyright 2007,2008 Freescale Semiconductor Inc.
6
-
*/
7
-
8
-
/dts-v1/;
9
-
10
-
/ {
11
-
model = "pq2fads";
12
-
compatible = "fsl,pq2fads";
13
-
#address-cells = <1>;
14
-
#size-cells = <1>;
15
-
16
-
aliases {
17
-
ethernet0 = &enet0;
18
-
ethernet1 = &enet1;
19
-
serial0 = &serial0;
20
-
serial1 = &serial1;
21
-
pci0 = &pci0;
22
-
};
23
-
24
-
cpus {
25
-
#address-cells = <1>;
26
-
#size-cells = <0>;
27
-
28
-
cpu@0 {
29
-
device_type = "cpu";
30
-
reg = <0x0>;
31
-
d-cache-line-size = <32>;
32
-
i-cache-line-size = <32>;
33
-
d-cache-size = <16384>;
34
-
i-cache-size = <16384>;
35
-
timebase-frequency = <0>;
36
-
clock-frequency = <0>;
37
-
};
38
-
};
39
-
40
-
memory {
41
-
device_type = "memory";
42
-
reg = <0x0 0x0>;
43
-
};
44
-
45
-
localbus@f0010100 {
46
-
compatible = "fsl,mpc8280-localbus",
47
-
"fsl,pq2-localbus";
48
-
#address-cells = <2>;
49
-
#size-cells = <1>;
50
-
reg = <0xf0010100 0x60>;
51
-
52
-
ranges = <0x0 0x0 0xff800000 0x800000
53
-
0x1 0x0 0xf4500000 0x8000
54
-
0x8 0x0 0xf8200000 0x8000>;
55
-
56
-
flash@0,0 {
57
-
compatible = "jedec-flash";
58
-
reg = <0x0 0x0 0x800000>;
59
-
bank-width = <4>;
60
-
device-width = <1>;
61
-
};
62
-
63
-
bcsr@1,0 {
64
-
reg = <0x1 0x0 0x20>;
65
-
compatible = "fsl,pq2fads-bcsr";
66
-
};
67
-
68
-
PCI_PIC: pic@8,0 {
69
-
#interrupt-cells = <1>;
70
-
interrupt-controller;
71
-
reg = <0x8 0x0 0x8>;
72
-
compatible = "fsl,pq2ads-pci-pic";
73
-
interrupt-parent = <&PIC>;
74
-
interrupts = <24 8>;
75
-
};
76
-
};
77
-
78
-
pci0: pci@f0010800 {
79
-
device_type = "pci";
80
-
reg = <0xf0010800 0x10c 0xf00101ac 0x8 0xf00101c4 0x8>;
81
-
compatible = "fsl,mpc8280-pci", "fsl,pq2-pci";
82
-
#interrupt-cells = <1>;
83
-
#size-cells = <2>;
84
-
#address-cells = <3>;
85
-
clock-frequency = <66000000>;
86
-
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
87
-
interrupt-map = <
88
-
/* IDSEL 0x16 */
89
-
0xb000 0x0 0x0 0x1 &PCI_PIC 0
90
-
0xb000 0x0 0x0 0x2 &PCI_PIC 1
91
-
0xb000 0x0 0x0 0x3 &PCI_PIC 2
92
-
0xb000 0x0 0x0 0x4 &PCI_PIC 3
93
-
94
-
/* IDSEL 0x17 */
95
-
0xb800 0x0 0x0 0x1 &PCI_PIC 4
96
-
0xb800 0x0 0x0 0x2 &PCI_PIC 5
97
-
0xb800 0x0 0x0 0x3 &PCI_PIC 6
98
-
0xb800 0x0 0x0 0x4 &PCI_PIC 7
99
-
100
-
/* IDSEL 0x18 */
101
-
0xc000 0x0 0x0 0x1 &PCI_PIC 8
102
-
0xc000 0x0 0x0 0x2 &PCI_PIC 9
103
-
0xc000 0x0 0x0 0x3 &PCI_PIC 10
104
-
0xc000 0x0 0x0 0x4 &PCI_PIC 11>;
105
-
106
-
interrupt-parent = <&PIC>;
107
-
interrupts = <18 8>;
108
-
ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x20000000
109
-
0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
110
-
0x1000000 0x0 0x0 0xf6000000 0x0 0x2000000>;
111
-
};
112
-
113
-
soc@f0000000 {
114
-
#address-cells = <1>;
115
-
#size-cells = <1>;
116
-
device_type = "soc";
117
-
compatible = "fsl,mpc8280", "fsl,pq2-soc";
118
-
ranges = <0x0 0xf0000000 0x53000>;
119
-
120
-
// Temporary -- will go away once kernel uses ranges for get_immrbase().
121
-
reg = <0xf0000000 0x53000>;
122
-
123
-
cpm@119c0 {
124
-
#address-cells = <1>;
125
-
#size-cells = <1>;
126
-
#interrupt-cells = <2>;
127
-
compatible = "fsl,mpc8280-cpm", "fsl,cpm2";
128
-
reg = <0x119c0 0x30>;
129
-
ranges;
130
-
131
-
muram@0 {
132
-
#address-cells = <1>;
133
-
#size-cells = <1>;
134
-
ranges = <0x0 0x0 0x10000>;
135
-
136
-
data@0 {
137
-
compatible = "fsl,cpm-muram-data";
138
-
reg = <0x0 0x2000 0x9800 0x800>;
139
-
};
140
-
};
141
-
142
-
brg@119f0 {
143
-
compatible = "fsl,mpc8280-brg",
144
-
"fsl,cpm2-brg",
145
-
"fsl,cpm-brg";
146
-
reg = <0x119f0 0x10 0x115f0 0x10>;
147
-
};
148
-
149
-
serial0: serial@11a00 {
150
-
device_type = "serial";
151
-
compatible = "fsl,mpc8280-scc-uart",
152
-
"fsl,cpm2-scc-uart";
153
-
reg = <0x11a00 0x20 0x8000 0x100>;
154
-
interrupts = <40 8>;
155
-
interrupt-parent = <&PIC>;
156
-
fsl,cpm-brg = <1>;
157
-
fsl,cpm-command = <0x800000>;
158
-
};
159
-
160
-
serial1: serial@11a20 {
161
-
device_type = "serial";
162
-
compatible = "fsl,mpc8280-scc-uart",
163
-
"fsl,cpm2-scc-uart";
164
-
reg = <0x11a20 0x20 0x8100 0x100>;
165
-
interrupts = <41 8>;
166
-
interrupt-parent = <&PIC>;
167
-
fsl,cpm-brg = <2>;
168
-
fsl,cpm-command = <0x4a00000>;
169
-
};
170
-
171
-
enet0: ethernet@11320 {
172
-
device_type = "network";
173
-
compatible = "fsl,mpc8280-fcc-enet",
174
-
"fsl,cpm2-fcc-enet";
175
-
reg = <0x11320 0x20 0x8500 0x100 0x113b0 0x1>;
176
-
interrupts = <33 8>;
177
-
interrupt-parent = <&PIC>;
178
-
phy-handle = <&PHY0>;
179
-
linux,network-index = <0>;
180
-
fsl,cpm-command = <0x16200300>;
181
-
};
182
-
183
-
enet1: ethernet@11340 {
184
-
device_type = "network";
185
-
compatible = "fsl,mpc8280-fcc-enet",
186
-
"fsl,cpm2-fcc-enet";
187
-
reg = <0x11340 0x20 0x8600 0x100 0x113d0 0x1>;
188
-
interrupts = <34 8>;
189
-
interrupt-parent = <&PIC>;
190
-
phy-handle = <&PHY1>;
191
-
linux,network-index = <1>;
192
-
fsl,cpm-command = <0x1a400300>;
193
-
local-mac-address = [00 e0 0c 00 79 01];
194
-
};
195
-
196
-
mdio@10d40 {
197
-
compatible = "fsl,pq2fads-mdio-bitbang",
198
-
"fsl,mpc8280-mdio-bitbang",
199
-
"fsl,cpm2-mdio-bitbang";
200
-
#address-cells = <1>;
201
-
#size-cells = <0>;
202
-
reg = <0x10d40 0x14>;
203
-
fsl,mdio-pin = <9>;
204
-
fsl,mdc-pin = <10>;
205
-
206
-
PHY0: ethernet-phy@0 {
207
-
interrupt-parent = <&PIC>;
208
-
interrupts = <25 2>;
209
-
reg = <0x0>;
210
-
};
211
-
212
-
PHY1: ethernet-phy@1 {
213
-
interrupt-parent = <&PIC>;
214
-
interrupts = <25 2>;
215
-
reg = <0x3>;
216
-
};
217
-
};
218
-
219
-
usb@11b60 {
220
-
#address-cells = <1>;
221
-
#size-cells = <0>;
222
-
compatible = "fsl,mpc8280-usb",
223
-
"fsl,cpm2-usb";
224
-
reg = <0x11b60 0x18 0x8b00 0x100>;
225
-
interrupt-parent = <&PIC>;
226
-
interrupts = <11 8>;
227
-
fsl,cpm-command = <0x2e600000>;
228
-
};
229
-
};
230
-
231
-
PIC: interrupt-controller@10c00 {
232
-
#interrupt-cells = <2>;
233
-
interrupt-controller;
234
-
reg = <0x10c00 0x80>;
235
-
compatible = "fsl,mpc8280-pic", "fsl,cpm2-pic";
236
-
};
237
-
238
-
};
239
-
240
-
chosen {
241
-
stdout-path = "/soc/cpm/serial@11a00";
242
-
};
243
-
};
+1
-1
arch/powerpc/boot/dts/turris1x.dts
+1
-1
arch/powerpc/boot/dts/turris1x.dts
-59
arch/powerpc/configs/83xx/mpc832x_mds_defconfig
-59
arch/powerpc/configs/83xx/mpc832x_mds_defconfig
···
1
-
CONFIG_SYSVIPC=y
2
-
CONFIG_NO_HZ=y
3
-
CONFIG_HIGH_RES_TIMERS=y
4
-
CONFIG_LOG_BUF_SHIFT=14
5
-
CONFIG_BLK_DEV_INITRD=y
6
-
CONFIG_EXPERT=y
7
-
# CONFIG_KALLSYMS is not set
8
-
CONFIG_MODULES=y
9
-
CONFIG_MODULE_UNLOAD=y
10
-
# CONFIG_BLK_DEV_BSG is not set
11
-
CONFIG_PARTITION_ADVANCED=y
12
-
# CONFIG_MSDOS_PARTITION is not set
13
-
# CONFIG_PPC_CHRP is not set
14
-
# CONFIG_PPC_PMAC is not set
15
-
CONFIG_PPC_83xx=y
16
-
CONFIG_MPC832x_MDS=y
17
-
CONFIG_MATH_EMULATION=y
18
-
CONFIG_PCI=y
19
-
CONFIG_NET=y
20
-
CONFIG_PACKET=y
21
-
CONFIG_UNIX=y
22
-
CONFIG_INET=y
23
-
CONFIG_IP_MULTICAST=y
24
-
CONFIG_IP_PNP=y
25
-
CONFIG_IP_PNP_DHCP=y
26
-
CONFIG_IP_PNP_BOOTP=y
27
-
CONFIG_SYN_COOKIES=y
28
-
# CONFIG_IPV6 is not set
29
-
# CONFIG_FW_LOADER is not set
30
-
CONFIG_BLK_DEV_LOOP=y
31
-
CONFIG_BLK_DEV_RAM=y
32
-
CONFIG_BLK_DEV_RAM_SIZE=32768
33
-
CONFIG_SCSI=y
34
-
CONFIG_NETDEVICES=y
35
-
CONFIG_UCC_GETH=y
36
-
CONFIG_DAVICOM_PHY=y
37
-
# CONFIG_INPUT_KEYBOARD is not set
38
-
# CONFIG_INPUT_MOUSE is not set
39
-
# CONFIG_SERIO is not set
40
-
# CONFIG_VT is not set
41
-
CONFIG_SERIAL_8250=y
42
-
CONFIG_SERIAL_8250_CONSOLE=y
43
-
CONFIG_HW_RANDOM=y
44
-
CONFIG_I2C=y
45
-
CONFIG_I2C_CHARDEV=y
46
-
CONFIG_I2C_MPC=y
47
-
CONFIG_WATCHDOG=y
48
-
CONFIG_RTC_CLASS=y
49
-
CONFIG_RTC_DRV_DS1374=y
50
-
CONFIG_QUICC_ENGINE=y
51
-
CONFIG_EXT2_FS=y
52
-
CONFIG_EXT4_FS=y
53
-
CONFIG_PROC_KCORE=y
54
-
CONFIG_TMPFS=y
55
-
CONFIG_NFS_FS=y
56
-
CONFIG_NFS_V4=y
57
-
CONFIG_ROOT_NFS=y
58
-
CONFIG_CRYPTO_ECB=m
59
-
CONFIG_CRYPTO_PCBC=m
-58
arch/powerpc/configs/83xx/mpc834x_mds_defconfig
-58
arch/powerpc/configs/83xx/mpc834x_mds_defconfig
···
1
-
CONFIG_SYSVIPC=y
2
-
CONFIG_NO_HZ=y
3
-
CONFIG_HIGH_RES_TIMERS=y
4
-
CONFIG_LOG_BUF_SHIFT=14
5
-
CONFIG_BLK_DEV_INITRD=y
6
-
CONFIG_EXPERT=y
7
-
# CONFIG_KALLSYMS is not set
8
-
CONFIG_MODULES=y
9
-
CONFIG_MODULE_UNLOAD=y
10
-
# CONFIG_BLK_DEV_BSG is not set
11
-
CONFIG_PARTITION_ADVANCED=y
12
-
# CONFIG_MSDOS_PARTITION is not set
13
-
# CONFIG_PPC_CHRP is not set
14
-
# CONFIG_PPC_PMAC is not set
15
-
CONFIG_PPC_83xx=y
16
-
CONFIG_MPC834x_MDS=y
17
-
CONFIG_PCI=y
18
-
CONFIG_NET=y
19
-
CONFIG_PACKET=y
20
-
CONFIG_UNIX=y
21
-
CONFIG_XFRM_USER=m
22
-
CONFIG_INET=y
23
-
CONFIG_IP_MULTICAST=y
24
-
CONFIG_IP_PNP=y
25
-
CONFIG_IP_PNP_DHCP=y
26
-
CONFIG_IP_PNP_BOOTP=y
27
-
CONFIG_SYN_COOKIES=y
28
-
# CONFIG_IPV6 is not set
29
-
# CONFIG_FW_LOADER is not set
30
-
CONFIG_BLK_DEV_LOOP=y
31
-
CONFIG_BLK_DEV_RAM=y
32
-
CONFIG_BLK_DEV_RAM_SIZE=32768
33
-
CONFIG_NETDEVICES=y
34
-
CONFIG_GIANFAR=y
35
-
CONFIG_E100=y
36
-
CONFIG_MARVELL_PHY=y
37
-
# CONFIG_INPUT_KEYBOARD is not set
38
-
# CONFIG_INPUT_MOUSE is not set
39
-
# CONFIG_SERIO is not set
40
-
# CONFIG_VT is not set
41
-
CONFIG_SERIAL_8250=y
42
-
CONFIG_SERIAL_8250_CONSOLE=y
43
-
# CONFIG_HW_RANDOM is not set
44
-
CONFIG_I2C=y
45
-
CONFIG_I2C_CHARDEV=y
46
-
CONFIG_I2C_MPC=y
47
-
CONFIG_WATCHDOG=y
48
-
CONFIG_RTC_CLASS=y
49
-
CONFIG_RTC_DRV_DS1374=y
50
-
CONFIG_EXT2_FS=y
51
-
CONFIG_EXT4_FS=y
52
-
CONFIG_PROC_KCORE=y
53
-
CONFIG_TMPFS=y
54
-
CONFIG_NFS_FS=y
55
-
CONFIG_NFS_V4=y
56
-
CONFIG_ROOT_NFS=y
57
-
CONFIG_CRYPTO_ECB=m
58
-
CONFIG_CRYPTO_PCBC=m
-64
arch/powerpc/configs/83xx/mpc836x_mds_defconfig
-64
arch/powerpc/configs/83xx/mpc836x_mds_defconfig
···
1
-
CONFIG_SYSVIPC=y
2
-
CONFIG_NO_HZ=y
3
-
CONFIG_HIGH_RES_TIMERS=y
4
-
CONFIG_LOG_BUF_SHIFT=14
5
-
CONFIG_BLK_DEV_INITRD=y
6
-
CONFIG_EXPERT=y
7
-
# CONFIG_KALLSYMS is not set
8
-
CONFIG_MODULES=y
9
-
CONFIG_MODULE_UNLOAD=y
10
-
# CONFIG_BLK_DEV_BSG is not set
11
-
CONFIG_PARTITION_ADVANCED=y
12
-
# CONFIG_MSDOS_PARTITION is not set
13
-
# CONFIG_PPC_CHRP is not set
14
-
# CONFIG_PPC_PMAC is not set
15
-
CONFIG_PPC_83xx=y
16
-
CONFIG_MPC836x_MDS=y
17
-
CONFIG_PCI=y
18
-
CONFIG_NET=y
19
-
CONFIG_PACKET=y
20
-
CONFIG_UNIX=y
21
-
CONFIG_INET=y
22
-
CONFIG_IP_MULTICAST=y
23
-
CONFIG_IP_PNP=y
24
-
CONFIG_IP_PNP_DHCP=y
25
-
CONFIG_IP_PNP_BOOTP=y
26
-
CONFIG_SYN_COOKIES=y
27
-
# CONFIG_IPV6 is not set
28
-
# CONFIG_FW_LOADER is not set
29
-
CONFIG_MTD=y
30
-
CONFIG_MTD_CMDLINE_PARTS=y
31
-
CONFIG_MTD_BLOCK=y
32
-
CONFIG_MTD_CFI=y
33
-
CONFIG_MTD_CFI_AMDSTD=y
34
-
CONFIG_MTD_PHYSMAP_OF=y
35
-
CONFIG_BLK_DEV_LOOP=y
36
-
CONFIG_BLK_DEV_RAM=y
37
-
CONFIG_BLK_DEV_RAM_SIZE=32768
38
-
CONFIG_SCSI=y
39
-
CONFIG_NETDEVICES=y
40
-
CONFIG_UCC_GETH=y
41
-
CONFIG_MARVELL_PHY=y
42
-
# CONFIG_INPUT_KEYBOARD is not set
43
-
# CONFIG_INPUT_MOUSE is not set
44
-
# CONFIG_SERIO is not set
45
-
# CONFIG_VT is not set
46
-
CONFIG_SERIAL_8250=y
47
-
CONFIG_SERIAL_8250_CONSOLE=y
48
-
CONFIG_HW_RANDOM=y
49
-
CONFIG_I2C=y
50
-
CONFIG_I2C_CHARDEV=y
51
-
CONFIG_I2C_MPC=y
52
-
CONFIG_WATCHDOG=y
53
-
CONFIG_RTC_CLASS=y
54
-
CONFIG_RTC_DRV_DS1374=y
55
-
CONFIG_QUICC_ENGINE=y
56
-
CONFIG_EXT2_FS=y
57
-
CONFIG_EXT4_FS=y
58
-
CONFIG_PROC_KCORE=y
59
-
CONFIG_TMPFS=y
60
-
CONFIG_NFS_FS=y
61
-
CONFIG_NFS_V4=y
62
-
CONFIG_ROOT_NFS=y
63
-
CONFIG_CRYPTO_ECB=m
64
-
CONFIG_CRYPTO_PCBC=m
-58
arch/powerpc/configs/83xx/mpc837x_mds_defconfig
-58
arch/powerpc/configs/83xx/mpc837x_mds_defconfig
···
1
-
CONFIG_SYSVIPC=y
2
-
CONFIG_LOG_BUF_SHIFT=14
3
-
CONFIG_BLK_DEV_INITRD=y
4
-
CONFIG_EXPERT=y
5
-
CONFIG_SLAB=y
6
-
CONFIG_MODULES=y
7
-
CONFIG_MODULE_UNLOAD=y
8
-
# CONFIG_BLK_DEV_BSG is not set
9
-
CONFIG_PARTITION_ADVANCED=y
10
-
# CONFIG_PPC_CHRP is not set
11
-
# CONFIG_PPC_PMAC is not set
12
-
CONFIG_PPC_83xx=y
13
-
CONFIG_MPC837x_MDS=y
14
-
CONFIG_GEN_RTC=y
15
-
CONFIG_PCI=y
16
-
CONFIG_NET=y
17
-
CONFIG_PACKET=y
18
-
CONFIG_UNIX=y
19
-
CONFIG_XFRM_USER=m
20
-
CONFIG_INET=y
21
-
CONFIG_IP_MULTICAST=y
22
-
CONFIG_IP_PNP=y
23
-
CONFIG_IP_PNP_DHCP=y
24
-
CONFIG_IP_PNP_BOOTP=y
25
-
CONFIG_SYN_COOKIES=y
26
-
# CONFIG_IPV6 is not set
27
-
# CONFIG_FW_LOADER is not set
28
-
CONFIG_BLK_DEV_LOOP=y
29
-
CONFIG_BLK_DEV_RAM=y
30
-
CONFIG_BLK_DEV_RAM_SIZE=32768
31
-
CONFIG_BLK_DEV_SD=y
32
-
CONFIG_CHR_DEV_SG=y
33
-
CONFIG_ATA=y
34
-
CONFIG_SATA_FSL=y
35
-
CONFIG_NETDEVICES=y
36
-
CONFIG_GIANFAR=y
37
-
CONFIG_MARVELL_PHY=y
38
-
# CONFIG_INPUT_KEYBOARD is not set
39
-
# CONFIG_INPUT_MOUSE is not set
40
-
# CONFIG_SERIO is not set
41
-
# CONFIG_VT is not set
42
-
CONFIG_SERIAL_8250=y
43
-
CONFIG_SERIAL_8250_CONSOLE=y
44
-
# CONFIG_HW_RANDOM is not set
45
-
CONFIG_I2C=y
46
-
CONFIG_I2C_CHARDEV=y
47
-
CONFIG_I2C_MPC=y
48
-
CONFIG_WATCHDOG=y
49
-
CONFIG_EXT2_FS=y
50
-
CONFIG_EXT4_FS=y
51
-
CONFIG_PROC_KCORE=y
52
-
CONFIG_TMPFS=y
53
-
CONFIG_NFS_FS=y
54
-
CONFIG_NFS_V4=y
55
-
CONFIG_ROOT_NFS=y
56
-
CONFIG_CRC_T10DIF=y
57
-
CONFIG_CRYPTO_ECB=m
58
-
CONFIG_CRYPTO_PCBC=m
+1
arch/powerpc/configs/corenet_base.config
+1
arch/powerpc/configs/corenet_base.config
+2
arch/powerpc/configs/guest.config
+2
arch/powerpc/configs/guest.config
-54
arch/powerpc/configs/mpc7448_hpc2_defconfig
-54
arch/powerpc/configs/mpc7448_hpc2_defconfig
···
1
-
CONFIG_ALTIVEC=y
2
-
CONFIG_SYSVIPC=y
3
-
CONFIG_NO_HZ=y
4
-
CONFIG_HIGH_RES_TIMERS=y
5
-
CONFIG_LOG_BUF_SHIFT=14
6
-
CONFIG_BLK_DEV_INITRD=y
7
-
CONFIG_EXPERT=y
8
-
# CONFIG_BLK_DEV_BSG is not set
9
-
CONFIG_PARTITION_ADVANCED=y
10
-
# CONFIG_PPC_CHRP is not set
11
-
# CONFIG_PPC_PMAC is not set
12
-
CONFIG_EMBEDDED6xx=y
13
-
CONFIG_MPC7448HPC2=y
14
-
CONFIG_GEN_RTC=y
15
-
CONFIG_BINFMT_MISC=y
16
-
# CONFIG_SECCOMP is not set
17
-
CONFIG_NET=y
18
-
CONFIG_PACKET=y
19
-
CONFIG_UNIX=y
20
-
CONFIG_XFRM_USER=y
21
-
CONFIG_INET=y
22
-
CONFIG_IP_MULTICAST=y
23
-
CONFIG_IP_PNP=y
24
-
CONFIG_IP_PNP_DHCP=y
25
-
CONFIG_IP_PNP_BOOTP=y
26
-
CONFIG_SYN_COOKIES=y
27
-
# CONFIG_IPV6 is not set
28
-
# CONFIG_FW_LOADER is not set
29
-
CONFIG_BLK_DEV_LOOP=y
30
-
CONFIG_BLK_DEV_RAM=y
31
-
CONFIG_BLK_DEV_RAM_SIZE=131072
32
-
CONFIG_BLK_DEV_SD=y
33
-
CONFIG_ATA=y
34
-
CONFIG_SATA_MV=y
35
-
CONFIG_NETDEVICES=y
36
-
CONFIG_E100=y
37
-
CONFIG_8139TOO=y
38
-
# CONFIG_8139TOO_PIO is not set
39
-
CONFIG_TSI108_ETH=y
40
-
CONFIG_PHYLIB=y
41
-
# CONFIG_INPUT_KEYBOARD is not set
42
-
# CONFIG_INPUT_MOUSE is not set
43
-
# CONFIG_SERIO is not set
44
-
# CONFIG_VT is not set
45
-
CONFIG_SERIAL_8250=y
46
-
CONFIG_SERIAL_8250_CONSOLE=y
47
-
# CONFIG_HW_RANDOM is not set
48
-
CONFIG_EXT2_FS=y
49
-
CONFIG_EXT4_FS=y
50
-
CONFIG_PROC_KCORE=y
51
-
CONFIG_TMPFS=y
52
-
CONFIG_NFS_FS=y
53
-
CONFIG_ROOT_NFS=y
54
-
CONFIG_CRC_T10DIF=y
-79
arch/powerpc/configs/mpc8272_ads_defconfig
-79
arch/powerpc/configs/mpc8272_ads_defconfig
···
1
-
CONFIG_SYSVIPC=y
2
-
CONFIG_NO_HZ=y
3
-
CONFIG_HIGH_RES_TIMERS=y
4
-
CONFIG_IKCONFIG=y
5
-
CONFIG_IKCONFIG_PROC=y
6
-
CONFIG_LOG_BUF_SHIFT=14
7
-
CONFIG_EXPERT=y
8
-
CONFIG_KALLSYMS_ALL=y
9
-
CONFIG_PARTITION_ADVANCED=y
10
-
# CONFIG_PPC_CHRP is not set
11
-
# CONFIG_PPC_PMAC is not set
12
-
CONFIG_PPC_82xx=y
13
-
CONFIG_MPC8272_ADS=y
14
-
CONFIG_BINFMT_MISC=y
15
-
CONFIG_PCI=y
16
-
CONFIG_NET=y
17
-
CONFIG_PACKET=y
18
-
CONFIG_UNIX=y
19
-
CONFIG_INET=y
20
-
CONFIG_IP_MULTICAST=y
21
-
CONFIG_IP_PNP=y
22
-
CONFIG_IP_PNP_DHCP=y
23
-
CONFIG_IP_PNP_BOOTP=y
24
-
CONFIG_SYN_COOKIES=y
25
-
CONFIG_NETFILTER=y
26
-
# CONFIG_FW_LOADER is not set
27
-
CONFIG_MTD=y
28
-
CONFIG_MTD_BLOCK=y
29
-
CONFIG_MTD_JEDECPROBE=y
30
-
CONFIG_MTD_CFI_ADV_OPTIONS=y
31
-
CONFIG_MTD_CFI_GEOMETRY=y
32
-
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
33
-
# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
34
-
# CONFIG_MTD_CFI_I1 is not set
35
-
# CONFIG_MTD_CFI_I2 is not set
36
-
CONFIG_MTD_CFI_I4=y
37
-
CONFIG_MTD_CFI_INTELEXT=y
38
-
CONFIG_MTD_PHYSMAP_OF=y
39
-
CONFIG_BLK_DEV_LOOP=y
40
-
CONFIG_NETDEVICES=y
41
-
CONFIG_TUN=y
42
-
CONFIG_FS_ENET=y
43
-
# CONFIG_FS_ENET_HAS_SCC is not set
44
-
CONFIG_FS_ENET_MDIO_FCC=y
45
-
CONFIG_DAVICOM_PHY=y
46
-
CONFIG_PPP=y
47
-
CONFIG_PPP_DEFLATE=y
48
-
CONFIG_PPP_ASYNC=y
49
-
CONFIG_PPP_SYNC_TTY=y
50
-
CONFIG_INPUT_EVDEV=y
51
-
# CONFIG_VT is not set
52
-
CONFIG_SERIAL_CPM=y
53
-
CONFIG_SERIAL_CPM_CONSOLE=y
54
-
# CONFIG_HWMON is not set
55
-
# CONFIG_USB_SUPPORT is not set
56
-
CONFIG_EXT2_FS=y
57
-
CONFIG_EXT4_FS=y
58
-
CONFIG_AUTOFS4_FS=y
59
-
CONFIG_PROC_KCORE=y
60
-
CONFIG_TMPFS=y
61
-
CONFIG_CRAMFS=y
62
-
CONFIG_NFS_FS=y
63
-
CONFIG_NFS_V3_ACL=y
64
-
CONFIG_ROOT_NFS=y
65
-
CONFIG_NLS=y
66
-
CONFIG_NLS_CODEPAGE_437=y
67
-
CONFIG_NLS_ASCII=y
68
-
CONFIG_NLS_ISO8859_1=y
69
-
CONFIG_NLS_UTF8=y
70
-
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
71
-
CONFIG_MAGIC_SYSRQ=y
72
-
CONFIG_DETECT_HUNG_TASK=y
73
-
CONFIG_BDI_SWITCH=y
74
-
CONFIG_CRYPTO_CBC=y
75
-
CONFIG_CRYPTO_ECB=y
76
-
CONFIG_CRYPTO_PCBC=y
77
-
CONFIG_CRYPTO_MD5=y
78
-
CONFIG_CRYPTO_DES=y
79
-
# CONFIG_CRYPTO_HW is not set
-4
arch/powerpc/configs/mpc83xx_defconfig
-4
arch/powerpc/configs/mpc83xx_defconfig
···
11
11
# CONFIG_PPC_PMAC is not set
12
12
CONFIG_PPC_83xx=y
13
13
CONFIG_MPC831x_RDB=y
14
-
CONFIG_MPC832x_MDS=y
15
14
CONFIG_MPC832x_RDB=y
16
-
CONFIG_MPC834x_MDS=y
17
15
CONFIG_MPC834x_ITX=y
18
-
CONFIG_MPC836x_MDS=y
19
16
CONFIG_MPC836x_RDK=y
20
-
CONFIG_MPC837x_MDS=y
21
17
CONFIG_MPC837x_RDB=y
22
18
CONFIG_ASP834x=y
23
19
CONFIG_QE_GPIO=y
-2
arch/powerpc/configs/mpc86xx_base.config
-2
arch/powerpc/configs/mpc86xx_base.config
+1
arch/powerpc/configs/powernv_defconfig
+1
arch/powerpc/configs/powernv_defconfig
+139
-44
arch/powerpc/configs/ppc64_defconfig
+139
-44
arch/powerpc/configs/ppc64_defconfig
···
1
1
CONFIG_SYSVIPC=y
2
2
CONFIG_POSIX_MQUEUE=y
3
-
# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
3
+
CONFIG_AUDIT=y
4
+
CONFIG_NO_HZ_FULL=y
4
5
CONFIG_NO_HZ=y
5
6
CONFIG_HIGH_RES_TIMERS=y
6
-
CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
7
+
CONFIG_BPF_SYSCALL=y
8
+
CONFIG_BPF_JIT=y
9
+
CONFIG_BPF_LSM=y
10
+
CONFIG_PREEMPT_VOLUNTARY=y
11
+
CONFIG_BSD_PROCESS_ACCT=y
12
+
CONFIG_BSD_PROCESS_ACCT_V3=y
7
13
CONFIG_TASKSTATS=y
8
14
CONFIG_TASK_DELAY_ACCT=y
15
+
CONFIG_TASK_XACCT=y
16
+
CONFIG_TASK_IO_ACCOUNTING=y
17
+
CONFIG_PSI=y
9
18
CONFIG_IKCONFIG=y
10
19
CONFIG_IKCONFIG_PROC=y
11
20
CONFIG_LOG_BUF_SHIFT=18
12
21
CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
13
22
CONFIG_NUMA_BALANCING=y
14
-
CONFIG_CGROUPS=y
15
23
CONFIG_MEMCG=y
16
-
CONFIG_CGROUP_SCHED=y
24
+
CONFIG_BLK_CGROUP=y
25
+
CONFIG_CFS_BANDWIDTH=y
26
+
CONFIG_CGROUP_PIDS=y
17
27
CONFIG_CGROUP_FREEZER=y
28
+
CONFIG_CGROUP_HUGETLB=y
18
29
CONFIG_CPUSETS=y
19
30
CONFIG_CGROUP_DEVICE=y
20
31
CONFIG_CGROUP_CPUACCT=y
21
32
CONFIG_CGROUP_PERF=y
22
33
CONFIG_CGROUP_BPF=y
34
+
CONFIG_CGROUP_MISC=y
35
+
CONFIG_USER_NS=y
36
+
CONFIG_CHECKPOINT_RESTORE=y
37
+
CONFIG_SCHED_AUTOGROUP=y
23
38
CONFIG_BLK_DEV_INITRD=y
24
-
CONFIG_BPF_SYSCALL=y
25
-
# CONFIG_COMPAT_BRK is not set
26
39
CONFIG_PROFILING=y
27
40
CONFIG_PPC64=y
28
41
CONFIG_NR_CPUS=2048
29
-
CONFIG_PPC_SPLPAR=y
30
42
CONFIG_DTL=y
31
43
CONFIG_PPC_SMLPAR=y
32
44
CONFIG_IBMEBUS=y
45
+
CONFIG_PAPR_SCM=m
33
46
CONFIG_PPC_SVM=y
34
47
CONFIG_PPC_MAPLE=y
35
48
CONFIG_PPC_PASEMI=y
···
67
54
CONFIG_FA_DUMP=y
68
55
CONFIG_IRQ_ALL_CPUS=y
69
56
CONFIG_SCHED_SMT=y
70
-
CONFIG_HOTPLUG_PCI=y
71
-
CONFIG_HOTPLUG_PCI_RPA=m
72
-
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
73
-
CONFIG_PCCARD=y
74
-
CONFIG_ELECTRA_CF=y
57
+
CONFIG_PPC_SECURE_BOOT=y
75
58
CONFIG_VIRTUALIZATION=y
76
59
CONFIG_KVM_BOOK3S_64=m
77
60
CONFIG_KVM_BOOK3S_64_HV=m
78
-
CONFIG_VHOST_NET=m
79
61
CONFIG_KPROBES=y
80
62
CONFIG_JUMP_LABEL=y
81
63
CONFIG_MODULES=y
82
64
CONFIG_MODULE_UNLOAD=y
83
65
CONFIG_MODVERSIONS=y
84
66
CONFIG_MODULE_SRCVERSION_ALL=y
67
+
CONFIG_MODULE_SIG_SHA512=y
85
68
CONFIG_PARTITION_ADVANCED=y
86
69
CONFIG_BINFMT_MISC=m
70
+
CONFIG_ZSWAP=y
71
+
CONFIG_Z3FOLD=y
72
+
CONFIG_ZSMALLOC=y
73
+
# CONFIG_SLAB_MERGE_DEFAULT is not set
74
+
CONFIG_SLAB_FREELIST_RANDOM=y
75
+
CONFIG_SLAB_FREELIST_HARDENED=y
76
+
CONFIG_SHUFFLE_PAGE_ALLOCATOR=y
77
+
# CONFIG_COMPAT_BRK is not set
87
78
CONFIG_MEMORY_HOTPLUG=y
88
79
CONFIG_MEMORY_HOTREMOVE=y
89
80
CONFIG_KSM=y
90
81
CONFIG_TRANSPARENT_HUGEPAGE=y
82
+
CONFIG_ZONE_DEVICE=y
91
83
CONFIG_NET=y
92
84
CONFIG_PACKET=y
93
85
CONFIG_UNIX=y
···
108
90
CONFIG_INET_AH=m
109
91
CONFIG_INET_ESP=m
110
92
CONFIG_INET_IPCOMP=m
111
-
CONFIG_IPV6=y
112
93
CONFIG_NETFILTER=y
113
94
# CONFIG_NETFILTER_ADVANCED is not set
114
95
CONFIG_BRIDGE=m
96
+
CONFIG_VLAN_8021Q=m
115
97
CONFIG_NET_SCHED=y
116
98
CONFIG_NET_CLS_BPF=m
117
99
CONFIG_NET_CLS_ACT=y
118
100
CONFIG_NET_ACT_BPF=m
119
-
CONFIG_BPF_JIT=y
101
+
CONFIG_HOTPLUG_PCI=y
102
+
CONFIG_HOTPLUG_PCI_RPA=m
103
+
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
104
+
CONFIG_PCCARD=y
105
+
CONFIG_ELECTRA_CF=y
120
106
CONFIG_DEVTMPFS=y
121
107
CONFIG_DEVTMPFS_MOUNT=y
122
108
CONFIG_BLK_DEV_FD=y
109
+
CONFIG_ZRAM=m
123
110
CONFIG_BLK_DEV_LOOP=y
124
111
CONFIG_BLK_DEV_NBD=m
125
112
CONFIG_BLK_DEV_RAM=y
126
113
CONFIG_BLK_DEV_RAM_SIZE=65536
127
114
CONFIG_VIRTIO_BLK=m
115
+
CONFIG_BLK_DEV_NVME=m
128
116
CONFIG_BLK_DEV_SD=y
129
117
CONFIG_CHR_DEV_ST=m
130
118
CONFIG_BLK_DEV_SR=y
···
167
143
CONFIG_MD_LINEAR=y
168
144
CONFIG_MD_RAID0=y
169
145
CONFIG_MD_RAID1=y
170
-
CONFIG_MD_RAID10=m
171
-
CONFIG_MD_RAID456=m
172
146
CONFIG_MD_MULTIPATH=m
173
147
CONFIG_MD_FAULTY=m
174
148
CONFIG_BLK_DEV_DM=y
149
+
CONFIG_DM_UNSTRIPED=m
175
150
CONFIG_DM_CRYPT=m
176
151
CONFIG_DM_SNAPSHOT=m
152
+
CONFIG_DM_THIN_PROVISIONING=m
153
+
CONFIG_DM_CACHE=m
154
+
CONFIG_DM_WRITECACHE=m
155
+
CONFIG_DM_EBS=m
156
+
CONFIG_DM_ERA=m
157
+
CONFIG_DM_CLONE=m
177
158
CONFIG_DM_MIRROR=m
159
+
CONFIG_DM_LOG_USERSPACE=m
160
+
CONFIG_DM_RAID=m
178
161
CONFIG_DM_ZERO=m
179
162
CONFIG_DM_MULTIPATH=m
180
163
CONFIG_DM_MULTIPATH_QL=m
181
164
CONFIG_DM_MULTIPATH_ST=m
165
+
CONFIG_DM_MULTIPATH_HST=m
166
+
CONFIG_DM_MULTIPATH_IOA=m
167
+
CONFIG_DM_DELAY=m
168
+
CONFIG_DM_DUST=m
169
+
CONFIG_DM_INIT=y
182
170
CONFIG_DM_UEVENT=y
183
171
CONFIG_ADB_PMU=y
184
172
CONFIG_PMAC_SMU=y
···
302
266
CONFIG_INFINIBAND=m
303
267
CONFIG_INFINIBAND_USER_MAD=m
304
268
CONFIG_INFINIBAND_USER_ACCESS=m
305
-
CONFIG_INFINIBAND_MTHCA=m
306
269
CONFIG_INFINIBAND_CXGB4=m
307
270
CONFIG_MLX4_INFINIBAND=m
271
+
CONFIG_INFINIBAND_MTHCA=m
308
272
CONFIG_INFINIBAND_IPOIB=m
309
273
CONFIG_INFINIBAND_IPOIB_CM=y
310
274
CONFIG_INFINIBAND_SRP=m
···
315
279
CONFIG_RTC_DRV_DS1307=y
316
280
CONFIG_VIRTIO_PCI=m
317
281
CONFIG_VIRTIO_BALLOON=m
318
-
CONFIG_LIBNVDIMM=y
282
+
CONFIG_VHOST_NET=m
319
283
CONFIG_RAS=y
320
-
CONFIG_EXT2_FS=y
321
-
CONFIG_EXT2_FS_XATTR=y
322
-
CONFIG_EXT2_FS_POSIX_ACL=y
323
-
CONFIG_EXT2_FS_SECURITY=y
284
+
CONFIG_LIBNVDIMM=y
324
285
CONFIG_EXT4_FS=y
325
286
CONFIG_EXT4_FS_POSIX_ACL=y
326
287
CONFIG_EXT4_FS_SECURITY=y
327
-
CONFIG_REISERFS_FS=m
328
-
CONFIG_REISERFS_FS_XATTR=y
329
-
CONFIG_REISERFS_FS_POSIX_ACL=y
330
-
CONFIG_REISERFS_FS_SECURITY=y
331
-
CONFIG_JFS_FS=m
332
-
CONFIG_JFS_POSIX_ACL=y
333
-
CONFIG_JFS_SECURITY=y
334
288
CONFIG_XFS_FS=y
335
289
CONFIG_XFS_POSIX_ACL=y
336
290
CONFIG_BTRFS_FS=m
···
345
319
CONFIG_SQUASHFS_XATTR=y
346
320
CONFIG_SQUASHFS_LZO=y
347
321
CONFIG_SQUASHFS_XZ=y
322
+
CONFIG_PSTORE=y
348
323
CONFIG_NFS_FS=y
349
324
CONFIG_NFS_V3_ACL=y
350
325
CONFIG_NFS_V4=y
···
361
334
CONFIG_NLS_ASCII=y
362
335
CONFIG_NLS_ISO8859_1=y
363
336
CONFIG_NLS_UTF8=y
337
+
CONFIG_SECURITY=y
338
+
CONFIG_SECURITY_NETWORK=y
339
+
CONFIG_SECURITY_SELINUX=y
340
+
CONFIG_SECURITY_SELINUX_BOOTPARAM=y
341
+
CONFIG_SECURITY_YAMA=y
342
+
CONFIG_SECURITY_LOCKDOWN_LSM=y
343
+
CONFIG_SECURITY_LOCKDOWN_LSM_EARLY=y
344
+
CONFIG_SECURITY_LANDLOCK=y
345
+
CONFIG_INTEGRITY_SIGNATURE=y
346
+
CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y
347
+
CONFIG_INTEGRITY_PLATFORM_KEYRING=y
348
+
CONFIG_IMA=y
349
+
CONFIG_IMA_KEXEC=y
350
+
CONFIG_IMA_DEFAULT_HASH_SHA256=y
351
+
CONFIG_IMA_WRITE_POLICY=y
352
+
CONFIG_IMA_APPRAISE=y
353
+
CONFIG_IMA_ARCH_POLICY=y
354
+
CONFIG_IMA_APPRAISE_MODSIG=y
364
355
CONFIG_CRYPTO_TEST=m
365
-
CONFIG_CRYPTO_PCBC=m
366
-
CONFIG_CRYPTO_HMAC=y
367
-
CONFIG_CRYPTO_CRC32C_VPMSUM=m
368
-
CONFIG_CRYPTO_MD5_PPC=m
369
-
CONFIG_CRYPTO_MICHAEL_MIC=m
370
-
CONFIG_CRYPTO_SHA1_PPC=m
371
-
CONFIG_CRYPTO_SHA256=y
372
-
CONFIG_CRYPTO_WP512=m
373
-
CONFIG_CRYPTO_ANUBIS=m
374
356
CONFIG_CRYPTO_BLOWFISH=m
375
357
CONFIG_CRYPTO_CAST6=m
376
-
CONFIG_CRYPTO_KHAZAD=m
377
358
CONFIG_CRYPTO_SERPENT=m
378
-
CONFIG_CRYPTO_TEA=m
379
359
CONFIG_CRYPTO_TWOFISH=m
360
+
CONFIG_CRYPTO_PCBC=m
361
+
CONFIG_CRYPTO_MICHAEL_MIC=m
362
+
CONFIG_CRYPTO_SHA256=y
363
+
CONFIG_CRYPTO_WP512=m
380
364
CONFIG_CRYPTO_LZO=m
365
+
CONFIG_CRYPTO_CRC32C_VPMSUM=m
366
+
CONFIG_CRYPTO_MD5_PPC=m
367
+
CONFIG_CRYPTO_SHA1_PPC=m
381
368
CONFIG_CRYPTO_DEV_NX=y
382
369
CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
383
370
CONFIG_CRYPTO_DEV_VMX=y
371
+
CONFIG_SYSTEM_TRUSTED_KEYRING=y
372
+
CONFIG_SYSTEM_BLACKLIST_KEYRING=y
384
373
CONFIG_PRINTK_TIME=y
385
374
CONFIG_PRINTK_CALLER=y
386
-
CONFIG_MAGIC_SYSRQ=y
387
375
CONFIG_DEBUG_KERNEL=y
376
+
CONFIG_MAGIC_SYSRQ=y
377
+
CONFIG_PAGE_OWNER=y
378
+
CONFIG_PAGE_POISONING=y
379
+
CONFIG_DEBUG_RODATA_TEST=y
380
+
CONFIG_DEBUG_WX=y
388
381
CONFIG_DEBUG_STACK_USAGE=y
382
+
CONFIG_DEBUG_VM=y
383
+
# CONFIG_DEBUG_VM_PGTABLE is not set
389
384
CONFIG_DEBUG_STACKOVERFLOW=y
390
385
CONFIG_SOFTLOCKUP_DETECTOR=y
391
386
CONFIG_HARDLOCKUP_DETECTOR=y
387
+
CONFIG_SCHEDSTATS=y
392
388
CONFIG_DEBUG_MUTEXES=y
393
389
CONFIG_FUNCTION_TRACER=y
394
-
CONFIG_FTRACE_SYSCALLS=y
395
-
CONFIG_SCHED_TRACER=y
390
+
CONFIG_LOCK_TORTURE_TEST=m
391
+
CONFIG_BUG_ON_DATA_CORRUPTION=y
396
392
CONFIG_STACK_TRACER=y
393
+
CONFIG_SCHED_TRACER=y
394
+
CONFIG_FTRACE_SYSCALLS=y
397
395
CONFIG_BLK_DEV_IO_TRACE=y
396
+
CONFIG_IO_STRICT_DEVMEM=y
397
+
CONFIG_PPC_EMULATED_STATS=y
398
398
CONFIG_CODE_PATCHING_SELFTEST=y
399
399
CONFIG_FTR_FIXUP_SELFTEST=y
400
400
CONFIG_MSI_BITMAP_SELFTEST=y
401
401
CONFIG_XMON=y
402
402
CONFIG_BOOTX_TEXT=y
403
+
CONFIG_KUNIT=m
404
+
CONFIG_KUNIT_ALL_TESTS=m
405
+
CONFIG_LKDTM=m
406
+
CONFIG_TEST_MIN_HEAP=m
407
+
CONFIG_TEST_DIV64=m
408
+
CONFIG_BACKTRACE_SELF_TEST=m
409
+
CONFIG_TEST_REF_TRACKER=m
410
+
CONFIG_RBTREE_TEST=m
411
+
CONFIG_REED_SOLOMON_TEST=m
412
+
CONFIG_INTERVAL_TREE_TEST=m
413
+
CONFIG_PERCPU_TEST=m
414
+
CONFIG_ATOMIC64_SELFTEST=m
415
+
CONFIG_ASYNC_RAID6_TEST=m
416
+
CONFIG_TEST_HEXDUMP=m
417
+
CONFIG_STRING_SELFTEST=m
418
+
CONFIG_TEST_STRING_HELPERS=m
419
+
CONFIG_TEST_KSTRTOX=m
420
+
CONFIG_TEST_PRINTF=m
421
+
CONFIG_TEST_SCANF=m
422
+
CONFIG_TEST_BITMAP=m
423
+
CONFIG_TEST_UUID=m
424
+
CONFIG_TEST_XARRAY=m
425
+
CONFIG_TEST_MAPLE_TREE=m
426
+
CONFIG_TEST_RHASHTABLE=m
427
+
CONFIG_TEST_IDA=m
428
+
CONFIG_TEST_BITOPS=m
429
+
CONFIG_TEST_VMALLOC=m
430
+
CONFIG_TEST_USER_COPY=m
431
+
CONFIG_TEST_BPF=m
432
+
CONFIG_TEST_BLACKHOLE_DEV=m
433
+
CONFIG_FIND_BIT_BENCHMARK=m
434
+
CONFIG_TEST_FIRMWARE=m
435
+
CONFIG_TEST_SYSCTL=m
436
+
CONFIG_LINEAR_RANGES_TEST=m
437
+
CONFIG_TEST_UDELAY=m
438
+
CONFIG_TEST_STATIC_KEYS=m
439
+
CONFIG_TEST_KMOD=m
440
+
CONFIG_TEST_MEMCAT_P=m
441
+
CONFIG_TEST_MEMINIT=m
442
+
CONFIG_TEST_FREE_PAGES=m
443
+
CONFIG_MEMTEST=y
-8
arch/powerpc/configs/ppc6xx_defconfig
-8
arch/powerpc/configs/ppc6xx_defconfig
···
38
38
CONFIG_PPC_EFIKA=y
39
39
CONFIG_PPC_MPC5200_BUGFIX=y
40
40
CONFIG_PPC_82xx=y
41
-
CONFIG_MPC8272_ADS=y
42
-
CONFIG_PQ2FADS=y
43
41
CONFIG_EP8248E=y
44
42
CONFIG_MGCOGE=y
45
43
CONFIG_PPC_83xx=y
46
44
CONFIG_MPC831x_RDB=y
47
-
CONFIG_MPC832x_MDS=y
48
45
CONFIG_MPC832x_RDB=y
49
-
CONFIG_MPC834x_MDS=y
50
46
CONFIG_MPC834x_ITX=y
51
-
CONFIG_MPC836x_MDS=y
52
47
CONFIG_MPC836x_RDK=y
53
-
CONFIG_MPC837x_MDS=y
54
48
CONFIG_MPC837x_RDB=y
55
49
CONFIG_ASP834x=y
56
50
CONFIG_PPC_86xx=y
57
-
CONFIG_MPC8641_HPCN=y
58
-
CONFIG_MPC8610_HPCD=y
59
51
CONFIG_GEF_SBC610=y
60
52
CONFIG_CPU_FREQ=y
61
53
CONFIG_CPU_FREQ_STAT=y
-80
arch/powerpc/configs/pq2fads_defconfig
-80
arch/powerpc/configs/pq2fads_defconfig
···
1
-
CONFIG_SYSVIPC=y
2
-
CONFIG_NO_HZ=y
3
-
CONFIG_HIGH_RES_TIMERS=y
4
-
CONFIG_IKCONFIG=y
5
-
CONFIG_IKCONFIG_PROC=y
6
-
CONFIG_LOG_BUF_SHIFT=14
7
-
CONFIG_BLK_DEV_INITRD=y
8
-
CONFIG_EXPERT=y
9
-
CONFIG_KALLSYMS_ALL=y
10
-
CONFIG_PARTITION_ADVANCED=y
11
-
# CONFIG_PPC_CHRP is not set
12
-
# CONFIG_PPC_PMAC is not set
13
-
CONFIG_PPC_82xx=y
14
-
CONFIG_PQ2FADS=y
15
-
CONFIG_BINFMT_MISC=y
16
-
CONFIG_PCI=y
17
-
CONFIG_NET=y
18
-
CONFIG_PACKET=y
19
-
CONFIG_UNIX=y
20
-
CONFIG_INET=y
21
-
CONFIG_IP_MULTICAST=y
22
-
CONFIG_IP_PNP=y
23
-
CONFIG_IP_PNP_DHCP=y
24
-
CONFIG_IP_PNP_BOOTP=y
25
-
CONFIG_SYN_COOKIES=y
26
-
CONFIG_NETFILTER=y
27
-
# CONFIG_FW_LOADER is not set
28
-
CONFIG_MTD=y
29
-
CONFIG_MTD_BLOCK=y
30
-
CONFIG_MTD_JEDECPROBE=y
31
-
CONFIG_MTD_CFI_ADV_OPTIONS=y
32
-
CONFIG_MTD_CFI_GEOMETRY=y
33
-
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
34
-
# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set
35
-
# CONFIG_MTD_CFI_I1 is not set
36
-
# CONFIG_MTD_CFI_I2 is not set
37
-
CONFIG_MTD_CFI_I4=y
38
-
CONFIG_MTD_CFI_INTELEXT=y
39
-
CONFIG_MTD_PHYSMAP_OF=y
40
-
CONFIG_BLK_DEV_LOOP=y
41
-
CONFIG_NETDEVICES=y
42
-
CONFIG_TUN=y
43
-
CONFIG_FS_ENET=y
44
-
# CONFIG_FS_ENET_HAS_SCC is not set
45
-
CONFIG_FS_ENET_MDIO_FCC=y
46
-
CONFIG_DAVICOM_PHY=y
47
-
CONFIG_PPP=y
48
-
CONFIG_PPP_DEFLATE=y
49
-
CONFIG_PPP_ASYNC=y
50
-
CONFIG_PPP_SYNC_TTY=y
51
-
CONFIG_INPUT_EVDEV=y
52
-
# CONFIG_VT is not set
53
-
CONFIG_SERIAL_CPM=y
54
-
CONFIG_SERIAL_CPM_CONSOLE=y
55
-
# CONFIG_HWMON is not set
56
-
CONFIG_USB_GADGET=y
57
-
CONFIG_USB_ETH=y
58
-
CONFIG_EXT2_FS=y
59
-
CONFIG_EXT4_FS=y
60
-
CONFIG_AUTOFS4_FS=y
61
-
CONFIG_PROC_KCORE=y
62
-
CONFIG_TMPFS=y
63
-
CONFIG_CRAMFS=y
64
-
CONFIG_NFS_FS=y
65
-
CONFIG_NFS_V3_ACL=y
66
-
CONFIG_ROOT_NFS=y
67
-
CONFIG_NLS_CODEPAGE_437=y
68
-
CONFIG_NLS_ASCII=y
69
-
CONFIG_NLS_ISO8859_1=y
70
-
CONFIG_NLS_UTF8=y
71
-
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
72
-
CONFIG_MAGIC_SYSRQ=y
73
-
CONFIG_DETECT_HUNG_TASK=y
74
-
# CONFIG_SCHED_DEBUG is not set
75
-
CONFIG_BDI_SWITCH=y
76
-
CONFIG_CRYPTO_CBC=y
77
-
CONFIG_CRYPTO_ECB=y
78
-
CONFIG_CRYPTO_PCBC=y
79
-
CONFIG_CRYPTO_MD5=y
80
-
CONFIG_CRYPTO_DES=y
-322
arch/powerpc/configs/pseries_defconfig
-322
arch/powerpc/configs/pseries_defconfig
···
1
-
CONFIG_PPC64=y
2
-
CONFIG_NR_CPUS=2048
3
-
CONFIG_SYSVIPC=y
4
-
CONFIG_POSIX_MQUEUE=y
5
-
CONFIG_AUDIT=y
6
-
# CONFIG_CONTEXT_TRACKING_USER_FORCE is not set
7
-
CONFIG_NO_HZ=y
8
-
CONFIG_HIGH_RES_TIMERS=y
9
-
CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
10
-
CONFIG_TASKSTATS=y
11
-
CONFIG_TASK_DELAY_ACCT=y
12
-
CONFIG_TASK_XACCT=y
13
-
CONFIG_TASK_IO_ACCOUNTING=y
14
-
CONFIG_IKCONFIG=y
15
-
CONFIG_IKCONFIG_PROC=y
16
-
CONFIG_LOG_BUF_SHIFT=18
17
-
CONFIG_LOG_CPU_MAX_BUF_SHIFT=13
18
-
CONFIG_NUMA_BALANCING=y
19
-
CONFIG_CGROUPS=y
20
-
CONFIG_MEMCG=y
21
-
CONFIG_CGROUP_SCHED=y
22
-
CONFIG_CGROUP_FREEZER=y
23
-
CONFIG_CPUSETS=y
24
-
CONFIG_CGROUP_DEVICE=y
25
-
CONFIG_CGROUP_CPUACCT=y
26
-
CONFIG_CGROUP_PERF=y
27
-
CONFIG_CGROUP_BPF=y
28
-
CONFIG_USER_NS=y
29
-
CONFIG_BLK_DEV_INITRD=y
30
-
CONFIG_BPF_SYSCALL=y
31
-
# CONFIG_COMPAT_BRK is not set
32
-
CONFIG_PROFILING=y
33
-
CONFIG_KPROBES=y
34
-
CONFIG_JUMP_LABEL=y
35
-
CONFIG_MODULES=y
36
-
CONFIG_MODULE_UNLOAD=y
37
-
CONFIG_MODVERSIONS=y
38
-
CONFIG_MODULE_SRCVERSION_ALL=y
39
-
CONFIG_PARTITION_ADVANCED=y
40
-
CONFIG_PPC_SPLPAR=y
41
-
CONFIG_DTL=y
42
-
CONFIG_PPC_SMLPAR=y
43
-
CONFIG_IBMEBUS=y
44
-
CONFIG_LIBNVDIMM=m
45
-
CONFIG_PAPR_SCM=m
46
-
CONFIG_PPC_SVM=y
47
-
# CONFIG_PPC_PMAC is not set
48
-
CONFIG_RTAS_FLASH=m
49
-
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
50
-
CONFIG_HZ_100=y
51
-
CONFIG_BINFMT_MISC=m
52
-
CONFIG_PPC_TRANSACTIONAL_MEM=y
53
-
CONFIG_KEXEC=y
54
-
CONFIG_KEXEC_FILE=y
55
-
CONFIG_IRQ_ALL_CPUS=y
56
-
CONFIG_MEMORY_HOTPLUG=y
57
-
CONFIG_MEMORY_HOTREMOVE=y
58
-
CONFIG_KSM=y
59
-
CONFIG_TRANSPARENT_HUGEPAGE=y
60
-
CONFIG_SCHED_SMT=y
61
-
CONFIG_HOTPLUG_PCI=y
62
-
CONFIG_HOTPLUG_PCI_RPA=m
63
-
CONFIG_HOTPLUG_PCI_RPA_DLPAR=m
64
-
CONFIG_NET=y
65
-
CONFIG_PACKET=y
66
-
CONFIG_UNIX=y
67
-
CONFIG_XFRM_USER=m
68
-
CONFIG_NET_KEY=m
69
-
CONFIG_INET=y
70
-
CONFIG_IP_MULTICAST=y
71
-
CONFIG_NET_IPIP=y
72
-
CONFIG_SYN_COOKIES=y
73
-
CONFIG_INET_AH=m
74
-
CONFIG_INET_ESP=m
75
-
CONFIG_INET_IPCOMP=m
76
-
# CONFIG_IPV6 is not set
77
-
CONFIG_NETFILTER=y
78
-
# CONFIG_NETFILTER_ADVANCED is not set
79
-
CONFIG_BRIDGE=m
80
-
CONFIG_VLAN_8021Q=m
81
-
CONFIG_NET_SCHED=y
82
-
CONFIG_NET_CLS_BPF=m
83
-
CONFIG_NET_CLS_ACT=y
84
-
CONFIG_NET_ACT_BPF=m
85
-
CONFIG_BPF_JIT=y
86
-
CONFIG_DEVTMPFS=y
87
-
CONFIG_DEVTMPFS_MOUNT=y
88
-
CONFIG_PARPORT=m
89
-
CONFIG_PARPORT_PC=m
90
-
CONFIG_BLK_DEV_FD=m
91
-
CONFIG_BLK_DEV_LOOP=y
92
-
CONFIG_BLK_DEV_NBD=m
93
-
CONFIG_BLK_DEV_RAM=y
94
-
CONFIG_BLK_DEV_RAM_SIZE=65536
95
-
CONFIG_VIRTIO_BLK=m
96
-
CONFIG_BLK_DEV_NVME=y
97
-
CONFIG_BLK_DEV_SD=y
98
-
CONFIG_CHR_DEV_ST=m
99
-
CONFIG_BLK_DEV_SR=y
100
-
CONFIG_CHR_DEV_SG=y
101
-
CONFIG_SCSI_CONSTANTS=y
102
-
CONFIG_SCSI_FC_ATTRS=y
103
-
CONFIG_SCSI_CXGB3_ISCSI=m
104
-
CONFIG_SCSI_CXGB4_ISCSI=m
105
-
CONFIG_SCSI_BNX2_ISCSI=m
106
-
CONFIG_BE2ISCSI=m
107
-
CONFIG_SCSI_MPT2SAS=m
108
-
CONFIG_SCSI_IBMVSCSI=y
109
-
CONFIG_SCSI_IBMVFC=m
110
-
CONFIG_SCSI_SYM53C8XX_2=m
111
-
CONFIG_SCSI_SYM53C8XX_DMA_ADDRESSING_MODE=0
112
-
CONFIG_SCSI_IPR=y
113
-
CONFIG_SCSI_QLA_FC=m
114
-
CONFIG_SCSI_QLA_ISCSI=m
115
-
CONFIG_SCSI_LPFC=m
116
-
CONFIG_SCSI_VIRTIO=m
117
-
CONFIG_SCSI_DH=y
118
-
CONFIG_SCSI_DH_RDAC=m
119
-
CONFIG_SCSI_DH_ALUA=m
120
-
CONFIG_ATA=y
121
-
CONFIG_SATA_AHCI=y
122
-
CONFIG_PATA_AMD=y
123
-
CONFIG_ATA_GENERIC=y
124
-
CONFIG_MD=y
125
-
CONFIG_BLK_DEV_MD=y
126
-
CONFIG_MD_LINEAR=y
127
-
CONFIG_MD_RAID0=y
128
-
CONFIG_MD_RAID1=y
129
-
CONFIG_MD_RAID10=m
130
-
CONFIG_MD_RAID456=m
131
-
CONFIG_MD_MULTIPATH=m
132
-
CONFIG_MD_FAULTY=m
133
-
CONFIG_BLK_DEV_DM=y
134
-
CONFIG_DM_CRYPT=m
135
-
CONFIG_DM_SNAPSHOT=m
136
-
CONFIG_DM_THIN_PROVISIONING=m
137
-
CONFIG_DM_MIRROR=m
138
-
CONFIG_DM_ZERO=m
139
-
CONFIG_DM_MULTIPATH=m
140
-
CONFIG_DM_MULTIPATH_QL=m
141
-
CONFIG_DM_MULTIPATH_ST=m
142
-
CONFIG_DM_UEVENT=y
143
-
CONFIG_BONDING=m
144
-
CONFIG_DUMMY=m
145
-
CONFIG_MACVLAN=m
146
-
CONFIG_MACVTAP=m
147
-
CONFIG_VXLAN=m
148
-
CONFIG_NETCONSOLE=y
149
-
CONFIG_TUN=m
150
-
CONFIG_VETH=m
151
-
CONFIG_VIRTIO_NET=m
152
-
CONFIG_VORTEX=m
153
-
CONFIG_ACENIC=m
154
-
CONFIG_ACENIC_OMIT_TIGON_I=y
155
-
CONFIG_PCNET32=m
156
-
CONFIG_TIGON3=y
157
-
CONFIG_BNX2X=m
158
-
CONFIG_CHELSIO_T1=m
159
-
CONFIG_BE2NET=m
160
-
CONFIG_S2IO=m
161
-
CONFIG_IBMVETH=y
162
-
CONFIG_EHEA=y
163
-
CONFIG_IBMVNIC=y
164
-
CONFIG_E100=y
165
-
CONFIG_E1000=y
166
-
CONFIG_E1000E=y
167
-
CONFIG_IXGBE=m
168
-
CONFIG_I40E=m
169
-
CONFIG_MLX4_EN=m
170
-
CONFIG_MYRI10GE=m
171
-
CONFIG_NETXEN_NIC=m
172
-
CONFIG_PPP=m
173
-
CONFIG_PPP_BSDCOMP=m
174
-
CONFIG_PPP_DEFLATE=m
175
-
CONFIG_PPPOE=m
176
-
CONFIG_PPP_ASYNC=m
177
-
CONFIG_PPP_SYNC_TTY=m
178
-
CONFIG_INPUT_EVDEV=m
179
-
CONFIG_INPUT_MISC=y
180
-
CONFIG_INPUT_PCSPKR=m
181
-
# CONFIG_SERIO_SERPORT is not set
182
-
CONFIG_SERIAL_8250=y
183
-
CONFIG_SERIAL_8250_CONSOLE=y
184
-
CONFIG_SERIAL_ICOM=m
185
-
CONFIG_SERIAL_JSM=m
186
-
CONFIG_HVC_CONSOLE=y
187
-
CONFIG_HVC_RTAS=y
188
-
CONFIG_HVCS=m
189
-
CONFIG_VIRTIO_CONSOLE=m
190
-
CONFIG_IBM_BSR=m
191
-
CONFIG_I2C_CHARDEV=y
192
-
CONFIG_FB=y
193
-
CONFIG_FIRMWARE_EDID=y
194
-
CONFIG_FB_OF=y
195
-
CONFIG_FB_MATROX=y
196
-
CONFIG_FB_MATROX_MILLENIUM=y
197
-
CONFIG_FB_MATROX_MYSTIQUE=y
198
-
CONFIG_FB_MATROX_G=y
199
-
CONFIG_FB_RADEON=y
200
-
CONFIG_FB_IBM_GXT4500=y
201
-
CONFIG_LCD_PLATFORM=m
202
-
# CONFIG_VGA_CONSOLE is not set
203
-
CONFIG_FRAMEBUFFER_CONSOLE=y
204
-
CONFIG_LOGO=y
205
-
CONFIG_HID_GYRATION=y
206
-
CONFIG_HID_PANTHERLORD=y
207
-
CONFIG_HID_PETALYNX=y
208
-
CONFIG_HID_SAMSUNG=y
209
-
CONFIG_HID_SUNPLUS=y
210
-
CONFIG_USB_HIDDEV=y
211
-
CONFIG_USB=y
212
-
CONFIG_USB_MON=m
213
-
CONFIG_USB_EHCI_HCD=y
214
-
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
215
-
CONFIG_USB_OHCI_HCD=y
216
-
CONFIG_USB_XHCI_HCD=y
217
-
CONFIG_USB_STORAGE=m
218
-
CONFIG_NEW_LEDS=y
219
-
CONFIG_LEDS_CLASS=m
220
-
CONFIG_LEDS_POWERNV=m
221
-
CONFIG_INFINIBAND=m
222
-
CONFIG_INFINIBAND_USER_MAD=m
223
-
CONFIG_INFINIBAND_USER_ACCESS=m
224
-
CONFIG_INFINIBAND_MTHCA=m
225
-
CONFIG_INFINIBAND_CXGB4=m
226
-
CONFIG_MLX4_INFINIBAND=m
227
-
CONFIG_INFINIBAND_IPOIB=m
228
-
CONFIG_INFINIBAND_IPOIB_CM=y
229
-
CONFIG_INFINIBAND_SRP=m
230
-
CONFIG_INFINIBAND_ISER=m
231
-
CONFIG_RTC_CLASS=y
232
-
CONFIG_RTC_DRV_GENERIC=y
233
-
CONFIG_VIRTIO_PCI=m
234
-
CONFIG_VIRTIO_BALLOON=m
235
-
CONFIG_EXT2_FS=y
236
-
CONFIG_EXT2_FS_XATTR=y
237
-
CONFIG_EXT2_FS_POSIX_ACL=y
238
-
CONFIG_EXT2_FS_SECURITY=y
239
-
CONFIG_EXT4_FS=y
240
-
CONFIG_EXT4_FS_POSIX_ACL=y
241
-
CONFIG_EXT4_FS_SECURITY=y
242
-
CONFIG_JFS_FS=m
243
-
CONFIG_JFS_POSIX_ACL=y
244
-
CONFIG_JFS_SECURITY=y
245
-
CONFIG_XFS_FS=m
246
-
CONFIG_XFS_POSIX_ACL=y
247
-
CONFIG_BTRFS_FS=m
248
-
CONFIG_BTRFS_FS_POSIX_ACL=y
249
-
CONFIG_NILFS2_FS=m
250
-
CONFIG_FS_DAX=y
251
-
CONFIG_AUTOFS4_FS=m
252
-
CONFIG_FUSE_FS=m
253
-
CONFIG_OVERLAY_FS=m
254
-
CONFIG_ISO9660_FS=y
255
-
CONFIG_UDF_FS=m
256
-
CONFIG_MSDOS_FS=y
257
-
CONFIG_VFAT_FS=m
258
-
CONFIG_PROC_KCORE=y
259
-
CONFIG_TMPFS=y
260
-
CONFIG_TMPFS_POSIX_ACL=y
261
-
CONFIG_HUGETLBFS=y
262
-
CONFIG_CRAMFS=m
263
-
CONFIG_SQUASHFS=m
264
-
CONFIG_SQUASHFS_XATTR=y
265
-
CONFIG_SQUASHFS_LZO=y
266
-
CONFIG_SQUASHFS_XZ=y
267
-
CONFIG_PSTORE=y
268
-
CONFIG_NFS_FS=y
269
-
CONFIG_NFS_V3_ACL=y
270
-
CONFIG_NFS_V4=y
271
-
CONFIG_NFSD=m
272
-
CONFIG_NFSD_V3_ACL=y
273
-
CONFIG_NFSD_V4=y
274
-
CONFIG_CIFS=m
275
-
CONFIG_CIFS_XATTR=y
276
-
CONFIG_CIFS_POSIX=y
277
-
CONFIG_NLS_DEFAULT="utf8"
278
-
CONFIG_NLS_CODEPAGE_437=y
279
-
CONFIG_NLS_ASCII=y
280
-
CONFIG_NLS_ISO8859_1=y
281
-
CONFIG_NLS_UTF8=y
282
-
CONFIG_MAGIC_SYSRQ=y
283
-
CONFIG_DEBUG_KERNEL=y
284
-
CONFIG_DEBUG_STACK_USAGE=y
285
-
CONFIG_DEBUG_STACKOVERFLOW=y
286
-
CONFIG_SOFTLOCKUP_DETECTOR=y
287
-
CONFIG_HARDLOCKUP_DETECTOR=y
288
-
CONFIG_FUNCTION_TRACER=y
289
-
CONFIG_FTRACE_SYSCALLS=y
290
-
CONFIG_SCHED_TRACER=y
291
-
CONFIG_STACK_TRACER=y
292
-
CONFIG_BLK_DEV_IO_TRACE=y
293
-
CONFIG_CODE_PATCHING_SELFTEST=y
294
-
CONFIG_FTR_FIXUP_SELFTEST=y
295
-
CONFIG_MSI_BITMAP_SELFTEST=y
296
-
CONFIG_XMON=y
297
-
CONFIG_CRYPTO_TEST=m
298
-
CONFIG_CRYPTO_PCBC=m
299
-
CONFIG_CRYPTO_HMAC=y
300
-
CONFIG_CRYPTO_CRC32C_VPMSUM=m
301
-
CONFIG_CRYPTO_MD5_PPC=m
302
-
CONFIG_CRYPTO_MICHAEL_MIC=m
303
-
CONFIG_CRYPTO_SHA1_PPC=m
304
-
CONFIG_CRYPTO_SHA256=y
305
-
CONFIG_CRYPTO_WP512=m
306
-
CONFIG_CRYPTO_ANUBIS=m
307
-
CONFIG_CRYPTO_BLOWFISH=m
308
-
CONFIG_CRYPTO_CAST6=m
309
-
CONFIG_CRYPTO_KHAZAD=m
310
-
CONFIG_CRYPTO_SERPENT=m
311
-
CONFIG_CRYPTO_TEA=m
312
-
CONFIG_CRYPTO_TWOFISH=m
313
-
CONFIG_CRYPTO_LZO=m
314
-
CONFIG_CRYPTO_DEV_NX=y
315
-
CONFIG_CRYPTO_DEV_NX_ENCRYPT=m
316
-
CONFIG_CRYPTO_DEV_VMX=y
317
-
CONFIG_VIRTUALIZATION=y
318
-
CONFIG_KVM_BOOK3S_64=m
319
-
CONFIG_KVM_BOOK3S_64_HV=m
320
-
CONFIG_VHOST_NET=m
321
-
CONFIG_PRINTK_TIME=y
322
-
CONFIG_PRINTK_CALLER=y
+20
-33
arch/powerpc/include/asm/atomic.h
+20
-33
arch/powerpc/include/asm/atomic.h
···
27
27
{
28
28
int t;
29
29
30
-
__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
30
+
/* -mprefixed can generate offsets beyond range, fall back hack */
31
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
32
+
__asm__ __volatile__("lwz %0,0(%1)" : "=r"(t) : "b"(&v->counter));
33
+
else
34
+
__asm__ __volatile__("lwz%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
31
35
32
36
return t;
33
37
}
34
38
35
39
static __inline__ void arch_atomic_set(atomic_t *v, int i)
36
40
{
37
-
__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
41
+
/* -mprefixed can generate offsets beyond range, fall back hack */
42
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
43
+
__asm__ __volatile__("stw %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter));
44
+
else
45
+
__asm__ __volatile__("stw%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
38
46
}
39
47
40
48
#define ATOMIC_OP(op, asm_op, suffix, sign, ...) \
···
138
130
#define arch_atomic_xchg_relaxed(v, new) \
139
131
arch_xchg_relaxed(&((v)->counter), (new))
140
132
141
-
/*
142
-
* Don't want to override the generic atomic_try_cmpxchg_acquire, because
143
-
* we add a lock hint to the lwarx, which may not be wanted for the
144
-
* _acquire case (and is not used by the other _acquire variants so it
145
-
* would be a surprise).
146
-
*/
147
-
static __always_inline bool
148
-
arch_atomic_try_cmpxchg_lock(atomic_t *v, int *old, int new)
149
-
{
150
-
int r, o = *old;
151
-
unsigned int eh = IS_ENABLED(CONFIG_PPC64);
152
-
153
-
__asm__ __volatile__ (
154
-
"1: lwarx %0,0,%2,%[eh] # atomic_try_cmpxchg_acquire \n"
155
-
" cmpw 0,%0,%3 \n"
156
-
" bne- 2f \n"
157
-
" stwcx. %4,0,%2 \n"
158
-
" bne- 1b \n"
159
-
"\t" PPC_ACQUIRE_BARRIER " \n"
160
-
"2: \n"
161
-
: "=&r" (r), "+m" (v->counter)
162
-
: "r" (&v->counter), "r" (o), "r" (new), [eh] "n" (eh)
163
-
: "cr0", "memory");
164
-
165
-
if (unlikely(r != o))
166
-
*old = r;
167
-
return likely(r == o);
168
-
}
169
-
170
133
/**
171
134
* atomic_fetch_add_unless - add unless the number is a given value
172
135
* @v: pointer of type atomic_t
···
205
226
{
206
227
s64 t;
207
228
208
-
__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
229
+
/* -mprefixed can generate offsets beyond range, fall back hack */
230
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
231
+
__asm__ __volatile__("ld %0,0(%1)" : "=r"(t) : "b"(&v->counter));
232
+
else
233
+
__asm__ __volatile__("ld%U1%X1 %0,%1" : "=r"(t) : "m<>"(v->counter));
209
234
210
235
return t;
211
236
}
212
237
213
238
static __inline__ void arch_atomic64_set(atomic64_t *v, s64 i)
214
239
{
215
-
__asm__ __volatile__("std%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
240
+
/* -mprefixed can generate offsets beyond range, fall back hack */
241
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PREFIXED))
242
+
__asm__ __volatile__("std %1,0(%2)" : "=m"(v->counter) : "r"(i), "b"(&v->counter));
243
+
else
244
+
__asm__ __volatile__("std%U0%X0 %1,%0" : "=m<>"(v->counter) : "r"(i));
216
245
}
217
246
218
247
#define ATOMIC64_OP(op, asm_op) \
+3
-1
arch/powerpc/include/asm/firmware.h
+3
-1
arch/powerpc/include/asm/firmware.h
···
56
56
#define FW_FEATURE_FORM2_AFFINITY ASM_CONST(0x0000020000000000)
57
57
#define FW_FEATURE_ENERGY_SCALE_INFO ASM_CONST(0x0000040000000000)
58
58
#define FW_FEATURE_WATCHDOG ASM_CONST(0x0000080000000000)
59
+
#define FW_FEATURE_PLPKS ASM_CONST(0x0000100000000000)
59
60
60
61
#ifndef __ASSEMBLY__
61
62
···
78
77
FW_FEATURE_DRC_INFO | FW_FEATURE_BLOCK_REMOVE |
79
78
FW_FEATURE_PAPR_SCM | FW_FEATURE_ULTRAVISOR |
80
79
FW_FEATURE_RPT_INVALIDATE | FW_FEATURE_FORM2_AFFINITY |
81
-
FW_FEATURE_ENERGY_SCALE_INFO | FW_FEATURE_WATCHDOG,
80
+
FW_FEATURE_ENERGY_SCALE_INFO | FW_FEATURE_WATCHDOG |
81
+
FW_FEATURE_PLPKS,
82
82
FW_FEATURE_PSERIES_ALWAYS = 0,
83
83
FW_FEATURE_POWERNV_POSSIBLE = FW_FEATURE_OPAL | FW_FEATURE_ULTRAVISOR,
84
84
FW_FEATURE_POWERNV_ALWAYS = 0,
+6
-6
arch/powerpc/include/asm/idle.h
+6
-6
arch/powerpc/include/asm/idle.h
···
9
9
DECLARE_PER_CPU(u64, idle_entry_purr_snap);
10
10
DECLARE_PER_CPU(u64, idle_entry_spurr_snap);
11
11
12
-
static inline void snapshot_purr_idle_entry(void)
12
+
static __always_inline void snapshot_purr_idle_entry(void)
13
13
{
14
14
*this_cpu_ptr(&idle_entry_purr_snap) = mfspr(SPRN_PURR);
15
15
}
16
16
17
-
static inline void snapshot_spurr_idle_entry(void)
17
+
static __always_inline void snapshot_spurr_idle_entry(void)
18
18
{
19
19
*this_cpu_ptr(&idle_entry_spurr_snap) = mfspr(SPRN_SPURR);
20
20
}
21
21
22
-
static inline void update_idle_purr_accounting(void)
22
+
static __always_inline void update_idle_purr_accounting(void)
23
23
{
24
24
u64 wait_cycles;
25
25
u64 in_purr = *this_cpu_ptr(&idle_entry_purr_snap);
···
29
29
get_lppaca()->wait_state_cycles = cpu_to_be64(wait_cycles);
30
30
}
31
31
32
-
static inline void update_idle_spurr_accounting(void)
32
+
static __always_inline void update_idle_spurr_accounting(void)
33
33
{
34
34
u64 *idle_spurr_cycles_ptr = this_cpu_ptr(&idle_spurr_cycles);
35
35
u64 in_spurr = *this_cpu_ptr(&idle_entry_spurr_snap);
···
37
37
*idle_spurr_cycles_ptr += mfspr(SPRN_SPURR) - in_spurr;
38
38
}
39
39
40
-
static inline void pseries_idle_prolog(void)
40
+
static __always_inline void pseries_idle_prolog(void)
41
41
{
42
42
ppc64_runlatch_off();
43
43
snapshot_purr_idle_entry();
···
49
49
get_lppaca()->idle = 1;
50
50
}
51
51
52
-
static inline void pseries_idle_epilog(void)
52
+
static __always_inline void pseries_idle_epilog(void)
53
53
{
54
54
update_idle_purr_accounting();
55
55
update_idle_spurr_accounting();
+37
arch/powerpc/include/asm/io.h
+37
arch/powerpc/include/asm/io.h
···
97
97
*
98
98
*/
99
99
100
+
/* -mprefixed can generate offsets beyond range, fall back hack */
101
+
#ifdef CONFIG_PPC_KERNEL_PREFIXED
102
+
#define DEF_MMIO_IN_X(name, size, insn) \
103
+
static inline u##size name(const volatile u##size __iomem *addr) \
104
+
{ \
105
+
u##size ret; \
106
+
__asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
107
+
: "=r" (ret) : "r" (addr) : "memory"); \
108
+
return ret; \
109
+
}
110
+
111
+
#define DEF_MMIO_OUT_X(name, size, insn) \
112
+
static inline void name(volatile u##size __iomem *addr, u##size val) \
113
+
{ \
114
+
__asm__ __volatile__("sync;"#insn" %1,0,%0" \
115
+
: : "r" (addr), "r" (val) : "memory"); \
116
+
mmiowb_set_pending(); \
117
+
}
118
+
119
+
#define DEF_MMIO_IN_D(name, size, insn) \
120
+
static inline u##size name(const volatile u##size __iomem *addr) \
121
+
{ \
122
+
u##size ret; \
123
+
__asm__ __volatile__("sync;"#insn" %0,0(%1);twi 0,%0,0;isync"\
124
+
: "=r" (ret) : "b" (addr) : "memory"); \
125
+
return ret; \
126
+
}
127
+
128
+
#define DEF_MMIO_OUT_D(name, size, insn) \
129
+
static inline void name(volatile u##size __iomem *addr, u##size val) \
130
+
{ \
131
+
__asm__ __volatile__("sync;"#insn" %1,0(%0)" \
132
+
: : "b" (addr), "r" (val) : "memory"); \
133
+
mmiowb_set_pending(); \
134
+
}
135
+
#else
100
136
#define DEF_MMIO_IN_X(name, size, insn) \
101
137
static inline u##size name(const volatile u##size __iomem *addr) \
102
138
{ \
···
166
130
: "=m<>" (*addr) : "r" (val) : "memory"); \
167
131
mmiowb_set_pending(); \
168
132
}
133
+
#endif
169
134
170
135
DEF_MMIO_IN_D(in_8, 8, lbz);
171
136
DEF_MMIO_OUT_D(out_8, 8, stb);
+3
-3
arch/powerpc/include/asm/iommu.h
+3
-3
arch/powerpc/include/asm/iommu.h
···
175
175
long (*unset_window)(struct iommu_table_group *table_group,
176
176
int num);
177
177
/* Switch ownership from platform code to external user (e.g. VFIO) */
178
-
void (*take_ownership)(struct iommu_table_group *table_group);
178
+
long (*take_ownership)(struct iommu_table_group *table_group);
179
179
/* Switch ownership from external user (e.g. VFIO) back to core */
180
180
void (*release_ownership)(struct iommu_table_group *table_group);
181
181
};
···
215
215
enum dma_data_direction *direction);
216
216
extern void iommu_tce_kill(struct iommu_table *tbl,
217
217
unsigned long entry, unsigned long pages);
218
+
219
+
extern struct iommu_table_group_ops spapr_tce_table_group_ops;
218
220
#else
219
221
static inline void iommu_register_group(struct iommu_table_group *table_group,
220
222
int pci_domain_number,
···
305
303
iommu_tce_check_gpa((tbl)->it_page_shift, (gpa)))
306
304
307
305
extern void iommu_flush_tce(struct iommu_table *tbl);
308
-
extern int iommu_take_ownership(struct iommu_table *tbl);
309
-
extern void iommu_release_ownership(struct iommu_table *tbl);
310
306
311
307
extern enum dma_data_direction iommu_tce_direction(unsigned long tce);
312
308
extern unsigned long iommu_direction_to_tce_perm(enum dma_data_direction dir);
+2
-2
arch/powerpc/include/asm/kvm_host.h
+2
-2
arch/powerpc/include/asm/kvm_host.h
···
758
758
u8 prodded;
759
759
u8 doorbell_request;
760
760
u8 irq_pending; /* Used by XIVE to signal pending guest irqs */
761
-
u32 last_inst;
761
+
unsigned long last_inst;
762
762
763
763
struct rcuwait wait;
764
764
struct rcuwait *waitp;
···
818
818
u64 busy_stolen;
819
819
u64 busy_preempt;
820
820
821
-
u32 emul_inst;
821
+
u64 emul_inst;
822
822
823
823
u32 online;
824
824
+45
-19
arch/powerpc/include/asm/kvm_ppc.h
+45
-19
arch/powerpc/include/asm/kvm_ppc.h
···
28
28
#include <asm/xive.h>
29
29
#include <asm/cpu_has_feature.h>
30
30
#endif
31
+
#include <asm/inst.h>
31
32
32
33
/*
33
34
* KVMPPC_INST_SW_BREAKPOINT is debug Instruction
···
85
84
int is_default_endian);
86
85
87
86
extern int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
88
-
enum instruction_fetch_type type, u32 *inst);
87
+
enum instruction_fetch_type type,
88
+
unsigned long *inst);
89
89
90
90
extern int kvmppc_ld(struct kvm_vcpu *vcpu, ulong *eaddr, int size, void *ptr,
91
91
bool data);
···
128
126
129
127
extern int kvmppc_core_prepare_to_enter(struct kvm_vcpu *vcpu);
130
128
extern int kvmppc_core_pending_dec(struct kvm_vcpu *vcpu);
131
-
extern void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu, ulong flags);
129
+
130
+
extern void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu,
131
+
ulong srr1_flags);
132
132
extern void kvmppc_core_queue_syscall(struct kvm_vcpu *vcpu);
133
-
extern void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags);
134
-
extern void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu);
135
-
extern void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu);
136
-
extern void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu);
133
+
extern void kvmppc_core_queue_program(struct kvm_vcpu *vcpu,
134
+
ulong srr1_flags);
135
+
extern void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu,
136
+
ulong srr1_flags);
137
+
extern void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu,
138
+
ulong srr1_flags);
139
+
extern void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu,
140
+
ulong srr1_flags);
137
141
extern void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu);
138
142
extern void kvmppc_core_dequeue_dec(struct kvm_vcpu *vcpu);
139
143
extern void kvmppc_core_queue_external(struct kvm_vcpu *vcpu,
140
144
struct kvm_interrupt *irq);
141
145
extern void kvmppc_core_dequeue_external(struct kvm_vcpu *vcpu);
142
-
extern void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu, ulong dear_flags,
146
+
extern void kvmppc_core_queue_dtlb_miss(struct kvm_vcpu *vcpu,
147
+
ulong dear_flags,
143
148
ulong esr_flags);
144
149
extern void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
145
-
ulong dear_flags,
146
-
ulong esr_flags);
150
+
ulong srr1_flags,
151
+
ulong dar,
152
+
ulong dsisr);
147
153
extern void kvmppc_core_queue_itlb_miss(struct kvm_vcpu *vcpu);
148
154
extern void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu,
149
-
ulong esr_flags);
155
+
ulong srr1_flags);
156
+
150
157
extern void kvmppc_core_flush_tlb(struct kvm_vcpu *vcpu);
151
158
extern int kvmppc_core_check_requests(struct kvm_vcpu *vcpu);
152
159
···
326
315
extern struct kvmppc_ops *kvmppc_pr_ops;
327
316
328
317
static inline int kvmppc_get_last_inst(struct kvm_vcpu *vcpu,
329
-
enum instruction_fetch_type type, u32 *inst)
318
+
enum instruction_fetch_type type, ppc_inst_t *inst)
330
319
{
331
320
int ret = EMULATE_DONE;
332
321
u32 fetched_inst;
···
337
326
ret = kvmppc_load_last_inst(vcpu, type, &vcpu->arch.last_inst);
338
327
339
328
/* Write fetch_failed unswapped if the fetch failed */
340
-
if (ret == EMULATE_DONE)
341
-
fetched_inst = kvmppc_need_byteswap(vcpu) ?
342
-
swab32(vcpu->arch.last_inst) :
343
-
vcpu->arch.last_inst;
344
-
else
345
-
fetched_inst = vcpu->arch.last_inst;
329
+
if (ret != EMULATE_DONE) {
330
+
*inst = ppc_inst(KVM_INST_FETCH_FAILED);
331
+
return ret;
332
+
}
346
333
347
-
*inst = fetched_inst;
348
-
return ret;
334
+
#ifdef CONFIG_PPC64
335
+
/* Is this a prefixed instruction? */
336
+
if ((vcpu->arch.last_inst >> 32) != 0) {
337
+
u32 prefix = vcpu->arch.last_inst >> 32;
338
+
u32 suffix = vcpu->arch.last_inst;
339
+
if (kvmppc_need_byteswap(vcpu)) {
340
+
prefix = swab32(prefix);
341
+
suffix = swab32(suffix);
342
+
}
343
+
*inst = ppc_inst_prefix(prefix, suffix);
344
+
return EMULATE_DONE;
345
+
}
346
+
#endif
347
+
348
+
fetched_inst = kvmppc_need_byteswap(vcpu) ?
349
+
swab32(vcpu->arch.last_inst) :
350
+
vcpu->arch.last_inst;
351
+
*inst = ppc_inst(fetched_inst);
352
+
return EMULATE_DONE;
349
353
}
350
354
351
355
static inline bool is_kvmppc_hv_enabled(struct kvm *kvm)
+2
-1
arch/powerpc/include/asm/machdep.h
+2
-1
arch/powerpc/include/asm/machdep.h
+9
-1
arch/powerpc/include/asm/module.h
+9
-1
arch/powerpc/include/asm/module.h
···
27
27
struct mod_arch_specific {
28
28
#ifdef __powerpc64__
29
29
unsigned int stubs_section; /* Index of stubs section in module */
30
+
#ifdef CONFIG_PPC_KERNEL_PCREL
31
+
unsigned int got_section; /* What section is the GOT? */
32
+
unsigned int pcpu_section; /* .data..percpu section */
33
+
#else
30
34
unsigned int toc_section; /* What section is the TOC? */
31
35
bool toc_fixed; /* Have we fixed up .TOC.? */
36
+
#endif
32
37
33
38
/* For module function descriptor dereference */
34
39
unsigned long start_opd;
···
57
52
58
53
/*
59
54
* Select ELF headers.
60
-
* Make empty section for module_frob_arch_sections to expand.
55
+
* Make empty sections for module_frob_arch_sections to expand.
61
56
*/
62
57
63
58
#ifdef __powerpc64__
64
59
# ifdef MODULE
65
60
asm(".section .stubs,\"ax\",@nobits; .align 3; .previous");
61
+
# ifdef CONFIG_PPC_KERNEL_PCREL
62
+
asm(".section .mygot,\"a\",@nobits; .align 3; .previous");
63
+
# endif
66
64
# endif
67
65
#else
68
66
# ifdef MODULE
-4
arch/powerpc/include/asm/mpc8260.h
-4
arch/powerpc/include/asm/mpc8260.h
+2
arch/powerpc/include/asm/paca.h
+2
arch/powerpc/include/asm/paca.h
···
88
88
u16 lock_token; /* Constant 0x8000, used in locks */
89
89
#endif
90
90
91
+
#ifndef CONFIG_PPC_KERNEL_PCREL
91
92
u64 kernel_toc; /* Kernel TOC address */
93
+
#endif
92
94
u64 kernelbase; /* Base address of kernel */
93
95
u64 kernel_msr; /* MSR while running in kernel */
94
96
void *emergency_sp; /* pointer to emergency stack */
+7
arch/powerpc/include/asm/pci-bridge.h
+7
arch/powerpc/include/asm/pci-bridge.h
···
8
8
#include <linux/list.h>
9
9
#include <linux/ioport.h>
10
10
#include <linux/numa.h>
11
+
#include <linux/iommu.h>
11
12
12
13
struct device_node;
13
14
···
45
44
#endif
46
45
47
46
void (*shutdown)(struct pci_controller *hose);
47
+
48
+
struct iommu_group *(*device_group)(struct pci_controller *hose,
49
+
struct pci_dev *pdev);
48
50
};
49
51
50
52
/*
···
135
131
struct irq_domain *dev_domain;
136
132
struct irq_domain *msi_domain;
137
133
struct fwnode_handle *fwnode;
134
+
135
+
/* iommu_ops support */
136
+
struct iommu_device iommu;
138
137
};
139
138
140
139
/* These are used for config access before all the PCI probing
+8
arch/powerpc/include/asm/ppc-opcode.h
+8
arch/powerpc/include/asm/ppc-opcode.h
···
120
120
* 16-bit immediate helper macros: HA() is for use with sign-extending instrs
121
121
* (e.g. LD, ADDI). If the bottom 16 bits is "-ve", add another bit into the
122
122
* top half to negate the effect (i.e. 0xffff + 1 = 0x(1)0000).
123
+
*
124
+
* XXX: should these mask out possible sign bits?
123
125
*/
124
126
#define IMM_H(i) ((uintptr_t)(i)>>16)
125
127
#define IMM_HA(i) (((uintptr_t)(i)>>16) + \
126
128
(((uintptr_t)(i) & 0x8000) >> 15))
129
+
130
+
/*
131
+
* 18-bit immediate helper for prefix 18-bit upper immediate si0 field.
132
+
*/
133
+
#define IMM_H18(i) (((uintptr_t)(i)>>16) & 0x3ffff)
127
134
128
135
129
136
/* opcode and xopcode for instructions */
···
313
306
#define PPC_PREFIX_8LS 0x04000000
314
307
315
308
/* Prefixed instructions */
309
+
#define PPC_INST_PADDI 0x38000000
316
310
#define PPC_INST_PLD 0xe4000000
317
311
#define PPC_INST_PSTD 0xf4000000
318
312
+8
arch/powerpc/include/asm/ppc-pci.h
+8
arch/powerpc/include/asm/ppc-pci.h
···
57
57
58
58
#endif /* CONFIG_EEH */
59
59
60
+
#ifdef CONFIG_FSL_ULI1575
61
+
void __init uli_init(void);
62
+
#endif /* CONFIG_FSL_ULI1575 */
63
+
60
64
#define PCI_BUSNO(bdfn) ((bdfn >> 8) & 0xff)
61
65
62
66
#else /* CONFIG_PCI */
63
67
static inline void init_pci_config_tokens(void) { }
64
68
#endif /* !CONFIG_PCI */
69
+
70
+
#if !defined(CONFIG_PCI) || !defined(CONFIG_FSL_ULI1575)
71
+
static inline void __init uli_init(void) {}
72
+
#endif /* !defined(CONFIG_PCI) || !defined(CONFIG_FSL_ULI1575) */
65
73
66
74
#endif /* __KERNEL__ */
67
75
#endif /* _ASM_POWERPC_PPC_PCI_H */
+32
arch/powerpc/include/asm/ppc_asm.h
+32
arch/powerpc/include/asm/ppc_asm.h
···
181
181
#ifdef __KERNEL__
182
182
183
183
/*
184
+
* Used to name C functions called from asm
185
+
*/
186
+
#ifdef CONFIG_PPC_KERNEL_PCREL
187
+
#define CFUNC(name) name@notoc
188
+
#else
189
+
#define CFUNC(name) name
190
+
#endif
191
+
192
+
/*
184
193
* We use __powerpc64__ here because we want the compat VDSO to use the 32-bit
185
194
* version below in the else case of the ifdef.
186
195
*/
···
216
207
.globl name; \
217
208
name:
218
209
210
+
#ifdef CONFIG_PPC_KERNEL_PCREL
211
+
#define _GLOBAL_TOC _GLOBAL
212
+
#else
219
213
#define _GLOBAL_TOC(name) \
220
214
.align 2 ; \
221
215
.type name,@function; \
···
227
215
0: addis r2,r12,(.TOC.-0b)@ha; \
228
216
addi r2,r2,(.TOC.-0b)@l; \
229
217
.localentry name,.-name
218
+
#endif
230
219
231
220
#define DOTSYM(a) a
232
221
···
359
346
360
347
#ifdef __powerpc64__
361
348
349
+
#ifdef CONFIG_PPC_KERNEL_PCREL
350
+
#define __LOAD_PACA_TOC(reg) \
351
+
li reg,-1
352
+
#else
362
353
#define __LOAD_PACA_TOC(reg) \
363
354
ld reg,PACATOC(r13)
355
+
#endif
364
356
365
357
#define LOAD_PACA_TOC() \
366
358
__LOAD_PACA_TOC(r2)
···
379
361
ori reg, reg, (expr)@l; \
380
362
rldimi reg, tmp, 32, 0
381
363
364
+
#ifdef CONFIG_PPC_KERNEL_PCREL
365
+
#define LOAD_REG_ADDR(reg,name) \
366
+
pla reg,name@pcrel
367
+
368
+
#else
382
369
#define LOAD_REG_ADDR(reg,name) \
383
370
addis reg,r2,name@toc@ha; \
384
371
addi reg,reg,name@toc@l
372
+
#endif
385
373
386
374
#ifdef CONFIG_PPC_BOOK3E_64
387
375
/*
···
860
836
#else
861
837
#define BTB_FLUSH(reg)
862
838
#endif /* CONFIG_PPC_E500 */
839
+
840
+
#if defined(CONFIG_PPC64_ELF_ABI_V1)
841
+
#define STACK_FRAME_PARAMS 48
842
+
#elif defined(CONFIG_PPC64_ELF_ABI_V2)
843
+
#define STACK_FRAME_PARAMS 32
844
+
#elif defined(CONFIG_PPC32)
845
+
#define STACK_FRAME_PARAMS 8
846
+
#endif
863
847
864
848
#endif /* _ASM_POWERPC_PPC_ASM_H */
+6
-2
arch/powerpc/include/asm/reg.h
+6
-2
arch/powerpc/include/asm/reg.h
···
382
382
#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
383
383
#define SPRN_RMOR 0x138 /* Real mode offset register */
384
384
#define SPRN_HRMOR 0x139 /* Real mode offset register */
385
-
#define SPRN_HSRR0 0x13A /* Hypervisor Save/Restore 0 */
386
-
#define SPRN_HSRR1 0x13B /* Hypervisor Save/Restore 1 */
387
385
#define SPRN_ASDR 0x330 /* Access segment descriptor register */
388
386
#define SPRN_IC 0x350 /* Virtual Instruction Count */
389
387
#define SPRN_VTB 0x351 /* Virtual Time Base */
···
415
417
#define FSCR_DSCR __MASK(FSCR_DSCR_LG)
416
418
#define FSCR_INTR_CAUSE (ASM_CONST(0xFF) << 56) /* interrupt cause */
417
419
#define SPRN_HFSCR 0xbe /* HV=1 Facility Status & Control Register */
420
+
#define HFSCR_PREFIX __MASK(FSCR_PREFIX_LG)
418
421
#define HFSCR_MSGP __MASK(FSCR_MSGP_LG)
419
422
#define HFSCR_TAR __MASK(FSCR_TAR_LG)
420
423
#define HFSCR_EBB __MASK(FSCR_EBB_LG)
···
1309
1310
#define PVR_VER_E500MC 0x8023
1310
1311
#define PVR_VER_E5500 0x8024
1311
1312
#define PVR_VER_E6500 0x8040
1313
+
#define PVR_VER_7450 0x8000
1314
+
#define PVR_VER_7455 0x8001
1315
+
#define PVR_VER_7447 0x8002
1316
+
#define PVR_VER_7447A 0x8003
1317
+
#define PVR_VER_7448 0x8004
1312
1318
1313
1319
/*
1314
1320
* For the 8xx processors, all of them report the same PVR family for
+2
-2
arch/powerpc/include/asm/rtas-types.h
+2
-2
arch/powerpc/include/asm/rtas-types.h
···
2
2
#ifndef _ASM_POWERPC_RTAS_TYPES_H
3
3
#define _ASM_POWERPC_RTAS_TYPES_H
4
4
5
-
#include <linux/spinlock_types.h>
5
+
#include <linux/compiler_attributes.h>
6
6
7
7
typedef __be32 rtas_arg_t;
8
8
···
12
12
__be32 nret;
13
13
rtas_arg_t args[16];
14
14
rtas_arg_t *rets; /* Pointer to return values in args[]. */
15
-
};
15
+
} __aligned(8);
16
16
17
17
struct rtas_t {
18
18
unsigned long entry; /* physical address pointer */
+5
arch/powerpc/include/asm/sections.h
+5
arch/powerpc/include/asm/sections.h
···
46
46
*/
47
47
static inline unsigned long kernel_toc_addr(void)
48
48
{
49
+
#ifdef CONFIG_PPC_KERNEL_PCREL
50
+
BUILD_BUG();
51
+
return -1UL;
52
+
#else
49
53
unsigned long toc_ptr;
50
54
51
55
asm volatile("mr %0, 2" : "=r" (toc_ptr));
52
56
return toc_ptr;
57
+
#endif
53
58
}
54
59
55
60
static inline int overlaps_interrupt_vector_text(unsigned long start,
+40
arch/powerpc/include/asm/thread_info.h
+40
arch/powerpc/include/asm/thread_info.h
···
45
45
#include <linux/cache.h>
46
46
#include <asm/processor.h>
47
47
#include <asm/accounting.h>
48
+
#include <asm/ppc_asm.h>
48
49
49
50
#define SLB_PRELOAD_NR 16U
50
51
/*
···
176
175
#ifdef CONFIG_COMPAT
177
176
#define is_32bit_task() (test_thread_flag(TIF_32BIT))
178
177
#define is_tsk_32bit_task(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT))
178
+
#define clear_tsk_compat_task(tsk) (clear_tsk_thread_flag(p, TIF_32BIT))
179
179
#else
180
180
#define is_32bit_task() (IS_ENABLED(CONFIG_PPC32))
181
181
#define is_tsk_32bit_task(tsk) (IS_ENABLED(CONFIG_PPC32))
182
+
#define clear_tsk_compat_task(tsk) do { } while (0)
182
183
#endif
183
184
184
185
#if defined(CONFIG_PPC64)
···
188
185
#else
189
186
#define is_elf2_task() (0)
190
187
#endif
188
+
189
+
/*
190
+
* Walks up the stack frames to make sure that the specified object is
191
+
* entirely contained by a single stack frame.
192
+
*
193
+
* Returns:
194
+
* GOOD_FRAME if within a frame
195
+
* BAD_STACK if placed across a frame boundary (or outside stack)
196
+
*/
197
+
static inline int arch_within_stack_frames(const void * const stack,
198
+
const void * const stackend,
199
+
const void *obj, unsigned long len)
200
+
{
201
+
const void *params;
202
+
const void *frame;
203
+
204
+
params = *(const void * const *)current_stack_pointer + STACK_FRAME_PARAMS;
205
+
frame = **(const void * const * const *)current_stack_pointer;
206
+
207
+
/*
208
+
* low -----------------------------------------------------------> high
209
+
* [backchain][metadata][params][local vars][saved registers][backchain]
210
+
* ^------------------------------------^
211
+
* | allows copies only in this region |
212
+
* | |
213
+
* params frame
214
+
* The metadata region contains the saved LR, CR etc.
215
+
*/
216
+
while (stack <= frame && frame < stackend) {
217
+
if (obj + len <= frame)
218
+
return obj >= params ? GOOD_FRAME : BAD_STACK;
219
+
params = frame + STACK_FRAME_PARAMS;
220
+
frame = *(const void * const *)frame;
221
+
}
222
+
223
+
return BAD_STACK;
224
+
}
191
225
192
226
#endif /* !__ASSEMBLY__ */
193
227
+26
-4
arch/powerpc/include/asm/uaccess.h
+26
-4
arch/powerpc/include/asm/uaccess.h
···
71
71
* because we do not write to any memory gcc knows about, so there
72
72
* are no aliasing issues.
73
73
*/
74
+
/* -mprefixed can generate offsets beyond range, fall back hack */
75
+
#ifdef CONFIG_PPC_KERNEL_PREFIXED
76
+
#define __put_user_asm_goto(x, addr, label, op) \
77
+
asm_volatile_goto( \
78
+
"1: " op " %0,0(%1) # put_user\n" \
79
+
EX_TABLE(1b, %l2) \
80
+
: \
81
+
: "r" (x), "b" (addr) \
82
+
: \
83
+
: label)
84
+
#else
74
85
#define __put_user_asm_goto(x, addr, label, op) \
75
86
asm_volatile_goto( \
76
87
"1: " op "%U1%X1 %0,%1 # put_user\n" \
77
88
EX_TABLE(1b, %l2) \
78
89
: \
79
-
: "r" (x), "m<>" (*addr) \
90
+
: "r" (x), "m<>" (*addr) \
80
91
: \
81
92
: label)
93
+
#endif
82
94
83
95
#ifdef __powerpc64__
84
96
#define __put_user_asm2_goto(x, ptr, label) \
···
143
131
144
132
#ifdef CONFIG_CC_HAS_ASM_GOTO_OUTPUT
145
133
134
+
/* -mprefixed can generate offsets beyond range, fall back hack */
135
+
#ifdef CONFIG_PPC_KERNEL_PREFIXED
136
+
#define __get_user_asm_goto(x, addr, label, op) \
137
+
asm_volatile_goto( \
138
+
"1: "op" %0,0(%1) # get_user\n" \
139
+
EX_TABLE(1b, %l2) \
140
+
: "=r" (x) \
141
+
: "b" (addr) \
142
+
: \
143
+
: label)
144
+
#else
146
145
#define __get_user_asm_goto(x, addr, label, op) \
147
146
asm_volatile_goto( \
148
147
"1: "op"%U1%X1 %0, %1 # get_user\n" \
149
148
EX_TABLE(1b, %l2) \
150
149
: "=r" (x) \
151
-
: "m<>" (*addr) \
150
+
: "m<>" (*addr) \
152
151
: \
153
152
: label)
153
+
#endif
154
154
155
155
#ifdef __powerpc64__
156
156
#define __get_user_asm2_goto(x, addr, label) \
···
385
361
386
362
extern long __copy_from_user_flushcache(void *dst, const void __user *src,
387
363
unsigned size);
388
-
extern void memcpy_page_flushcache(char *to, struct page *page, size_t offset,
389
-
size_t len);
390
364
391
365
static __must_check inline bool user_access_begin(const void __user *ptr, size_t len)
392
366
{
+4
arch/powerpc/include/uapi/asm/elf.h
+4
arch/powerpc/include/uapi/asm/elf.h
···
279
279
#define R_PPC64_TLSLD 108
280
280
#define R_PPC64_TOCSAVE 109
281
281
282
+
#define R_PPC64_REL24_NOTOC 116
282
283
#define R_PPC64_ENTRY 118
284
+
285
+
#define R_PPC64_PCREL34 132
286
+
#define R_PPC64_GOT_PCREL34 133
283
287
284
288
#define R_PPC64_REL16 249
285
289
#define R_PPC64_REL16_LO 250
+2
arch/powerpc/kernel/asm-offsets.c
+2
arch/powerpc/kernel/asm-offsets.c
···
185
185
offsetof(struct task_struct, thread_info));
186
186
OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
187
187
OFFSET(PACAR1, paca_struct, saved_r1);
188
+
#ifndef CONFIG_PPC_KERNEL_PCREL
188
189
OFFSET(PACATOC, paca_struct, kernel_toc);
190
+
#endif
189
191
OFFSET(PACAKBASE, paca_struct, kernelbase);
190
192
OFFSET(PACAKMSR, paca_struct, kernel_msr);
191
193
#ifdef CONFIG_PPC_BOOK3S_64
+1
-1
arch/powerpc/kernel/btext.c
+1
-1
arch/powerpc/kernel/btext.c
+19
-4
arch/powerpc/kernel/entry_32.S
+19
-4
arch/powerpc/kernel/entry_32.S
···
183
183
ret_from_fork:
184
184
REST_NVGPRS(r1)
185
185
bl schedule_tail
186
-
li r3,0
186
+
li r3,0 /* fork() return value */
187
187
b ret_from_syscall
188
188
189
-
.globl ret_from_kernel_thread
190
-
ret_from_kernel_thread:
191
-
REST_NVGPRS(r1)
189
+
.globl ret_from_kernel_user_thread
190
+
ret_from_kernel_user_thread:
192
191
bl schedule_tail
193
192
mtctr r14
194
193
mr r3,r15
···
195
196
bctrl
196
197
li r3,0
197
198
b ret_from_syscall
199
+
200
+
.globl start_kernel_thread
201
+
start_kernel_thread:
202
+
bl schedule_tail
203
+
mtctr r14
204
+
mr r3,r15
205
+
PPC440EP_ERR42
206
+
bctrl
207
+
/*
208
+
* This must not return. We actually want to BUG here, not WARN,
209
+
* because BUG will exit the process which is what the kernel thread
210
+
* should have done, which may give some hope of continuing.
211
+
*/
212
+
100: trap
213
+
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
214
+
198
215
199
216
/*
200
217
* This routine switches between two different tasks. The process
+56
-56
arch/powerpc/kernel/exceptions-64s.S
+56
-56
arch/powerpc/kernel/exceptions-64s.S
···
1075
1075
__GEN_COMMON_BODY system_reset
1076
1076
1077
1077
addi r3,r1,STACK_INT_FRAME_REGS
1078
-
bl system_reset_exception
1078
+
bl CFUNC(system_reset_exception)
1079
1079
1080
1080
/* Clear MSR_RI before setting SRR0 and SRR1. */
1081
1081
li r9,0
···
1223
1223
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1224
1224
addi r3,r1,STACK_INT_FRAME_REGS
1225
1225
BEGIN_FTR_SECTION
1226
-
bl machine_check_early_boot
1226
+
bl CFUNC(machine_check_early_boot)
1227
1227
END_FTR_SECTION(0, 1) // nop out after boot
1228
-
bl machine_check_early
1228
+
bl CFUNC(machine_check_early)
1229
1229
std r3,RESULT(r1) /* Save result */
1230
1230
ld r12,_MSR(r1)
1231
1231
···
1286
1286
* Queue up the MCE event so that we can log it later, while
1287
1287
* returning from kernel or opal call.
1288
1288
*/
1289
-
bl machine_check_queue_event
1289
+
bl CFUNC(machine_check_queue_event)
1290
1290
MACHINE_CHECK_HANDLER_WINDUP
1291
1291
RFI_TO_KERNEL
1292
1292
···
1312
1312
*/
1313
1313
GEN_COMMON machine_check
1314
1314
addi r3,r1,STACK_INT_FRAME_REGS
1315
-
bl machine_check_exception_async
1315
+
bl CFUNC(machine_check_exception_async)
1316
1316
b interrupt_return_srr
1317
1317
1318
1318
···
1322
1322
* done. Queue the event then call the idle code to do the wake up.
1323
1323
*/
1324
1324
EXC_COMMON_BEGIN(machine_check_idle_common)
1325
-
bl machine_check_queue_event
1325
+
bl CFUNC(machine_check_queue_event)
1326
1326
1327
1327
/*
1328
1328
* GPR-loss wakeups are relatively straightforward, because the
···
1361
1361
BEGIN_FTR_SECTION
1362
1362
li r10,0 /* clear MSR_RI */
1363
1363
mtmsrd r10,1
1364
-
bl disable_machine_check
1364
+
bl CFUNC(disable_machine_check)
1365
1365
END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1366
1366
ld r10,PACAKMSR(r13)
1367
1367
li r3,MSR_ME
···
1378
1378
* the early handler which is a true NMI.
1379
1379
*/
1380
1380
addi r3,r1,STACK_INT_FRAME_REGS
1381
-
bl machine_check_exception
1381
+
bl CFUNC(machine_check_exception)
1382
1382
1383
1383
/*
1384
1384
* We will not reach here. Even if we did, there is no way out.
1385
1385
* Call unrecoverable_exception and die.
1386
1386
*/
1387
1387
addi r3,r1,STACK_INT_FRAME_REGS
1388
-
bl unrecoverable_exception
1388
+
bl CFUNC(unrecoverable_exception)
1389
1389
b .
1390
1390
1391
1391
···
1440
1440
bne- 1f
1441
1441
#ifdef CONFIG_PPC_64S_HASH_MMU
1442
1442
BEGIN_MMU_FTR_SECTION
1443
-
bl do_hash_fault
1443
+
bl CFUNC(do_hash_fault)
1444
1444
MMU_FTR_SECTION_ELSE
1445
-
bl do_page_fault
1445
+
bl CFUNC(do_page_fault)
1446
1446
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1447
1447
#else
1448
-
bl do_page_fault
1448
+
bl CFUNC(do_page_fault)
1449
1449
#endif
1450
1450
b interrupt_return_srr
1451
1451
1452
-
1: bl do_break
1452
+
1: bl CFUNC(do_break)
1453
1453
/*
1454
1454
* do_break() may have changed the NV GPRS while handling a breakpoint.
1455
1455
* If so, we need to restore them with their updated values.
···
1493
1493
BEGIN_MMU_FTR_SECTION
1494
1494
/* HPT case, do SLB fault */
1495
1495
addi r3,r1,STACK_INT_FRAME_REGS
1496
-
bl do_slb_fault
1496
+
bl CFUNC(do_slb_fault)
1497
1497
cmpdi r3,0
1498
1498
bne- 1f
1499
1499
b fast_interrupt_return_srr
···
1507
1507
#endif
1508
1508
std r3,RESULT(r1)
1509
1509
addi r3,r1,STACK_INT_FRAME_REGS
1510
-
bl do_bad_segment_interrupt
1510
+
bl CFUNC(do_bad_segment_interrupt)
1511
1511
b interrupt_return_srr
1512
1512
1513
1513
···
1541
1541
addi r3,r1,STACK_INT_FRAME_REGS
1542
1542
#ifdef CONFIG_PPC_64S_HASH_MMU
1543
1543
BEGIN_MMU_FTR_SECTION
1544
-
bl do_hash_fault
1544
+
bl CFUNC(do_hash_fault)
1545
1545
MMU_FTR_SECTION_ELSE
1546
-
bl do_page_fault
1546
+
bl CFUNC(do_page_fault)
1547
1547
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
1548
1548
#else
1549
-
bl do_page_fault
1549
+
bl CFUNC(do_page_fault)
1550
1550
#endif
1551
1551
b interrupt_return_srr
1552
1552
···
1581
1581
BEGIN_MMU_FTR_SECTION
1582
1582
/* HPT case, do SLB fault */
1583
1583
addi r3,r1,STACK_INT_FRAME_REGS
1584
-
bl do_slb_fault
1584
+
bl CFUNC(do_slb_fault)
1585
1585
cmpdi r3,0
1586
1586
bne- 1f
1587
1587
b fast_interrupt_return_srr
···
1595
1595
#endif
1596
1596
std r3,RESULT(r1)
1597
1597
addi r3,r1,STACK_INT_FRAME_REGS
1598
-
bl do_bad_segment_interrupt
1598
+
bl CFUNC(do_bad_segment_interrupt)
1599
1599
b interrupt_return_srr
1600
1600
1601
1601
···
1649
1649
EXC_COMMON_BEGIN(hardware_interrupt_common)
1650
1650
GEN_COMMON hardware_interrupt
1651
1651
addi r3,r1,STACK_INT_FRAME_REGS
1652
-
bl do_IRQ
1652
+
bl CFUNC(do_IRQ)
1653
1653
BEGIN_FTR_SECTION
1654
1654
b interrupt_return_hsrr
1655
1655
FTR_SECTION_ELSE
···
1679
1679
EXC_COMMON_BEGIN(alignment_common)
1680
1680
GEN_COMMON alignment
1681
1681
addi r3,r1,STACK_INT_FRAME_REGS
1682
-
bl alignment_exception
1682
+
bl CFUNC(alignment_exception)
1683
1683
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
1684
1684
b interrupt_return_srr
1685
1685
···
1745
1745
1746
1746
.Ldo_program_check:
1747
1747
addi r3,r1,STACK_INT_FRAME_REGS
1748
-
bl program_check_exception
1748
+
bl CFUNC(program_check_exception)
1749
1749
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
1750
1750
b interrupt_return_srr
1751
1751
···
1777
1777
GEN_COMMON fp_unavailable
1778
1778
bne 1f /* if from user, just load it up */
1779
1779
addi r3,r1,STACK_INT_FRAME_REGS
1780
-
bl kernel_fp_unavailable_exception
1780
+
bl CFUNC(kernel_fp_unavailable_exception)
1781
1781
0: trap
1782
1782
EMIT_BUG_ENTRY 0b, __FILE__, __LINE__, 0
1783
1783
1:
···
1790
1790
bne- 2f
1791
1791
END_FTR_SECTION_IFSET(CPU_FTR_TM)
1792
1792
#endif
1793
-
bl load_up_fpu
1793
+
bl CFUNC(load_up_fpu)
1794
1794
b fast_interrupt_return_srr
1795
1795
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1796
1796
2: /* User process was in a transaction */
1797
1797
addi r3,r1,STACK_INT_FRAME_REGS
1798
-
bl fp_unavailable_tm
1798
+
bl CFUNC(fp_unavailable_tm)
1799
1799
b interrupt_return_srr
1800
1800
#endif
1801
1801
···
1839
1839
EXC_COMMON_BEGIN(decrementer_common)
1840
1840
GEN_COMMON decrementer
1841
1841
addi r3,r1,STACK_INT_FRAME_REGS
1842
-
bl timer_interrupt
1842
+
bl CFUNC(timer_interrupt)
1843
1843
b interrupt_return_srr
1844
1844
1845
1845
···
1925
1925
GEN_COMMON doorbell_super
1926
1926
addi r3,r1,STACK_INT_FRAME_REGS
1927
1927
#ifdef CONFIG_PPC_DOORBELL
1928
-
bl doorbell_exception
1928
+
bl CFUNC(doorbell_exception)
1929
1929
#else
1930
-
bl unknown_async_exception
1930
+
bl CFUNC(unknown_async_exception)
1931
1931
#endif
1932
1932
b interrupt_return_srr
1933
1933
···
2091
2091
EXC_COMMON_BEGIN(single_step_common)
2092
2092
GEN_COMMON single_step
2093
2093
addi r3,r1,STACK_INT_FRAME_REGS
2094
-
bl single_step_exception
2094
+
bl CFUNC(single_step_exception)
2095
2095
b interrupt_return_srr
2096
2096
2097
2097
···
2126
2126
GEN_COMMON h_data_storage
2127
2127
addi r3,r1,STACK_INT_FRAME_REGS
2128
2128
BEGIN_MMU_FTR_SECTION
2129
-
bl do_bad_page_fault_segv
2129
+
bl CFUNC(do_bad_page_fault_segv)
2130
2130
MMU_FTR_SECTION_ELSE
2131
-
bl unknown_exception
2131
+
bl CFUNC(unknown_exception)
2132
2132
ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_TYPE_RADIX)
2133
2133
b interrupt_return_hsrr
2134
2134
···
2154
2154
EXC_COMMON_BEGIN(h_instr_storage_common)
2155
2155
GEN_COMMON h_instr_storage
2156
2156
addi r3,r1,STACK_INT_FRAME_REGS
2157
-
bl unknown_exception
2157
+
bl CFUNC(unknown_exception)
2158
2158
b interrupt_return_hsrr
2159
2159
2160
2160
···
2177
2177
EXC_COMMON_BEGIN(emulation_assist_common)
2178
2178
GEN_COMMON emulation_assist
2179
2179
addi r3,r1,STACK_INT_FRAME_REGS
2180
-
bl emulation_assist_interrupt
2180
+
bl CFUNC(emulation_assist_interrupt)
2181
2181
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2182
2182
b interrupt_return_hsrr
2183
2183
···
2237
2237
__GEN_COMMON_BODY hmi_exception_early
2238
2238
2239
2239
addi r3,r1,STACK_INT_FRAME_REGS
2240
-
bl hmi_exception_realmode
2240
+
bl CFUNC(hmi_exception_realmode)
2241
2241
cmpdi cr0,r3,0
2242
2242
bne 1f
2243
2243
···
2255
2255
EXC_COMMON_BEGIN(hmi_exception_common)
2256
2256
GEN_COMMON hmi_exception
2257
2257
addi r3,r1,STACK_INT_FRAME_REGS
2258
-
bl handle_hmi_exception
2258
+
bl CFUNC(handle_hmi_exception)
2259
2259
b interrupt_return_hsrr
2260
2260
2261
2261
···
2290
2290
GEN_COMMON h_doorbell
2291
2291
addi r3,r1,STACK_INT_FRAME_REGS
2292
2292
#ifdef CONFIG_PPC_DOORBELL
2293
-
bl doorbell_exception
2293
+
bl CFUNC(doorbell_exception)
2294
2294
#else
2295
-
bl unknown_async_exception
2295
+
bl CFUNC(unknown_async_exception)
2296
2296
#endif
2297
2297
b interrupt_return_hsrr
2298
2298
···
2325
2325
EXC_COMMON_BEGIN(h_virt_irq_common)
2326
2326
GEN_COMMON h_virt_irq
2327
2327
addi r3,r1,STACK_INT_FRAME_REGS
2328
-
bl do_IRQ
2328
+
bl CFUNC(do_IRQ)
2329
2329
b interrupt_return_hsrr
2330
2330
2331
2331
···
2374
2374
lbz r4,PACAIRQSOFTMASK(r13)
2375
2375
cmpdi r4,IRQS_ENABLED
2376
2376
bne 1f
2377
-
bl performance_monitor_exception_async
2377
+
bl CFUNC(performance_monitor_exception_async)
2378
2378
b interrupt_return_srr
2379
2379
1:
2380
-
bl performance_monitor_exception_nmi
2380
+
bl CFUNC(performance_monitor_exception_nmi)
2381
2381
/* Clear MSR_RI before setting SRR0 and SRR1. */
2382
2382
li r9,0
2383
2383
mtmsrd r9,1
···
2421
2421
bne- 2f
2422
2422
END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
2423
2423
#endif
2424
-
bl load_up_altivec
2424
+
bl CFUNC(load_up_altivec)
2425
2425
b fast_interrupt_return_srr
2426
2426
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2427
2427
2: /* User process was in a transaction */
2428
2428
addi r3,r1,STACK_INT_FRAME_REGS
2429
-
bl altivec_unavailable_tm
2429
+
bl CFUNC(altivec_unavailable_tm)
2430
2430
b interrupt_return_srr
2431
2431
#endif
2432
2432
1:
2433
2433
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2434
2434
#endif
2435
2435
addi r3,r1,STACK_INT_FRAME_REGS
2436
-
bl altivec_unavailable_exception
2436
+
bl CFUNC(altivec_unavailable_exception)
2437
2437
b interrupt_return_srr
2438
2438
2439
2439
···
2475
2475
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2476
2476
2: /* User process was in a transaction */
2477
2477
addi r3,r1,STACK_INT_FRAME_REGS
2478
-
bl vsx_unavailable_tm
2478
+
bl CFUNC(vsx_unavailable_tm)
2479
2479
b interrupt_return_srr
2480
2480
#endif
2481
2481
1:
2482
2482
END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2483
2483
#endif
2484
2484
addi r3,r1,STACK_INT_FRAME_REGS
2485
-
bl vsx_unavailable_exception
2485
+
bl CFUNC(vsx_unavailable_exception)
2486
2486
b interrupt_return_srr
2487
2487
2488
2488
···
2509
2509
EXC_COMMON_BEGIN(facility_unavailable_common)
2510
2510
GEN_COMMON facility_unavailable
2511
2511
addi r3,r1,STACK_INT_FRAME_REGS
2512
-
bl facility_unavailable_exception
2512
+
bl CFUNC(facility_unavailable_exception)
2513
2513
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2514
2514
b interrupt_return_srr
2515
2515
···
2537
2537
EXC_COMMON_BEGIN(h_facility_unavailable_common)
2538
2538
GEN_COMMON h_facility_unavailable
2539
2539
addi r3,r1,STACK_INT_FRAME_REGS
2540
-
bl facility_unavailable_exception
2540
+
bl CFUNC(facility_unavailable_exception)
2541
2541
/* XXX Shouldn't be necessary in practice */
2542
2542
HANDLER_RESTORE_NVGPRS()
2543
2543
b interrupt_return_hsrr
···
2568
2568
EXC_COMMON_BEGIN(cbe_system_error_common)
2569
2569
GEN_COMMON cbe_system_error
2570
2570
addi r3,r1,STACK_INT_FRAME_REGS
2571
-
bl cbe_system_error_exception
2571
+
bl CFUNC(cbe_system_error_exception)
2572
2572
b interrupt_return_hsrr
2573
2573
2574
2574
#else /* CONFIG_CBE_RAS */
···
2599
2599
EXC_COMMON_BEGIN(instruction_breakpoint_common)
2600
2600
GEN_COMMON instruction_breakpoint
2601
2601
addi r3,r1,STACK_INT_FRAME_REGS
2602
-
bl instruction_breakpoint_exception
2602
+
bl CFUNC(instruction_breakpoint_exception)
2603
2603
b interrupt_return_srr
2604
2604
2605
2605
···
2721
2721
EXC_COMMON_BEGIN(denorm_exception_common)
2722
2722
GEN_COMMON denorm_exception
2723
2723
addi r3,r1,STACK_INT_FRAME_REGS
2724
-
bl unknown_exception
2724
+
bl CFUNC(unknown_exception)
2725
2725
b interrupt_return_hsrr
2726
2726
2727
2727
···
2738
2738
EXC_COMMON_BEGIN(cbe_maintenance_common)
2739
2739
GEN_COMMON cbe_maintenance
2740
2740
addi r3,r1,STACK_INT_FRAME_REGS
2741
-
bl cbe_maintenance_exception
2741
+
bl CFUNC(cbe_maintenance_exception)
2742
2742
b interrupt_return_hsrr
2743
2743
2744
2744
#else /* CONFIG_CBE_RAS */
···
2764
2764
GEN_COMMON altivec_assist
2765
2765
addi r3,r1,STACK_INT_FRAME_REGS
2766
2766
#ifdef CONFIG_ALTIVEC
2767
-
bl altivec_assist_exception
2767
+
bl CFUNC(altivec_assist_exception)
2768
2768
HANDLER_RESTORE_NVGPRS() /* instruction emulation may change GPRs */
2769
2769
#else
2770
-
bl unknown_exception
2770
+
bl CFUNC(unknown_exception)
2771
2771
#endif
2772
2772
b interrupt_return_srr
2773
2773
···
2785
2785
EXC_COMMON_BEGIN(cbe_thermal_common)
2786
2786
GEN_COMMON cbe_thermal
2787
2787
addi r3,r1,STACK_INT_FRAME_REGS
2788
-
bl cbe_thermal_exception
2788
+
bl CFUNC(cbe_thermal_exception)
2789
2789
b interrupt_return_hsrr
2790
2790
2791
2791
#else /* CONFIG_CBE_RAS */
···
2818
2818
__GEN_COMMON_BODY soft_nmi
2819
2819
2820
2820
addi r3,r1,STACK_INT_FRAME_REGS
2821
-
bl soft_nmi_interrupt
2821
+
bl CFUNC(soft_nmi_interrupt)
2822
2822
2823
2823
/* Clear MSR_RI before setting SRR0 and SRR1. */
2824
2824
li r9,0
+83
-50
arch/powerpc/kernel/head_64.S
+83
-50
arch/powerpc/kernel/head_64.S
···
76
76
* 2. The kernel is entered at __start
77
77
*/
78
78
79
+
/*
80
+
* boot_from_prom and prom_init run at the physical address. Everything
81
+
* after prom and kexec entry run at the virtual address (PAGE_OFFSET).
82
+
* Secondaries run at the virtual address from generic_secondary_common_init
83
+
* onward.
84
+
*/
85
+
79
86
OPEN_FIXED_SECTION(first_256B, 0x0, 0x100)
80
87
USE_FIXED_SECTION(first_256B)
81
88
/*
···
310
303
/* turn on 64-bit mode */
311
304
bl enable_64b_mode
312
305
313
-
/* get a valid TOC pointer, wherever we're mapped at */
314
-
bl relative_toc
315
-
tovirt(r2,r2)
316
-
317
306
/* Book3E initialization */
318
307
mr r3,r24
319
308
bl book3e_secondary_thread_init
309
+
bl relative_toc
310
+
320
311
b generic_secondary_common_init
321
312
322
313
#endif /* CONFIG_PPC_BOOK3E_64 */
···
330
325
*/
331
326
_GLOBAL(generic_secondary_smp_init)
332
327
FIXUP_ENDIAN
328
+
329
+
li r13,0
330
+
331
+
/* Poison TOC */
332
+
li r2,-1
333
+
333
334
mr r24,r3
334
335
mr r25,r4
335
336
336
337
/* turn on 64-bit mode */
337
338
bl enable_64b_mode
338
339
339
-
/* get a valid TOC pointer, wherever we're mapped at */
340
-
bl relative_toc
341
-
tovirt(r2,r2)
342
-
343
340
#ifdef CONFIG_PPC_BOOK3E_64
344
341
/* Book3E initialization */
345
342
mr r3,r24
346
343
mr r4,r25
347
344
bl book3e_secondary_core_init
348
-
345
+
/* Now NIA and r2 are relocated to PAGE_OFFSET if not already */
349
346
/*
350
347
* After common core init has finished, check if the current thread is the
351
348
* one we wanted to boot. If not, start the specified thread and stop the
···
385
378
10:
386
379
b 10b
387
380
20:
381
+
#else
382
+
/* Now the MMU is off, can branch to our PAGE_OFFSET address */
383
+
bcl 20,31,$+4
384
+
1: mflr r11
385
+
addi r11,r11,(2f - 1b)
386
+
tovirt(r11, r11)
387
+
mtctr r11
388
+
bctr
389
+
2:
390
+
bl relative_toc
388
391
#endif
389
392
390
393
generic_secondary_common_init:
···
509
492
/* Switch off MMU if not already off */
510
493
bl __mmu_off
511
494
495
+
/* Now the MMU is off, can return to our PAGE_OFFSET address */
496
+
tovirt(r25,r25)
512
497
mtlr r25
513
498
blr
514
499
SYM_FUNC_END(start_initialization_book3s)
···
534
515
/* Zero r13 (paca) so early program check / mce don't use it */
535
516
li r13,0
536
517
537
-
/* Get TOC pointer (current runtime address) */
538
-
bl relative_toc
539
-
540
-
/* find out where we are now */
541
-
bcl 20,31,$+4
542
-
0: mflr r26 /* r26 = runtime addr here */
543
-
addis r26,r26,(_stext - 0b)@ha
544
-
addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
518
+
/* Poison TOC */
519
+
li r2,-1
545
520
546
521
/*
547
522
* Are we booted from a PROM Of-type client-interface ?
···
553
540
mr r29,r9
554
541
#endif
555
542
543
+
/* Get TOC pointer (current runtime address) */
544
+
bl relative_toc
545
+
546
+
/* These functions return to the virtual (PAGE_OFFSET) address */
556
547
#ifdef CONFIG_PPC_BOOK3E_64
557
548
bl start_initialization_book3e
558
549
#else
559
550
bl start_initialization_book3s
560
551
#endif /* CONFIG_PPC_BOOK3E_64 */
552
+
553
+
/* Get TOC pointer, virtual */
554
+
bl relative_toc
555
+
556
+
/* find out where we are now */
557
+
558
+
/* OPAL doesn't pass base address in r4, have to derive it. */
559
+
bcl 20,31,$+4
560
+
0: mflr r26 /* r26 = runtime addr here */
561
+
addis r26,r26,(_stext - 0b)@ha
562
+
addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
563
+
561
564
b __after_prom_start
562
565
563
566
__REF
564
567
__boot_from_prom:
565
568
#ifdef CONFIG_PPC_OF_BOOT_TRAMPOLINE
569
+
/* Get TOC pointer, non-virtual */
570
+
bl relative_toc
571
+
572
+
/* find out where we are now */
573
+
bcl 20,31,$+4
574
+
0: mflr r26 /* r26 = runtime addr here */
575
+
addis r26,r26,(_stext - 0b)@ha
576
+
addi r26,r26,(_stext - 0b)@l /* current runtime base addr */
577
+
566
578
/* Save parameters */
567
579
mr r31,r3
568
580
mr r30,r4
···
617
579
618
580
/* Do all of the interaction with OF client interface */
619
581
mr r8,r26
620
-
bl prom_init
582
+
bl CFUNC(prom_init)
621
583
#endif /* #CONFIG_PPC_OF_BOOT_TRAMPOLINE */
622
584
623
585
/* We never return. We also hit that trap if trying to boot
···
628
590
__after_prom_start:
629
591
#ifdef CONFIG_RELOCATABLE
630
592
/* process relocations for the final address of the kernel */
631
-
lis r25,PAGE_OFFSET@highest /* compute virtual base of kernel */
632
-
sldi r25,r25,32
633
-
#if defined(CONFIG_PPC_BOOK3E_64)
634
-
tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
635
-
#endif
636
593
lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
637
-
#if defined(CONFIG_PPC_BOOK3E_64)
638
-
tophys(r26,r26)
639
-
#endif
640
594
cmplwi cr0,r7,1 /* flagged to stay where we are ? */
641
-
bne 1f
642
-
add r25,r25,r26
595
+
mr r25,r26 /* then use current kernel base */
596
+
beq 1f
597
+
LOAD_REG_IMMEDIATE(r25, PAGE_OFFSET) /* else use static kernel base */
643
598
1: mr r3,r25
644
599
bl relocate
645
600
#if defined(CONFIG_PPC_BOOK3E_64)
···
648
617
*
649
618
* Note: This process overwrites the OF exception vectors.
650
619
*/
651
-
li r3,0 /* target addr */
652
-
#ifdef CONFIG_PPC_BOOK3E_64
653
-
tovirt(r3,r3) /* on booke, we already run at PAGE_OFFSET */
654
-
#endif
620
+
LOAD_REG_IMMEDIATE(r3, PAGE_OFFSET)
655
621
mr. r4,r26 /* In some cases the loader may */
656
-
#if defined(CONFIG_PPC_BOOK3E_64)
657
-
tovirt(r4,r4)
658
-
#endif
659
622
beq 9f /* have already put us at zero */
660
623
li r6,0x100 /* Start offset, the first 0x100 */
661
624
/* bytes were copied earlier. */
···
660
635
* variable __run_at_load, if it is set the kernel is treated as relocatable
661
636
* kernel, otherwise it will be moved to PHYSICAL_START
662
637
*/
663
-
#if defined(CONFIG_PPC_BOOK3E_64)
664
-
tovirt(r26,r26) /* on booke, we already run at PAGE_OFFSET */
665
-
#endif
666
638
lwz r7,(FIXED_SYMBOL_ABS_ADDR(__run_at_load))(r26)
667
639
cmplwi cr0,r7,1
668
640
bne 3f
···
778
756
sync
779
757
slbia
780
758
781
-
/* get TOC pointer (real address) */
759
+
/* Branch to our PAGE_OFFSET address */
760
+
bcl 20,31,$+4
761
+
1: mflr r11
762
+
addi r11,r11,(2f - 1b)
763
+
tovirt(r11, r11)
764
+
mtctr r11
765
+
bctr
766
+
2:
782
767
bl relative_toc
783
-
tovirt(r2,r2)
784
768
785
769
/* Copy some CPU settings from CPU 0 */
786
770
bl __restore_cpu_ppc970
···
845
817
* can turn it on below. This is a call to C, which is OK, we're still
846
818
* running on the emergency stack.
847
819
*/
848
-
bl early_setup_secondary
820
+
bl CFUNC(early_setup_secondary)
849
821
850
822
/*
851
823
* The primary has initialized our kernel stack for us in the paca, grab
···
884
856
LOAD_PACA_TOC()
885
857
li r3,0
886
858
std r3,0(r1) /* Zero the stack frame pointer */
887
-
bl start_secondary
859
+
bl CFUNC(start_secondary)
888
860
b .
889
861
/*
890
862
* Reset stack pointer and call start_secondary
···
895
867
ld r1,PACAKSAVE(r13) /* Reload kernel stack pointer */
896
868
li r3,0
897
869
std r3,0(r1) /* Zero the stack frame pointer */
898
-
bl start_secondary
870
+
bl CFUNC(start_secondary)
899
871
b .
900
872
#endif
901
873
···
925
897
* TOC in -mcmodel=medium mode. After we relocate to 0 but before
926
898
* the MMU is on we need our TOC to be a virtual address otherwise
927
899
* these pointers will be real addresses which may get stored and
928
-
* accessed later with the MMU on. We use tovirt() at the call
929
-
* sites to handle this.
900
+
* accessed later with the MMU on. We branch to the virtual address
901
+
* while still in real mode then call relative_toc again to handle
902
+
* this.
930
903
*/
931
904
_GLOBAL(relative_toc)
905
+
#ifdef CONFIG_PPC_KERNEL_PCREL
906
+
tdnei r2,-1
907
+
blr
908
+
#else
932
909
mflr r0
933
910
bcl 20,31,$+4
934
911
0: mflr r11
···
944
911
945
912
.balign 8
946
913
p_toc: .8byte .TOC. - 0b
914
+
#endif
947
915
948
916
/*
949
917
* This is where the main kernel code starts.
950
918
*/
951
919
__REF
952
920
start_here_multiplatform:
953
-
/* set up the TOC */
954
-
bl relative_toc
955
-
tovirt(r2,r2)
921
+
/* Adjust TOC for moved kernel. Could adjust when moving it instead. */
922
+
bl relative_toc
956
923
957
924
/* Clear out the BSS. It may have been done in prom_init,
958
925
* already but that's irrelevant since prom_init will soon
···
1005
972
*/
1006
973
1007
974
#ifdef CONFIG_KASAN
1008
-
bl kasan_early_init
975
+
bl CFUNC(kasan_early_init)
1009
976
#endif
1010
977
/* Restore parameters passed from prom_init/kexec */
1011
978
mr r3,r31
···
1038
1005
stb r0,PACAIRQHAPPENED(r13)
1039
1006
1040
1007
/* Generic kernel entry */
1041
-
bl start_kernel
1008
+
bl CFUNC(start_kernel)
1042
1009
1043
1010
/* Not reached */
1044
1011
0: trap
+1
arch/powerpc/kernel/head_booke.h
+1
arch/powerpc/kernel/head_booke.h
+1
-9
arch/powerpc/kernel/idle.c
+1
-9
arch/powerpc/kernel/idle.c
···
107
107
},
108
108
{}
109
109
};
110
-
static struct ctl_table powersave_nap_sysctl_root[] = {
111
-
{
112
-
.procname = "kernel",
113
-
.mode = 0555,
114
-
.child = powersave_nap_ctl_table,
115
-
},
116
-
{}
117
-
};
118
110
119
111
static int __init
120
112
register_powersave_nap_sysctl(void)
121
113
{
122
-
register_sysctl_table(powersave_nap_sysctl_root);
114
+
register_sysctl("kernel", powersave_nap_ctl_table);
123
115
124
116
return 0;
125
117
}
+1
-1
arch/powerpc/kernel/interrupt.c
+1
-1
arch/powerpc/kernel/interrupt.c
+38
-18
arch/powerpc/kernel/interrupt_64.S
+38
-18
arch/powerpc/kernel/interrupt_64.S
···
101
101
* state of kernel code.
102
102
*/
103
103
SANITIZE_SYSCALL_GPRS()
104
-
bl system_call_exception
104
+
bl CFUNC(system_call_exception)
105
105
106
106
.Lsyscall_vectored_\name\()_exit:
107
107
addi r4,r1,STACK_INT_FRAME_REGS
108
108
li r5,1 /* scv */
109
-
bl syscall_exit_prepare
109
+
bl CFUNC(syscall_exit_prepare)
110
110
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
111
111
.Lsyscall_vectored_\name\()_rst_start:
112
112
lbz r11,PACAIRQHAPPENED(r13)
···
185
185
addi r4,r1,STACK_INT_FRAME_REGS
186
186
li r11,IRQS_ALL_DISABLED
187
187
stb r11,PACAIRQSOFTMASK(r13)
188
-
bl syscall_exit_restart
188
+
bl CFUNC(syscall_exit_restart)
189
189
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
190
190
b .Lsyscall_vectored_\name\()_rst_start
191
191
1:
···
286
286
* state of kernel code.
287
287
*/
288
288
SANITIZE_SYSCALL_GPRS()
289
-
bl system_call_exception
289
+
bl CFUNC(system_call_exception)
290
290
291
291
.Lsyscall_exit:
292
292
addi r4,r1,STACK_INT_FRAME_REGS
293
293
li r5,0 /* !scv */
294
-
bl syscall_exit_prepare
294
+
bl CFUNC(syscall_exit_prepare)
295
295
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
296
296
#ifdef CONFIG_PPC_BOOK3S
297
297
.Lsyscall_rst_start:
···
372
372
addi r4,r1,STACK_INT_FRAME_REGS
373
373
li r11,IRQS_ALL_DISABLED
374
374
stb r11,PACAIRQSOFTMASK(r13)
375
-
bl syscall_exit_restart
375
+
bl CFUNC(syscall_exit_restart)
376
376
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
377
377
b .Lsyscall_rst_start
378
378
1:
···
401
401
li r3,0 /* 0 return value, no EMULATE_STACK_STORE */
402
402
bne+ .Lfast_kernel_interrupt_return_srr
403
403
addi r3,r1,STACK_INT_FRAME_REGS
404
-
bl unrecoverable_exception
404
+
bl CFUNC(unrecoverable_exception)
405
405
b . /* should not get here */
406
406
#else
407
407
bne .Lfast_user_interrupt_return_srr
···
419
419
interrupt_return_\srr\()_user: /* make backtraces match the _kernel variant */
420
420
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_user)
421
421
addi r3,r1,STACK_INT_FRAME_REGS
422
-
bl interrupt_exit_user_prepare
422
+
bl CFUNC(interrupt_exit_user_prepare)
423
423
#ifndef CONFIG_INTERRUPT_SANITIZE_REGISTERS
424
424
cmpdi r3,0
425
425
bne- .Lrestore_nvgprs_\srr
···
523
523
addi r3,r1,STACK_INT_FRAME_REGS
524
524
li r11,IRQS_ALL_DISABLED
525
525
stb r11,PACAIRQSOFTMASK(r13)
526
-
bl interrupt_exit_user_restart
526
+
bl CFUNC(interrupt_exit_user_restart)
527
527
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
528
528
b .Linterrupt_return_\srr\()_user_rst_start
529
529
1:
···
536
536
interrupt_return_\srr\()_kernel:
537
537
_ASM_NOKPROBE_SYMBOL(interrupt_return_\srr\()_kernel)
538
538
addi r3,r1,STACK_INT_FRAME_REGS
539
-
bl interrupt_exit_kernel_prepare
539
+
bl CFUNC(interrupt_exit_kernel_prepare)
540
540
541
541
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
542
542
.Linterrupt_return_\srr\()_kernel_rst_start:
···
705
705
addi r3,r1,STACK_INT_FRAME_REGS
706
706
li r11,IRQS_ALL_DISABLED
707
707
stb r11,PACAIRQSOFTMASK(r13)
708
-
bl interrupt_exit_kernel_restart
708
+
bl CFUNC(interrupt_exit_kernel_restart)
709
709
std r1,PACA_EXIT_SAVE_R1(r13) /* save r1 for restart */
710
710
b .Linterrupt_return_\srr\()_kernel_rst_start
711
711
1:
···
727
727
728
728
#ifdef CONFIG_PPC_BOOK3S
729
729
_GLOBAL(ret_from_fork_scv)
730
-
bl schedule_tail
731
-
REST_NVGPRS(r1)
730
+
bl CFUNC(schedule_tail)
731
+
HANDLER_RESTORE_NVGPRS()
732
732
li r3,0 /* fork() return value */
733
733
b .Lsyscall_vectored_common_exit
734
734
#endif
735
735
736
736
_GLOBAL(ret_from_fork)
737
-
bl schedule_tail
738
-
REST_NVGPRS(r1)
737
+
bl CFUNC(schedule_tail)
738
+
HANDLER_RESTORE_NVGPRS()
739
739
li r3,0 /* fork() return value */
740
740
b .Lsyscall_exit
741
741
742
-
_GLOBAL(ret_from_kernel_thread)
743
-
bl schedule_tail
744
-
REST_NVGPRS(r1)
742
+
_GLOBAL(ret_from_kernel_user_thread)
743
+
bl CFUNC(schedule_tail)
745
744
mtctr r14
746
745
mr r3,r15
747
746
#ifdef CONFIG_PPC64_ELF_ABI_V2
···
748
749
#endif
749
750
bctrl
750
751
li r3,0
752
+
/*
753
+
* It does not matter whether this returns via the scv or sc path
754
+
* because it returns as execve() and therefore has no calling ABI
755
+
* (i.e., it sets registers according to the exec()ed entry point).
756
+
*/
751
757
b .Lsyscall_exit
758
+
759
+
_GLOBAL(start_kernel_thread)
760
+
bl CFUNC(schedule_tail)
761
+
mtctr r14
762
+
mr r3,r15
763
+
#ifdef CONFIG_PPC64_ELF_ABI_V2
764
+
mr r12,r14
765
+
#endif
766
+
bctrl
767
+
/*
768
+
* This must not return. We actually want to BUG here, not WARN,
769
+
* because BUG will exit the process which is what the kernel thread
770
+
* should have done, which may give some hope of continuing.
771
+
*/
772
+
100: trap
773
+
EMIT_BUG_ENTRY 100b,__FILE__,__LINE__,0
+240
-6
arch/powerpc/kernel/iommu.c
+240
-6
arch/powerpc/kernel/iommu.c
···
35
35
#include <asm/vio.h>
36
36
#include <asm/tce.h>
37
37
#include <asm/mmu_context.h>
38
+
#include <asm/ppc-pci.h>
38
39
39
40
#define DBG(...)
40
41
···
1087
1086
}
1088
1087
EXPORT_SYMBOL_GPL(iommu_tce_kill);
1089
1088
1090
-
int iommu_take_ownership(struct iommu_table *tbl)
1089
+
static int iommu_take_ownership(struct iommu_table *tbl)
1091
1090
{
1092
1091
unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1093
1092
int ret = 0;
···
1119
1118
1120
1119
return ret;
1121
1120
}
1122
-
EXPORT_SYMBOL_GPL(iommu_take_ownership);
1123
1121
1124
-
void iommu_release_ownership(struct iommu_table *tbl)
1122
+
static void iommu_release_ownership(struct iommu_table *tbl)
1125
1123
{
1126
1124
unsigned long flags, i, sz = (tbl->it_size + 7) >> 3;
1127
1125
···
1137
1137
spin_unlock(&tbl->pools[i].lock);
1138
1138
spin_unlock_irqrestore(&tbl->large_pool.lock, flags);
1139
1139
}
1140
-
EXPORT_SYMBOL_GPL(iommu_release_ownership);
1141
1140
1142
1141
int iommu_add_device(struct iommu_table_group *table_group, struct device *dev)
1143
1142
{
···
1157
1158
1158
1159
pr_debug("%s: Adding %s to iommu group %d\n",
1159
1160
__func__, dev_name(dev), iommu_group_id(table_group->group));
1160
-
1161
-
return iommu_group_add_device(table_group->group, dev);
1161
+
/*
1162
+
* This is still not adding devices via the IOMMU bus notifier because
1163
+
* of pcibios_init() from arch/powerpc/kernel/pci_64.c which calls
1164
+
* pcibios_scan_phb() first (and this guy adds devices and triggers
1165
+
* the notifier) and only then it calls pci_bus_add_devices() which
1166
+
* configures DMA for buses which also creates PEs and IOMMU groups.
1167
+
*/
1168
+
return iommu_probe_device(dev);
1162
1169
}
1163
1170
EXPORT_SYMBOL_GPL(iommu_add_device);
1164
1171
···
1184
1179
iommu_group_remove_device(dev);
1185
1180
}
1186
1181
EXPORT_SYMBOL_GPL(iommu_del_device);
1182
+
1183
+
/*
1184
+
* A simple iommu_table_group_ops which only allows reusing the existing
1185
+
* iommu_table. This handles VFIO for POWER7 or the nested KVM.
1186
+
* The ops does not allow creating windows and only allows reusing the existing
1187
+
* one if it matches table_group->tce32_start/tce32_size/page_shift.
1188
+
*/
1189
+
static unsigned long spapr_tce_get_table_size(__u32 page_shift,
1190
+
__u64 window_size, __u32 levels)
1191
+
{
1192
+
unsigned long size;
1193
+
1194
+
if (levels > 1)
1195
+
return ~0U;
1196
+
size = window_size >> (page_shift - 3);
1197
+
return size;
1198
+
}
1199
+
1200
+
static long spapr_tce_create_table(struct iommu_table_group *table_group, int num,
1201
+
__u32 page_shift, __u64 window_size, __u32 levels,
1202
+
struct iommu_table **ptbl)
1203
+
{
1204
+
struct iommu_table *tbl = table_group->tables[0];
1205
+
1206
+
if (num > 0)
1207
+
return -EPERM;
1208
+
1209
+
if (tbl->it_page_shift != page_shift ||
1210
+
tbl->it_size != (window_size >> page_shift) ||
1211
+
tbl->it_indirect_levels != levels - 1)
1212
+
return -EINVAL;
1213
+
1214
+
*ptbl = iommu_tce_table_get(tbl);
1215
+
return 0;
1216
+
}
1217
+
1218
+
static long spapr_tce_set_window(struct iommu_table_group *table_group,
1219
+
int num, struct iommu_table *tbl)
1220
+
{
1221
+
return tbl == table_group->tables[num] ? 0 : -EPERM;
1222
+
}
1223
+
1224
+
static long spapr_tce_unset_window(struct iommu_table_group *table_group, int num)
1225
+
{
1226
+
return 0;
1227
+
}
1228
+
1229
+
static long spapr_tce_take_ownership(struct iommu_table_group *table_group)
1230
+
{
1231
+
int i, j, rc = 0;
1232
+
1233
+
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
1234
+
struct iommu_table *tbl = table_group->tables[i];
1235
+
1236
+
if (!tbl || !tbl->it_map)
1237
+
continue;
1238
+
1239
+
rc = iommu_take_ownership(tbl);
1240
+
if (!rc)
1241
+
continue;
1242
+
1243
+
for (j = 0; j < i; ++j)
1244
+
iommu_release_ownership(table_group->tables[j]);
1245
+
return rc;
1246
+
}
1247
+
return 0;
1248
+
}
1249
+
1250
+
static void spapr_tce_release_ownership(struct iommu_table_group *table_group)
1251
+
{
1252
+
int i;
1253
+
1254
+
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
1255
+
struct iommu_table *tbl = table_group->tables[i];
1256
+
1257
+
if (!tbl)
1258
+
continue;
1259
+
1260
+
iommu_table_clear(tbl);
1261
+
if (tbl->it_map)
1262
+
iommu_release_ownership(tbl);
1263
+
}
1264
+
}
1265
+
1266
+
struct iommu_table_group_ops spapr_tce_table_group_ops = {
1267
+
.get_table_size = spapr_tce_get_table_size,
1268
+
.create_table = spapr_tce_create_table,
1269
+
.set_window = spapr_tce_set_window,
1270
+
.unset_window = spapr_tce_unset_window,
1271
+
.take_ownership = spapr_tce_take_ownership,
1272
+
.release_ownership = spapr_tce_release_ownership,
1273
+
};
1274
+
1275
+
/*
1276
+
* A simple iommu_ops to allow less cruft in generic VFIO code.
1277
+
*/
1278
+
static int spapr_tce_blocking_iommu_attach_dev(struct iommu_domain *dom,
1279
+
struct device *dev)
1280
+
{
1281
+
struct iommu_group *grp = iommu_group_get(dev);
1282
+
struct iommu_table_group *table_group;
1283
+
int ret = -EINVAL;
1284
+
1285
+
if (!grp)
1286
+
return -ENODEV;
1287
+
1288
+
table_group = iommu_group_get_iommudata(grp);
1289
+
ret = table_group->ops->take_ownership(table_group);
1290
+
iommu_group_put(grp);
1291
+
1292
+
return ret;
1293
+
}
1294
+
1295
+
static void spapr_tce_blocking_iommu_set_platform_dma(struct device *dev)
1296
+
{
1297
+
struct iommu_group *grp = iommu_group_get(dev);
1298
+
struct iommu_table_group *table_group;
1299
+
1300
+
table_group = iommu_group_get_iommudata(grp);
1301
+
table_group->ops->release_ownership(table_group);
1302
+
}
1303
+
1304
+
static const struct iommu_domain_ops spapr_tce_blocking_domain_ops = {
1305
+
.attach_dev = spapr_tce_blocking_iommu_attach_dev,
1306
+
};
1307
+
1308
+
static bool spapr_tce_iommu_capable(struct device *dev, enum iommu_cap cap)
1309
+
{
1310
+
switch (cap) {
1311
+
case IOMMU_CAP_CACHE_COHERENCY:
1312
+
return true;
1313
+
default:
1314
+
break;
1315
+
}
1316
+
1317
+
return false;
1318
+
}
1319
+
1320
+
static struct iommu_domain *spapr_tce_iommu_domain_alloc(unsigned int type)
1321
+
{
1322
+
struct iommu_domain *dom;
1323
+
1324
+
if (type != IOMMU_DOMAIN_BLOCKED)
1325
+
return NULL;
1326
+
1327
+
dom = kzalloc(sizeof(*dom), GFP_KERNEL);
1328
+
if (!dom)
1329
+
return NULL;
1330
+
1331
+
dom->ops = &spapr_tce_blocking_domain_ops;
1332
+
1333
+
return dom;
1334
+
}
1335
+
1336
+
static struct iommu_device *spapr_tce_iommu_probe_device(struct device *dev)
1337
+
{
1338
+
struct pci_dev *pdev;
1339
+
struct pci_controller *hose;
1340
+
1341
+
if (!dev_is_pci(dev))
1342
+
return ERR_PTR(-EPERM);
1343
+
1344
+
pdev = to_pci_dev(dev);
1345
+
hose = pdev->bus->sysdata;
1346
+
1347
+
return &hose->iommu;
1348
+
}
1349
+
1350
+
static void spapr_tce_iommu_release_device(struct device *dev)
1351
+
{
1352
+
}
1353
+
1354
+
static struct iommu_group *spapr_tce_iommu_device_group(struct device *dev)
1355
+
{
1356
+
struct pci_controller *hose;
1357
+
struct pci_dev *pdev;
1358
+
1359
+
pdev = to_pci_dev(dev);
1360
+
hose = pdev->bus->sysdata;
1361
+
1362
+
if (!hose->controller_ops.device_group)
1363
+
return ERR_PTR(-ENOENT);
1364
+
1365
+
return hose->controller_ops.device_group(hose, pdev);
1366
+
}
1367
+
1368
+
static const struct iommu_ops spapr_tce_iommu_ops = {
1369
+
.capable = spapr_tce_iommu_capable,
1370
+
.domain_alloc = spapr_tce_iommu_domain_alloc,
1371
+
.probe_device = spapr_tce_iommu_probe_device,
1372
+
.release_device = spapr_tce_iommu_release_device,
1373
+
.device_group = spapr_tce_iommu_device_group,
1374
+
.set_platform_dma_ops = spapr_tce_blocking_iommu_set_platform_dma,
1375
+
};
1376
+
1377
+
static struct attribute *spapr_tce_iommu_attrs[] = {
1378
+
NULL,
1379
+
};
1380
+
1381
+
static struct attribute_group spapr_tce_iommu_group = {
1382
+
.name = "spapr-tce-iommu",
1383
+
.attrs = spapr_tce_iommu_attrs,
1384
+
};
1385
+
1386
+
static const struct attribute_group *spapr_tce_iommu_groups[] = {
1387
+
&spapr_tce_iommu_group,
1388
+
NULL,
1389
+
};
1390
+
1391
+
/*
1392
+
* This registers IOMMU devices of PHBs. This needs to happen
1393
+
* after core_initcall(iommu_init) + postcore_initcall(pci_driver_init) and
1394
+
* before subsys_initcall(iommu_subsys_init).
1395
+
*/
1396
+
static int __init spapr_tce_setup_phb_iommus_initcall(void)
1397
+
{
1398
+
struct pci_controller *hose;
1399
+
1400
+
list_for_each_entry(hose, &hose_list, list_node) {
1401
+
iommu_device_sysfs_add(&hose->iommu, hose->parent,
1402
+
spapr_tce_iommu_groups, "iommu-phb%04x",
1403
+
hose->global_number);
1404
+
iommu_device_register(&hose->iommu, &spapr_tce_iommu_ops,
1405
+
hose->parent);
1406
+
}
1407
+
return 0;
1408
+
}
1409
+
postcore_initcall_sync(spapr_tce_setup_phb_iommus_initcall);
1410
+
1187
1411
#endif /* CONFIG_IOMMU_API */
+8
arch/powerpc/kernel/irq.c
+8
arch/powerpc/kernel/irq.c
···
206
206
asm volatile (
207
207
PPC_STLU " %%r1, %[offset](%[sp]) ;"
208
208
"mr %%r1, %[sp] ;"
209
+
#ifdef CONFIG_PPC_KERNEL_PCREL
210
+
"bl %[callee]@notoc ;"
211
+
#else
209
212
"bl %[callee] ;"
213
+
#endif
210
214
PPC_LL " %%r1, 0(%%r1) ;"
211
215
: // Outputs
212
216
: // Inputs
···
263
259
PPC_STLU " %%r1, %[offset](%[sp]) ;"
264
260
"mr %%r4, %%r1 ;"
265
261
"mr %%r1, %[sp] ;"
262
+
#ifdef CONFIG_PPC_KERNEL_PCREL
263
+
"bl %[callee]@notoc ;"
264
+
#else
266
265
"bl %[callee] ;"
266
+
#endif
267
267
PPC_LL " %%r1, 0(%%r1) ;"
268
268
: // Outputs
269
269
"+r" (r3)
+3
-7
arch/powerpc/kernel/irq_64.c
+3
-7
arch/powerpc/kernel/irq_64.c
···
348
348
* already the case when ppc_md.power_save is called). The function
349
349
* will return whether to enter power save or just return.
350
350
*
351
-
* In the former case, it will have notified lockdep of interrupts
352
-
* being re-enabled and generally sanitized the lazy irq state,
353
-
* and in the latter case it will leave with interrupts hard
351
+
* In the former case, it will have generally sanitized the lazy irq
352
+
* state, and in the latter case it will leave with interrupts hard
354
353
* disabled and marked as such, so the local_irq_enable() call
355
354
* in arch_cpu_idle() will properly re-enable everything.
356
355
*/
357
-
bool prep_irq_for_idle(void)
356
+
__cpuidle bool prep_irq_for_idle(void)
358
357
{
359
358
/*
360
359
* First we need to hard disable to ensure no interrupt
···
368
369
*/
369
370
if (lazy_irq_pending())
370
371
return false;
371
-
372
-
/* Tell lockdep we are about to re-enable */
373
-
trace_hardirqs_on();
374
372
375
373
/*
376
374
* Mark interrupts as soft-enabled and clear the
+40
-132
arch/powerpc/kernel/isa-bridge.c
+40
-132
arch/powerpc/kernel/isa-bridge.c
···
55
55
}
56
56
}
57
57
58
-
static void pci_process_ISA_OF_ranges(struct device_node *isa_node,
59
-
unsigned long phb_io_base_phys)
58
+
static int process_ISA_OF_ranges(struct device_node *isa_node,
59
+
unsigned long phb_io_base_phys)
60
60
{
61
-
/* We should get some saner parsing here and remove these structs */
62
-
struct pci_address {
63
-
u32 a_hi;
64
-
u32 a_mid;
65
-
u32 a_lo;
66
-
};
67
-
68
-
struct isa_address {
69
-
u32 a_hi;
70
-
u32 a_lo;
71
-
};
72
-
73
-
struct isa_range {
74
-
struct isa_address isa_addr;
75
-
struct pci_address pci_addr;
76
-
unsigned int size;
77
-
};
78
-
79
-
const struct isa_range *range;
80
-
unsigned long pci_addr;
81
-
unsigned int isa_addr;
82
61
unsigned int size;
83
-
int rlen = 0;
62
+
struct of_range_parser parser;
63
+
struct of_range range;
84
64
85
-
range = of_get_property(isa_node, "ranges", &rlen);
86
-
if (range == NULL || (rlen < sizeof(struct isa_range)))
65
+
if (of_range_parser_init(&parser, isa_node))
87
66
goto inval_range;
88
67
89
-
/* From "ISA Binding to 1275"
90
-
* The ranges property is laid out as an array of elements,
91
-
* each of which comprises:
92
-
* cells 0 - 1: an ISA address
93
-
* cells 2 - 4: a PCI address
94
-
* (size depending on dev->n_addr_cells)
95
-
* cell 5: the size of the range
96
-
*/
97
-
if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO) {
98
-
range++;
99
-
rlen -= sizeof(struct isa_range);
100
-
if (rlen < sizeof(struct isa_range))
101
-
goto inval_range;
68
+
for_each_of_range(&parser, &range) {
69
+
if ((range.flags & ISA_SPACE_MASK) != ISA_SPACE_IO)
70
+
continue;
71
+
72
+
if (range.cpu_addr == OF_BAD_ADDR) {
73
+
pr_err("ISA: Bad CPU mapping: %s\n", __func__);
74
+
return -EINVAL;
75
+
}
76
+
77
+
/* We need page alignment */
78
+
if ((range.bus_addr & ~PAGE_MASK) || (range.cpu_addr & ~PAGE_MASK)) {
79
+
pr_warn("ISA: bridge %pOF has non aligned IO range\n", isa_node);
80
+
return -EINVAL;
81
+
}
82
+
83
+
/* Align size and make sure it's cropped to 64K */
84
+
size = PAGE_ALIGN(range.size);
85
+
if (size > 0x10000)
86
+
size = 0x10000;
87
+
88
+
if (!phb_io_base_phys)
89
+
phb_io_base_phys = range.cpu_addr;
90
+
91
+
remap_isa_base(phb_io_base_phys, size);
92
+
return 0;
102
93
}
103
-
if ((range->isa_addr.a_hi & ISA_SPACE_MASK) != ISA_SPACE_IO)
104
-
goto inval_range;
105
-
106
-
isa_addr = range->isa_addr.a_lo;
107
-
pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
108
-
range->pci_addr.a_lo;
109
-
110
-
/* Assume these are both zero. Note: We could fix that and
111
-
* do a proper parsing instead ... oh well, that will do for
112
-
* now as nobody uses fancy mappings for ISA bridges
113
-
*/
114
-
if ((pci_addr != 0) || (isa_addr != 0)) {
115
-
printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
116
-
__func__);
117
-
return;
118
-
}
119
-
120
-
/* Align size and make sure it's cropped to 64K */
121
-
size = PAGE_ALIGN(range->size);
122
-
if (size > 0x10000)
123
-
size = 0x10000;
124
-
125
-
remap_isa_base(phb_io_base_phys, size);
126
-
return;
127
94
128
95
inval_range:
129
-
printk(KERN_ERR "no ISA IO ranges or unexpected isa range, "
130
-
"mapping 64k\n");
131
-
remap_isa_base(phb_io_base_phys, 0x10000);
96
+
if (!phb_io_base_phys) {
97
+
pr_err("no ISA IO ranges or unexpected isa range, mapping 64k\n");
98
+
remap_isa_base(phb_io_base_phys, 0x10000);
99
+
}
100
+
return 0;
132
101
}
133
102
134
103
···
139
170
isa_bridge_devnode = np;
140
171
141
172
/* Now parse the "ranges" property and setup the ISA mapping */
142
-
pci_process_ISA_OF_ranges(np, hose->io_base_phys);
173
+
process_ISA_OF_ranges(np, hose->io_base_phys);
143
174
144
175
/* Set the global ISA io base to indicate we have an ISA bridge */
145
176
isa_io_base = ISA_IO_BASE;
···
155
186
*/
156
187
void __init isa_bridge_init_non_pci(struct device_node *np)
157
188
{
158
-
const __be32 *ranges, *pbasep = NULL;
159
-
int rlen, i, rs;
160
-
u32 na, ns, pna;
161
-
u64 cbase, pbase, size = 0;
189
+
int ret;
162
190
163
191
/* If we already have an ISA bridge, bail off */
164
192
if (isa_bridge_devnode != NULL)
165
193
return;
166
194
167
-
pna = of_n_addr_cells(np);
168
-
if (of_property_read_u32(np, "#address-cells", &na) ||
169
-
of_property_read_u32(np, "#size-cells", &ns)) {
170
-
pr_warn("ISA: Non-PCI bridge %pOF is missing address format\n",
171
-
np);
195
+
ret = process_ISA_OF_ranges(np, 0);
196
+
if (ret)
172
197
return;
173
-
}
174
-
175
-
/* Check it's a supported address format */
176
-
if (na != 2 || ns != 1) {
177
-
pr_warn("ISA: Non-PCI bridge %pOF has unsupported address format\n",
178
-
np);
179
-
return;
180
-
}
181
-
rs = na + ns + pna;
182
-
183
-
/* Grab the ranges property */
184
-
ranges = of_get_property(np, "ranges", &rlen);
185
-
if (ranges == NULL || rlen < rs) {
186
-
pr_warn("ISA: Non-PCI bridge %pOF has absent or invalid ranges\n",
187
-
np);
188
-
return;
189
-
}
190
-
191
-
/* Parse it. We are only looking for IO space */
192
-
for (i = 0; (i + rs - 1) < rlen; i += rs) {
193
-
if (be32_to_cpup(ranges + i) != 1)
194
-
continue;
195
-
cbase = be32_to_cpup(ranges + i + 1);
196
-
size = of_read_number(ranges + i + na + pna, ns);
197
-
pbasep = ranges + i + na;
198
-
break;
199
-
}
200
-
201
-
/* Got something ? */
202
-
if (!size || !pbasep) {
203
-
pr_warn("ISA: Non-PCI bridge %pOF has no usable IO range\n",
204
-
np);
205
-
return;
206
-
}
207
-
208
-
/* Align size and make sure it's cropped to 64K */
209
-
size = PAGE_ALIGN(size);
210
-
if (size > 0x10000)
211
-
size = 0x10000;
212
-
213
-
/* Map pbase */
214
-
pbase = of_translate_address(np, pbasep);
215
-
if (pbase == OF_BAD_ADDR) {
216
-
pr_warn("ISA: Non-PCI bridge %pOF failed to translate IO base\n",
217
-
np);
218
-
return;
219
-
}
220
-
221
-
/* We need page alignment */
222
-
if ((cbase & ~PAGE_MASK) || (pbase & ~PAGE_MASK)) {
223
-
pr_warn("ISA: Non-PCI bridge %pOF has non aligned IO range\n",
224
-
np);
225
-
return;
226
-
}
227
198
228
199
/* Got it */
229
200
isa_bridge_devnode = np;
···
172
263
* and map it
173
264
*/
174
265
isa_io_base = ISA_IO_BASE;
175
-
remap_isa_base(pbase, size);
176
266
177
267
pr_debug("ISA: Non-PCI bridge is %pOF\n", np);
178
268
}
···
190
282
isa_bridge_pcidev = pdev;
191
283
192
284
/* Now parse the "ranges" property and setup the ISA mapping */
193
-
pci_process_ISA_OF_ranges(devnode, hose->io_base_phys);
285
+
process_ISA_OF_ranges(devnode, hose->io_base_phys);
194
286
195
287
/* Set the global ISA io base to indicate we have an ISA bridge */
196
288
isa_io_base = ISA_IO_BASE;
+5
-5
arch/powerpc/kernel/legacy_serial.c
+5
-5
arch/powerpc/kernel/legacy_serial.c
···
171
171
/* We only support ports that have a clock frequency properly
172
172
* encoded in the device-tree.
173
173
*/
174
-
if (of_get_property(np, "clock-frequency", NULL) == NULL)
174
+
if (!of_property_present(np, "clock-frequency"))
175
175
return -1;
176
176
177
177
/* if reg-offset don't try to use it */
178
-
if ((of_get_property(np, "reg-offset", NULL) != NULL))
178
+
if (of_property_present(np, "reg-offset"))
179
179
return -1;
180
180
181
181
/* if rtas uses this device, don't try to use it as well */
182
-
if (of_get_property(np, "used-by-rtas", NULL) != NULL)
182
+
if (of_property_read_bool(np, "used-by-rtas"))
183
183
return -1;
184
184
185
185
/* Get the address */
···
237
237
* Note: Don't even try on P8 lpc, we know it's not directly mapped
238
238
*/
239
239
if (!of_device_is_compatible(isa_brg, "ibm,power8-lpc") ||
240
-
of_get_property(isa_brg, "ranges", NULL)) {
240
+
of_property_present(isa_brg, "ranges")) {
241
241
taddr = of_translate_address(np, reg);
242
242
if (taddr == OF_BAD_ADDR)
243
243
taddr = 0;
···
268
268
* compatible UARTs on PCI need all sort of quirks (port offsets
269
269
* etc...) that this code doesn't know about
270
270
*/
271
-
if (of_get_property(np, "clock-frequency", NULL) == NULL)
271
+
if (!of_property_present(np, "clock-frequency"))
272
272
return -1;
273
273
274
274
/* Get the PCI address. Assume BAR 0 */
+1
-1
arch/powerpc/kernel/misc_64.S
+1
-1
arch/powerpc/kernel/misc_64.S
+336
-43
arch/powerpc/kernel/module_64.c
+336
-43
arch/powerpc/kernel/module_64.c
···
101
101
/* Like PPC32, we need little trampolines to do > 24-bit jumps (into
102
102
the kernel itself). But on PPC64, these need to be used for every
103
103
jump, actually, to reset r2 (TOC+0x8000). */
104
-
struct ppc64_stub_entry
105
-
{
106
-
/* 28 byte jump instruction sequence (7 instructions). We only
107
-
* need 6 instructions on ABIv2 but we always allocate 7 so
108
-
* so we don't have to modify the trampoline load instruction. */
104
+
struct ppc64_stub_entry {
105
+
/*
106
+
* 28 byte jump instruction sequence (7 instructions) that can
107
+
* hold ppc64_stub_insns or stub_insns. Must be 8-byte aligned
108
+
* with PCREL kernels that use prefix instructions in the stub.
109
+
*/
109
110
u32 jump[7];
110
111
/* Used by ftrace to identify stubs */
111
112
u32 magic;
112
113
/* Data for the above code */
113
114
func_desc_t funcdata;
115
+
} __aligned(8);
116
+
117
+
struct ppc64_got_entry {
118
+
u64 addr;
114
119
};
115
120
116
121
/*
117
122
* PPC64 uses 24 bit jumps, but we need to jump into other modules or
118
123
* the kernel which may be further. So we jump to a stub.
119
124
*
120
-
* For ELFv1 we need to use this to set up the new r2 value (aka TOC
121
-
* pointer). For ELFv2 it's the callee's responsibility to set up the
122
-
* new r2, but for both we need to save the old r2.
125
+
* Target address and TOC are loaded from function descriptor in the
126
+
* ppc64_stub_entry.
123
127
*
124
-
* We could simply patch the new r2 value and function pointer into
125
-
* the stub, but it's significantly shorter to put these values at the
126
-
* end of the stub code, and patch the stub address (32-bits relative
127
-
* to the TOC ptr, r2) into the stub.
128
+
* r12 is used to generate the target address, which is required for the
129
+
* ELFv2 global entry point calling convention.
130
+
*
131
+
* TOC handling:
132
+
* - PCREL does not have a TOC.
133
+
* - ELFv2 non-PCREL just has to save r2, the callee is responsible for
134
+
* setting its own TOC pointer at the global entry address.
135
+
* - ELFv1 must load the new TOC pointer from the function descriptor.
128
136
*/
129
137
static u32 ppc64_stub_insns[] = {
138
+
#ifdef CONFIG_PPC_KERNEL_PCREL
139
+
/* pld r12,addr */
140
+
PPC_PREFIX_8LS | __PPC_PRFX_R(1),
141
+
PPC_INST_PLD | ___PPC_RT(_R12),
142
+
#else
130
143
PPC_RAW_ADDIS(_R11, _R2, 0),
131
144
PPC_RAW_ADDI(_R11, _R11, 0),
132
145
/* Save current r2 value in magic place on the stack. */
···
149
136
/* Set up new r2 from function descriptor */
150
137
PPC_RAW_LD(_R2, _R11, 40),
151
138
#endif
139
+
#endif
152
140
PPC_RAW_MTCTR(_R12),
153
141
PPC_RAW_BCTR(),
154
142
};
155
143
156
-
/* Count how many different 24-bit relocations (different symbol,
157
-
different addend) */
158
-
static unsigned int count_relocs(const Elf64_Rela *rela, unsigned int num)
144
+
/*
145
+
* Count how many different r_type relocations (different symbol,
146
+
* different addend).
147
+
*/
148
+
static unsigned int count_relocs(const Elf64_Rela *rela, unsigned int num,
149
+
unsigned long r_type)
159
150
{
160
151
unsigned int i, r_info, r_addend, _count_relocs;
161
152
···
168
151
r_info = 0;
169
152
r_addend = 0;
170
153
for (i = 0; i < num; i++)
171
-
/* Only count 24-bit relocs, others don't need stubs */
172
-
if (ELF64_R_TYPE(rela[i].r_info) == R_PPC_REL24 &&
154
+
/* Only count r_type relocs, others don't need stubs */
155
+
if (ELF64_R_TYPE(rela[i].r_info) == r_type &&
173
156
(r_info != ELF64_R_SYM(rela[i].r_info) ||
174
157
r_addend != rela[i].r_addend)) {
175
158
_count_relocs++;
···
230
213
231
214
relocs += count_relocs((void *)sechdrs[i].sh_addr,
232
215
sechdrs[i].sh_size
233
-
/ sizeof(Elf64_Rela));
216
+
/ sizeof(Elf64_Rela),
217
+
R_PPC_REL24);
218
+
#ifdef CONFIG_PPC_KERNEL_PCREL
219
+
relocs += count_relocs((void *)sechdrs[i].sh_addr,
220
+
sechdrs[i].sh_size
221
+
/ sizeof(Elf64_Rela),
222
+
R_PPC64_REL24_NOTOC);
223
+
#endif
234
224
}
235
225
}
236
226
···
253
229
pr_debug("Looks like a total of %lu stubs, max\n", relocs);
254
230
return relocs * sizeof(struct ppc64_stub_entry);
255
231
}
232
+
233
+
#ifdef CONFIG_PPC_KERNEL_PCREL
234
+
static int count_pcpu_relocs(const Elf64_Shdr *sechdrs,
235
+
const Elf64_Rela *rela, unsigned int num,
236
+
unsigned int symindex, unsigned int pcpu)
237
+
{
238
+
unsigned int i, r_info, r_addend, _count_relocs;
239
+
240
+
_count_relocs = 0;
241
+
r_info = 0;
242
+
r_addend = 0;
243
+
244
+
for (i = 0; i < num; i++) {
245
+
Elf64_Sym *sym;
246
+
247
+
/* This is the symbol it is referring to */
248
+
sym = (Elf64_Sym *)sechdrs[symindex].sh_addr
249
+
+ ELF64_R_SYM(rela[i].r_info);
250
+
251
+
if (sym->st_shndx == pcpu &&
252
+
(r_info != ELF64_R_SYM(rela[i].r_info) ||
253
+
r_addend != rela[i].r_addend)) {
254
+
_count_relocs++;
255
+
r_info = ELF64_R_SYM(rela[i].r_info);
256
+
r_addend = rela[i].r_addend;
257
+
}
258
+
}
259
+
260
+
return _count_relocs;
261
+
}
262
+
263
+
/* Get size of potential GOT required. */
264
+
static unsigned long get_got_size(const Elf64_Ehdr *hdr,
265
+
const Elf64_Shdr *sechdrs,
266
+
struct module *me)
267
+
{
268
+
/* One extra reloc so it's always 0-addr terminated */
269
+
unsigned long relocs = 1;
270
+
unsigned int i, symindex = 0;
271
+
272
+
for (i = 1; i < hdr->e_shnum; i++) {
273
+
if (sechdrs[i].sh_type == SHT_SYMTAB) {
274
+
symindex = i;
275
+
break;
276
+
}
277
+
}
278
+
WARN_ON_ONCE(!symindex);
279
+
280
+
/* Every relocated section... */
281
+
for (i = 1; i < hdr->e_shnum; i++) {
282
+
if (sechdrs[i].sh_type == SHT_RELA) {
283
+
pr_debug("Found relocations in section %u\n", i);
284
+
pr_debug("Ptr: %p. Number: %llu\n", (void *)sechdrs[i].sh_addr,
285
+
sechdrs[i].sh_size / sizeof(Elf64_Rela));
286
+
287
+
/*
288
+
* Sort the relocation information based on a symbol and
289
+
* addend key. This is a stable O(n*log n) complexity
290
+
* algorithm but it will reduce the complexity of
291
+
* count_relocs() to linear complexity O(n)
292
+
*/
293
+
sort((void *)sechdrs[i].sh_addr,
294
+
sechdrs[i].sh_size / sizeof(Elf64_Rela),
295
+
sizeof(Elf64_Rela), relacmp, NULL);
296
+
297
+
relocs += count_relocs((void *)sechdrs[i].sh_addr,
298
+
sechdrs[i].sh_size
299
+
/ sizeof(Elf64_Rela),
300
+
R_PPC64_GOT_PCREL34);
301
+
302
+
/*
303
+
* Percpu data access typically gets linked with
304
+
* REL34 relocations, but the percpu section gets
305
+
* moved at load time and requires that to be
306
+
* converted to GOT linkage.
307
+
*/
308
+
if (IS_ENABLED(CONFIG_SMP) && symindex)
309
+
relocs += count_pcpu_relocs(sechdrs,
310
+
(void *)sechdrs[i].sh_addr,
311
+
sechdrs[i].sh_size
312
+
/ sizeof(Elf64_Rela),
313
+
symindex, me->arch.pcpu_section);
314
+
}
315
+
}
316
+
317
+
pr_debug("Looks like a total of %lu GOT entries, max\n", relocs);
318
+
return relocs * sizeof(struct ppc64_got_entry);
319
+
}
320
+
#else /* CONFIG_PPC_KERNEL_PCREL */
256
321
257
322
/* Still needed for ELFv2, for .TOC. */
258
323
static void dedotify_versions(struct modversion_info *vers,
···
392
279
}
393
280
return NULL;
394
281
}
282
+
#endif /* CONFIG_PPC_KERNEL_PCREL */
395
283
396
284
bool module_init_section(const char *name)
397
285
{
···
411
297
for (i = 1; i < hdr->e_shnum; i++) {
412
298
if (strcmp(secstrings + sechdrs[i].sh_name, ".stubs") == 0)
413
299
me->arch.stubs_section = i;
300
+
#ifdef CONFIG_PPC_KERNEL_PCREL
301
+
else if (strcmp(secstrings + sechdrs[i].sh_name, ".data..percpu") == 0)
302
+
me->arch.pcpu_section = i;
303
+
else if (strcmp(secstrings + sechdrs[i].sh_name, ".mygot") == 0) {
304
+
me->arch.got_section = i;
305
+
if (sechdrs[i].sh_addralign < 8)
306
+
sechdrs[i].sh_addralign = 8;
307
+
}
308
+
#else
414
309
else if (strcmp(secstrings + sechdrs[i].sh_name, ".toc") == 0) {
415
310
me->arch.toc_section = i;
416
311
if (sechdrs[i].sh_addralign < 8)
···
434
311
sechdrs[i].sh_size / sizeof(Elf64_Sym),
435
312
(void *)hdr
436
313
+ sechdrs[sechdrs[i].sh_link].sh_offset);
314
+
#endif
437
315
}
438
316
439
317
if (!me->arch.stubs_section) {
···
442
318
return -ENOEXEC;
443
319
}
444
320
321
+
#ifdef CONFIG_PPC_KERNEL_PCREL
322
+
if (!me->arch.got_section) {
323
+
pr_err("%s: doesn't contain .mygot.\n", me->name);
324
+
return -ENOEXEC;
325
+
}
326
+
327
+
/* Override the got size */
328
+
sechdrs[me->arch.got_section].sh_size = get_got_size(hdr, sechdrs, me);
329
+
#else
445
330
/* If we don't have a .toc, just use .stubs. We need to set r2
446
331
to some reasonable value in case the module calls out to
447
332
other functions via a stub, or if a function pointer escapes
448
333
the module by some means. */
449
334
if (!me->arch.toc_section)
450
335
me->arch.toc_section = me->arch.stubs_section;
336
+
#endif
451
337
452
338
/* Override the stubs size */
453
339
sechdrs[me->arch.stubs_section].sh_size = get_stubs_size(hdr, sechdrs);
340
+
454
341
return 0;
455
342
}
456
343
457
344
#ifdef CONFIG_MPROFILE_KERNEL
458
345
459
346
static u32 stub_insns[] = {
347
+
#ifdef CONFIG_PPC_KERNEL_PCREL
348
+
PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernelbase)),
349
+
PPC_RAW_NOP(), /* align the prefix insn */
350
+
/* paddi r12,r12,addr */
351
+
PPC_PREFIX_MLS | __PPC_PRFX_R(0),
352
+
PPC_INST_PADDI | ___PPC_RT(_R12) | ___PPC_RA(_R12),
353
+
PPC_RAW_MTCTR(_R12),
354
+
PPC_RAW_BCTR(),
355
+
#else
460
356
PPC_RAW_LD(_R12, _R13, offsetof(struct paca_struct, kernel_toc)),
461
357
PPC_RAW_ADDIS(_R12, _R12, 0),
462
358
PPC_RAW_ADDI(_R12, _R12, 0),
463
359
PPC_RAW_MTCTR(_R12),
464
360
PPC_RAW_BCTR(),
361
+
#endif
465
362
};
466
363
467
364
/*
···
503
358
{
504
359
long reladdr;
505
360
506
-
memcpy(entry->jump, stub_insns, sizeof(stub_insns));
507
-
508
-
/* Stub uses address relative to kernel toc (from the paca) */
509
-
reladdr = addr - kernel_toc_addr();
510
-
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
511
-
pr_err("%s: Address of %ps out of range of kernel_toc.\n",
512
-
me->name, (void *)addr);
361
+
if ((unsigned long)entry->jump % 8 != 0) {
362
+
pr_err("%s: Address of stub entry is not 8-byte aligned\n", me->name);
513
363
return 0;
514
364
}
515
365
516
-
entry->jump[1] |= PPC_HA(reladdr);
517
-
entry->jump[2] |= PPC_LO(reladdr);
366
+
BUILD_BUG_ON(sizeof(stub_insns) > sizeof(entry->jump));
367
+
memcpy(entry->jump, stub_insns, sizeof(stub_insns));
368
+
369
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) {
370
+
/* Stub uses address relative to kernel base (from the paca) */
371
+
reladdr = addr - local_paca->kernelbase;
372
+
if (reladdr > 0x1FFFFFFFFL || reladdr < -0x200000000L) {
373
+
pr_err("%s: Address of %ps out of range of 34-bit relative address.\n",
374
+
me->name, (void *)addr);
375
+
return 0;
376
+
}
377
+
378
+
entry->jump[2] |= IMM_H18(reladdr);
379
+
entry->jump[3] |= IMM_L(reladdr);
380
+
} else {
381
+
/* Stub uses address relative to kernel toc (from the paca) */
382
+
reladdr = addr - kernel_toc_addr();
383
+
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
384
+
pr_err("%s: Address of %ps out of range of kernel_toc.\n",
385
+
me->name, (void *)addr);
386
+
return 0;
387
+
}
388
+
389
+
entry->jump[1] |= PPC_HA(reladdr);
390
+
entry->jump[2] |= PPC_LO(reladdr);
391
+
}
518
392
519
393
/* Even though we don't use funcdata in the stub, it's needed elsewhere. */
520
394
entry->funcdata = func_desc(addr);
···
579
415
*/
580
416
static inline unsigned long my_r2(const Elf64_Shdr *sechdrs, struct module *me)
581
417
{
418
+
#ifndef CONFIG_PPC_KERNEL_PCREL
582
419
return (sechdrs[me->arch.toc_section].sh_addr & ~0xfful) + 0x8000;
420
+
#else
421
+
return -1;
422
+
#endif
583
423
}
584
424
585
425
/* Patch stub to reference function and correct r2 value. */
···
600
432
if (is_mprofile_ftrace_call(name))
601
433
return create_ftrace_stub(entry, addr, me);
602
434
435
+
if ((unsigned long)entry->jump % 8 != 0) {
436
+
pr_err("%s: Address of stub entry is not 8-byte aligned\n", me->name);
437
+
return 0;
438
+
}
439
+
440
+
BUILD_BUG_ON(sizeof(ppc64_stub_insns) > sizeof(entry->jump));
603
441
for (i = 0; i < ARRAY_SIZE(ppc64_stub_insns); i++) {
604
442
if (patch_instruction(&entry->jump[i],
605
443
ppc_inst(ppc64_stub_insns[i])))
606
444
return 0;
607
445
}
608
446
609
-
/* Stub uses address relative to r2. */
610
-
reladdr = (unsigned long)entry - my_r2(sechdrs, me);
611
-
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
612
-
pr_err("%s: Address %p of stub out of range of %p.\n",
613
-
me->name, (void *)reladdr, (void *)my_r2);
614
-
return 0;
447
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) {
448
+
/* Stub uses address relative to itself! */
449
+
reladdr = 0 + offsetof(struct ppc64_stub_entry, funcdata);
450
+
BUILD_BUG_ON(reladdr != 32);
451
+
if (reladdr > 0x1FFFFFFFFL || reladdr < -0x200000000L) {
452
+
pr_err("%s: Address of %p out of range of 34-bit relative address.\n",
453
+
me->name, (void *)reladdr);
454
+
return 0;
455
+
}
456
+
pr_debug("Stub %p get data from reladdr %li\n", entry, reladdr);
457
+
458
+
/* May not even need this if we're relative to 0 */
459
+
if (patch_instruction(&entry->jump[0],
460
+
ppc_inst_prefix(entry->jump[0] | IMM_H18(reladdr),
461
+
entry->jump[1] | IMM_L(reladdr))))
462
+
return 0;
463
+
464
+
} else {
465
+
/* Stub uses address relative to r2. */
466
+
reladdr = (unsigned long)entry - my_r2(sechdrs, me);
467
+
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
468
+
pr_err("%s: Address %p of stub out of range of %p.\n",
469
+
me->name, (void *)reladdr, (void *)my_r2);
470
+
return 0;
471
+
}
472
+
pr_debug("Stub %p get data from reladdr %li\n", entry, reladdr);
473
+
474
+
if (patch_instruction(&entry->jump[0],
475
+
ppc_inst(entry->jump[0] | PPC_HA(reladdr))))
476
+
return 0;
477
+
478
+
if (patch_instruction(&entry->jump[1],
479
+
ppc_inst(entry->jump[1] | PPC_LO(reladdr))))
480
+
return 0;
615
481
}
616
-
pr_debug("Stub %p get data from reladdr %li\n", entry, reladdr);
617
-
618
-
if (patch_instruction(&entry->jump[0],
619
-
ppc_inst(entry->jump[0] | PPC_HA(reladdr))))
620
-
return 0;
621
-
622
-
if (patch_instruction(&entry->jump[1],
623
-
ppc_inst(entry->jump[1] | PPC_LO(reladdr))))
624
-
return 0;
625
482
626
483
// func_desc_t is 8 bytes if ABIv2, else 16 bytes
627
484
desc = func_desc(addr);
···
690
497
return (unsigned long)&stubs[i];
691
498
}
692
499
500
+
#ifdef CONFIG_PPC_KERNEL_PCREL
501
+
/* Create GOT to load the location described in this ptr */
502
+
static unsigned long got_for_addr(const Elf64_Shdr *sechdrs,
503
+
unsigned long addr,
504
+
struct module *me,
505
+
const char *name)
506
+
{
507
+
struct ppc64_got_entry *got;
508
+
unsigned int i, num_got;
509
+
510
+
if (!IS_ENABLED(CONFIG_PPC_KERNEL_PCREL))
511
+
return addr;
512
+
513
+
num_got = sechdrs[me->arch.got_section].sh_size / sizeof(*got);
514
+
515
+
/* Find this stub, or if that fails, the next avail. entry */
516
+
got = (void *)sechdrs[me->arch.got_section].sh_addr;
517
+
for (i = 0; got[i].addr; i++) {
518
+
if (WARN_ON(i >= num_got))
519
+
return 0;
520
+
521
+
if (got[i].addr == addr)
522
+
return (unsigned long)&got[i];
523
+
}
524
+
525
+
got[i].addr = addr;
526
+
527
+
return (unsigned long)&got[i];
528
+
}
529
+
#endif
530
+
693
531
/* We expect a noop next: if it is, replace it with instruction to
694
532
restore r2. */
695
533
static int restore_r2(const char *name, u32 *instruction, struct module *me)
696
534
{
697
535
u32 *prev_insn = instruction - 1;
698
536
u32 insn_val = *instruction;
537
+
538
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL))
539
+
return 0;
699
540
700
541
if (is_mprofile_ftrace_call(name))
701
542
return 0;
···
776
549
pr_debug("Applying ADD relocate section %u to %u\n", relsec,
777
550
sechdrs[relsec].sh_info);
778
551
552
+
#ifndef CONFIG_PPC_KERNEL_PCREL
779
553
/* First time we're called, we can fix up .TOC. */
780
554
if (!me->arch.toc_fixed) {
781
555
sym = find_dot_toc(sechdrs, strtab, symindex);
···
786
558
sym->st_value = my_r2(sechdrs, me);
787
559
me->arch.toc_fixed = true;
788
560
}
789
-
561
+
#endif
790
562
for (i = 0; i < sechdrs[relsec].sh_size / sizeof(*rela); i++) {
791
563
/* This is where to make the change */
792
564
location = (void *)sechdrs[sechdrs[relsec].sh_info].sh_addr
···
814
586
*(unsigned long *)location = value;
815
587
break;
816
588
589
+
#ifndef CONFIG_PPC_KERNEL_PCREL
817
590
case R_PPC64_TOC:
818
591
*(unsigned long *)location = my_r2(sechdrs, me);
819
592
break;
···
874
645
= (*((uint16_t *) location) & ~0xffff)
875
646
| (value & 0xffff);
876
647
break;
648
+
#endif
877
649
878
650
case R_PPC_REL24:
651
+
#ifdef CONFIG_PPC_KERNEL_PCREL
652
+
/* PCREL still generates REL24 for mcount */
653
+
case R_PPC64_REL24_NOTOC:
654
+
#endif
879
655
/* FIXME: Handle weak symbols here --RR */
880
656
if (sym->st_shndx == SHN_UNDEF ||
881
657
sym->st_shndx == SHN_LIVEPATCH) {
···
928
694
*(u32 *)location = value;
929
695
break;
930
696
697
+
#ifdef CONFIG_PPC_KERNEL_PCREL
698
+
case R_PPC64_PCREL34: {
699
+
unsigned long absvalue = value;
700
+
701
+
/* Convert value to relative */
702
+
value -= (unsigned long)location;
703
+
704
+
if (value + 0x200000000 > 0x3ffffffff) {
705
+
if (sym->st_shndx != me->arch.pcpu_section) {
706
+
pr_err("%s: REL34 %li out of range!\n",
707
+
me->name, (long)value);
708
+
return -ENOEXEC;
709
+
}
710
+
711
+
/*
712
+
* per-cpu section is special cased because
713
+
* it is moved during loading, so has to be
714
+
* converted to use GOT.
715
+
*/
716
+
value = got_for_addr(sechdrs, absvalue, me,
717
+
strtab + sym->st_name);
718
+
if (!value)
719
+
return -ENOENT;
720
+
value -= (unsigned long)location;
721
+
722
+
/* Turn pla into pld */
723
+
if (patch_instruction((u32 *)location,
724
+
ppc_inst_prefix((*(u32 *)location & ~0x02000000),
725
+
(*((u32 *)location + 1) & ~0xf8000000) | 0xe4000000)))
726
+
return -EFAULT;
727
+
}
728
+
729
+
if (patch_instruction((u32 *)location,
730
+
ppc_inst_prefix((*(u32 *)location & ~0x3ffff) | IMM_H18(value),
731
+
(*((u32 *)location + 1) & ~0xffff) | IMM_L(value))))
732
+
return -EFAULT;
733
+
734
+
break;
735
+
}
736
+
737
+
#else
931
738
case R_PPC64_TOCSAVE:
932
739
/*
933
740
* Marker reloc indicates we don't have to save r2.
···
976
701
* it.
977
702
*/
978
703
break;
704
+
#endif
979
705
980
706
case R_PPC64_ENTRY:
707
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL))
708
+
break;
709
+
981
710
/*
982
711
* Optimize ELFv2 large code model entry point if
983
712
* the TOC is within 2GB range of current location.
···
1023
744
= (*((uint16_t *) location) & ~0xffff)
1024
745
| (value & 0xffff);
1025
746
break;
747
+
748
+
#ifdef CONFIG_PPC_KERNEL_PCREL
749
+
case R_PPC64_GOT_PCREL34:
750
+
value = got_for_addr(sechdrs, value, me,
751
+
strtab + sym->st_name);
752
+
if (!value)
753
+
return -ENOENT;
754
+
value -= (unsigned long)location;
755
+
((uint32_t *)location)[0] = (((uint32_t *)location)[0] & ~0x3ffff) |
756
+
((value >> 16) & 0x3ffff);
757
+
((uint32_t *)location)[1] = (((uint32_t *)location)[1] & ~0xffff) |
758
+
(value & 0xffff);
759
+
break;
760
+
#endif
1026
761
1027
762
default:
1028
763
pr_err("%s: Unknown ADD relocation: %lu\n",
+2
arch/powerpc/kernel/paca.c
+2
arch/powerpc/kernel/paca.c
···
191
191
#endif
192
192
new_paca->lock_token = 0x8000;
193
193
new_paca->paca_index = cpu;
194
+
#ifndef CONFIG_PPC_KERNEL_PCREL
194
195
new_paca->kernel_toc = kernel_toc_addr();
196
+
#endif
195
197
new_paca->kernelbase = (unsigned long) _stext;
196
198
/* Only set MSR:IR/DR when MMU is initialized */
197
199
new_paca->kernel_msr = MSR_KERNEL & ~(MSR_IR | MSR_DR);
+1
-1
arch/powerpc/kernel/pci_64.c
+1
-1
arch/powerpc/kernel/pci_64.c
+69
-57
arch/powerpc/kernel/process.c
+69
-57
arch/powerpc/kernel/process.c
···
1630
1630
}
1631
1631
1632
1632
#ifdef CONFIG_PPC64
1633
-
/**
1633
+
/*
1634
1634
* Assign a TIDR (thread ID) for task @t and set it in the thread
1635
1635
* structure. For now, we only support setting TIDR for 'current' task.
1636
1636
*
···
1738
1738
*/
1739
1739
int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
1740
1740
{
1741
-
unsigned long clone_flags = args->flags;
1742
-
unsigned long usp = args->stack;
1743
-
unsigned long tls = args->tls;
1744
-
struct pt_regs *childregs, *kregs;
1741
+
struct pt_regs *kregs; /* Switch frame regs */
1745
1742
extern void ret_from_fork(void);
1746
1743
extern void ret_from_fork_scv(void);
1747
-
extern void ret_from_kernel_thread(void);
1744
+
extern void ret_from_kernel_user_thread(void);
1745
+
extern void start_kernel_thread(void);
1748
1746
void (*f)(void);
1749
1747
unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1750
-
struct thread_info *ti = task_thread_info(p);
1751
1748
#ifdef CONFIG_HAVE_HW_BREAKPOINT
1752
1749
int i;
1753
1750
#endif
1754
1751
1755
1752
klp_init_thread_info(p);
1756
1753
1757
-
/* Create initial stack frame. */
1758
-
sp -= STACK_USER_INT_FRAME_SIZE;
1759
-
*(unsigned long *)(sp + STACK_INT_FRAME_MARKER) = STACK_FRAME_REGS_MARKER;
1760
-
1761
-
/* Copy registers */
1762
-
childregs = (struct pt_regs *)(sp + STACK_INT_FRAME_REGS);
1763
-
if (unlikely(args->fn)) {
1754
+
if (unlikely(p->flags & PF_KTHREAD)) {
1764
1755
/* kernel thread */
1756
+
1757
+
/* Create initial minimum stack frame. */
1758
+
sp -= STACK_FRAME_MIN_SIZE;
1765
1759
((unsigned long *)sp)[0] = 0;
1766
-
memset(childregs, 0, sizeof(struct pt_regs));
1767
-
childregs->gpr[1] = sp + STACK_USER_INT_FRAME_SIZE;
1768
-
/* function */
1769
-
if (args->fn)
1770
-
childregs->gpr[14] = ppc_function_entry((void *)args->fn);
1771
-
#ifdef CONFIG_PPC64
1772
-
clear_tsk_thread_flag(p, TIF_32BIT);
1773
-
childregs->softe = IRQS_ENABLED;
1774
-
#endif
1775
-
childregs->gpr[15] = (unsigned long)args->fn_arg;
1760
+
1761
+
f = start_kernel_thread;
1776
1762
p->thread.regs = NULL; /* no user register state */
1777
-
ti->flags |= _TIF_RESTOREALL;
1778
-
f = ret_from_kernel_thread;
1763
+
clear_tsk_compat_task(p);
1779
1764
} else {
1780
1765
/* user thread */
1781
-
struct pt_regs *regs = current_pt_regs();
1782
-
*childregs = *regs;
1783
-
if (usp)
1784
-
childregs->gpr[1] = usp;
1785
-
((unsigned long *)sp)[0] = childregs->gpr[1];
1786
-
p->thread.regs = childregs;
1787
-
/* 64s sets this in ret_from_fork */
1788
-
if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64))
1789
-
childregs->gpr[3] = 0; /* Result from fork() */
1790
-
if (clone_flags & CLONE_SETTLS) {
1791
-
if (!is_32bit_task())
1792
-
childregs->gpr[13] = tls;
1766
+
struct pt_regs *childregs;
1767
+
1768
+
/* Create initial user return stack frame. */
1769
+
sp -= STACK_USER_INT_FRAME_SIZE;
1770
+
*(unsigned long *)(sp + STACK_INT_FRAME_MARKER) = STACK_FRAME_REGS_MARKER;
1771
+
1772
+
childregs = (struct pt_regs *)(sp + STACK_INT_FRAME_REGS);
1773
+
1774
+
if (unlikely(args->fn)) {
1775
+
/*
1776
+
* A user space thread, but it first runs a kernel
1777
+
* thread, and then returns as though it had called
1778
+
* execve rather than fork, so user regs will be
1779
+
* filled in (e.g., by kernel_execve()).
1780
+
*/
1781
+
((unsigned long *)sp)[0] = 0;
1782
+
memset(childregs, 0, sizeof(struct pt_regs));
1783
+
#ifdef CONFIG_PPC64
1784
+
childregs->softe = IRQS_ENABLED;
1785
+
#endif
1786
+
f = ret_from_kernel_user_thread;
1787
+
} else {
1788
+
struct pt_regs *regs = current_pt_regs();
1789
+
unsigned long clone_flags = args->flags;
1790
+
unsigned long usp = args->stack;
1791
+
1792
+
/* Copy registers */
1793
+
*childregs = *regs;
1794
+
if (usp)
1795
+
childregs->gpr[1] = usp;
1796
+
((unsigned long *)sp)[0] = childregs->gpr[1];
1797
+
#ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
1798
+
WARN_ON_ONCE(childregs->softe != IRQS_ENABLED);
1799
+
#endif
1800
+
if (clone_flags & CLONE_SETTLS) {
1801
+
unsigned long tls = args->tls;
1802
+
1803
+
if (!is_32bit_task())
1804
+
childregs->gpr[13] = tls;
1805
+
else
1806
+
childregs->gpr[2] = tls;
1807
+
}
1808
+
1809
+
if (trap_is_scv(regs))
1810
+
f = ret_from_fork_scv;
1793
1811
else
1794
-
childregs->gpr[2] = tls;
1812
+
f = ret_from_fork;
1795
1813
}
1796
1814
1797
-
if (trap_is_scv(regs))
1798
-
f = ret_from_fork_scv;
1799
-
else
1800
-
f = ret_from_fork;
1815
+
childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1816
+
p->thread.regs = childregs;
1801
1817
}
1802
-
childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1803
1818
1804
1819
/*
1805
1820
* The way this works is that at some point in the future
···
1828
1813
sp -= STACK_SWITCH_FRAME_SIZE;
1829
1814
((unsigned long *)sp)[0] = sp + STACK_SWITCH_FRAME_SIZE;
1830
1815
kregs = (struct pt_regs *)(sp + STACK_SWITCH_FRAME_REGS);
1816
+
kregs->nip = ppc_function_entry(f);
1817
+
if (unlikely(args->fn)) {
1818
+
/*
1819
+
* Put kthread fn, arg parameters in non-volatile GPRs in the
1820
+
* switch frame so they are loaded by _switch before it returns
1821
+
* to ret_from_kernel_thread.
1822
+
*/
1823
+
kregs->gpr[14] = ppc_function_entry((void *)args->fn);
1824
+
kregs->gpr[15] = (unsigned long)args->fn_arg;
1825
+
}
1831
1826
p->thread.ksp = sp;
1832
1827
1833
1828
#ifdef CONFIG_HAVE_HW_BREAKPOINT
···
1865
1840
p->thread.dscr_inherit = current->thread.dscr_inherit;
1866
1841
p->thread.dscr = mfspr(SPRN_DSCR);
1867
1842
}
1868
-
if (cpu_has_feature(CPU_FTR_HAS_PPR))
1869
-
childregs->ppr = DEFAULT_PPR;
1870
1843
1871
1844
p->thread.tidr = 0;
1872
1845
#endif
1873
-
/*
1874
-
* Run with the current AMR value of the kernel
1875
-
*/
1876
-
#ifdef CONFIG_PPC_PKEY
1877
-
if (mmu_has_feature(MMU_FTR_BOOK3S_KUAP))
1878
-
kregs->amr = AMR_KUAP_BLOCKED;
1879
-
1880
-
if (mmu_has_feature(MMU_FTR_BOOK3S_KUEP))
1881
-
kregs->iamr = AMR_KUEP_BLOCKED;
1882
-
#endif
1883
-
kregs->nip = ppc_function_entry(f);
1884
1846
return 0;
1885
1847
}
1886
1848
+42
-12
arch/powerpc/kernel/rtas.c
+42
-12
arch/powerpc/kernel/rtas.c
···
16
16
#include <linux/init.h>
17
17
#include <linux/kconfig.h>
18
18
#include <linux/kernel.h>
19
+
#include <linux/lockdep.h>
19
20
#include <linux/memblock.h>
20
21
#include <linux/of.h>
21
22
#include <linux/of_fdt.h>
···
69
68
* functions are believed to have no users on
70
69
* ppc64le, and we want to keep it that way. It does
71
70
* not make sense for this to be set when @filter
72
-
* is false.
71
+
* is NULL.
73
72
*/
74
73
struct rtas_function {
75
74
s32 token;
···
454
453
},
455
454
};
456
455
456
+
/*
457
+
* Nearly all RTAS calls need to be serialized. All uses of the
458
+
* default rtas_args block must hold rtas_lock.
459
+
*
460
+
* Exceptions to the RTAS serialization requirement (e.g. stop-self)
461
+
* must use a separate rtas_args structure.
462
+
*/
463
+
static DEFINE_RAW_SPINLOCK(rtas_lock);
464
+
static struct rtas_args rtas_args;
465
+
457
466
/**
458
467
* rtas_function_token() - RTAS function token lookup.
459
468
* @handle: Function handle, e.g. RTAS_FN_EVENT_SCAN.
···
571
560
static void __do_enter_rtas_trace(struct rtas_args *args)
572
561
{
573
562
const char *name = NULL;
563
+
564
+
if (args == &rtas_args)
565
+
lockdep_assert_held(&rtas_lock);
574
566
/*
575
567
* If the tracepoints that consume the function name aren't
576
568
* active, avoid the lookup.
···
632
618
}
633
619
634
620
struct rtas_t rtas;
635
-
636
-
/*
637
-
* Nearly all RTAS calls need to be serialized. All uses of the
638
-
* default rtas_args block must hold rtas_lock.
639
-
*
640
-
* Exceptions to the RTAS serialization requirement (e.g. stop-self)
641
-
* must use a separate rtas_args structure.
642
-
*/
643
-
static DEFINE_RAW_SPINLOCK(rtas_lock);
644
-
static struct rtas_args rtas_args;
645
621
646
622
DEFINE_SPINLOCK(rtas_data_buf_lock);
647
623
EXPORT_SYMBOL_GPL(rtas_data_buf_lock);
···
955
951
u32 bufsz;
956
952
char *buf = NULL;
957
953
954
+
lockdep_assert_held(&rtas_lock);
955
+
958
956
if (token == -1)
959
957
return NULL;
960
958
···
987
981
buf = kmalloc(RTAS_ERROR_LOG_MAX, GFP_ATOMIC);
988
982
}
989
983
if (buf)
990
-
memcpy(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX);
984
+
memmove(buf, rtas_err_buf, RTAS_ERROR_LOG_MAX);
991
985
}
992
986
993
987
return buf;
···
1022
1016
do_enter_rtas(args);
1023
1017
}
1024
1018
1019
+
/**
1020
+
* rtas_call_unlocked() - Invoke an RTAS firmware function without synchronization.
1021
+
* @args: RTAS parameter block to be used for the call, must obey RTAS addressing
1022
+
* constraints.
1023
+
* @token: Identifies the function being invoked.
1024
+
* @nargs: Number of input parameters. Does not include token.
1025
+
* @nret: Number of output parameters, including the call status.
1026
+
* @....: List of @nargs input parameters.
1027
+
*
1028
+
* Invokes the RTAS function indicated by @token, which the caller
1029
+
* should obtain via rtas_function_token().
1030
+
*
1031
+
* This function is similar to rtas_call(), but must be used with a
1032
+
* limited set of RTAS calls specifically exempted from the general
1033
+
* requirement that only one RTAS call may be in progress at any
1034
+
* time. Examples include stop-self and ibm,nmi-interlock.
1035
+
*/
1025
1036
void rtas_call_unlocked(struct rtas_args *args, int token, int nargs, int nret, ...)
1026
1037
{
1027
1038
va_list list;
···
1114
1091
*/
1115
1092
int rtas_call(int token, int nargs, int nret, int *outputs, ...)
1116
1093
{
1094
+
struct pin_cookie cookie;
1117
1095
va_list list;
1118
1096
int i;
1119
1097
unsigned long flags;
···
1141
1117
}
1142
1118
1143
1119
raw_spin_lock_irqsave(&rtas_lock, flags);
1120
+
cookie = lockdep_pin_lock(&rtas_lock);
1121
+
1144
1122
/* We use the global rtas args buffer */
1145
1123
args = &rtas_args;
1146
1124
···
1160
1134
outputs[i] = be32_to_cpu(args->rets[i + 1]);
1161
1135
ret = (nret > 0) ? be32_to_cpu(args->rets[0]) : 0;
1162
1136
1137
+
lockdep_unpin_lock(&rtas_lock, cookie);
1163
1138
raw_spin_unlock_irqrestore(&rtas_lock, flags);
1164
1139
1165
1140
if (buff_copy) {
···
1792
1765
/* We assume to be passed big endian arguments */
1793
1766
SYSCALL_DEFINE1(rtas, struct rtas_args __user *, uargs)
1794
1767
{
1768
+
struct pin_cookie cookie;
1795
1769
struct rtas_args args;
1796
1770
unsigned long flags;
1797
1771
char *buff_copy, *errbuf = NULL;
···
1861
1833
buff_copy = get_errorlog_buffer();
1862
1834
1863
1835
raw_spin_lock_irqsave(&rtas_lock, flags);
1836
+
cookie = lockdep_pin_lock(&rtas_lock);
1864
1837
1865
1838
rtas_args = args;
1866
1839
do_enter_rtas(&rtas_args);
···
1872
1843
if (be32_to_cpu(args.rets[0]) == -1)
1873
1844
errbuf = __fetch_rtas_last_error(buff_copy);
1874
1845
1846
+
lockdep_unpin_lock(&rtas_lock, cookie);
1875
1847
raw_spin_unlock_irqrestore(&rtas_lock, flags);
1876
1848
1877
1849
if (buff_copy) {
+7
-6
arch/powerpc/kernel/setup-common.c
+7
-6
arch/powerpc/kernel/setup-common.c
···
630
630
for (machine_id = &__machine_desc_start;
631
631
machine_id < &__machine_desc_end;
632
632
machine_id++) {
633
-
DBG(" %s ...", machine_id->name);
633
+
DBG(" %s ...\n", machine_id->name);
634
+
if (machine_id->compatible && !of_machine_is_compatible(machine_id->compatible))
635
+
continue;
634
636
memcpy(&ppc_md, machine_id, sizeof(struct machdep_calls));
635
-
if (ppc_md.probe()) {
636
-
DBG(" match !\n");
637
-
break;
638
-
}
639
-
DBG("\n");
637
+
if (ppc_md.probe && !ppc_md.probe())
638
+
continue;
639
+
DBG(" %s match !\n", machine_id->name);
640
+
break;
640
641
}
641
642
/* What can we do if we didn't find ? */
642
643
if (machine_id >= &__machine_desc_end) {
+5
-1
arch/powerpc/kernel/time.c
+5
-1
arch/powerpc/kernel/time.c
···
887
887
unsigned shift;
888
888
889
889
/* Normal PowerPC with timebase register */
890
-
ppc_md.calibrate_decr();
890
+
if (ppc_md.calibrate_decr)
891
+
ppc_md.calibrate_decr();
892
+
else
893
+
generic_calibrate_decr();
894
+
891
895
printk(KERN_DEBUG "time_init: decrementer frequency = %lu.%.6lu MHz\n",
892
896
ppc_tb_freq / 1000000, ppc_tb_freq % 1000000);
893
897
printk(KERN_DEBUG "time_init: processor frequency = %lu.%.6lu MHz\n",
+40
-10
arch/powerpc/kernel/trace/ftrace.c
+40
-10
arch/powerpc/kernel/trace/ftrace.c
···
194
194
* get corrupted.
195
195
*
196
196
* Use a b +8 to jump over the load.
197
+
* XXX: could make PCREL depend on MPROFILE_KERNEL
198
+
* XXX: check PCREL && MPROFILE_KERNEL calling sequence
197
199
*/
198
200
if (IS_ENABLED(CONFIG_MPROFILE_KERNEL) || IS_ENABLED(CONFIG_PPC32))
199
201
pop = ppc_inst(PPC_RAW_NOP());
···
727
725
{
728
726
int i;
729
727
unsigned int *tramp[] = { ftrace_tramp_text, ftrace_tramp_init };
728
+
#ifdef CONFIG_PPC_KERNEL_PCREL
729
+
u32 stub_insns[] = {
730
+
/* pla r12,addr */
731
+
PPC_PREFIX_MLS | __PPC_PRFX_R(1),
732
+
PPC_INST_PADDI | ___PPC_RT(_R12),
733
+
PPC_RAW_MTCTR(_R12),
734
+
PPC_RAW_BCTR()
735
+
};
736
+
#else
730
737
u32 stub_insns[] = {
731
738
PPC_RAW_LD(_R12, _R13, PACATOC),
732
739
PPC_RAW_ADDIS(_R12, _R12, 0),
···
743
732
PPC_RAW_MTCTR(_R12),
744
733
PPC_RAW_BCTR()
745
734
};
735
+
#endif
736
+
746
737
unsigned long addr;
747
738
long reladdr;
748
739
···
753
740
else
754
741
addr = ppc_global_function_entry((void *)ftrace_caller);
755
742
756
-
reladdr = addr - kernel_toc_addr();
743
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) {
744
+
for (i = 0; i < 2; i++) {
745
+
reladdr = addr - (unsigned long)tramp[i];
757
746
758
-
if (reladdr >= SZ_2G || reladdr < -(long)SZ_2G) {
759
-
pr_err("Address of %ps out of range of kernel_toc.\n",
747
+
if (reladdr >= (long)SZ_8G || reladdr < -(long)SZ_8G) {
748
+
pr_err("Address of %ps out of range of pcrel address.\n",
749
+
(void *)addr);
750
+
return -1;
751
+
}
752
+
753
+
memcpy(tramp[i], stub_insns, sizeof(stub_insns));
754
+
tramp[i][0] |= IMM_H18(reladdr);
755
+
tramp[i][1] |= IMM_L(reladdr);
756
+
add_ftrace_tramp((unsigned long)tramp[i]);
757
+
}
758
+
} else {
759
+
reladdr = addr - kernel_toc_addr();
760
+
761
+
if (reladdr >= (long)SZ_2G || reladdr < -(long)SZ_2G) {
762
+
pr_err("Address of %ps out of range of kernel_toc.\n",
760
763
(void *)addr);
761
-
return -1;
762
-
}
764
+
return -1;
765
+
}
763
766
764
-
for (i = 0; i < 2; i++) {
765
-
memcpy(tramp[i], stub_insns, sizeof(stub_insns));
766
-
tramp[i][1] |= PPC_HA(reladdr);
767
-
tramp[i][2] |= PPC_LO(reladdr);
768
-
add_ftrace_tramp((unsigned long)tramp[i]);
767
+
for (i = 0; i < 2; i++) {
768
+
memcpy(tramp[i], stub_insns, sizeof(stub_insns));
769
+
tramp[i][1] |= PPC_HA(reladdr);
770
+
tramp[i][2] |= PPC_LO(reladdr);
771
+
add_ftrace_tramp((unsigned long)tramp[i]);
772
+
}
769
773
}
770
774
771
775
return 0;
+5
-1
arch/powerpc/kernel/vdso/gettimeofday.S
+5
-1
arch/powerpc/kernel/vdso/gettimeofday.S
···
38
38
.else
39
39
addi r4, r5, VDSO_DATA_OFFSET
40
40
.endif
41
-
bl DOTSYM(\funct)
41
+
#ifdef __powerpc64__
42
+
bl CFUNC(DOTSYM(\funct))
43
+
#else
44
+
bl \funct
45
+
#endif
42
46
PPC_LL r0, PPC_MIN_STKFRM + PPC_LR_STKOFF(r1)
43
47
#ifdef __powerpc64__
44
48
PPC_LL r2, PPC_MIN_STKFRM + STK_GOT(r1)
+6
arch/powerpc/kernel/vector.S
+6
arch/powerpc/kernel/vector.S
···
177
177
fphalf:
178
178
.quad 0x3fe0000000000000 /* 0.5 */
179
179
180
+
#ifdef CONFIG_PPC_KERNEL_PCREL
181
+
#define LDCONST(fr, name) \
182
+
pla r11,name@pcrel; \
183
+
lfd fr,0(r11)
184
+
#else
180
185
#define LDCONST(fr, name) \
181
186
addis r11,r2,name@toc@ha; \
182
187
lfd fr,name@toc@l(r11)
188
+
#endif
183
189
#endif
184
190
.text
185
191
/*
+6
arch/powerpc/kernel/vmlinux.lds.S
+6
arch/powerpc/kernel/vmlinux.lds.S
···
169
169
}
170
170
171
171
#else /* CONFIG_PPC32 */
172
+
#ifndef CONFIG_PPC_KERNEL_PCREL
172
173
.toc1 : AT(ADDR(.toc1) - LOAD_OFFSET) {
173
174
*(.toc1)
174
175
}
176
+
#endif
175
177
176
178
.got : AT(ADDR(.got) - LOAD_OFFSET) ALIGN(256) {
179
+
#ifdef CONFIG_PPC_KERNEL_PCREL
180
+
*(.got)
181
+
#else
177
182
*(.got .toc)
183
+
#endif
178
184
}
179
185
180
186
SOFT_MASK_TABLE(8)
+43
-21
arch/powerpc/kvm/book3s.c
+43
-21
arch/powerpc/kvm/book3s.c
···
188
188
}
189
189
EXPORT_SYMBOL_GPL(kvmppc_book3s_queue_irqprio);
190
190
191
-
void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu, ulong flags)
191
+
void kvmppc_core_queue_machine_check(struct kvm_vcpu *vcpu, ulong srr1_flags)
192
192
{
193
193
/* might as well deliver this straight away */
194
-
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_MACHINE_CHECK, flags);
194
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_MACHINE_CHECK, srr1_flags);
195
195
}
196
196
EXPORT_SYMBOL_GPL(kvmppc_core_queue_machine_check);
197
197
···
201
201
}
202
202
EXPORT_SYMBOL(kvmppc_core_queue_syscall);
203
203
204
-
void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong flags)
204
+
void kvmppc_core_queue_program(struct kvm_vcpu *vcpu, ulong srr1_flags)
205
205
{
206
206
/* might as well deliver this straight away */
207
-
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_PROGRAM, flags);
207
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_PROGRAM, srr1_flags);
208
208
}
209
209
EXPORT_SYMBOL_GPL(kvmppc_core_queue_program);
210
210
211
-
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu)
211
+
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
212
212
{
213
213
/* might as well deliver this straight away */
214
-
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, 0);
214
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, srr1_flags);
215
215
}
216
216
217
-
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu)
217
+
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
218
218
{
219
219
/* might as well deliver this straight away */
220
-
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_ALTIVEC, 0);
220
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_ALTIVEC, srr1_flags);
221
221
}
222
222
223
-
void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu)
223
+
void kvmppc_core_queue_vsx_unavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
224
224
{
225
225
/* might as well deliver this straight away */
226
-
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_VSX, 0);
226
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_VSX, srr1_flags);
227
227
}
228
228
229
229
void kvmppc_core_queue_dec(struct kvm_vcpu *vcpu)
···
278
278
kvmppc_book3s_dequeue_irqprio(vcpu, BOOK3S_INTERRUPT_EXTERNAL);
279
279
}
280
280
281
-
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, ulong dar,
282
-
ulong flags)
281
+
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, ulong srr1_flags,
282
+
ulong dar, ulong dsisr)
283
283
{
284
284
kvmppc_set_dar(vcpu, dar);
285
-
kvmppc_set_dsisr(vcpu, flags);
286
-
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE, 0);
285
+
kvmppc_set_dsisr(vcpu, dsisr);
286
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_DATA_STORAGE, srr1_flags);
287
287
}
288
288
EXPORT_SYMBOL_GPL(kvmppc_core_queue_data_storage);
289
289
290
-
void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong flags)
290
+
void kvmppc_core_queue_inst_storage(struct kvm_vcpu *vcpu, ulong srr1_flags)
291
291
{
292
-
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_INST_STORAGE, flags);
292
+
kvmppc_inject_interrupt(vcpu, BOOK3S_INTERRUPT_INST_STORAGE, srr1_flags);
293
293
}
294
294
EXPORT_SYMBOL_GPL(kvmppc_core_queue_inst_storage);
295
295
···
481
481
return r;
482
482
}
483
483
484
+
/*
485
+
* Returns prefixed instructions with the prefix in the high 32 bits
486
+
* of *inst and suffix in the low 32 bits. This is the same convention
487
+
* as used in HEIR, vcpu->arch.last_inst and vcpu->arch.emul_inst.
488
+
* Like vcpu->arch.last_inst but unlike vcpu->arch.emul_inst, each
489
+
* half of the value needs byte-swapping if the guest endianness is
490
+
* different from the host endianness.
491
+
*/
484
492
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
485
-
enum instruction_fetch_type type, u32 *inst)
493
+
enum instruction_fetch_type type, unsigned long *inst)
486
494
{
487
495
ulong pc = kvmppc_get_pc(vcpu);
488
496
int r;
497
+
u32 iw;
489
498
490
499
if (type == INST_SC)
491
500
pc -= 4;
492
501
493
-
r = kvmppc_ld(vcpu, &pc, sizeof(u32), inst, false);
494
-
if (r == EMULATE_DONE)
495
-
return r;
496
-
else
502
+
r = kvmppc_ld(vcpu, &pc, sizeof(u32), &iw, false);
503
+
if (r != EMULATE_DONE)
497
504
return EMULATE_AGAIN;
505
+
/*
506
+
* If [H]SRR1 indicates that the instruction that caused the
507
+
* current interrupt is a prefixed instruction, get the suffix.
508
+
*/
509
+
if (kvmppc_get_msr(vcpu) & SRR1_PREFIXED) {
510
+
u32 suffix;
511
+
pc += 4;
512
+
r = kvmppc_ld(vcpu, &pc, sizeof(u32), &suffix, false);
513
+
if (r != EMULATE_DONE)
514
+
return EMULATE_AGAIN;
515
+
*inst = ((u64)iw << 32) | suffix;
516
+
} else {
517
+
*inst = iw;
518
+
}
519
+
return r;
498
520
}
499
521
EXPORT_SYMBOL_GPL(kvmppc_load_last_inst);
500
522
+20
-6
arch/powerpc/kvm/book3s_64_mmu_hv.c
+20
-6
arch/powerpc/kvm/book3s_64_mmu_hv.c
···
415
415
* embodied here.) If the instruction isn't a load or store, then
416
416
* this doesn't return anything useful.
417
417
*/
418
-
static int instruction_is_store(unsigned int instr)
418
+
static int instruction_is_store(ppc_inst_t instr)
419
419
{
420
420
unsigned int mask;
421
+
unsigned int suffix;
421
422
422
423
mask = 0x10000000;
423
-
if ((instr & 0xfc000000) == 0x7c000000)
424
+
suffix = ppc_inst_val(instr);
425
+
if (ppc_inst_prefixed(instr))
426
+
suffix = ppc_inst_suffix(instr);
427
+
else if ((suffix & 0xfc000000) == 0x7c000000)
424
428
mask = 0x100; /* major opcode 31 */
425
-
return (instr & mask) != 0;
429
+
return (suffix & mask) != 0;
426
430
}
427
431
428
432
int kvmppc_hv_emulate_mmio(struct kvm_vcpu *vcpu,
429
433
unsigned long gpa, gva_t ea, int is_store)
430
434
{
431
-
u32 last_inst;
435
+
ppc_inst_t last_inst;
436
+
bool is_prefixed = !!(kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
432
437
433
438
/*
434
439
* Fast path - check if the guest physical address corresponds to a
···
448
443
NULL);
449
444
srcu_read_unlock(&vcpu->kvm->srcu, idx);
450
445
if (!ret) {
451
-
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
446
+
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + (is_prefixed ? 8 : 4));
452
447
return RESUME_GUEST;
453
448
}
454
449
}
···
463
458
/*
464
459
* WARNING: We do not know for sure whether the instruction we just
465
460
* read from memory is the same that caused the fault in the first
466
-
* place. If the instruction we read is neither an load or a store,
461
+
* place.
462
+
*
463
+
* If the fault is prefixed but the instruction is not or vice
464
+
* versa, try again so that we don't advance pc the wrong amount.
465
+
*/
466
+
if (ppc_inst_prefixed(last_inst) != is_prefixed)
467
+
return RESUME_GUEST;
468
+
469
+
/*
470
+
* If the instruction we read is neither an load or a store,
467
471
* then it can't access memory, so we don't need to worry about
468
472
* enforcing access permissions. So, assuming it is a load or
469
473
* store, we just check that its direction (load or store) is
+9
-4
arch/powerpc/kvm/book3s_64_mmu_radix.c
+9
-4
arch/powerpc/kvm/book3s_64_mmu_radix.c
···
954
954
if (dsisr & DSISR_BADACCESS) {
955
955
/* Reflect to the guest as DSI */
956
956
pr_err("KVM: Got radix HV page fault with DSISR=%lx\n", dsisr);
957
-
kvmppc_core_queue_data_storage(vcpu, ea, dsisr);
957
+
kvmppc_core_queue_data_storage(vcpu,
958
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
959
+
ea, dsisr);
958
960
return RESUME_GUEST;
959
961
}
960
962
···
981
979
* Bad address in guest page table tree, or other
982
980
* unusual error - reflect it to the guest as DSI.
983
981
*/
984
-
kvmppc_core_queue_data_storage(vcpu, ea, dsisr);
982
+
kvmppc_core_queue_data_storage(vcpu,
983
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
984
+
ea, dsisr);
985
985
return RESUME_GUEST;
986
986
}
987
987
return kvmppc_hv_emulate_mmio(vcpu, gpa, ea, writing);
···
992
988
if (memslot->flags & KVM_MEM_READONLY) {
993
989
if (writing) {
994
990
/* give the guest a DSI */
995
-
kvmppc_core_queue_data_storage(vcpu, ea, DSISR_ISSTORE |
996
-
DSISR_PROTFAULT);
991
+
kvmppc_core_queue_data_storage(vcpu,
992
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
993
+
ea, DSISR_ISSTORE | DSISR_PROTFAULT);
997
994
return RESUME_GUEST;
998
995
}
999
996
kvm_ro = true;
+32
-15
arch/powerpc/kvm/book3s_hv.c
+32
-15
arch/powerpc/kvm/book3s_hv.c
···
477
477
for (r = 0; r < vcpu->arch.slb_max; ++r)
478
478
pr_err(" ESID = %.16llx VSID = %.16llx\n",
479
479
vcpu->arch.slb[r].orige, vcpu->arch.slb[r].origv);
480
-
pr_err("lpcr = %.16lx sdr1 = %.16lx last_inst = %.8x\n",
480
+
pr_err("lpcr = %.16lx sdr1 = %.16lx last_inst = %.16lx\n",
481
481
vcpu->arch.vcore->lpcr, vcpu->kvm->arch.sdr1,
482
482
vcpu->arch.last_inst);
483
483
}
···
1415
1415
1416
1416
static int kvmppc_emulate_debug_inst(struct kvm_vcpu *vcpu)
1417
1417
{
1418
-
u32 last_inst;
1418
+
ppc_inst_t last_inst;
1419
1419
1420
1420
if (kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst) !=
1421
1421
EMULATE_DONE) {
···
1426
1426
return RESUME_GUEST;
1427
1427
}
1428
1428
1429
-
if (last_inst == KVMPPC_INST_SW_BREAKPOINT) {
1429
+
if (ppc_inst_val(last_inst) == KVMPPC_INST_SW_BREAKPOINT) {
1430
1430
vcpu->run->exit_reason = KVM_EXIT_DEBUG;
1431
1431
vcpu->run->debug.arch.address = kvmppc_get_pc(vcpu);
1432
1432
return RESUME_HOST;
1433
1433
} else {
1434
-
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
1434
+
kvmppc_core_queue_program(vcpu, SRR1_PROGILL |
1435
+
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
1435
1436
return RESUME_GUEST;
1436
1437
}
1437
1438
}
···
1480
1479
unsigned long arg;
1481
1480
struct kvm *kvm = vcpu->kvm;
1482
1481
struct kvm_vcpu *tvcpu;
1482
+
ppc_inst_t pinst;
1483
1483
1484
-
if (kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst) != EMULATE_DONE)
1484
+
if (kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst) != EMULATE_DONE)
1485
1485
return RESUME_GUEST;
1486
+
inst = ppc_inst_val(pinst);
1486
1487
if (get_op(inst) != 31)
1487
1488
return EMULATE_FAIL;
1488
1489
rb = get_rb(inst);
···
1636
1633
* so that it knows that the machine check occurred.
1637
1634
*/
1638
1635
if (!vcpu->kvm->arch.fwnmi_enabled) {
1639
-
ulong flags = vcpu->arch.shregs.msr & 0x083c0000;
1636
+
ulong flags = (vcpu->arch.shregs.msr & 0x083c0000) |
1637
+
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
1640
1638
kvmppc_core_queue_machine_check(vcpu, flags);
1641
1639
r = RESUME_GUEST;
1642
1640
break;
···
1666
1662
* as a result of a hypervisor emulation interrupt
1667
1663
* (e40) getting turned into a 700 by BML RTAS.
1668
1664
*/
1669
-
flags = vcpu->arch.shregs.msr & 0x1f0000ull;
1665
+
flags = (vcpu->arch.shregs.msr & 0x1f0000ull) |
1666
+
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
1670
1667
kvmppc_core_queue_program(vcpu, flags);
1671
1668
r = RESUME_GUEST;
1672
1669
break;
···
1748
1743
1749
1744
if (!(vcpu->arch.fault_dsisr & (DSISR_NOHPTE | DSISR_PROTFAULT))) {
1750
1745
kvmppc_core_queue_data_storage(vcpu,
1746
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
1751
1747
vcpu->arch.fault_dar, vcpu->arch.fault_dsisr);
1752
1748
r = RESUME_GUEST;
1753
1749
break;
···
1767
1761
r = RESUME_PAGE_FAULT;
1768
1762
} else {
1769
1763
kvmppc_core_queue_data_storage(vcpu,
1764
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
1770
1765
vcpu->arch.fault_dar, err);
1771
1766
r = RESUME_GUEST;
1772
1767
}
···
1795
1788
1796
1789
if (!(vcpu->arch.fault_dsisr & SRR1_ISI_NOPT)) {
1797
1790
kvmppc_core_queue_inst_storage(vcpu,
1798
-
vcpu->arch.fault_dsisr);
1791
+
vcpu->arch.fault_dsisr |
1792
+
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
1799
1793
r = RESUME_GUEST;
1800
1794
break;
1801
1795
}
···
1813
1805
} else if (err == -1) {
1814
1806
r = RESUME_PAGE_FAULT;
1815
1807
} else {
1816
-
kvmppc_core_queue_inst_storage(vcpu, err);
1808
+
kvmppc_core_queue_inst_storage(vcpu,
1809
+
err | (kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
1817
1810
r = RESUME_GUEST;
1818
1811
}
1819
1812
break;
···
1835
1826
if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) {
1836
1827
r = kvmppc_emulate_debug_inst(vcpu);
1837
1828
} else {
1838
-
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
1829
+
kvmppc_core_queue_program(vcpu, SRR1_PROGILL |
1830
+
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
1839
1831
r = RESUME_GUEST;
1840
1832
}
1841
1833
break;
···
1877
1867
r = kvmppc_tm_unavailable(vcpu);
1878
1868
}
1879
1869
if (r == EMULATE_FAIL) {
1880
-
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
1870
+
kvmppc_core_queue_program(vcpu, SRR1_PROGILL |
1871
+
(kvmppc_get_msr(vcpu) & SRR1_PREFIXED));
1881
1872
r = RESUME_GUEST;
1882
1873
}
1883
1874
break;
···
2008
1997
*/
2009
1998
if (!(vcpu->arch.hfscr_permitted & (1UL << cause)) ||
2010
1999
(vcpu->arch.nested_hfscr & (1UL << cause))) {
2000
+
ppc_inst_t pinst;
2011
2001
vcpu->arch.trap = BOOK3S_INTERRUPT_H_EMUL_ASSIST;
2012
2002
2013
2003
/*
2014
2004
* If the fetch failed, return to guest and
2015
2005
* try executing it again.
2016
2006
*/
2017
-
r = kvmppc_get_last_inst(vcpu, INST_GENERIC,
2018
-
&vcpu->arch.emul_inst);
2007
+
r = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
2008
+
vcpu->arch.emul_inst = ppc_inst_val(pinst);
2019
2009
if (r != EMULATE_DONE)
2020
2010
r = RESUME_GUEST;
2021
2011
else
···
2933
2921
2934
2922
/*
2935
2923
* Set the default HFSCR for the guest from the host value.
2936
-
* This value is only used on POWER9.
2937
-
* On POWER9, we want to virtualize the doorbell facility, so we
2924
+
* This value is only used on POWER9 and later.
2925
+
* On >= POWER9, we want to virtualize the doorbell facility, so we
2938
2926
* don't set the HFSCR_MSGP bit, and that causes those instructions
2939
2927
* to trap and then we emulate them.
2940
2928
*/
2941
2929
vcpu->arch.hfscr = HFSCR_TAR | HFSCR_EBB | HFSCR_PM | HFSCR_BHRB |
2942
2930
HFSCR_DSCR | HFSCR_VECVSX | HFSCR_FP;
2931
+
2932
+
/* On POWER10 and later, allow prefixed instructions */
2933
+
if (cpu_has_feature(CPU_FTR_ARCH_31))
2934
+
vcpu->arch.hfscr |= HFSCR_PREFIX;
2935
+
2943
2936
if (cpu_has_feature(CPU_FTR_HVMODE)) {
2944
2937
vcpu->arch.hfscr &= mfspr(SPRN_HFSCR);
2945
2938
#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+6
-3
arch/powerpc/kvm/book3s_hv_nested.c
+6
-3
arch/powerpc/kvm/book3s_hv_nested.c
···
1560
1560
if (!memslot || (memslot->flags & KVM_MEMSLOT_INVALID)) {
1561
1561
if (dsisr & (DSISR_PRTABLE_FAULT | DSISR_BADACCESS)) {
1562
1562
/* unusual error -> reflect to the guest as a DSI */
1563
-
kvmppc_core_queue_data_storage(vcpu, ea, dsisr);
1563
+
kvmppc_core_queue_data_storage(vcpu,
1564
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
1565
+
ea, dsisr);
1564
1566
return RESUME_GUEST;
1565
1567
}
1566
1568
···
1572
1570
if (memslot->flags & KVM_MEM_READONLY) {
1573
1571
if (writing) {
1574
1572
/* Give the guest a DSI */
1575
-
kvmppc_core_queue_data_storage(vcpu, ea,
1576
-
DSISR_ISSTORE | DSISR_PROTFAULT);
1573
+
kvmppc_core_queue_data_storage(vcpu,
1574
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
1575
+
ea, DSISR_ISSTORE | DSISR_PROTFAULT);
1577
1576
return RESUME_GUEST;
1578
1577
}
1579
1578
kvm_ro = true;
+13
-13
arch/powerpc/kvm/book3s_hv_rmhandlers.S
+13
-13
arch/powerpc/kvm/book3s_hv_rmhandlers.S
···
381
381
bne kvm_no_guest
382
382
383
383
li r3,0 /* NULL argument */
384
-
bl hmi_exception_realmode
384
+
bl CFUNC(hmi_exception_realmode)
385
385
/*
386
386
* At this point we have finished executing in the guest.
387
387
* We need to wait for hwthread_req to become zero, since
···
458
458
cmpwi r12, BOOK3S_INTERRUPT_HMI
459
459
bne 55f
460
460
li r3, 0 /* NULL argument */
461
-
bl hmi_exception_realmode
461
+
bl CFUNC(hmi_exception_realmode)
462
462
55:
463
463
/*
464
464
* Ensure that secondary doesn't nap when it has
···
502
502
* *
503
503
*****************************************************************************/
504
504
505
-
.global kvmppc_hv_entry
506
-
kvmppc_hv_entry:
505
+
SYM_CODE_START_LOCAL(kvmppc_hv_entry)
507
506
508
507
/* Required state:
509
508
*
···
858
859
cmpdi r0, 0
859
860
beq 71f
860
861
mr r3, r4
861
-
bl kvmppc_guest_entry_inject_int
862
+
bl CFUNC(kvmppc_guest_entry_inject_int)
862
863
ld r4, HSTATE_KVM_VCPU(r13)
863
864
71:
864
865
ld r6, VCPU_SRR0(r4)
···
939
940
ld r4, VCPU_GPR(R4)(r4)
940
941
HRFI_TO_GUEST
941
942
b .
943
+
SYM_CODE_END(kvmppc_hv_entry)
942
944
943
945
secondary_too_late:
944
946
li r12, 0
···
1071
1071
/* Save HEIR (HV emulation assist reg) in emul_inst
1072
1072
if this is an HEI (HV emulation interrupt, e40) */
1073
1073
li r3,KVM_INST_FETCH_FAILED
1074
-
stw r3,VCPU_LAST_INST(r9)
1074
+
std r3,VCPU_LAST_INST(r9)
1075
1075
cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1076
1076
bne 11f
1077
1077
mfspr r3,SPRN_HEIR
1078
-
11: stw r3,VCPU_HEIR(r9)
1078
+
11: std r3,VCPU_HEIR(r9)
1079
1079
1080
1080
/* these are volatile across C function calls */
1081
1081
mfctr r3
···
1544
1544
/* External interrupt, first check for host_ipi. If this is
1545
1545
* set, we know the host wants us out so let's do it now
1546
1546
*/
1547
-
bl kvmppc_read_intr
1547
+
bl CFUNC(kvmppc_read_intr)
1548
1548
1549
1549
/*
1550
1550
* Restore the active volatile registers after returning from
···
1626
1626
/* Search the hash table. */
1627
1627
mr r3, r9 /* vcpu pointer */
1628
1628
li r7, 1 /* data fault */
1629
-
bl kvmppc_hpte_hv_fault
1629
+
bl CFUNC(kvmppc_hpte_hv_fault)
1630
1630
ld r9, HSTATE_KVM_VCPU(r13)
1631
1631
ld r10, VCPU_PC(r9)
1632
1632
ld r11, VCPU_MSR(r9)
···
1676
1676
mtmsrd r3
1677
1677
1678
1678
/* Store the result */
1679
-
stw r8, VCPU_LAST_INST(r9)
1679
+
std r8, VCPU_LAST_INST(r9)
1680
1680
1681
1681
/* Unset guest mode. */
1682
1682
li r0, KVM_GUEST_MODE_HOST_HV
···
1702
1702
mr r4, r10
1703
1703
mr r6, r11
1704
1704
li r7, 0 /* instruction fault */
1705
-
bl kvmppc_hpte_hv_fault
1705
+
bl CFUNC(kvmppc_hpte_hv_fault)
1706
1706
ld r9, HSTATE_KVM_VCPU(r13)
1707
1707
ld r10, VCPU_PC(r9)
1708
1708
ld r11, VCPU_MSR(r9)
···
2342
2342
lbz r0, HSTATE_PTID(r13)
2343
2343
cmpwi r0, 0
2344
2344
bne guest_exit_cont
2345
-
bl kvmppc_realmode_hmi_handler
2345
+
bl CFUNC(kvmppc_realmode_hmi_handler)
2346
2346
ld r9, HSTATE_KVM_VCPU(r13)
2347
2347
li r12, BOOK3S_INTERRUPT_HMI
2348
2348
b guest_exit_cont
···
2413
2413
7: mflr r0
2414
2414
std r0, PPC_LR_STKOFF(r1)
2415
2415
stdu r1, -PPC_MIN_STKFRM(r1)
2416
-
bl kvmppc_read_intr
2416
+
bl CFUNC(kvmppc_read_intr)
2417
2417
nop
2418
2418
li r12, BOOK3S_INTERRUPT_EXTERNAL
2419
2419
cmpdi r3, 1
+3
-1
arch/powerpc/kvm/book3s_paired_singles.c
+3
-1
arch/powerpc/kvm/book3s_paired_singles.c
···
621
621
int kvmppc_emulate_paired_single(struct kvm_vcpu *vcpu)
622
622
{
623
623
u32 inst;
624
+
ppc_inst_t pinst;
624
625
enum emulation_result emulated = EMULATE_DONE;
625
626
int ax_rd, ax_ra, ax_rb, ax_rc;
626
627
short full_d;
···
633
632
int i;
634
633
#endif
635
634
636
-
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
635
+
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
636
+
inst = ppc_inst_val(pinst);
637
637
if (emulated != EMULATE_DONE)
638
638
return emulated;
639
639
+14
-12
arch/powerpc/kvm/book3s_pr.c
+14
-12
arch/powerpc/kvm/book3s_pr.c
···
759
759
flags = DSISR_NOHPTE;
760
760
if (data) {
761
761
flags |= vcpu->arch.fault_dsisr & DSISR_ISSTORE;
762
-
kvmppc_core_queue_data_storage(vcpu, eaddr, flags);
762
+
kvmppc_core_queue_data_storage(vcpu, 0, eaddr, flags);
763
763
} else {
764
764
kvmppc_core_queue_inst_storage(vcpu, flags);
765
765
}
···
1044
1044
{
1045
1045
if (fscr & FSCR_SCV)
1046
1046
fscr &= ~FSCR_SCV; /* SCV must not be enabled */
1047
+
/* Prohibit prefixed instructions for now */
1048
+
fscr &= ~FSCR_PREFIX;
1047
1049
if ((vcpu->arch.fscr & FSCR_TAR) && !(fscr & FSCR_TAR)) {
1048
1050
/* TAR got dropped, drop it in shadow too */
1049
1051
kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
···
1081
1079
{
1082
1080
enum emulation_result er;
1083
1081
ulong flags;
1084
-
u32 last_inst;
1082
+
ppc_inst_t last_inst;
1085
1083
int emul, r;
1086
1084
1087
1085
/*
···
1102
1100
if (kvmppc_get_msr(vcpu) & MSR_PR) {
1103
1101
#ifdef EXIT_DEBUG
1104
1102
pr_info("Userspace triggered 0x700 exception at\n 0x%lx (0x%x)\n",
1105
-
kvmppc_get_pc(vcpu), last_inst);
1103
+
kvmppc_get_pc(vcpu), ppc_inst_val(last_inst));
1106
1104
#endif
1107
-
if ((last_inst & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) {
1105
+
if ((ppc_inst_val(last_inst) & 0xff0007ff) != (INS_DCBZ & 0xfffffff7)) {
1108
1106
kvmppc_core_queue_program(vcpu, flags);
1109
1107
return RESUME_GUEST;
1110
1108
}
···
1121
1119
break;
1122
1120
case EMULATE_FAIL:
1123
1121
pr_crit("%s: emulation at %lx failed (%08x)\n",
1124
-
__func__, kvmppc_get_pc(vcpu), last_inst);
1122
+
__func__, kvmppc_get_pc(vcpu), ppc_inst_val(last_inst));
1125
1123
kvmppc_core_queue_program(vcpu, flags);
1126
1124
r = RESUME_GUEST;
1127
1125
break;
···
1238
1236
r = kvmppc_handle_pagefault(vcpu, dar, exit_nr);
1239
1237
srcu_read_unlock(&vcpu->kvm->srcu, idx);
1240
1238
} else {
1241
-
kvmppc_core_queue_data_storage(vcpu, dar, fault_dsisr);
1239
+
kvmppc_core_queue_data_storage(vcpu, 0, dar, fault_dsisr);
1242
1240
r = RESUME_GUEST;
1243
1241
}
1244
1242
break;
···
1283
1281
break;
1284
1282
case BOOK3S_INTERRUPT_SYSCALL:
1285
1283
{
1286
-
u32 last_sc;
1284
+
ppc_inst_t last_sc;
1287
1285
int emul;
1288
1286
1289
1287
/* Get last sc for papr */
···
1298
1296
}
1299
1297
1300
1298
if (vcpu->arch.papr_enabled &&
1301
-
(last_sc == 0x44000022) &&
1299
+
(ppc_inst_val(last_sc) == 0x44000022) &&
1302
1300
!(kvmppc_get_msr(vcpu) & MSR_PR)) {
1303
1301
/* SC 1 papr hypercalls */
1304
1302
ulong cmd = kvmppc_get_gpr(vcpu, 3);
···
1350
1348
{
1351
1349
int ext_msr = 0;
1352
1350
int emul;
1353
-
u32 last_inst;
1351
+
ppc_inst_t last_inst;
1354
1352
1355
1353
if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE) {
1356
1354
/* Do paired single instruction emulation */
···
1384
1382
}
1385
1383
case BOOK3S_INTERRUPT_ALIGNMENT:
1386
1384
{
1387
-
u32 last_inst;
1385
+
ppc_inst_t last_inst;
1388
1386
int emul = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
1389
1387
1390
1388
if (emul == EMULATE_DONE) {
1391
1389
u32 dsisr;
1392
1390
u64 dar;
1393
1391
1394
-
dsisr = kvmppc_alignment_dsisr(vcpu, last_inst);
1395
-
dar = kvmppc_alignment_dar(vcpu, last_inst);
1392
+
dsisr = kvmppc_alignment_dsisr(vcpu, ppc_inst_val(last_inst));
1393
+
dar = kvmppc_alignment_dar(vcpu, ppc_inst_val(last_inst));
1396
1394
1397
1395
kvmppc_set_dsisr(vcpu, dsisr);
1398
1396
kvmppc_set_dar(vcpu, dar);
+1
arch/powerpc/kvm/book3s_rmhandlers.S
+1
arch/powerpc/kvm/book3s_rmhandlers.S
+19
-11
arch/powerpc/kvm/booke.c
+19
-11
arch/powerpc/kvm/booke.c
···
283
283
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DTLB_MISS);
284
284
}
285
285
286
-
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu,
286
+
void kvmppc_core_queue_data_storage(struct kvm_vcpu *vcpu, ulong srr1_flags,
287
287
ulong dear_flags, ulong esr_flags)
288
288
{
289
+
WARN_ON_ONCE(srr1_flags);
289
290
vcpu->arch.queued_dear = dear_flags;
290
291
vcpu->arch.queued_esr = esr_flags;
291
292
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_DATA_STORAGE);
···
317
316
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_PROGRAM);
318
317
}
319
318
320
-
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu)
319
+
void kvmppc_core_queue_fpunavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
321
320
{
321
+
WARN_ON_ONCE(srr1_flags);
322
322
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_FP_UNAVAIL);
323
323
}
324
324
325
325
#ifdef CONFIG_ALTIVEC
326
-
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu)
326
+
void kvmppc_core_queue_vec_unavail(struct kvm_vcpu *vcpu, ulong srr1_flags)
327
327
{
328
+
WARN_ON_ONCE(srr1_flags);
328
329
kvmppc_booke_queue_irqprio(vcpu, BOOKE_IRQPRIO_ALTIVEC_UNAVAIL);
329
330
}
330
331
#endif
···
626
623
spin_unlock_irqrestore(&vcpu->arch.wdt_lock, flags);
627
624
}
628
625
629
-
void kvmppc_watchdog_func(struct timer_list *t)
626
+
static void kvmppc_watchdog_func(struct timer_list *t)
630
627
{
631
628
struct kvm_vcpu *vcpu = from_timer(vcpu, t, arch.wdt_timer);
632
629
u32 tsr, new_tsr;
···
844
841
return RESUME_GUEST;
845
842
846
843
case EMULATE_FAIL:
847
-
printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
844
+
printk(KERN_CRIT "%s: emulation at %lx failed (%08lx)\n",
848
845
__func__, vcpu->arch.regs.nip, vcpu->arch.last_inst);
849
846
/* For debugging, encode the failing instruction and
850
847
* report it to userspace. */
···
1003
1000
}
1004
1001
}
1005
1002
1006
-
/**
1003
+
/*
1007
1004
* kvmppc_handle_exit
1008
1005
*
1009
1006
* Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
···
1015
1012
int s;
1016
1013
int idx;
1017
1014
u32 last_inst = KVM_INST_FETCH_FAILED;
1015
+
ppc_inst_t pinst;
1018
1016
enum emulation_result emulated = EMULATE_DONE;
1019
1017
1020
1018
/* Fix irq state (pairs with kvmppc_fix_ee_before_entry()) */
···
1035
1031
case BOOKE_INTERRUPT_DATA_STORAGE:
1036
1032
case BOOKE_INTERRUPT_DTLB_MISS:
1037
1033
case BOOKE_INTERRUPT_HV_PRIV:
1038
-
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
1034
+
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
1035
+
last_inst = ppc_inst_val(pinst);
1039
1036
break;
1040
1037
case BOOKE_INTERRUPT_PROGRAM:
1041
1038
/* SW breakpoints arrive as illegal instructions on HV */
1042
-
if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1043
-
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
1039
+
if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP) {
1040
+
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
1041
+
last_inst = ppc_inst_val(pinst);
1042
+
}
1044
1043
break;
1045
1044
default:
1046
1045
break;
···
1232
1225
#endif
1233
1226
1234
1227
case BOOKE_INTERRUPT_DATA_STORAGE:
1235
-
kvmppc_core_queue_data_storage(vcpu, vcpu->arch.fault_dear,
1228
+
kvmppc_core_queue_data_storage(vcpu, 0, vcpu->arch.fault_dear,
1236
1229
vcpu->arch.fault_esr);
1237
1230
kvmppc_account_exit(vcpu, DSI_EXITS);
1238
1231
r = RESUME_GUEST;
···
1953
1946
dbg_reg->dbcr0 |= DBCR0_IDM;
1954
1947
return 0;
1955
1948
}
1956
-
void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap, bool set)
1949
+
static void kvm_guest_protect_msr(struct kvm_vcpu *vcpu, ulong prot_bitmap,
1950
+
bool set)
1957
1951
{
1958
1952
/* XXX: Add similar MSR protection for BookE-PR */
1959
1953
#ifdef CONFIG_KVM_BOOKE_HV
+3
arch/powerpc/kvm/booke.h
+3
arch/powerpc/kvm/booke.h
+1
-1
arch/powerpc/kvm/bookehv_interrupts.S
+1
-1
arch/powerpc/kvm/bookehv_interrupts.S
+2
-2
arch/powerpc/kvm/e500_mmu_host.c
+2
-2
arch/powerpc/kvm/e500_mmu_host.c
···
623
623
624
624
#ifdef CONFIG_KVM_BOOKE_HV
625
625
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
626
-
enum instruction_fetch_type type, u32 *instr)
626
+
enum instruction_fetch_type type, unsigned long *instr)
627
627
{
628
628
gva_t geaddr;
629
629
hpa_t addr;
···
713
713
}
714
714
#else
715
715
int kvmppc_load_last_inst(struct kvm_vcpu *vcpu,
716
-
enum instruction_fetch_type type, u32 *instr)
716
+
enum instruction_fetch_type type, unsigned long *instr)
717
717
{
718
718
return EMULATE_AGAIN;
719
719
}
+1
-1
arch/powerpc/kvm/e500mc.c
+1
-1
arch/powerpc/kvm/e500mc.c
+7
-1
arch/powerpc/kvm/emulate.c
+7
-1
arch/powerpc/kvm/emulate.c
···
194
194
int kvmppc_emulate_instruction(struct kvm_vcpu *vcpu)
195
195
{
196
196
u32 inst;
197
+
ppc_inst_t pinst;
197
198
int rs, rt, sprn;
198
199
enum emulation_result emulated;
199
200
int advance = 1;
···
202
201
/* this default type might be overwritten by subcategories */
203
202
kvmppc_set_exit_type(vcpu, EMULATED_INST_EXITS);
204
203
205
-
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &inst);
204
+
emulated = kvmppc_get_last_inst(vcpu, INST_GENERIC, &pinst);
205
+
inst = ppc_inst_val(pinst);
206
206
if (emulated != EMULATE_DONE)
207
207
return emulated;
208
208
···
301
299
trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
302
300
303
301
/* Advance past emulated instruction. */
302
+
/*
303
+
* If this ever handles prefixed instructions, the 4
304
+
* will need to become ppc_inst_len(pinst) instead.
305
+
*/
304
306
if (advance)
305
307
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
306
308
+7
-7
arch/powerpc/kvm/emulate_loadstore.c
+7
-7
arch/powerpc/kvm/emulate_loadstore.c
···
28
28
static bool kvmppc_check_fp_disabled(struct kvm_vcpu *vcpu)
29
29
{
30
30
if (!(kvmppc_get_msr(vcpu) & MSR_FP)) {
31
-
kvmppc_core_queue_fpunavail(vcpu);
31
+
kvmppc_core_queue_fpunavail(vcpu, kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
32
32
return true;
33
33
}
34
34
···
40
40
static bool kvmppc_check_vsx_disabled(struct kvm_vcpu *vcpu)
41
41
{
42
42
if (!(kvmppc_get_msr(vcpu) & MSR_VSX)) {
43
-
kvmppc_core_queue_vsx_unavail(vcpu);
43
+
kvmppc_core_queue_vsx_unavail(vcpu, kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
44
44
return true;
45
45
}
46
46
···
52
52
static bool kvmppc_check_altivec_disabled(struct kvm_vcpu *vcpu)
53
53
{
54
54
if (!(kvmppc_get_msr(vcpu) & MSR_VEC)) {
55
-
kvmppc_core_queue_vec_unavail(vcpu);
55
+
kvmppc_core_queue_vec_unavail(vcpu, kvmppc_get_msr(vcpu) & SRR1_PREFIXED);
56
56
return true;
57
57
}
58
58
···
71
71
*/
72
72
int kvmppc_emulate_loadstore(struct kvm_vcpu *vcpu)
73
73
{
74
-
u32 inst;
74
+
ppc_inst_t inst;
75
75
enum emulation_result emulated = EMULATE_FAIL;
76
76
struct instruction_op op;
77
77
···
93
93
94
94
emulated = EMULATE_FAIL;
95
95
vcpu->arch.regs.msr = vcpu->arch.shared->msr;
96
-
if (analyse_instr(&op, &vcpu->arch.regs, ppc_inst(inst)) == 0) {
96
+
if (analyse_instr(&op, &vcpu->arch.regs, inst) == 0) {
97
97
int type = op.type & INSTR_TYPE_MASK;
98
98
int size = GETSIZE(op.type);
99
99
···
356
356
}
357
357
}
358
358
359
-
trace_kvm_ppc_instr(inst, kvmppc_get_pc(vcpu), emulated);
359
+
trace_kvm_ppc_instr(ppc_inst_val(inst), kvmppc_get_pc(vcpu), emulated);
360
360
361
361
/* Advance past emulated instruction. */
362
362
if (emulated != EMULATE_FAIL)
363
-
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
363
+
kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + ppc_inst_len(inst));
364
364
365
365
return emulated;
366
366
}
+5
-3
arch/powerpc/kvm/powerpc.c
+5
-3
arch/powerpc/kvm/powerpc.c
···
304
304
break;
305
305
case EMULATE_FAIL:
306
306
{
307
-
u32 last_inst;
307
+
ppc_inst_t last_inst;
308
308
309
309
kvmppc_get_last_inst(vcpu, INST_GENERIC, &last_inst);
310
310
kvm_debug_ratelimited("Guest access to device memory using unsupported instruction (opcode: %#08x)\n",
311
-
last_inst);
311
+
ppc_inst_val(last_inst));
312
312
313
313
/*
314
314
* Injecting a Data Storage here is a bit more
···
321
321
if (vcpu->mmio_is_write)
322
322
dsisr |= DSISR_ISSTORE;
323
323
324
-
kvmppc_core_queue_data_storage(vcpu, vcpu->arch.vaddr_accessed, dsisr);
324
+
kvmppc_core_queue_data_storage(vcpu,
325
+
kvmppc_get_msr(vcpu) & SRR1_PREFIXED,
326
+
vcpu->arch.vaddr_accessed, dsisr);
325
327
} else {
326
328
/*
327
329
* BookE does not send a SIGBUS on a bad
+10
arch/powerpc/lib/copypage_64.S
+10
arch/powerpc/lib/copypage_64.S
···
18
18
#endif
19
19
ALT_FTR_SECTION_END_IFCLR(CPU_FTR_VMX_COPY)
20
20
ori r5,r5,PAGE_SIZE@l
21
+
#ifdef CONFIG_PPC_KERNEL_PCREL
22
+
/*
23
+
* Hack for toolchain - prefixed instructions cause label difference to
24
+
* be non-constant even if 8 byte alignment is known, so they can not
25
+
* be put in FTR sections.
26
+
*/
27
+
LOAD_REG_ADDR(r10, ppc64_caches)
28
+
BEGIN_FTR_SECTION
29
+
#else
21
30
BEGIN_FTR_SECTION
22
31
LOAD_REG_ADDR(r10, ppc64_caches)
32
+
#endif
23
33
lwz r11,DCACHEL1LOGBLOCKSIZE(r10) /* log2 of cache block size */
24
34
lwz r12,DCACHEL1BLOCKSIZE(r10) /* get cache block size */
25
35
li r9,0
+2
-2
arch/powerpc/lib/copypage_power7.S
+2
-2
arch/powerpc/lib/copypage_power7.S
···
45
45
std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
46
46
std r0,16(r1)
47
47
stdu r1,-STACKFRAMESIZE(r1)
48
-
bl enter_vmx_ops
48
+
bl CFUNC(enter_vmx_ops)
49
49
cmpwi r3,0
50
50
ld r0,STACKFRAMESIZE+16(r1)
51
51
ld r3,STK_REG(R31)(r1)
···
88
88
addi r3,r3,128
89
89
bdnz 1b
90
90
91
-
b exit_vmx_ops /* tail call optimise */
91
+
b CFUNC(exit_vmx_ops) /* tail call optimise */
92
92
93
93
#else
94
94
li r0,(PAGE_SIZE/128)
+4
-4
arch/powerpc/lib/copyuser_power7.S
+4
-4
arch/powerpc/lib/copyuser_power7.S
···
47
47
ld r15,STK_REG(R15)(r1)
48
48
ld r14,STK_REG(R14)(r1)
49
49
.Ldo_err3:
50
-
bl exit_vmx_usercopy
50
+
bl CFUNC(exit_vmx_usercopy)
51
51
ld r0,STACKFRAMESIZE+16(r1)
52
52
mtlr r0
53
53
b .Lexit
···
272
272
mflr r0
273
273
std r0,16(r1)
274
274
stdu r1,-STACKFRAMESIZE(r1)
275
-
bl enter_vmx_usercopy
275
+
bl CFUNC(enter_vmx_usercopy)
276
276
cmpwi cr1,r3,0
277
277
ld r0,STACKFRAMESIZE+16(r1)
278
278
ld r3,STK_REG(R31)(r1)
···
488
488
err3; stb r0,0(r3)
489
489
490
490
15: addi r1,r1,STACKFRAMESIZE
491
-
b exit_vmx_usercopy /* tail call optimise */
491
+
b CFUNC(exit_vmx_usercopy) /* tail call optimise */
492
492
493
493
.Lvmx_unaligned_copy:
494
494
/* Get the destination 16B aligned */
···
691
691
err3; stb r0,0(r3)
692
692
693
693
15: addi r1,r1,STACKFRAMESIZE
694
-
b exit_vmx_usercopy /* tail call optimise */
694
+
b CFUNC(exit_vmx_usercopy) /* tail call optimise */
695
695
#endif /* CONFIG_ALTIVEC */
+4
-4
arch/powerpc/lib/hweight_64.S
+4
-4
arch/powerpc/lib/hweight_64.S
···
14
14
15
15
_GLOBAL(__arch_hweight8)
16
16
BEGIN_FTR_SECTION
17
-
b __sw_hweight8
17
+
b CFUNC(__sw_hweight8)
18
18
nop
19
19
nop
20
20
FTR_SECTION_ELSE
···
26
26
27
27
_GLOBAL(__arch_hweight16)
28
28
BEGIN_FTR_SECTION
29
-
b __sw_hweight16
29
+
b CFUNC(__sw_hweight16)
30
30
nop
31
31
nop
32
32
nop
···
49
49
50
50
_GLOBAL(__arch_hweight32)
51
51
BEGIN_FTR_SECTION
52
-
b __sw_hweight32
52
+
b CFUNC(__sw_hweight32)
53
53
nop
54
54
nop
55
55
nop
···
75
75
76
76
_GLOBAL(__arch_hweight64)
77
77
BEGIN_FTR_SECTION
78
-
b __sw_hweight64
78
+
b CFUNC(__sw_hweight64)
79
79
nop
80
80
nop
81
81
nop
+2
-2
arch/powerpc/lib/memcmp_64.S
+2
-2
arch/powerpc/lib/memcmp_64.S
···
44
44
std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
45
45
std r0,16(r1); \
46
46
stdu r1,-STACKFRAMESIZE(r1); \
47
-
bl enter_vmx_ops; \
47
+
bl CFUNC(enter_vmx_ops); \
48
48
cmpwi cr1,r3,0; \
49
49
ld r0,STACKFRAMESIZE+16(r1); \
50
50
ld r3,STK_REG(R31)(r1); \
···
60
60
std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
61
61
std r0,16(r1); \
62
62
stdu r1,-STACKFRAMESIZE(r1); \
63
-
bl exit_vmx_ops; \
63
+
bl CFUNC(exit_vmx_ops); \
64
64
ld r0,STACKFRAMESIZE+16(r1); \
65
65
ld r3,STK_REG(R31)(r1); \
66
66
ld r4,STK_REG(R30)(r1); \
+3
-3
arch/powerpc/lib/memcpy_power7.S
+3
-3
arch/powerpc/lib/memcpy_power7.S
···
218
218
std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
219
219
std r0,16(r1)
220
220
stdu r1,-STACKFRAMESIZE(r1)
221
-
bl enter_vmx_ops
221
+
bl CFUNC(enter_vmx_ops)
222
222
cmpwi cr1,r3,0
223
223
ld r0,STACKFRAMESIZE+16(r1)
224
224
ld r3,STK_REG(R31)(r1)
···
433
433
434
434
15: addi r1,r1,STACKFRAMESIZE
435
435
ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
436
-
b exit_vmx_ops /* tail call optimise */
436
+
b CFUNC(exit_vmx_ops) /* tail call optimise */
437
437
438
438
.Lvmx_unaligned_copy:
439
439
/* Get the destination 16B aligned */
···
637
637
638
638
15: addi r1,r1,STACKFRAMESIZE
639
639
ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
640
-
b exit_vmx_ops /* tail call optimise */
640
+
b CFUNC(exit_vmx_ops) /* tail call optimise */
641
641
#endif /* CONFIG_ALTIVEC */
-7
arch/powerpc/lib/pmem.c
-7
arch/powerpc/lib/pmem.c
···
85
85
clean_pmem_range(start, start + size);
86
86
}
87
87
EXPORT_SYMBOL(memcpy_flushcache);
88
-
89
-
void memcpy_page_flushcache(char *to, struct page *page, size_t offset,
90
-
size_t len)
91
-
{
92
-
memcpy_flushcache(to, page_to_virt(page) + offset, len);
93
-
}
94
-
EXPORT_SYMBOL(memcpy_page_flushcache);
+7
-14
arch/powerpc/mm/numa.c
+7
-14
arch/powerpc/mm/numa.c
···
16
16
#include <linux/cpu.h>
17
17
#include <linux/notifier.h>
18
18
#include <linux/of.h>
19
+
#include <linux/of_address.h>
19
20
#include <linux/pfn.h>
20
21
#include <linux/cpuset.h>
21
22
#include <linux/node.h>
···
1290
1289
int nid = NUMA_NO_NODE;
1291
1290
1292
1291
for_each_node_by_type(memory, "memory") {
1293
-
unsigned long start, size;
1294
-
int ranges;
1295
-
const __be32 *memcell_buf;
1296
-
unsigned int len;
1292
+
int i = 0;
1297
1293
1298
-
memcell_buf = of_get_property(memory, "reg", &len);
1299
-
if (!memcell_buf || len <= 0)
1300
-
continue;
1294
+
while (1) {
1295
+
struct resource res;
1301
1296
1302
-
/* ranges in cell */
1303
-
ranges = (len >> 2) / (n_mem_addr_cells + n_mem_size_cells);
1297
+
if (of_address_to_resource(memory, i++, &res))
1298
+
break;
1304
1299
1305
-
while (ranges--) {
1306
-
start = read_n_cells(n_mem_addr_cells, &memcell_buf);
1307
-
size = read_n_cells(n_mem_size_cells, &memcell_buf);
1308
-
1309
-
if ((scn_addr < start) || (scn_addr >= (start + size)))
1300
+
if ((scn_addr < res.start) || (scn_addr > res.end))
1310
1301
continue;
1311
1302
1312
1303
nid = of_node_to_nid_single(memory);
+6
-4
arch/powerpc/net/bpf_jit.h
+6
-4
arch/powerpc/net/bpf_jit.h
···
19
19
#define FUNCTION_DESCR_SIZE 0
20
20
#endif
21
21
22
+
#define CTX_NIA(ctx) ((unsigned long)ctx->idx * 4)
23
+
22
24
#define PLANT_INSTR(d, idx, instr) \
23
25
do { if (d) { (d)[idx] = instr; } idx++; } while (0)
24
26
#define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
···
28
26
/* Long jump; (unconditional 'branch') */
29
27
#define PPC_JMP(dest) \
30
28
do { \
31
-
long offset = (long)(dest) - (ctx->idx * 4); \
29
+
long offset = (long)(dest) - CTX_NIA(ctx); \
32
30
if ((dest) != 0 && !is_offset_in_branch_range(offset)) { \
33
31
pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
34
32
return -ERANGE; \
···
42
40
/* "cond" here covers BO:BI fields. */
43
41
#define PPC_BCC_SHORT(cond, dest) \
44
42
do { \
45
-
long offset = (long)(dest) - (ctx->idx * 4); \
43
+
long offset = (long)(dest) - CTX_NIA(ctx); \
46
44
if ((dest) != 0 && !is_offset_in_cond_branch_range(offset)) { \
47
45
pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
48
46
return -ERANGE; \
···
94
92
* state.
95
93
*/
96
94
#define PPC_BCC(cond, dest) do { \
97
-
if (is_offset_in_cond_branch_range((long)(dest) - (ctx->idx * 4))) { \
95
+
if (is_offset_in_cond_branch_range((long)(dest) - CTX_NIA(ctx))) { \
98
96
PPC_BCC_SHORT(cond, dest); \
99
97
EMIT(PPC_RAW_NOP()); \
100
98
} else { \
101
99
/* Flip the 'T or F' bit to invert comparison */ \
102
-
PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \
100
+
PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, CTX_NIA(ctx) + 2*4); \
103
101
PPC_JMP(dest); \
104
102
} } while(0)
105
103
+27
-9
arch/powerpc/net/bpf_jit_comp64.c
+27
-9
arch/powerpc/net/bpf_jit_comp64.c
···
126
126
{
127
127
int i;
128
128
129
+
#ifndef CONFIG_PPC_KERNEL_PCREL
129
130
if (IS_ENABLED(CONFIG_PPC64_ELF_ABI_V2))
130
131
EMIT(PPC_RAW_LD(_R2, _R13, offsetof(struct paca_struct, kernel_toc)));
132
+
#endif
131
133
132
134
/*
133
135
* Initialize tail_call_cnt if we do tail calls.
···
210
208
if (WARN_ON_ONCE(!core_kernel_text(func_addr)))
211
209
return -EINVAL;
212
210
213
-
reladdr = func_addr - kernel_toc_addr();
214
-
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
215
-
pr_err("eBPF: address of %ps out of range of kernel_toc.\n", (void *)func);
216
-
return -ERANGE;
217
-
}
211
+
if (IS_ENABLED(CONFIG_PPC_KERNEL_PCREL)) {
212
+
reladdr = func_addr - CTX_NIA(ctx);
218
213
219
-
EMIT(PPC_RAW_ADDIS(_R12, _R2, PPC_HA(reladdr)));
220
-
EMIT(PPC_RAW_ADDI(_R12, _R12, PPC_LO(reladdr)));
221
-
EMIT(PPC_RAW_MTCTR(_R12));
222
-
EMIT(PPC_RAW_BCTRL());
214
+
if (reladdr >= (long)SZ_8G || reladdr < -(long)SZ_8G) {
215
+
pr_err("eBPF: address of %ps out of range of pcrel address.\n",
216
+
(void *)func);
217
+
return -ERANGE;
218
+
}
219
+
/* pla r12,addr */
220
+
EMIT(PPC_PREFIX_MLS | __PPC_PRFX_R(1) | IMM_H18(reladdr));
221
+
EMIT(PPC_INST_PADDI | ___PPC_RT(_R12) | IMM_L(reladdr));
222
+
EMIT(PPC_RAW_MTCTR(_R12));
223
+
EMIT(PPC_RAW_BCTR());
224
+
225
+
} else {
226
+
reladdr = func_addr - kernel_toc_addr();
227
+
if (reladdr > 0x7FFFFFFF || reladdr < -(0x80000000L)) {
228
+
pr_err("eBPF: address of %ps out of range of kernel_toc.\n", (void *)func);
229
+
return -ERANGE;
230
+
}
231
+
232
+
EMIT(PPC_RAW_ADDIS(_R12, _R2, PPC_HA(reladdr)));
233
+
EMIT(PPC_RAW_ADDI(_R12, _R12, PPC_LO(reladdr)));
234
+
EMIT(PPC_RAW_MTCTR(_R12));
235
+
EMIT(PPC_RAW_BCTRL());
236
+
}
223
237
224
238
return 0;
225
239
}
+3
-3
arch/powerpc/perf/mpc7450-pmu.c
+3
-3
arch/powerpc/perf/mpc7450-pmu.c
···
417
417
418
418
static int __init init_mpc7450_pmu(void)
419
419
{
420
-
unsigned int pvr = mfspr(SPRN_PVR);
421
-
422
-
if (PVR_VER(pvr) != PVR_7450)
420
+
if (!pvr_version_is(PVR_VER_7450) && !pvr_version_is(PVR_VER_7455) &&
421
+
!pvr_version_is(PVR_VER_7447) && !pvr_version_is(PVR_VER_7447A) &&
422
+
!pvr_version_is(PVR_VER_7448))
423
423
return -ENODEV;
424
424
425
425
return register_power_pmu(&mpc7450_pmu);
-1
arch/powerpc/platforms/40x/ppc40x_simple.c
-1
arch/powerpc/platforms/40x/ppc40x_simple.c
+4
-6
arch/powerpc/platforms/44x/canyonlands.c
+4
-6
arch/powerpc/platforms/44x/canyonlands.c
···
39
39
40
40
static int __init ppc460ex_probe(void)
41
41
{
42
-
if (of_machine_is_compatible("amcc,canyonlands")) {
43
-
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
44
-
return 1;
45
-
}
46
-
return 0;
42
+
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
43
+
44
+
return 1;
47
45
}
48
46
49
47
/* USB PHY fixup code on Canyonlands kit. */
···
108
110
machine_device_initcall(canyonlands, ppc460ex_canyonlands_fixup);
109
111
define_machine(canyonlands) {
110
112
.name = "Canyonlands",
113
+
.compatible = "amcc,canyonlands",
111
114
.probe = ppc460ex_probe,
112
115
.progress = udbg_progress,
113
116
.init_IRQ = uic_init_tree,
114
117
.get_irq = uic_get_irq,
115
118
.restart = ppc4xx_reset_system,
116
-
.calibrate_decr = generic_calibrate_decr,
117
119
};
+1
-4
arch/powerpc/platforms/44x/ebony.c
+1
-4
arch/powerpc/platforms/44x/ebony.c
···
45
45
*/
46
46
static int __init ebony_probe(void)
47
47
{
48
-
if (!of_machine_is_compatible("ibm,ebony"))
49
-
return 0;
50
-
51
48
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
52
49
53
50
return 1;
···
52
55
53
56
define_machine(ebony) {
54
57
.name = "Ebony",
58
+
.compatible = "ibm,ebony",
55
59
.probe = ebony_probe,
56
60
.progress = udbg_progress,
57
61
.init_IRQ = uic_init_tree,
58
62
.get_irq = uic_get_irq,
59
63
.restart = ppc4xx_reset_system,
60
-
.calibrate_decr = generic_calibrate_decr,
61
64
};
-1
arch/powerpc/platforms/44x/fsp2.c
-1
arch/powerpc/platforms/44x/fsp2.c
+2
-14
arch/powerpc/platforms/44x/iss4xx.c
+2
-14
arch/powerpc/platforms/44x/iss4xx.c
···
52
52
53
53
/* Find top level interrupt controller */
54
54
for_each_node_with_property(np, "interrupt-controller") {
55
-
if (of_get_property(np, "interrupts", NULL) == NULL)
55
+
if (!of_property_present(np, "interrupts"))
56
56
break;
57
57
}
58
58
if (np == NULL)
···
140
140
iss4xx_smp_init();
141
141
}
142
142
143
-
/*
144
-
* Called very early, MMU is off, device-tree isn't unflattened
145
-
*/
146
-
static int __init iss4xx_probe(void)
147
-
{
148
-
if (!of_machine_is_compatible("ibm,iss-4xx"))
149
-
return 0;
150
-
151
-
return 1;
152
-
}
153
-
154
143
define_machine(iss4xx) {
155
144
.name = "ISS-4xx",
156
-
.probe = iss4xx_probe,
145
+
.compatible = "ibm,iss-4xx",
157
146
.progress = udbg_progress,
158
147
.init_IRQ = iss4xx_init_irq,
159
148
.setup_arch = iss4xx_setup_arch,
160
149
.restart = ppc4xx_reset_system,
161
-
.calibrate_decr = generic_calibrate_decr,
162
150
};
-1
arch/powerpc/platforms/44x/ppc44x_simple.c
-1
arch/powerpc/platforms/44x/ppc44x_simple.c
+18
-23
arch/powerpc/platforms/44x/ppc476.c
+18
-23
arch/powerpc/platforms/44x/ppc476.c
···
114
114
115
115
return 0;
116
116
}
117
-
machine_device_initcall(ppc47x, ppc47x_device_probe);
117
+
machine_device_initcall(ppc47x_akebono, ppc47x_device_probe);
118
+
machine_device_initcall(ppc47x_currituck, ppc47x_device_probe);
118
119
119
120
static void __init ppc47x_init_irq(void)
120
121
{
···
123
122
124
123
/* Find top level interrupt controller */
125
124
for_each_node_with_property(np, "interrupt-controller") {
126
-
if (of_get_property(np, "interrupts", NULL) == NULL)
125
+
if (!of_property_present(np, "interrupts"))
127
126
break;
128
127
}
129
128
if (np == NULL)
···
250
249
pr_info("%s: Unable to find board revision\n", __func__);
251
250
return 0;
252
251
}
253
-
machine_arch_initcall(ppc47x, ppc47x_get_board_rev);
252
+
machine_arch_initcall(ppc47x_akebono, ppc47x_get_board_rev);
253
+
machine_arch_initcall(ppc47x_currituck, ppc47x_get_board_rev);
254
254
255
255
/* Use USB controller should have been hardware swizzled but it wasn't :( */
256
256
static void ppc47x_pci_irq_fixup(struct pci_dev *dev)
···
270
268
}
271
269
}
272
270
273
-
/*
274
-
* Called very early, MMU is off, device-tree isn't unflattened
275
-
*/
276
-
static int __init ppc47x_probe(void)
277
-
{
278
-
if (of_machine_is_compatible("ibm,akebono"))
279
-
return 1;
280
-
281
-
if (of_machine_is_compatible("ibm,currituck")) {
282
-
ppc_md.pci_irq_fixup = ppc47x_pci_irq_fixup;
283
-
return 1;
284
-
}
285
-
286
-
return 0;
287
-
}
288
-
289
-
define_machine(ppc47x) {
290
-
.name = "PowerPC 47x",
291
-
.probe = ppc47x_probe,
271
+
define_machine(ppc47x_akebono) {
272
+
.name = "PowerPC 47x (akebono)",
273
+
.compatible = "ibm,akebono",
292
274
.progress = udbg_progress,
293
275
.init_IRQ = ppc47x_init_irq,
294
276
.setup_arch = ppc47x_setup_arch,
295
277
.restart = ppc4xx_reset_system,
296
-
.calibrate_decr = generic_calibrate_decr,
278
+
};
279
+
280
+
define_machine(ppc47x_currituck) {
281
+
.name = "PowerPC 47x (currituck)",
282
+
.compatible = "ibm,currituck",
283
+
.progress = udbg_progress,
284
+
.init_IRQ = ppc47x_init_irq,
285
+
.pci_irq_fixup = ppc47x_pci_irq_fixup,
286
+
.setup_arch = ppc47x_setup_arch,
287
+
.restart = ppc4xx_reset_system,
297
288
};
+1
-4
arch/powerpc/platforms/44x/sam440ep.c
+1
-4
arch/powerpc/platforms/44x/sam440ep.c
···
41
41
42
42
static int __init sam440ep_probe(void)
43
43
{
44
-
if (!of_machine_is_compatible("acube,sam440ep"))
45
-
return 0;
46
-
47
44
pci_set_flags(PCI_REASSIGN_ALL_RSRC);
48
45
49
46
return 1;
···
48
51
49
52
define_machine(sam440ep) {
50
53
.name = "Sam440ep",
54
+
.compatible = "acube,sam440ep",
51
55
.probe = sam440ep_probe,
52
56
.progress = udbg_progress,
53
57
.init_IRQ = uic_init_tree,
54
58
.get_irq = uic_get_irq,
55
59
.restart = ppc4xx_reset_system,
56
-
.calibrate_decr = generic_calibrate_decr,
57
60
};
58
61
59
62
static struct i2c_board_info sam440ep_rtc_info = {
+1
-10
arch/powerpc/platforms/44x/warp.c
+1
-10
arch/powerpc/platforms/44x/warp.c
···
41
41
}
42
42
machine_device_initcall(warp, warp_device_probe);
43
43
44
-
static int __init warp_probe(void)
45
-
{
46
-
if (!of_machine_is_compatible("pika,warp"))
47
-
return 0;
48
-
49
-
return 1;
50
-
}
51
-
52
44
define_machine(warp) {
53
45
.name = "Warp",
54
-
.probe = warp_probe,
46
+
.compatible = "pika,warp",
55
47
.progress = udbg_progress,
56
48
.init_IRQ = uic_init_tree,
57
49
.get_irq = uic_get_irq,
58
50
.restart = ppc4xx_reset_system,
59
-
.calibrate_decr = generic_calibrate_decr,
60
51
};
61
52
62
53
+7
-11
arch/powerpc/platforms/4xx/pci.c
+7
-11
arch/powerpc/platforms/4xx/pci.c
···
348
348
}
349
349
350
350
/* Check if primary bridge */
351
-
if (of_get_property(np, "primary", NULL))
351
+
if (of_property_read_bool(np, "primary"))
352
352
primary = 1;
353
353
354
354
/* Get bus range if any */
···
530
530
struct pci_controller *hose = NULL;
531
531
void __iomem *reg = NULL;
532
532
const int *bus_range;
533
-
int big_pim = 0, msi = 0, primary = 0;
533
+
int big_pim, msi, primary;
534
534
535
535
/* Fetch config space registers address */
536
536
if (of_address_to_resource(np, 0, &rsrc_cfg)) {
···
546
546
}
547
547
548
548
/* Check if it supports large PIMs (440GX) */
549
-
if (of_get_property(np, "large-inbound-windows", NULL))
550
-
big_pim = 1;
549
+
big_pim = of_property_read_bool(np, "large-inbound-windows");
551
550
552
551
/* Check if we should enable MSIs inbound hole */
553
-
if (of_get_property(np, "enable-msi-hole", NULL))
554
-
msi = 1;
552
+
msi = of_property_read_bool(np, "enable-msi-hole");
555
553
556
554
/* Check if primary bridge */
557
-
if (of_get_property(np, "primary", NULL))
558
-
primary = 1;
555
+
primary = of_property_read_bool(np, "primary");
559
556
560
557
/* Get bus range if any */
561
558
bus_range = of_get_property(np, "bus-range", NULL);
···
1912
1915
struct resource dma_window;
1913
1916
struct pci_controller *hose = NULL;
1914
1917
const int *bus_range;
1915
-
int primary = 0, busses;
1918
+
int primary, busses;
1916
1919
void __iomem *mbase = NULL, *cfg_data = NULL;
1917
1920
const u32 *pval;
1918
1921
u32 val;
1919
1922
1920
1923
/* Check if primary bridge */
1921
-
if (of_get_property(port->node, "primary", NULL))
1922
-
primary = 1;
1924
+
primary = of_property_read_bool(port->node, "primary");
1923
1925
1924
1926
/* Get bus range if any */
1925
1927
bus_range = of_get_property(port->node, "bus-range", NULL);
+1
-1
arch/powerpc/platforms/512x/clock-commonclk.c
+1
-1
arch/powerpc/platforms/512x/clock-commonclk.c
···
986
986
987
987
#define NODE_PREP do { \
988
988
of_address_to_resource(np, 0, &res); \
989
-
snprintf(devname, sizeof(devname), "%08x.%s", res.start, np->name); \
989
+
snprintf(devname, sizeof(devname), "%pa.%s", &res.start, np->name); \
990
990
} while (0)
991
991
992
992
#define NODE_CHK(clkname, clkitem, regnode, regflag) do { \
+1
-4
arch/powerpc/platforms/512x/mpc5121_ads.c
+1
-4
arch/powerpc/platforms/512x/mpc5121_ads.c
···
53
53
*/
54
54
static int __init mpc5121_ads_probe(void)
55
55
{
56
-
if (!of_machine_is_compatible("fsl,mpc5121ads"))
57
-
return 0;
58
-
59
56
mpc512x_init_early();
60
57
61
58
return 1;
···
60
63
61
64
define_machine(mpc5121_ads) {
62
65
.name = "MPC5121 ADS",
66
+
.compatible = "fsl,mpc5121ads",
63
67
.probe = mpc5121_ads_probe,
64
68
.setup_arch = mpc5121_ads_setup_arch,
65
69
.discover_phbs = mpc5121_ads_setup_pci,
66
70
.init = mpc512x_init,
67
71
.init_IRQ = mpc5121_ads_init_IRQ,
68
72
.get_irq = ipic_get_irq,
69
-
.calibrate_decr = generic_calibrate_decr,
70
73
.restart = mpc512x_restart,
71
74
};
-1
arch/powerpc/platforms/512x/mpc512x_generic.c
-1
arch/powerpc/platforms/512x/mpc512x_generic.c
+1
-4
arch/powerpc/platforms/512x/pdm360ng.c
+1
-4
arch/powerpc/platforms/512x/pdm360ng.c
···
108
108
109
109
static int __init pdm360ng_probe(void)
110
110
{
111
-
if (!of_machine_is_compatible("ifm,pdm360ng"))
112
-
return 0;
113
-
114
111
mpc512x_init_early();
115
112
116
113
return 1;
···
115
118
116
119
define_machine(pdm360ng) {
117
120
.name = "PDM360NG",
121
+
.compatible = "ifm,pdm360ng",
118
122
.probe = pdm360ng_probe,
119
123
.setup_arch = mpc512x_setup_arch,
120
124
.init = pdm360ng_init,
121
125
.init_IRQ = mpc512x_init_IRQ,
122
126
.get_irq = ipic_get_irq,
123
-
.calibrate_decr = generic_calibrate_decr,
124
127
.restart = mpc512x_restart,
125
128
};
-1
arch/powerpc/platforms/52xx/efika.c
-1
arch/powerpc/platforms/52xx/efika.c
-1
arch/powerpc/platforms/52xx/lite5200.c
-1
arch/powerpc/platforms/52xx/lite5200.c
+3
-6
arch/powerpc/platforms/52xx/lite5200_pm.c
+3
-6
arch/powerpc/platforms/52xx/lite5200_pm.c
···
54
54
{ .type = "builtin", .compatible = "mpc5200", }, /* efika */
55
55
{}
56
56
};
57
-
u64 regaddr64 = 0;
58
-
const u32 *regaddr_p;
57
+
struct resource res;
59
58
60
59
/* deep sleep? let mpc52xx code handle that */
61
60
if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
···
65
66
66
67
/* map registers */
67
68
np = of_find_matching_node(NULL, immr_ids);
68
-
regaddr_p = of_get_address(np, 0, NULL, NULL);
69
-
if (regaddr_p)
70
-
regaddr64 = of_translate_address(np, regaddr_p);
69
+
of_address_to_resource(np, 0, &res);
71
70
of_node_put(np);
72
71
73
-
mbar = ioremap((u32) regaddr64, 0xC000);
72
+
mbar = ioremap(res.start, 0xC000);
74
73
if (!mbar) {
75
74
printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
76
75
return -ENOSYS;
+1
-16
arch/powerpc/platforms/52xx/media5200.c
+1
-16
arch/powerpc/platforms/52xx/media5200.c
···
227
227
228
228
}
229
229
230
-
/* list of the supported boards */
231
-
static const char * const board[] __initconst = {
232
-
"fsl,media5200",
233
-
NULL
234
-
};
235
-
236
-
/*
237
-
* Called very early, MMU is off, device-tree isn't unflattened
238
-
*/
239
-
static int __init media5200_probe(void)
240
-
{
241
-
return of_device_compatible_match(of_root, board);
242
-
}
243
-
244
230
define_machine(media5200_platform) {
245
231
.name = "media5200-platform",
246
-
.probe = media5200_probe,
232
+
.compatible = "fsl,media5200",
247
233
.setup_arch = media5200_setup_arch,
248
234
.discover_phbs = mpc52xx_setup_pci,
249
235
.init = mpc52xx_declare_of_platform_devices,
250
236
.init_IRQ = media5200_init_irq,
251
237
.get_irq = mpc52xx_get_irq,
252
238
.restart = mpc52xx_restart,
253
-
.calibrate_decr = generic_calibrate_decr,
254
239
};
-1
arch/powerpc/platforms/52xx/mpc5200_simple.c
-1
arch/powerpc/platforms/52xx/mpc5200_simple.c
+2
-2
arch/powerpc/platforms/52xx/mpc52xx_common.c
+2
-2
arch/powerpc/platforms/52xx/mpc52xx_common.c
···
141
141
* on a gpt0, so check has-wdt property before mapping.
142
142
*/
143
143
for_each_matching_node(np, mpc52xx_gpt_ids) {
144
-
if (of_get_property(np, "fsl,has-wdt", NULL) ||
145
-
of_get_property(np, "has-wdt", NULL)) {
144
+
if (of_property_read_bool(np, "fsl,has-wdt") ||
145
+
of_property_read_bool(np, "has-wdt")) {
146
146
mpc52xx_wdt = of_iomap(np, 0);
147
147
of_node_put(np);
148
148
break;
+2
-2
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
+2
-2
arch/powerpc/platforms/52xx/mpc52xx_gpt.c
···
735
735
mutex_unlock(&mpc52xx_gpt_list_mutex);
736
736
737
737
/* check if this device could be a watchdog */
738
-
if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
739
-
of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
738
+
if (of_property_read_bool(ofdev->dev.of_node, "fsl,has-wdt") ||
739
+
of_property_read_bool(ofdev->dev.of_node, "has-wdt")) {
740
740
const u32 *on_boot_wdt;
741
741
742
742
gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
-27
arch/powerpc/platforms/82xx/Kconfig
-27
arch/powerpc/platforms/82xx/Kconfig
···
5
5
6
6
if PPC_82xx
7
7
8
-
config MPC8272_ADS
9
-
bool "Freescale MPC8272 ADS"
10
-
select DEFAULT_UIMAGE
11
-
select PQ2ADS
12
-
select 8272
13
-
select 8260
14
-
select FSL_SOC
15
-
select PQ2_ADS_PCI_PIC if PCI
16
-
help
17
-
This option enables support for the MPC8272 ADS board
18
-
19
-
config PQ2FADS
20
-
bool "Freescale PQ2FADS"
21
-
select DEFAULT_UIMAGE
22
-
select PQ2ADS
23
-
select 8260
24
-
select FSL_SOC
25
-
select PQ2_ADS_PCI_PIC if PCI
26
-
help
27
-
This option enables support for the PQ2FADS board
28
-
29
8
config EP8248E
30
9
bool "Embedded Planet EP8248E (a.k.a. CWH-PPC-8248N-VE)"
31
10
select 8272
···
28
49
29
50
endif
30
51
31
-
config PQ2ADS
32
-
bool
33
-
34
52
config 8260
35
53
bool
36
54
depends on PPC_BOOK3S_32
···
43
67
help
44
68
The MPC8272 CPM has a different internal dpram setup than other CPM2
45
69
devices
46
-
47
-
config PQ2_ADS_PCI_PIC
48
-
bool
-3
arch/powerpc/platforms/82xx/Makefile
-3
arch/powerpc/platforms/82xx/Makefile
···
2
2
#
3
3
# Makefile for the PowerPC 82xx linux kernel.
4
4
#
5
-
obj-$(CONFIG_MPC8272_ADS) += mpc8272_ads.o
6
5
obj-$(CONFIG_CPM2) += pq2.o
7
-
obj-$(CONFIG_PQ2_ADS_PCI_PIC) += pq2ads-pci-pic.o
8
-
obj-$(CONFIG_PQ2FADS) += pq2fads.o
9
6
obj-$(CONFIG_EP8248E) += ep8248e.o
10
7
obj-$(CONFIG_MGCOGE) += km82xx.o
+1
-10
arch/powerpc/platforms/82xx/ep8248e.c
+1
-10
arch/powerpc/platforms/82xx/ep8248e.c
···
301
301
}
302
302
machine_device_initcall(ep8248e, declare_of_platform_devices);
303
303
304
-
/*
305
-
* Called very early, device-tree isn't unflattened
306
-
*/
307
-
static int __init ep8248e_probe(void)
308
-
{
309
-
return of_machine_is_compatible("fsl,ep8248e");
310
-
}
311
-
312
304
define_machine(ep8248e)
313
305
{
314
306
.name = "Embedded Planet EP8248E",
315
-
.probe = ep8248e_probe,
307
+
.compatible = "fsl,ep8248e",
316
308
.setup_arch = ep8248e_setup_arch,
317
309
.init_IRQ = ep8248e_pic_init,
318
310
.get_irq = cpm2_get_irq,
319
-
.calibrate_decr = generic_calibrate_decr,
320
311
.restart = pq2_restart,
321
312
.progress = udbg_progress,
322
313
};
+1
-10
arch/powerpc/platforms/82xx/km82xx.c
+1
-10
arch/powerpc/platforms/82xx/km82xx.c
···
188
188
}
189
189
machine_device_initcall(km82xx, declare_of_platform_devices);
190
190
191
-
/*
192
-
* Called very early, device-tree isn't unflattened
193
-
*/
194
-
static int __init km82xx_probe(void)
195
-
{
196
-
return of_machine_is_compatible("keymile,km82xx");
197
-
}
198
-
199
191
define_machine(km82xx)
200
192
{
201
193
.name = "Keymile km82xx",
202
-
.probe = km82xx_probe,
194
+
.compatible = "keymile,km82xx",
203
195
.setup_arch = km82xx_setup_arch,
204
196
.init_IRQ = km82xx_pic_init,
205
197
.get_irq = cpm2_get_irq,
206
-
.calibrate_decr = generic_calibrate_decr,
207
198
.restart = pq2_restart,
208
199
.progress = udbg_progress,
209
200
};
-213
arch/powerpc/platforms/82xx/mpc8272_ads.c
-213
arch/powerpc/platforms/82xx/mpc8272_ads.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8272 ADS board support
4
-
*
5
-
* Copyright 2007 Freescale Semiconductor, Inc.
6
-
* Author: Scott Wood <scottwood@freescale.com>
7
-
*
8
-
* Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
9
-
* Copyright (c) 2006 MontaVista Software, Inc.
10
-
*/
11
-
12
-
#include <linux/init.h>
13
-
#include <linux/interrupt.h>
14
-
#include <linux/fsl_devices.h>
15
-
#include <linux/of_address.h>
16
-
#include <linux/of_fdt.h>
17
-
#include <linux/of_platform.h>
18
-
#include <linux/io.h>
19
-
20
-
#include <asm/cpm2.h>
21
-
#include <asm/udbg.h>
22
-
#include <asm/machdep.h>
23
-
#include <asm/time.h>
24
-
25
-
#include <platforms/82xx/pq2.h>
26
-
27
-
#include <sysdev/fsl_soc.h>
28
-
#include <sysdev/cpm2_pic.h>
29
-
30
-
#include "pq2.h"
31
-
32
-
static void __init mpc8272_ads_pic_init(void)
33
-
{
34
-
struct device_node *np = of_find_compatible_node(NULL, NULL,
35
-
"fsl,cpm2-pic");
36
-
if (!np) {
37
-
printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
38
-
return;
39
-
}
40
-
41
-
cpm2_pic_init(np);
42
-
of_node_put(np);
43
-
44
-
/* Initialize stuff for the 82xx CPLD IC and install demux */
45
-
pq2ads_pci_init_irq();
46
-
}
47
-
48
-
struct cpm_pin {
49
-
int port, pin, flags;
50
-
};
51
-
52
-
static struct cpm_pin mpc8272_ads_pins[] = {
53
-
/* SCC1 */
54
-
{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
55
-
{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
56
-
57
-
/* SCC4 */
58
-
{3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
59
-
{3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
60
-
61
-
/* FCC1 */
62
-
{0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
63
-
{0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
64
-
{0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
65
-
{0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
66
-
{0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
67
-
{0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
68
-
{0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
69
-
{0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
70
-
{0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
71
-
{0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
72
-
{0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
73
-
{0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
74
-
{0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
75
-
{0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
76
-
{2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
77
-
{2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
78
-
79
-
/* FCC2 */
80
-
{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
81
-
{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
82
-
{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
83
-
{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
84
-
{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
85
-
{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
86
-
{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
87
-
{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
88
-
{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
89
-
{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
90
-
{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
91
-
{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
92
-
{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
93
-
{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
94
-
{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
95
-
{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
96
-
97
-
/* I2C */
98
-
{3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
99
-
{3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
100
-
101
-
/* USB */
102
-
{2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
103
-
{2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
104
-
{2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
105
-
{2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
106
-
{3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
107
-
{3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
108
-
{3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
109
-
};
110
-
111
-
static void __init init_ioports(void)
112
-
{
113
-
int i;
114
-
115
-
for (i = 0; i < ARRAY_SIZE(mpc8272_ads_pins); i++) {
116
-
struct cpm_pin *pin = &mpc8272_ads_pins[i];
117
-
cpm2_set_pin(pin->port, pin->pin, pin->flags);
118
-
}
119
-
120
-
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
121
-
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
122
-
cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_RX);
123
-
cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX);
124
-
cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX);
125
-
cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX);
126
-
cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
127
-
cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
128
-
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK15, CPM_CLK_RX);
129
-
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK16, CPM_CLK_TX);
130
-
}
131
-
132
-
static void __init mpc8272_ads_setup_arch(void)
133
-
{
134
-
struct device_node *np;
135
-
__be32 __iomem *bcsr;
136
-
137
-
if (ppc_md.progress)
138
-
ppc_md.progress("mpc8272_ads_setup_arch()", 0);
139
-
140
-
cpm2_reset();
141
-
142
-
np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr");
143
-
if (!np) {
144
-
printk(KERN_ERR "No bcsr in device tree\n");
145
-
return;
146
-
}
147
-
148
-
bcsr = of_iomap(np, 0);
149
-
of_node_put(np);
150
-
if (!bcsr) {
151
-
printk(KERN_ERR "Cannot map BCSR registers\n");
152
-
return;
153
-
}
154
-
155
-
#define BCSR1_FETHIEN 0x08000000
156
-
#define BCSR1_FETH_RST 0x04000000
157
-
#define BCSR1_RS232_EN1 0x02000000
158
-
#define BCSR1_RS232_EN2 0x01000000
159
-
#define BCSR3_USB_nEN 0x80000000
160
-
#define BCSR3_FETHIEN2 0x10000000
161
-
#define BCSR3_FETH2_RST 0x08000000
162
-
163
-
clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
164
-
setbits32(&bcsr[1], BCSR1_FETH_RST);
165
-
166
-
clrbits32(&bcsr[3], BCSR3_FETHIEN2);
167
-
setbits32(&bcsr[3], BCSR3_FETH2_RST);
168
-
169
-
clrbits32(&bcsr[3], BCSR3_USB_nEN);
170
-
171
-
iounmap(bcsr);
172
-
173
-
init_ioports();
174
-
175
-
if (ppc_md.progress)
176
-
ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
177
-
}
178
-
179
-
static const struct of_device_id of_bus_ids[] __initconst = {
180
-
{ .name = "soc", },
181
-
{ .name = "cpm", },
182
-
{ .name = "localbus", },
183
-
{},
184
-
};
185
-
186
-
static int __init declare_of_platform_devices(void)
187
-
{
188
-
/* Publish the QE devices */
189
-
of_platform_bus_probe(NULL, of_bus_ids, NULL);
190
-
return 0;
191
-
}
192
-
machine_device_initcall(mpc8272_ads, declare_of_platform_devices);
193
-
194
-
/*
195
-
* Called very early, device-tree isn't unflattened
196
-
*/
197
-
static int __init mpc8272_ads_probe(void)
198
-
{
199
-
return of_machine_is_compatible("fsl,mpc8272ads");
200
-
}
201
-
202
-
define_machine(mpc8272_ads)
203
-
{
204
-
.name = "Freescale MPC8272 ADS",
205
-
.probe = mpc8272_ads_probe,
206
-
.setup_arch = mpc8272_ads_setup_arch,
207
-
.discover_phbs = pq2_init_pci,
208
-
.init_IRQ = mpc8272_ads_pic_init,
209
-
.get_irq = cpm2_get_irq,
210
-
.calibrate_decr = generic_calibrate_decr,
211
-
.restart = pq2_restart,
212
-
.progress = udbg_progress,
213
-
};
-172
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
-172
arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* PQ2 ADS-style PCI interrupt controller
4
-
*
5
-
* Copyright 2007 Freescale Semiconductor, Inc.
6
-
* Author: Scott Wood <scottwood@freescale.com>
7
-
*
8
-
* Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
9
-
* Copyright (c) 2006 MontaVista Software, Inc.
10
-
*/
11
-
12
-
#include <linux/init.h>
13
-
#include <linux/spinlock.h>
14
-
#include <linux/irq.h>
15
-
#include <linux/types.h>
16
-
#include <linux/slab.h>
17
-
#include <linux/of_irq.h>
18
-
19
-
#include <asm/io.h>
20
-
#include <asm/cpm2.h>
21
-
22
-
#include "pq2.h"
23
-
24
-
static DEFINE_RAW_SPINLOCK(pci_pic_lock);
25
-
26
-
struct pq2ads_pci_pic {
27
-
struct device_node *node;
28
-
struct irq_domain *host;
29
-
30
-
struct {
31
-
u32 stat;
32
-
u32 mask;
33
-
} __iomem *regs;
34
-
};
35
-
36
-
#define NUM_IRQS 32
37
-
38
-
static void pq2ads_pci_mask_irq(struct irq_data *d)
39
-
{
40
-
struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
41
-
int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
42
-
43
-
if (irq != -1) {
44
-
unsigned long flags;
45
-
raw_spin_lock_irqsave(&pci_pic_lock, flags);
46
-
47
-
setbits32(&priv->regs->mask, 1 << irq);
48
-
mb();
49
-
50
-
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
51
-
}
52
-
}
53
-
54
-
static void pq2ads_pci_unmask_irq(struct irq_data *d)
55
-
{
56
-
struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
57
-
int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
58
-
59
-
if (irq != -1) {
60
-
unsigned long flags;
61
-
62
-
raw_spin_lock_irqsave(&pci_pic_lock, flags);
63
-
clrbits32(&priv->regs->mask, 1 << irq);
64
-
raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
65
-
}
66
-
}
67
-
68
-
static struct irq_chip pq2ads_pci_ic = {
69
-
.name = "PQ2 ADS PCI",
70
-
.irq_mask = pq2ads_pci_mask_irq,
71
-
.irq_mask_ack = pq2ads_pci_mask_irq,
72
-
.irq_ack = pq2ads_pci_mask_irq,
73
-
.irq_unmask = pq2ads_pci_unmask_irq,
74
-
.irq_enable = pq2ads_pci_unmask_irq,
75
-
.irq_disable = pq2ads_pci_mask_irq
76
-
};
77
-
78
-
static void pq2ads_pci_irq_demux(struct irq_desc *desc)
79
-
{
80
-
struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
81
-
u32 stat, mask, pend;
82
-
int bit;
83
-
84
-
for (;;) {
85
-
stat = in_be32(&priv->regs->stat);
86
-
mask = in_be32(&priv->regs->mask);
87
-
88
-
pend = stat & ~mask;
89
-
90
-
if (!pend)
91
-
break;
92
-
93
-
for (bit = 0; pend != 0; ++bit, pend <<= 1) {
94
-
if (pend & 0x80000000)
95
-
generic_handle_domain_irq(priv->host, bit);
96
-
}
97
-
}
98
-
}
99
-
100
-
static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
101
-
irq_hw_number_t hw)
102
-
{
103
-
irq_set_status_flags(virq, IRQ_LEVEL);
104
-
irq_set_chip_data(virq, h->host_data);
105
-
irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
106
-
return 0;
107
-
}
108
-
109
-
static const struct irq_domain_ops pci_pic_host_ops = {
110
-
.map = pci_pic_host_map,
111
-
};
112
-
113
-
int __init pq2ads_pci_init_irq(void)
114
-
{
115
-
struct pq2ads_pci_pic *priv;
116
-
struct irq_domain *host;
117
-
struct device_node *np;
118
-
int ret = -ENODEV;
119
-
int irq;
120
-
121
-
np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
122
-
if (!np) {
123
-
printk(KERN_ERR "No pci pic node in device tree.\n");
124
-
goto out;
125
-
}
126
-
127
-
irq = irq_of_parse_and_map(np, 0);
128
-
if (!irq) {
129
-
printk(KERN_ERR "No interrupt in pci pic node.\n");
130
-
goto out_put_node;
131
-
}
132
-
133
-
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
134
-
if (!priv) {
135
-
ret = -ENOMEM;
136
-
goto out_unmap_irq;
137
-
}
138
-
139
-
/* PCI interrupt controller registers: status and mask */
140
-
priv->regs = of_iomap(np, 0);
141
-
if (!priv->regs) {
142
-
printk(KERN_ERR "Cannot map PCI PIC registers.\n");
143
-
goto out_free_kmalloc;
144
-
}
145
-
146
-
/* mask all PCI interrupts */
147
-
out_be32(&priv->regs->mask, ~0);
148
-
mb();
149
-
150
-
host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
151
-
if (!host) {
152
-
ret = -ENOMEM;
153
-
goto out_unmap_regs;
154
-
}
155
-
156
-
priv->host = host;
157
-
irq_set_handler_data(irq, priv);
158
-
irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
159
-
ret = 0;
160
-
goto out_put_node;
161
-
162
-
out_unmap_regs:
163
-
iounmap(priv->regs);
164
-
out_free_kmalloc:
165
-
kfree(priv);
166
-
out_unmap_irq:
167
-
irq_dispose_mapping(irq);
168
-
out_put_node:
169
-
of_node_put(np);
170
-
out:
171
-
return ret;
172
-
}
-40
arch/powerpc/platforms/82xx/pq2ads.h
-40
arch/powerpc/platforms/82xx/pq2ads.h
···
1
-
/* SPDX-License-Identifier: GPL-2.0-or-later */
2
-
/*
3
-
* PQ2/mpc8260 board-specific stuff
4
-
*
5
-
* A collection of structures, addresses, and values associated with
6
-
* the Freescale MPC8260ADS/MPC8266ADS-PCI boards.
7
-
* Copied from the RPX-Classic and SBS8260 stuff.
8
-
*
9
-
* Author: Vitaly Bordug <vbordug@ru.mvista.com>
10
-
*
11
-
* Originally written by Dan Malek for Motorola MPC8260 family
12
-
*
13
-
* Copyright (c) 2001 Dan Malek <dan@embeddedalley.com>
14
-
* Copyright (c) 2006 MontaVista Software, Inc.
15
-
*/
16
-
17
-
#ifdef __KERNEL__
18
-
#ifndef __MACH_ADS8260_DEFS
19
-
#define __MACH_ADS8260_DEFS
20
-
21
-
#include <linux/seq_file.h>
22
-
23
-
/* The ADS8260 has 16, 32-bit wide control/status registers, accessed
24
-
* only on word boundaries.
25
-
* Not all are used (yet), or are interesting to us (yet).
26
-
*/
27
-
28
-
/* Things of interest in the CSR.
29
-
*/
30
-
#define BCSR0_LED0 ((uint)0x02000000) /* 0 == on */
31
-
#define BCSR0_LED1 ((uint)0x01000000) /* 0 == on */
32
-
#define BCSR1_FETHIEN ((uint)0x08000000) /* 0 == enable*/
33
-
#define BCSR1_FETH_RST ((uint)0x04000000) /* 0 == reset */
34
-
#define BCSR1_RS232_EN1 ((uint)0x02000000) /* 0 ==enable */
35
-
#define BCSR1_RS232_EN2 ((uint)0x01000000) /* 0 ==enable */
36
-
#define BCSR3_FETHIEN2 ((uint)0x10000000) /* 0 == enable*/
37
-
#define BCSR3_FETH2_RST ((uint)0x80000000) /* 0 == reset */
38
-
39
-
#endif /* __MACH_ADS8260_DEFS */
40
-
#endif /* __KERNEL__ */
-191
arch/powerpc/platforms/82xx/pq2fads.c
-191
arch/powerpc/platforms/82xx/pq2fads.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-only
2
-
/*
3
-
* PQ2FADS board support
4
-
*
5
-
* Copyright 2007 Freescale Semiconductor, Inc.
6
-
* Author: Scott Wood <scottwood@freescale.com>
7
-
*
8
-
* Loosely based on mp82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
9
-
* Copyright (c) 2006 MontaVista Software, Inc.
10
-
*/
11
-
12
-
#include <linux/init.h>
13
-
#include <linux/interrupt.h>
14
-
#include <linux/fsl_devices.h>
15
-
#include <linux/of_address.h>
16
-
#include <linux/of_fdt.h>
17
-
#include <linux/of_platform.h>
18
-
19
-
#include <asm/io.h>
20
-
#include <asm/cpm2.h>
21
-
#include <asm/udbg.h>
22
-
#include <asm/machdep.h>
23
-
#include <asm/time.h>
24
-
25
-
#include <sysdev/fsl_soc.h>
26
-
#include <sysdev/cpm2_pic.h>
27
-
28
-
#include "pq2ads.h"
29
-
#include "pq2.h"
30
-
31
-
static void __init pq2fads_pic_init(void)
32
-
{
33
-
struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
34
-
if (!np) {
35
-
printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
36
-
return;
37
-
}
38
-
39
-
cpm2_pic_init(np);
40
-
of_node_put(np);
41
-
42
-
/* Initialize stuff for the 82xx CPLD IC and install demux */
43
-
pq2ads_pci_init_irq();
44
-
}
45
-
46
-
struct cpm_pin {
47
-
int port, pin, flags;
48
-
};
49
-
50
-
static struct cpm_pin pq2fads_pins[] = {
51
-
/* SCC1 */
52
-
{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
53
-
{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
54
-
55
-
/* SCC2 */
56
-
{3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
57
-
{3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
58
-
59
-
/* FCC2 */
60
-
{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
61
-
{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
62
-
{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
63
-
{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
64
-
{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
65
-
{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
66
-
{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
67
-
{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
68
-
{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
69
-
{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
70
-
{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
71
-
{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
72
-
{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
73
-
{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
74
-
{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
75
-
{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
76
-
77
-
/* FCC3 */
78
-
{1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
79
-
{1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
80
-
{1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
81
-
{1, 7, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
82
-
{1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
83
-
{1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
84
-
{1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
85
-
{1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
86
-
{1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
87
-
{1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
88
-
{1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
89
-
{1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
90
-
{1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
91
-
{1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
92
-
{2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
93
-
{2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
94
-
};
95
-
96
-
static void __init init_ioports(void)
97
-
{
98
-
int i;
99
-
100
-
for (i = 0; i < ARRAY_SIZE(pq2fads_pins); i++) {
101
-
struct cpm_pin *pin = &pq2fads_pins[i];
102
-
cpm2_set_pin(pin->port, pin->pin, pin->flags);
103
-
}
104
-
105
-
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
106
-
cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
107
-
cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
108
-
cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
109
-
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
110
-
cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
111
-
cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
112
-
cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
113
-
}
114
-
115
-
static void __init pq2fads_setup_arch(void)
116
-
{
117
-
struct device_node *np;
118
-
__be32 __iomem *bcsr;
119
-
120
-
if (ppc_md.progress)
121
-
ppc_md.progress("pq2fads_setup_arch()", 0);
122
-
123
-
cpm2_reset();
124
-
125
-
np = of_find_compatible_node(NULL, NULL, "fsl,pq2fads-bcsr");
126
-
if (!np) {
127
-
printk(KERN_ERR "No fsl,pq2fads-bcsr in device tree\n");
128
-
return;
129
-
}
130
-
131
-
bcsr = of_iomap(np, 0);
132
-
of_node_put(np);
133
-
if (!bcsr) {
134
-
printk(KERN_ERR "Cannot map BCSR registers\n");
135
-
return;
136
-
}
137
-
138
-
/* Enable the serial and ethernet ports */
139
-
140
-
clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
141
-
setbits32(&bcsr[1], BCSR1_FETH_RST);
142
-
143
-
clrbits32(&bcsr[3], BCSR3_FETHIEN2);
144
-
setbits32(&bcsr[3], BCSR3_FETH2_RST);
145
-
146
-
iounmap(bcsr);
147
-
148
-
init_ioports();
149
-
150
-
/* Enable external IRQs */
151
-
clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_siumcr, 0x0c000000);
152
-
153
-
if (ppc_md.progress)
154
-
ppc_md.progress("pq2fads_setup_arch(), finish", 0);
155
-
}
156
-
157
-
/*
158
-
* Called very early, device-tree isn't unflattened
159
-
*/
160
-
static int __init pq2fads_probe(void)
161
-
{
162
-
return of_machine_is_compatible("fsl,pq2fads");
163
-
}
164
-
165
-
static const struct of_device_id of_bus_ids[] __initconst = {
166
-
{ .name = "soc", },
167
-
{ .name = "cpm", },
168
-
{ .name = "localbus", },
169
-
{},
170
-
};
171
-
172
-
static int __init declare_of_platform_devices(void)
173
-
{
174
-
/* Publish the QE devices */
175
-
of_platform_bus_probe(NULL, of_bus_ids, NULL);
176
-
return 0;
177
-
}
178
-
machine_device_initcall(pq2fads, declare_of_platform_devices);
179
-
180
-
define_machine(pq2fads)
181
-
{
182
-
.name = "Freescale PQ2FADS",
183
-
.probe = pq2fads_probe,
184
-
.setup_arch = pq2fads_setup_arch,
185
-
.discover_phbs = pq2_init_pci,
186
-
.init_IRQ = pq2fads_pic_init,
187
-
.get_irq = cpm2_get_irq,
188
-
.calibrate_decr = generic_calibrate_decr,
189
-
.restart = pq2_restart,
190
-
.progress = udbg_progress,
191
-
};
-32
arch/powerpc/platforms/83xx/Kconfig
-32
arch/powerpc/platforms/83xx/Kconfig
···
25
25
help
26
26
This option enables support for the MPC8313 RDB and MPC8315 RDB boards.
27
27
28
-
config MPC832x_MDS
29
-
bool "Freescale MPC832x MDS"
30
-
select DEFAULT_UIMAGE
31
-
select PPC_MPC832x
32
-
help
33
-
This option enables support for the MPC832x MDS evaluation board.
34
-
35
28
config MPC832x_RDB
36
29
bool "Freescale MPC832x RDB"
37
30
select DEFAULT_UIMAGE
38
31
select PPC_MPC832x
39
32
help
40
33
This option enables support for the MPC8323 RDB board.
41
-
42
-
config MPC834x_MDS
43
-
bool "Freescale MPC834x MDS"
44
-
select DEFAULT_UIMAGE
45
-
select PPC_MPC834x
46
-
help
47
-
This option enables support for the MPC 834x MDS evaluation board.
48
-
49
-
Be aware that PCI buses can only function when MDS board is plugged
50
-
into the PIB (Platform IO Board) board from Freescale which provide
51
-
3 PCI slots. The PIBs PCI initialization is the bootloader's
52
-
responsibility.
53
34
54
35
config MPC834x_ITX
55
36
bool "Freescale MPC834x ITX"
···
42
61
Be aware that PCI initialization is the bootloader's
43
62
responsibility.
44
63
45
-
config MPC836x_MDS
46
-
bool "Freescale MPC836x MDS"
47
-
select DEFAULT_UIMAGE
48
-
help
49
-
This option enables support for the MPC836x MDS Processor Board.
50
-
51
64
config MPC836x_RDK
52
65
bool "Freescale/Logic MPC836x RDK"
53
66
select DEFAULT_UIMAGE
···
50
75
help
51
76
This option enables support for the MPC836x RDK Processor Board,
52
77
also known as ZOOM PowerQUICC Kit.
53
-
54
-
config MPC837x_MDS
55
-
bool "Freescale MPC837x MDS"
56
-
select DEFAULT_UIMAGE
57
-
select PPC_MPC837x
58
-
help
59
-
This option enables support for the MPC837x MDS Processor Board.
60
78
61
79
config MPC837x_RDB
62
80
bool "Freescale MPC837x RDB/WLAN"
-4
arch/powerpc/platforms/83xx/Makefile
-4
arch/powerpc/platforms/83xx/Makefile
···
8
8
obj-$(CONFIG_MPC830x_RDB) += mpc830x_rdb.o
9
9
obj-$(CONFIG_MPC831x_RDB) += mpc831x_rdb.o
10
10
obj-$(CONFIG_MPC832x_RDB) += mpc832x_rdb.o
11
-
obj-$(CONFIG_MPC834x_MDS) += mpc834x_mds.o
12
11
obj-$(CONFIG_MPC834x_ITX) += mpc834x_itx.o
13
-
obj-$(CONFIG_MPC836x_MDS) += mpc836x_mds.o
14
12
obj-$(CONFIG_MPC836x_RDK) += mpc836x_rdk.o
15
-
obj-$(CONFIG_MPC832x_MDS) += mpc832x_mds.o
16
-
obj-$(CONFIG_MPC837x_MDS) += mpc837x_mds.o
17
13
obj-$(CONFIG_MPC837x_RDB) += mpc837x_rdb.o
18
14
obj-$(CONFIG_ASP834x) += asp834x.o
19
15
obj-$(CONFIG_KMETER1) += km83xx.o
+1
-10
arch/powerpc/platforms/83xx/asp834x.c
+1
-10
arch/powerpc/platforms/83xx/asp834x.c
···
32
32
33
33
machine_device_initcall(asp834x, mpc83xx_declare_of_platform_devices);
34
34
35
-
/*
36
-
* Called very early, MMU is off, device-tree isn't unflattened
37
-
*/
38
-
static int __init asp834x_probe(void)
39
-
{
40
-
return of_machine_is_compatible("analogue-and-micro,asp8347e");
41
-
}
42
-
43
35
define_machine(asp834x) {
44
36
.name = "ASP8347E",
45
-
.probe = asp834x_probe,
37
+
.compatible = "analogue-and-micro,asp8347e",
46
38
.setup_arch = asp834x_setup_arch,
47
39
.discover_phbs = mpc83xx_setup_pci,
48
40
.init_IRQ = mpc83xx_ipic_init_IRQ,
49
41
.get_irq = ipic_get_irq,
50
42
.restart = mpc83xx_restart,
51
43
.time_init = mpc83xx_time_init,
52
-
.calibrate_decr = generic_calibrate_decr,
53
44
.progress = udbg_progress,
54
45
};
-1
arch/powerpc/platforms/83xx/km83xx.c
-1
arch/powerpc/platforms/83xx/km83xx.c
-1
arch/powerpc/platforms/83xx/mpc830x_rdb.c
-1
arch/powerpc/platforms/83xx/mpc830x_rdb.c
-1
arch/powerpc/platforms/83xx/mpc831x_rdb.c
-1
arch/powerpc/platforms/83xx/mpc831x_rdb.c
-110
arch/powerpc/platforms/83xx/mpc832x_mds.c
-110
arch/powerpc/platforms/83xx/mpc832x_mds.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
4
-
*
5
-
* Description:
6
-
* MPC832xE MDS board specific routines.
7
-
*/
8
-
9
-
#include <linux/stddef.h>
10
-
#include <linux/kernel.h>
11
-
#include <linux/init.h>
12
-
#include <linux/errno.h>
13
-
#include <linux/reboot.h>
14
-
#include <linux/pci.h>
15
-
#include <linux/kdev_t.h>
16
-
#include <linux/major.h>
17
-
#include <linux/console.h>
18
-
#include <linux/delay.h>
19
-
#include <linux/seq_file.h>
20
-
#include <linux/root_dev.h>
21
-
#include <linux/initrd.h>
22
-
#include <linux/of_platform.h>
23
-
#include <linux/of_device.h>
24
-
25
-
#include <linux/atomic.h>
26
-
#include <asm/time.h>
27
-
#include <asm/io.h>
28
-
#include <asm/machdep.h>
29
-
#include <asm/ipic.h>
30
-
#include <asm/irq.h>
31
-
#include <asm/udbg.h>
32
-
#include <sysdev/fsl_soc.h>
33
-
#include <sysdev/fsl_pci.h>
34
-
#include <soc/fsl/qe/qe.h>
35
-
36
-
#include "mpc83xx.h"
37
-
38
-
#undef DEBUG
39
-
#ifdef DEBUG
40
-
#define DBG(fmt...) udbg_printf(fmt)
41
-
#else
42
-
#define DBG(fmt...)
43
-
#endif
44
-
45
-
/* ************************************************************************
46
-
*
47
-
* Setup the architecture
48
-
*
49
-
*/
50
-
static void __init mpc832x_sys_setup_arch(void)
51
-
{
52
-
struct device_node *np;
53
-
u8 __iomem *bcsr_regs = NULL;
54
-
55
-
mpc83xx_setup_arch();
56
-
57
-
/* Map BCSR area */
58
-
np = of_find_node_by_name(NULL, "bcsr");
59
-
if (np) {
60
-
struct resource res;
61
-
62
-
of_address_to_resource(np, 0, &res);
63
-
bcsr_regs = ioremap(res.start, resource_size(&res));
64
-
of_node_put(np);
65
-
}
66
-
67
-
#ifdef CONFIG_QUICC_ENGINE
68
-
if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
69
-
par_io_init(np);
70
-
of_node_put(np);
71
-
72
-
for_each_node_by_name(np, "ucc")
73
-
par_io_of_config(np);
74
-
}
75
-
76
-
if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
77
-
!= NULL){
78
-
/* Reset the Ethernet PHYs */
79
-
#define BCSR8_FETH_RST 0x50
80
-
clrbits8(&bcsr_regs[8], BCSR8_FETH_RST);
81
-
udelay(1000);
82
-
setbits8(&bcsr_regs[8], BCSR8_FETH_RST);
83
-
iounmap(bcsr_regs);
84
-
of_node_put(np);
85
-
}
86
-
#endif /* CONFIG_QUICC_ENGINE */
87
-
}
88
-
89
-
machine_device_initcall(mpc832x_mds, mpc83xx_declare_of_platform_devices);
90
-
91
-
/*
92
-
* Called very early, MMU is off, device-tree isn't unflattened
93
-
*/
94
-
static int __init mpc832x_sys_probe(void)
95
-
{
96
-
return of_machine_is_compatible("MPC832xMDS");
97
-
}
98
-
99
-
define_machine(mpc832x_mds) {
100
-
.name = "MPC832x MDS",
101
-
.probe = mpc832x_sys_probe,
102
-
.setup_arch = mpc832x_sys_setup_arch,
103
-
.discover_phbs = mpc83xx_setup_pci,
104
-
.init_IRQ = mpc83xx_ipic_init_IRQ,
105
-
.get_irq = ipic_get_irq,
106
-
.restart = mpc83xx_restart,
107
-
.time_init = mpc83xx_time_init,
108
-
.calibrate_decr = generic_calibrate_decr,
109
-
.progress = udbg_progress,
110
-
};
+1
-10
arch/powerpc/platforms/83xx/mpc832x_rdb.c
+1
-10
arch/powerpc/platforms/83xx/mpc832x_rdb.c
···
212
212
213
213
machine_device_initcall(mpc832x_rdb, mpc83xx_declare_of_platform_devices);
214
214
215
-
/*
216
-
* Called very early, MMU is off, device-tree isn't unflattened
217
-
*/
218
-
static int __init mpc832x_rdb_probe(void)
219
-
{
220
-
return of_machine_is_compatible("MPC832xRDB");
221
-
}
222
-
223
215
define_machine(mpc832x_rdb) {
224
216
.name = "MPC832x RDB",
225
-
.probe = mpc832x_rdb_probe,
217
+
.compatible = "MPC832xRDB",
226
218
.setup_arch = mpc832x_rdb_setup_arch,
227
219
.discover_phbs = mpc83xx_setup_pci,
228
220
.init_IRQ = mpc83xx_ipic_init_IRQ,
229
221
.get_irq = ipic_get_irq,
230
222
.restart = mpc83xx_restart,
231
223
.time_init = mpc83xx_time_init,
232
-
.calibrate_decr = generic_calibrate_decr,
233
224
.progress = udbg_progress,
234
225
};
+1
-10
arch/powerpc/platforms/83xx/mpc834x_itx.c
+1
-10
arch/powerpc/platforms/83xx/mpc834x_itx.c
···
57
57
mpc834x_usb_cfg();
58
58
}
59
59
60
-
/*
61
-
* Called very early, MMU is off, device-tree isn't unflattened
62
-
*/
63
-
static int __init mpc834x_itx_probe(void)
64
-
{
65
-
return of_machine_is_compatible("MPC834xMITX");
66
-
}
67
-
68
60
define_machine(mpc834x_itx) {
69
61
.name = "MPC834x ITX",
70
-
.probe = mpc834x_itx_probe,
62
+
.compatible = "MPC834xMITX",
71
63
.setup_arch = mpc834x_itx_setup_arch,
72
64
.discover_phbs = mpc83xx_setup_pci,
73
65
.init_IRQ = mpc83xx_ipic_init_IRQ,
74
66
.get_irq = ipic_get_irq,
75
67
.restart = mpc83xx_restart,
76
68
.time_init = mpc83xx_time_init,
77
-
.calibrate_decr = generic_calibrate_decr,
78
69
.progress = udbg_progress,
79
70
};
-101
arch/powerpc/platforms/83xx/mpc834x_mds.c
-101
arch/powerpc/platforms/83xx/mpc834x_mds.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/powerpc/platforms/83xx/mpc834x_mds.c
4
-
*
5
-
* MPC834x MDS board specific routines
6
-
*
7
-
* Maintainer: Kumar Gala <galak@kernel.crashing.org>
8
-
*/
9
-
10
-
#include <linux/stddef.h>
11
-
#include <linux/kernel.h>
12
-
#include <linux/init.h>
13
-
#include <linux/errno.h>
14
-
#include <linux/reboot.h>
15
-
#include <linux/pci.h>
16
-
#include <linux/kdev_t.h>
17
-
#include <linux/major.h>
18
-
#include <linux/console.h>
19
-
#include <linux/delay.h>
20
-
#include <linux/seq_file.h>
21
-
#include <linux/root_dev.h>
22
-
#include <linux/of_address.h>
23
-
#include <linux/of_platform.h>
24
-
25
-
#include <linux/atomic.h>
26
-
#include <asm/time.h>
27
-
#include <asm/io.h>
28
-
#include <asm/machdep.h>
29
-
#include <asm/ipic.h>
30
-
#include <asm/irq.h>
31
-
#include <asm/udbg.h>
32
-
#include <sysdev/fsl_soc.h>
33
-
#include <sysdev/fsl_pci.h>
34
-
35
-
#include "mpc83xx.h"
36
-
37
-
#define BCSR5_INT_USB 0x02
38
-
static int __init mpc834xemds_usb_cfg(void)
39
-
{
40
-
struct device_node *np;
41
-
void __iomem *bcsr_regs = NULL;
42
-
u8 bcsr5;
43
-
44
-
mpc834x_usb_cfg();
45
-
/* Map BCSR area */
46
-
np = of_find_node_by_name(NULL, "bcsr");
47
-
if (np) {
48
-
struct resource res;
49
-
50
-
of_address_to_resource(np, 0, &res);
51
-
bcsr_regs = ioremap(res.start, resource_size(&res));
52
-
of_node_put(np);
53
-
}
54
-
if (!bcsr_regs)
55
-
return -1;
56
-
57
-
/*
58
-
* if Processor Board is plugged into PIB board,
59
-
* force to use the PHY on Processor Board
60
-
*/
61
-
bcsr5 = in_8(bcsr_regs + 5);
62
-
if (!(bcsr5 & BCSR5_INT_USB))
63
-
out_8(bcsr_regs + 5, (bcsr5 | BCSR5_INT_USB));
64
-
iounmap(bcsr_regs);
65
-
return 0;
66
-
}
67
-
68
-
/* ************************************************************************
69
-
*
70
-
* Setup the architecture
71
-
*
72
-
*/
73
-
static void __init mpc834x_mds_setup_arch(void)
74
-
{
75
-
mpc83xx_setup_arch();
76
-
77
-
mpc834xemds_usb_cfg();
78
-
}
79
-
80
-
machine_device_initcall(mpc834x_mds, mpc83xx_declare_of_platform_devices);
81
-
82
-
/*
83
-
* Called very early, MMU is off, device-tree isn't unflattened
84
-
*/
85
-
static int __init mpc834x_mds_probe(void)
86
-
{
87
-
return of_machine_is_compatible("MPC834xMDS");
88
-
}
89
-
90
-
define_machine(mpc834x_mds) {
91
-
.name = "MPC834x MDS",
92
-
.probe = mpc834x_mds_probe,
93
-
.setup_arch = mpc834x_mds_setup_arch,
94
-
.discover_phbs = mpc83xx_setup_pci,
95
-
.init_IRQ = mpc83xx_ipic_init_IRQ,
96
-
.get_irq = ipic_get_irq,
97
-
.restart = mpc83xx_restart,
98
-
.time_init = mpc83xx_time_init,
99
-
.calibrate_decr = generic_calibrate_decr,
100
-
.progress = udbg_progress,
101
-
};
-210
arch/powerpc/platforms/83xx/mpc836x_mds.c
-210
arch/powerpc/platforms/83xx/mpc836x_mds.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
4
-
*
5
-
* Author: Li Yang <LeoLi@freescale.com>
6
-
* Yin Olivia <Hong-hua.Yin@freescale.com>
7
-
*
8
-
* Description:
9
-
* MPC8360E MDS board specific routines.
10
-
*
11
-
* Changelog:
12
-
* Jun 21, 2006 Initial version
13
-
*/
14
-
15
-
#include <linux/stddef.h>
16
-
#include <linux/kernel.h>
17
-
#include <linux/compiler.h>
18
-
#include <linux/init.h>
19
-
#include <linux/errno.h>
20
-
#include <linux/reboot.h>
21
-
#include <linux/pci.h>
22
-
#include <linux/kdev_t.h>
23
-
#include <linux/major.h>
24
-
#include <linux/console.h>
25
-
#include <linux/delay.h>
26
-
#include <linux/seq_file.h>
27
-
#include <linux/root_dev.h>
28
-
#include <linux/initrd.h>
29
-
#include <linux/of_platform.h>
30
-
#include <linux/of_device.h>
31
-
32
-
#include <linux/atomic.h>
33
-
#include <asm/time.h>
34
-
#include <asm/io.h>
35
-
#include <asm/machdep.h>
36
-
#include <asm/ipic.h>
37
-
#include <asm/irq.h>
38
-
#include <asm/udbg.h>
39
-
#include <sysdev/fsl_soc.h>
40
-
#include <sysdev/fsl_pci.h>
41
-
#include <soc/fsl/qe/qe.h>
42
-
43
-
#include "mpc83xx.h"
44
-
45
-
#undef DEBUG
46
-
#ifdef DEBUG
47
-
#define DBG(fmt...) udbg_printf(fmt)
48
-
#else
49
-
#define DBG(fmt...)
50
-
#endif
51
-
52
-
/* ************************************************************************
53
-
*
54
-
* Setup the architecture
55
-
*
56
-
*/
57
-
static void __init mpc836x_mds_setup_arch(void)
58
-
{
59
-
struct device_node *np;
60
-
u8 __iomem *bcsr_regs = NULL;
61
-
62
-
mpc83xx_setup_arch();
63
-
64
-
/* Map BCSR area */
65
-
np = of_find_node_by_name(NULL, "bcsr");
66
-
if (np) {
67
-
struct resource res;
68
-
69
-
of_address_to_resource(np, 0, &res);
70
-
bcsr_regs = ioremap(res.start, resource_size(&res));
71
-
of_node_put(np);
72
-
}
73
-
74
-
#ifdef CONFIG_QUICC_ENGINE
75
-
if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
76
-
par_io_init(np);
77
-
of_node_put(np);
78
-
79
-
for_each_node_by_name(np, "ucc")
80
-
par_io_of_config(np);
81
-
#ifdef CONFIG_QE_USB
82
-
/* Must fixup Par IO before QE GPIO chips are registered. */
83
-
par_io_config_pin(1, 2, 1, 0, 3, 0); /* USBOE */
84
-
par_io_config_pin(1, 3, 1, 0, 3, 0); /* USBTP */
85
-
par_io_config_pin(1, 8, 1, 0, 1, 0); /* USBTN */
86
-
par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
87
-
par_io_config_pin(1, 9, 2, 1, 3, 0); /* USBRP */
88
-
par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN */
89
-
par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21 */
90
-
#endif /* CONFIG_QE_USB */
91
-
}
92
-
93
-
if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
94
-
!= NULL){
95
-
uint svid;
96
-
97
-
/* Reset the Ethernet PHY */
98
-
#define BCSR9_GETHRST 0x20
99
-
clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
100
-
udelay(1000);
101
-
setbits8(&bcsr_regs[9], BCSR9_GETHRST);
102
-
103
-
/* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
104
-
svid = mfspr(SPRN_SVR);
105
-
if (svid == 0x80480021) {
106
-
void __iomem *immap;
107
-
108
-
immap = ioremap(get_immrbase() + 0x14a8, 8);
109
-
110
-
/*
111
-
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
112
-
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
113
-
*/
114
-
setbits32(immap, 0x0c003000);
115
-
116
-
/*
117
-
* IMMR + 0x14AC[20:27] = 10101010
118
-
* (data delay for both UCC's)
119
-
*/
120
-
clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
121
-
122
-
iounmap(immap);
123
-
}
124
-
125
-
iounmap(bcsr_regs);
126
-
of_node_put(np);
127
-
}
128
-
#endif /* CONFIG_QUICC_ENGINE */
129
-
}
130
-
131
-
machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
132
-
133
-
#ifdef CONFIG_QE_USB
134
-
static int __init mpc836x_usb_cfg(void)
135
-
{
136
-
u8 __iomem *bcsr;
137
-
struct device_node *np;
138
-
const char *mode;
139
-
int ret = 0;
140
-
141
-
np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
142
-
if (!np)
143
-
return -ENODEV;
144
-
145
-
bcsr = of_iomap(np, 0);
146
-
of_node_put(np);
147
-
if (!bcsr)
148
-
return -ENOMEM;
149
-
150
-
np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
151
-
if (!np) {
152
-
ret = -ENODEV;
153
-
goto err;
154
-
}
155
-
156
-
#define BCSR8_TSEC1M_MASK (0x3 << 6)
157
-
#define BCSR8_TSEC1M_RGMII (0x0 << 6)
158
-
#define BCSR8_TSEC2M_MASK (0x3 << 4)
159
-
#define BCSR8_TSEC2M_RGMII (0x0 << 4)
160
-
/*
161
-
* Default is GMII (2), but we should set it to RGMII (0) if we use
162
-
* USB (Eth PHY is in RGMII mode anyway).
163
-
*/
164
-
clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
165
-
BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
166
-
167
-
#define BCSR13_USBMASK 0x0f
168
-
#define BCSR13_nUSBEN 0x08 /* 1 - Disable, 0 - Enable */
169
-
#define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low */
170
-
#define BCSR13_USBMODE 0x02 /* 1 - Host, 0 - Function */
171
-
#define BCSR13_nUSBVCC 0x01 /* 1 - gets VBUS, 0 - supplies VBUS */
172
-
173
-
clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
174
-
175
-
mode = of_get_property(np, "mode", NULL);
176
-
if (mode && !strcmp(mode, "peripheral")) {
177
-
setbits8(&bcsr[13], BCSR13_nUSBVCC);
178
-
qe_usb_clock_set(QE_CLK21, 48000000);
179
-
} else {
180
-
setbits8(&bcsr[13], BCSR13_USBMODE);
181
-
}
182
-
183
-
of_node_put(np);
184
-
err:
185
-
iounmap(bcsr);
186
-
return ret;
187
-
}
188
-
machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
189
-
#endif /* CONFIG_QE_USB */
190
-
191
-
/*
192
-
* Called very early, MMU is off, device-tree isn't unflattened
193
-
*/
194
-
static int __init mpc836x_mds_probe(void)
195
-
{
196
-
return of_machine_is_compatible("MPC836xMDS");
197
-
}
198
-
199
-
define_machine(mpc836x_mds) {
200
-
.name = "MPC836x MDS",
201
-
.probe = mpc836x_mds_probe,
202
-
.setup_arch = mpc836x_mds_setup_arch,
203
-
.discover_phbs = mpc83xx_setup_pci,
204
-
.init_IRQ = mpc83xx_ipic_init_IRQ,
205
-
.get_irq = ipic_get_irq,
206
-
.restart = mpc83xx_restart,
207
-
.time_init = mpc83xx_time_init,
208
-
.calibrate_decr = generic_calibrate_decr,
209
-
.progress = udbg_progress,
210
-
};
+1
-10
arch/powerpc/platforms/83xx/mpc836x_rdk.c
+1
-10
arch/powerpc/platforms/83xx/mpc836x_rdk.c
···
28
28
mpc83xx_setup_arch();
29
29
}
30
30
31
-
/*
32
-
* Called very early, MMU is off, device-tree isn't unflattened.
33
-
*/
34
-
static int __init mpc836x_rdk_probe(void)
35
-
{
36
-
return of_machine_is_compatible("fsl,mpc8360rdk");
37
-
}
38
-
39
31
define_machine(mpc836x_rdk) {
40
32
.name = "MPC836x RDK",
41
-
.probe = mpc836x_rdk_probe,
33
+
.compatible = "fsl,mpc8360rdk",
42
34
.setup_arch = mpc836x_rdk_setup_arch,
43
35
.discover_phbs = mpc83xx_setup_pci,
44
36
.init_IRQ = mpc83xx_ipic_init_IRQ,
45
37
.get_irq = ipic_get_irq,
46
38
.restart = mpc83xx_restart,
47
39
.time_init = mpc83xx_time_init,
48
-
.calibrate_decr = generic_calibrate_decr,
49
40
.progress = udbg_progress,
50
41
};
-103
arch/powerpc/platforms/83xx/mpc837x_mds.c
-103
arch/powerpc/platforms/83xx/mpc837x_mds.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* arch/powerpc/platforms/83xx/mpc837x_mds.c
4
-
*
5
-
* Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
6
-
*
7
-
* MPC837x MDS board specific routines
8
-
*/
9
-
10
-
#include <linux/pci.h>
11
-
#include <linux/of.h>
12
-
#include <linux/of_address.h>
13
-
#include <linux/of_platform.h>
14
-
15
-
#include <asm/time.h>
16
-
#include <asm/ipic.h>
17
-
#include <asm/udbg.h>
18
-
#include <sysdev/fsl_pci.h>
19
-
20
-
#include "mpc83xx.h"
21
-
22
-
#define BCSR12_USB_SER_MASK 0x8a
23
-
#define BCSR12_USB_SER_PIN 0x80
24
-
#define BCSR12_USB_SER_DEVICE 0x02
25
-
26
-
static int __init mpc837xmds_usb_cfg(void)
27
-
{
28
-
struct device_node *np;
29
-
const void *phy_type, *mode;
30
-
void __iomem *bcsr_regs = NULL;
31
-
u8 bcsr12;
32
-
int ret;
33
-
34
-
ret = mpc837x_usb_cfg();
35
-
if (ret)
36
-
return ret;
37
-
/* Map BCSR area */
38
-
np = of_find_compatible_node(NULL, NULL, "fsl,mpc837xmds-bcsr");
39
-
if (np) {
40
-
bcsr_regs = of_iomap(np, 0);
41
-
of_node_put(np);
42
-
}
43
-
if (!bcsr_regs)
44
-
return -1;
45
-
46
-
np = of_find_node_by_name(NULL, "usb");
47
-
if (!np) {
48
-
ret = -ENODEV;
49
-
goto out;
50
-
}
51
-
phy_type = of_get_property(np, "phy_type", NULL);
52
-
if (phy_type && !strcmp(phy_type, "ulpi")) {
53
-
clrbits8(bcsr_regs + 12, BCSR12_USB_SER_PIN);
54
-
} else if (phy_type && !strcmp(phy_type, "serial")) {
55
-
mode = of_get_property(np, "dr_mode", NULL);
56
-
bcsr12 = in_8(bcsr_regs + 12) & ~BCSR12_USB_SER_MASK;
57
-
bcsr12 |= BCSR12_USB_SER_PIN;
58
-
if (mode && !strcmp(mode, "peripheral"))
59
-
bcsr12 |= BCSR12_USB_SER_DEVICE;
60
-
out_8(bcsr_regs + 12, bcsr12);
61
-
} else {
62
-
printk(KERN_ERR "USB DR: unsupported PHY\n");
63
-
}
64
-
65
-
of_node_put(np);
66
-
out:
67
-
iounmap(bcsr_regs);
68
-
return ret;
69
-
}
70
-
71
-
/* ************************************************************************
72
-
*
73
-
* Setup the architecture
74
-
*
75
-
*/
76
-
static void __init mpc837x_mds_setup_arch(void)
77
-
{
78
-
mpc83xx_setup_arch();
79
-
mpc837xmds_usb_cfg();
80
-
}
81
-
82
-
machine_device_initcall(mpc837x_mds, mpc83xx_declare_of_platform_devices);
83
-
84
-
/*
85
-
* Called very early, MMU is off, device-tree isn't unflattened
86
-
*/
87
-
static int __init mpc837x_mds_probe(void)
88
-
{
89
-
return of_machine_is_compatible("fsl,mpc837xmds");
90
-
}
91
-
92
-
define_machine(mpc837x_mds) {
93
-
.name = "MPC837x MDS",
94
-
.probe = mpc837x_mds_probe,
95
-
.setup_arch = mpc837x_mds_setup_arch,
96
-
.discover_phbs = mpc83xx_setup_pci,
97
-
.init_IRQ = mpc83xx_ipic_init_IRQ,
98
-
.get_irq = ipic_get_irq,
99
-
.restart = mpc83xx_restart,
100
-
.time_init = mpc83xx_time_init,
101
-
.calibrate_decr = generic_calibrate_decr,
102
-
.progress = udbg_progress,
103
-
};
-1
arch/powerpc/platforms/83xx/mpc837x_rdb.c
-1
arch/powerpc/platforms/83xx/mpc837x_rdb.c
+18
-5
arch/powerpc/platforms/85xx/Kconfig
+18
-5
arch/powerpc/platforms/85xx/Kconfig
···
78
78
This option enables support for the MPC8536 DS board
79
79
80
80
config MPC85xx_DS
81
-
bool "Freescale MPC8544 DS / MPC8572 DS / P2020 DS"
81
+
bool "Freescale MPC8544 DS / MPC8572 DS"
82
82
select PPC_I8259
83
83
select DEFAULT_UIMAGE
84
84
select FSL_ULI1575 if PCI
85
85
select SWIOTLB
86
86
help
87
-
This option enables support for the MPC8544 DS, MPC8572 DS and P2020 DS boards
87
+
This option enables support for the MPC8544 DS and MPC8572 DS boards
88
88
89
89
config MPC85xx_RDB
90
-
bool "Freescale P102x MBG/UTM/RDB and P2020 RDB"
90
+
bool "Freescale P102x MBG/UTM/RDB"
91
91
select PPC_I8259
92
92
select DEFAULT_UIMAGE
93
-
select FSL_ULI1575 if PCI
94
93
select SWIOTLB
95
94
help
96
95
This option enables support for the P1020 MBG PC, P1020 UTM PC,
97
96
P1020 RDB PC, P1020 RDB PD, P1020 RDB, P1021 RDB PC, P1024 RDB,
98
-
P1025 RDB, P2020 RDB and P2020 RDB PC boards
97
+
and P1025 RDB boards
98
+
99
+
config PPC_P2020
100
+
bool "Freescale P2020"
101
+
default y if MPC85xx_DS || MPC85xx_RDB
102
+
select DEFAULT_UIMAGE
103
+
select SWIOTLB
104
+
imply PPC_I8259
105
+
imply FSL_ULI1575 if PCI
106
+
help
107
+
This option enables generic unified support for any board with the
108
+
Freescale P2020 processor.
109
+
110
+
For example: P2020 DS board, P2020 RDB board, P2020 RDB PC board or
111
+
CZ.NIC Turris 1.x boards.
99
112
100
113
config P1010_RDB
101
114
bool "Freescale P1010 RDB"
+3
-1
arch/powerpc/platforms/85xx/Makefile
+3
-1
arch/powerpc/platforms/85xx/Makefile
···
16
16
obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o
17
17
obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o
18
18
obj-$(CONFIG_MPC8536_DS) += mpc8536_ds.o
19
-
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o
19
+
obj8259-$(CONFIG_PPC_I8259) += mpc85xx_8259.o
20
+
obj-$(CONFIG_MPC85xx_DS) += mpc85xx_ds.o $(obj8259-y)
20
21
obj-$(CONFIG_MPC85xx_MDS) += mpc85xx_mds.o
21
22
obj-$(CONFIG_MPC85xx_RDB) += mpc85xx_rdb.o
22
23
obj-$(CONFIG_P1010_RDB) += p1010rdb.o
23
24
obj-$(CONFIG_P1022_DS) += p1022_ds.o
24
25
obj-$(CONFIG_P1022_RDK) += p1022_rdk.o
25
26
obj-$(CONFIG_P1023_RDB) += p1023_rdb.o
27
+
obj-$(CONFIG_PPC_P2020) += p2020.o $(obj8259-y)
26
28
obj-$(CONFIG_TWR_P102x) += twr_p102x.o
27
29
obj-$(CONFIG_CORENET_GENERIC) += corenet_generic.o
28
30
obj-$(CONFIG_FB_FSL_DIU) += t1042rdb_diu.o
+1
-11
arch/powerpc/platforms/85xx/bsc913x_qds.c
+1
-11
arch/powerpc/platforms/85xx/bsc913x_qds.c
···
50
50
51
51
machine_arch_initcall(bsc9132_qds, mpc85xx_common_publish_devices);
52
52
53
-
/*
54
-
* Called very early, device-tree isn't unflattened
55
-
*/
56
-
57
-
static int __init bsc9132_qds_probe(void)
58
-
{
59
-
return of_machine_is_compatible("fsl,bsc9132qds");
60
-
}
61
-
62
53
define_machine(bsc9132_qds) {
63
54
.name = "BSC9132 QDS",
64
-
.probe = bsc9132_qds_probe,
55
+
.compatible = "fsl,bsc9132qds",
65
56
.setup_arch = bsc913x_qds_setup_arch,
66
57
.init_IRQ = bsc913x_qds_pic_init,
67
58
#ifdef CONFIG_PCI
68
59
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
69
60
#endif
70
61
.get_irq = mpic_get_irq,
71
-
.calibrate_decr = generic_calibrate_decr,
72
62
.progress = udbg_progress,
73
63
};
+1
-11
arch/powerpc/platforms/85xx/bsc913x_rdb.c
+1
-11
arch/powerpc/platforms/85xx/bsc913x_rdb.c
···
40
40
41
41
machine_device_initcall(bsc9131_rdb, mpc85xx_common_publish_devices);
42
42
43
-
/*
44
-
* Called very early, device-tree isn't unflattened
45
-
*/
46
-
47
-
static int __init bsc9131_rdb_probe(void)
48
-
{
49
-
return of_machine_is_compatible("fsl,bsc9131rdb");
50
-
}
51
-
52
43
define_machine(bsc9131_rdb) {
53
44
.name = "BSC9131 RDB",
54
-
.probe = bsc9131_rdb_probe,
45
+
.compatible = "fsl,bsc9131rdb",
55
46
.setup_arch = bsc913x_rdb_setup_arch,
56
47
.init_IRQ = bsc913x_rdb_pic_init,
57
48
.get_irq = mpic_get_irq,
58
-
.calibrate_decr = generic_calibrate_decr,
59
49
.progress = udbg_progress,
60
50
};
+1
-12
arch/powerpc/platforms/85xx/c293pcie.c
+1
-12
arch/powerpc/platforms/85xx/c293pcie.c
···
45
45
46
46
machine_arch_initcall(c293_pcie, mpc85xx_common_publish_devices);
47
47
48
-
/*
49
-
* Called very early, device-tree isn't unflattened
50
-
*/
51
-
static int __init c293_pcie_probe(void)
52
-
{
53
-
if (of_machine_is_compatible("fsl,C293PCIE"))
54
-
return 1;
55
-
return 0;
56
-
}
57
-
58
48
define_machine(c293_pcie) {
59
49
.name = "C293 PCIE",
60
-
.probe = c293_pcie_probe,
50
+
.compatible = "fsl,C293PCIE",
61
51
.setup_arch = c293_pcie_setup_arch,
62
52
.init_IRQ = c293_pcie_pic_init,
63
53
.get_irq = mpic_get_irq,
64
-
.calibrate_decr = generic_calibrate_decr,
65
54
.progress = udbg_progress,
66
55
};
-1
arch/powerpc/platforms/85xx/corenet_generic.c
-1
arch/powerpc/platforms/85xx/corenet_generic.c
+1
-10
arch/powerpc/platforms/85xx/ge_imp3a.c
+1
-10
arch/powerpc/platforms/85xx/ge_imp3a.c
···
190
190
ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
191
191
}
192
192
193
-
/*
194
-
* Called very early, device-tree isn't unflattened
195
-
*/
196
-
static int __init ge_imp3a_probe(void)
197
-
{
198
-
return of_machine_is_compatible("ge,IMP3A");
199
-
}
200
-
201
193
machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);
202
194
203
195
define_machine(ge_imp3a) {
204
196
.name = "GE_IMP3A",
205
-
.probe = ge_imp3a_probe,
197
+
.compatible = "ge,IMP3A",
206
198
.setup_arch = ge_imp3a_setup_arch,
207
199
.init_IRQ = ge_imp3a_pic_init,
208
200
.show_cpuinfo = ge_imp3a_show_cpuinfo,
···
203
211
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
204
212
#endif
205
213
.get_irq = mpic_get_irq,
206
-
.calibrate_decr = generic_calibrate_decr,
207
214
.progress = udbg_progress,
208
215
};
+1
-10
arch/powerpc/platforms/85xx/ksi8560.c
+1
-10
arch/powerpc/platforms/85xx/ksi8560.c
···
172
172
173
173
machine_device_initcall(ksi8560, mpc85xx_common_publish_devices);
174
174
175
-
/*
176
-
* Called very early, device-tree isn't unflattened
177
-
*/
178
-
static int __init ksi8560_probe(void)
179
-
{
180
-
return of_machine_is_compatible("emerson,KSI8560");
181
-
}
182
-
183
175
define_machine(ksi8560) {
184
176
.name = "KSI8560",
185
-
.probe = ksi8560_probe,
177
+
.compatible = "emerson,KSI8560",
186
178
.setup_arch = ksi8560_setup_arch,
187
179
.init_IRQ = ksi8560_pic_init,
188
180
.show_cpuinfo = ksi8560_show_cpuinfo,
189
181
.get_irq = mpic_get_irq,
190
182
.restart = machine_restart,
191
-
.calibrate_decr = generic_calibrate_decr,
192
183
};
+1
-10
arch/powerpc/platforms/85xx/mpc8536_ds.c
+1
-10
arch/powerpc/platforms/85xx/mpc8536_ds.c
···
52
52
53
53
machine_arch_initcall(mpc8536_ds, mpc85xx_common_publish_devices);
54
54
55
-
/*
56
-
* Called very early, device-tree isn't unflattened
57
-
*/
58
-
static int __init mpc8536_ds_probe(void)
59
-
{
60
-
return of_machine_is_compatible("fsl,mpc8536ds");
61
-
}
62
-
63
55
define_machine(mpc8536_ds) {
64
56
.name = "MPC8536 DS",
65
-
.probe = mpc8536_ds_probe,
57
+
.compatible = "fsl,mpc8536ds",
66
58
.setup_arch = mpc8536_ds_setup_arch,
67
59
.init_IRQ = mpc8536_ds_pic_init,
68
60
#ifdef CONFIG_PCI
···
62
70
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
63
71
#endif
64
72
.get_irq = mpic_get_irq,
65
-
.calibrate_decr = generic_calibrate_decr,
66
73
.progress = udbg_progress,
67
74
};
+6
arch/powerpc/platforms/85xx/mpc85xx.h
+6
arch/powerpc/platforms/85xx/mpc85xx.h
+64
arch/powerpc/platforms/85xx/mpc85xx_8259.c
+64
arch/powerpc/platforms/85xx/mpc85xx_8259.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* MPC85xx 8259 functions for DS Board Setup
4
+
*
5
+
* Author Xianghua Xiao (x.xiao@freescale.com)
6
+
* Roy Zang <tie-fei.zang@freescale.com>
7
+
* - Add PCI/PCI Express support
8
+
* Copyright 2007 Freescale Semiconductor Inc.
9
+
*/
10
+
11
+
#include <linux/stddef.h>
12
+
#include <linux/kernel.h>
13
+
#include <linux/interrupt.h>
14
+
#include <linux/of_irq.h>
15
+
#include <linux/of_platform.h>
16
+
17
+
#include <asm/mpic.h>
18
+
#include <asm/i8259.h>
19
+
20
+
#include "mpc85xx.h"
21
+
22
+
static void mpc85xx_8259_cascade(struct irq_desc *desc)
23
+
{
24
+
struct irq_chip *chip = irq_desc_get_chip(desc);
25
+
unsigned int cascade_irq = i8259_irq();
26
+
27
+
if (cascade_irq)
28
+
generic_handle_irq(cascade_irq);
29
+
30
+
chip->irq_eoi(&desc->irq_data);
31
+
}
32
+
33
+
void __init mpc85xx_8259_init(void)
34
+
{
35
+
struct device_node *np;
36
+
struct device_node *cascade_node = NULL;
37
+
int cascade_irq;
38
+
39
+
/* Initialize the i8259 controller */
40
+
for_each_node_by_type(np, "interrupt-controller") {
41
+
if (of_device_is_compatible(np, "chrp,iic")) {
42
+
cascade_node = np;
43
+
break;
44
+
}
45
+
}
46
+
47
+
if (cascade_node == NULL) {
48
+
pr_debug("i8259: Could not find i8259 PIC\n");
49
+
return;
50
+
}
51
+
52
+
cascade_irq = irq_of_parse_and_map(cascade_node, 0);
53
+
if (!cascade_irq) {
54
+
pr_err("i8259: Failed to map cascade interrupt\n");
55
+
return;
56
+
}
57
+
58
+
pr_debug("i8259: cascade mapped to irq %d\n", cascade_irq);
59
+
60
+
i8259_init(cascade_node, 0);
61
+
of_node_put(cascade_node);
62
+
63
+
irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
64
+
}
+1
-10
arch/powerpc/platforms/85xx/mpc85xx_ads.c
+1
-10
arch/powerpc/platforms/85xx/mpc85xx_ads.c
···
151
151
152
152
machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
153
153
154
-
/*
155
-
* Called very early, device-tree isn't unflattened
156
-
*/
157
-
static int __init mpc85xx_ads_probe(void)
158
-
{
159
-
return of_machine_is_compatible("MPC85xxADS");
160
-
}
161
-
162
154
define_machine(mpc85xx_ads) {
163
155
.name = "MPC85xx ADS",
164
-
.probe = mpc85xx_ads_probe,
156
+
.compatible = "MPC85xxADS",
165
157
.setup_arch = mpc85xx_ads_setup_arch,
166
158
.init_IRQ = mpc85xx_ads_pic_init,
167
159
.show_cpuinfo = mpc85xx_ads_show_cpuinfo,
168
160
.get_irq = mpic_get_irq,
169
-
.calibrate_decr = generic_calibrate_decr,
170
161
.progress = udbg_progress,
171
162
};
+1
-11
arch/powerpc/platforms/85xx/mpc85xx_cds.c
+1
-11
arch/powerpc/platforms/85xx/mpc85xx_cds.c
···
370
370
seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
371
371
}
372
372
373
-
374
-
/*
375
-
* Called very early, device-tree isn't unflattened
376
-
*/
377
-
static int __init mpc85xx_cds_probe(void)
378
-
{
379
-
return of_machine_is_compatible("MPC85xxCDS");
380
-
}
381
-
382
373
machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
383
374
384
375
define_machine(mpc85xx_cds) {
385
376
.name = "MPC85xx CDS",
386
-
.probe = mpc85xx_cds_probe,
377
+
.compatible = "MPC85xxCDS",
387
378
.setup_arch = mpc85xx_cds_setup_arch,
388
379
.init_IRQ = mpc85xx_cds_pic_init,
389
380
.show_cpuinfo = mpc85xx_cds_show_cpuinfo,
···
383
392
.pcibios_fixup_bus = mpc85xx_cds_fixup_bus,
384
393
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
385
394
#endif
386
-
.calibrate_decr = generic_calibrate_decr,
387
395
.progress = udbg_progress,
388
396
};
+16
-147
arch/powerpc/platforms/85xx/mpc85xx_ds.c
+16
-147
arch/powerpc/platforms/85xx/mpc85xx_ds.c
···
26
26
#include <asm/mpic.h>
27
27
#include <asm/i8259.h>
28
28
#include <asm/swiotlb.h>
29
+
#include <asm/ppc-pci.h>
29
30
30
31
#include <sysdev/fsl_soc.h>
31
32
#include <sysdev/fsl_pci.h>
···
34
33
35
34
#include "mpc85xx.h"
36
35
37
-
#undef DEBUG
38
-
39
-
#ifdef DEBUG
40
-
#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
41
-
#else
42
-
#define DBG(fmt, args...)
43
-
#endif
44
-
45
-
#ifdef CONFIG_PPC_I8259
46
-
static void mpc85xx_8259_cascade(struct irq_desc *desc)
47
-
{
48
-
struct irq_chip *chip = irq_desc_get_chip(desc);
49
-
unsigned int cascade_irq = i8259_irq();
50
-
51
-
if (cascade_irq) {
52
-
generic_handle_irq(cascade_irq);
53
-
}
54
-
chip->irq_eoi(&desc->irq_data);
55
-
}
56
-
#endif /* CONFIG_PPC_I8259 */
57
-
58
-
void __init mpc85xx_ds_pic_init(void)
36
+
static void __init mpc85xx_ds_pic_init(void)
59
37
{
60
38
struct mpic *mpic;
61
-
#ifdef CONFIG_PPC_I8259
62
-
struct device_node *np;
63
-
struct device_node *cascade_node = NULL;
64
-
int cascade_irq;
65
-
#endif
66
-
if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) {
67
-
mpic = mpic_alloc(NULL, 0,
68
-
MPIC_NO_RESET |
69
-
MPIC_BIG_ENDIAN |
70
-
MPIC_SINGLE_DEST_CPU,
71
-
0, 256, " OpenPIC ");
72
-
} else {
73
-
mpic = mpic_alloc(NULL, 0,
74
-
MPIC_BIG_ENDIAN |
75
-
MPIC_SINGLE_DEST_CPU,
76
-
0, 256, " OpenPIC ");
77
-
}
39
+
int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU;
78
40
79
-
BUG_ON(mpic == NULL);
41
+
if (of_machine_is_compatible("fsl,MPC8572DS-CAMP"))
42
+
flags |= MPIC_NO_RESET;
43
+
44
+
mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
45
+
46
+
if (WARN_ON(!mpic))
47
+
return;
48
+
80
49
mpic_init(mpic);
81
50
82
-
#ifdef CONFIG_PPC_I8259
83
-
/* Initialize the i8259 controller */
84
-
for_each_node_by_type(np, "interrupt-controller")
85
-
if (of_device_is_compatible(np, "chrp,iic")) {
86
-
cascade_node = np;
87
-
break;
88
-
}
89
-
90
-
if (cascade_node == NULL) {
91
-
printk(KERN_DEBUG "Could not find i8259 PIC\n");
92
-
return;
93
-
}
94
-
95
-
cascade_irq = irq_of_parse_and_map(cascade_node, 0);
96
-
if (!cascade_irq) {
97
-
printk(KERN_ERR "Failed to map cascade interrupt\n");
98
-
return;
99
-
}
100
-
101
-
DBG("mpc85xxds: cascade mapped to irq %d\n", cascade_irq);
102
-
103
-
i8259_init(cascade_node, 0);
104
-
of_node_put(cascade_node);
105
-
106
-
irq_set_chained_handler(cascade_irq, mpc85xx_8259_cascade);
107
-
#endif /* CONFIG_PPC_I8259 */
108
-
}
109
-
110
-
#ifdef CONFIG_PCI
111
-
extern int uli_exclude_device(struct pci_controller *hose,
112
-
u_char bus, u_char devfn);
113
-
114
-
static struct device_node *pci_with_uli;
115
-
116
-
static int mpc85xx_exclude_device(struct pci_controller *hose,
117
-
u_char bus, u_char devfn)
118
-
{
119
-
if (hose->dn == pci_with_uli)
120
-
return uli_exclude_device(hose, bus, devfn);
121
-
122
-
return PCIBIOS_SUCCESSFUL;
123
-
}
124
-
#endif /* CONFIG_PCI */
125
-
126
-
static void __init mpc85xx_ds_uli_init(void)
127
-
{
128
-
#ifdef CONFIG_PCI
129
-
struct device_node *node;
130
-
131
-
/* See if we have a ULI under the primary */
132
-
133
-
node = of_find_node_by_name(NULL, "uli1575");
134
-
while ((pci_with_uli = of_get_parent(node))) {
135
-
of_node_put(node);
136
-
node = pci_with_uli;
137
-
138
-
if (pci_with_uli == fsl_pci_primary) {
139
-
ppc_md.pci_exclude_device = mpc85xx_exclude_device;
140
-
break;
141
-
}
142
-
}
143
-
#endif
51
+
mpc85xx_8259_init();
144
52
}
145
53
146
54
/*
···
62
152
63
153
swiotlb_detect_4g();
64
154
fsl_pci_assign_primary();
65
-
mpc85xx_ds_uli_init();
155
+
uli_init();
66
156
mpc85xx_smp_init();
67
157
68
-
printk("MPC85xx DS board from Freescale Semiconductor\n");
69
-
}
70
-
71
-
/*
72
-
* Called very early, device-tree isn't unflattened
73
-
*/
74
-
static int __init mpc8544_ds_probe(void)
75
-
{
76
-
return !!of_machine_is_compatible("MPC8544DS");
158
+
pr_info("MPC85xx DS board from Freescale Semiconductor\n");
77
159
}
78
160
79
161
machine_arch_initcall(mpc8544_ds, mpc85xx_common_publish_devices);
80
162
machine_arch_initcall(mpc8572_ds, mpc85xx_common_publish_devices);
81
-
machine_arch_initcall(p2020_ds, mpc85xx_common_publish_devices);
82
-
83
-
/*
84
-
* Called very early, device-tree isn't unflattened
85
-
*/
86
-
static int __init mpc8572_ds_probe(void)
87
-
{
88
-
return !!of_machine_is_compatible("fsl,MPC8572DS");
89
-
}
90
-
91
-
/*
92
-
* Called very early, device-tree isn't unflattened
93
-
*/
94
-
static int __init p2020_ds_probe(void)
95
-
{
96
-
return !!of_machine_is_compatible("fsl,P2020DS");
97
-
}
98
163
99
164
define_machine(mpc8544_ds) {
100
165
.name = "MPC8544 DS",
101
-
.probe = mpc8544_ds_probe,
166
+
.compatible = "MPC8544DS",
102
167
.setup_arch = mpc85xx_ds_setup_arch,
103
168
.init_IRQ = mpc85xx_ds_pic_init,
104
169
#ifdef CONFIG_PCI
···
81
196
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
82
197
#endif
83
198
.get_irq = mpic_get_irq,
84
-
.calibrate_decr = generic_calibrate_decr,
85
199
.progress = udbg_progress,
86
200
};
87
201
88
202
define_machine(mpc8572_ds) {
89
203
.name = "MPC8572 DS",
90
-
.probe = mpc8572_ds_probe,
204
+
.compatible = "fsl,MPC8572DS",
91
205
.setup_arch = mpc85xx_ds_setup_arch,
92
206
.init_IRQ = mpc85xx_ds_pic_init,
93
207
#ifdef CONFIG_PCI
···
94
210
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
95
211
#endif
96
212
.get_irq = mpic_get_irq,
97
-
.calibrate_decr = generic_calibrate_decr,
98
-
.progress = udbg_progress,
99
-
};
100
-
101
-
define_machine(p2020_ds) {
102
-
.name = "P2020 DS",
103
-
.probe = p2020_ds_probe,
104
-
.setup_arch = mpc85xx_ds_setup_arch,
105
-
.init_IRQ = mpc85xx_ds_pic_init,
106
-
#ifdef CONFIG_PCI
107
-
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
108
-
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
109
-
#endif
110
-
.get_irq = mpic_get_irq,
111
-
.calibrate_decr = generic_calibrate_decr,
112
213
.progress = udbg_progress,
113
214
};
+3
-29
arch/powerpc/platforms/85xx/mpc85xx_mds.c
+3
-29
arch/powerpc/platforms/85xx/mpc85xx_mds.c
···
49
49
50
50
#include "mpc85xx.h"
51
51
52
-
#undef DEBUG
53
-
#ifdef DEBUG
54
-
#define DBG(fmt...) udbg_printf(fmt)
55
-
#else
56
-
#define DBG(fmt...)
57
-
#endif
58
-
59
52
#if IS_BUILTIN(CONFIG_PHYLIB)
60
53
61
54
#define MV88E1111_SCR 0x10
···
332
339
mpic_init(mpic);
333
340
}
334
341
335
-
static int __init mpc85xx_mds_probe(void)
336
-
{
337
-
return of_machine_is_compatible("MPC85xxMDS");
338
-
}
339
-
340
342
define_machine(mpc8568_mds) {
341
343
.name = "MPC8568 MDS",
342
-
.probe = mpc85xx_mds_probe,
344
+
.compatible = "MPC85xxMDS",
343
345
.setup_arch = mpc85xx_mds_setup_arch,
344
346
.init_IRQ = mpc85xx_mds_pic_init,
345
347
.get_irq = mpic_get_irq,
346
-
.calibrate_decr = generic_calibrate_decr,
347
348
.progress = udbg_progress,
348
349
#ifdef CONFIG_PCI
349
350
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
350
351
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
351
352
#endif
352
353
};
353
-
354
-
static int __init mpc8569_mds_probe(void)
355
-
{
356
-
return of_machine_is_compatible("fsl,MPC8569EMDS");
357
-
}
358
354
359
355
define_machine(mpc8569_mds) {
360
356
.name = "MPC8569 MDS",
361
-
.probe = mpc8569_mds_probe,
357
+
.compatible = "fsl,MPC8569EMDS",
362
358
.setup_arch = mpc85xx_mds_setup_arch,
363
359
.init_IRQ = mpc85xx_mds_pic_init,
364
360
.get_irq = mpic_get_irq,
365
-
.calibrate_decr = generic_calibrate_decr,
366
361
.progress = udbg_progress,
367
362
#ifdef CONFIG_PCI
368
363
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
···
358
377
#endif
359
378
};
360
379
361
-
static int __init p1021_mds_probe(void)
362
-
{
363
-
return of_machine_is_compatible("fsl,P1021MDS");
364
-
365
-
}
366
-
367
380
define_machine(p1021_mds) {
368
381
.name = "P1021 MDS",
369
-
.probe = p1021_mds_probe,
382
+
.compatible = "fsl,P1021MDS",
370
383
.setup_arch = mpc85xx_mds_setup_arch,
371
384
.init_IRQ = mpc85xx_mds_pic_init,
372
385
.get_irq = mpic_get_irq,
373
-
.calibrate_decr = generic_calibrate_decr,
374
386
.progress = udbg_progress,
375
387
#ifdef CONFIG_PCI
376
388
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+18
-132
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+18
-132
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
···
29
29
30
30
#include "mpc85xx.h"
31
31
32
-
#undef DEBUG
33
-
34
-
#ifdef DEBUG
35
-
#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
36
-
#else
37
-
#define DBG(fmt, args...)
38
-
#endif
39
-
40
-
41
-
void __init mpc85xx_rdb_pic_init(void)
32
+
static void __init mpc85xx_rdb_pic_init(void)
42
33
{
43
34
struct mpic *mpic;
35
+
int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU;
44
36
45
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
46
-
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
47
-
MPIC_BIG_ENDIAN |
48
-
MPIC_SINGLE_DEST_CPU,
49
-
0, 256, " OpenPIC ");
50
-
} else {
51
-
mpic = mpic_alloc(NULL, 0,
52
-
MPIC_BIG_ENDIAN |
53
-
MPIC_SINGLE_DEST_CPU,
54
-
0, 256, " OpenPIC ");
55
-
}
37
+
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP"))
38
+
flags |= MPIC_NO_RESET;
56
39
57
-
BUG_ON(mpic == NULL);
40
+
mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
41
+
42
+
if (WARN_ON(!mpic))
43
+
return;
44
+
58
45
mpic_init(mpic);
59
46
}
60
47
···
57
70
58
71
fsl_pci_assign_primary();
59
72
60
-
#ifdef CONFIG_QUICC_ENGINE
61
73
mpc85xx_qe_par_io_init();
62
74
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
63
75
if (machine_is(p1025_rdb)) {
···
89
103
90
104
}
91
105
#endif
92
-
#endif /* CONFIG_QUICC_ENGINE */
93
106
94
-
printk(KERN_INFO "MPC85xx RDB board from Freescale Semiconductor\n");
107
+
pr_info("MPC85xx RDB board from Freescale Semiconductor\n");
95
108
}
96
109
97
-
machine_arch_initcall(p2020_rdb, mpc85xx_common_publish_devices);
98
-
machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
99
110
machine_arch_initcall(p1020_mbg_pc, mpc85xx_common_publish_devices);
100
111
machine_arch_initcall(p1020_rdb, mpc85xx_common_publish_devices);
101
112
machine_arch_initcall(p1020_rdb_pc, mpc85xx_common_publish_devices);
···
102
119
machine_arch_initcall(p1025_rdb, mpc85xx_common_publish_devices);
103
120
machine_arch_initcall(p1024_rdb, mpc85xx_common_publish_devices);
104
121
105
-
/*
106
-
* Called very early, device-tree isn't unflattened
107
-
*/
108
-
static int __init p2020_rdb_probe(void)
109
-
{
110
-
if (of_machine_is_compatible("fsl,P2020RDB"))
111
-
return 1;
112
-
return 0;
113
-
}
114
-
115
-
static int __init p1020_rdb_probe(void)
116
-
{
117
-
if (of_machine_is_compatible("fsl,P1020RDB"))
118
-
return 1;
119
-
return 0;
120
-
}
121
-
122
-
static int __init p1020_rdb_pc_probe(void)
123
-
{
124
-
return of_machine_is_compatible("fsl,P1020RDB-PC");
125
-
}
126
-
127
-
static int __init p1020_rdb_pd_probe(void)
128
-
{
129
-
return of_machine_is_compatible("fsl,P1020RDB-PD");
130
-
}
131
-
132
-
static int __init p1021_rdb_pc_probe(void)
133
-
{
134
-
if (of_machine_is_compatible("fsl,P1021RDB-PC"))
135
-
return 1;
136
-
return 0;
137
-
}
138
-
139
-
static int __init p2020_rdb_pc_probe(void)
140
-
{
141
-
if (of_machine_is_compatible("fsl,P2020RDB-PC"))
142
-
return 1;
143
-
return 0;
144
-
}
145
-
146
-
static int __init p1025_rdb_probe(void)
147
-
{
148
-
return of_machine_is_compatible("fsl,P1025RDB");
149
-
}
150
-
151
-
static int __init p1020_mbg_pc_probe(void)
152
-
{
153
-
return of_machine_is_compatible("fsl,P1020MBG-PC");
154
-
}
155
-
156
-
static int __init p1020_utm_pc_probe(void)
157
-
{
158
-
return of_machine_is_compatible("fsl,P1020UTM-PC");
159
-
}
160
-
161
-
static int __init p1024_rdb_probe(void)
162
-
{
163
-
return of_machine_is_compatible("fsl,P1024RDB");
164
-
}
165
-
166
-
define_machine(p2020_rdb) {
167
-
.name = "P2020 RDB",
168
-
.probe = p2020_rdb_probe,
169
-
.setup_arch = mpc85xx_rdb_setup_arch,
170
-
.init_IRQ = mpc85xx_rdb_pic_init,
171
-
#ifdef CONFIG_PCI
172
-
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
173
-
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
174
-
#endif
175
-
.get_irq = mpic_get_irq,
176
-
.calibrate_decr = generic_calibrate_decr,
177
-
.progress = udbg_progress,
178
-
};
179
-
180
122
define_machine(p1020_rdb) {
181
123
.name = "P1020 RDB",
182
-
.probe = p1020_rdb_probe,
124
+
.compatible = "fsl,P1020RDB",
183
125
.setup_arch = mpc85xx_rdb_setup_arch,
184
126
.init_IRQ = mpc85xx_rdb_pic_init,
185
127
#ifdef CONFIG_PCI
···
112
204
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
113
205
#endif
114
206
.get_irq = mpic_get_irq,
115
-
.calibrate_decr = generic_calibrate_decr,
116
207
.progress = udbg_progress,
117
208
};
118
209
119
210
define_machine(p1021_rdb_pc) {
120
211
.name = "P1021 RDB-PC",
121
-
.probe = p1021_rdb_pc_probe,
212
+
.compatible = "fsl,P1021RDB-PC",
122
213
.setup_arch = mpc85xx_rdb_setup_arch,
123
214
.init_IRQ = mpc85xx_rdb_pic_init,
124
215
#ifdef CONFIG_PCI
···
125
218
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
126
219
#endif
127
220
.get_irq = mpic_get_irq,
128
-
.calibrate_decr = generic_calibrate_decr,
129
-
.progress = udbg_progress,
130
-
};
131
-
132
-
define_machine(p2020_rdb_pc) {
133
-
.name = "P2020RDB-PC",
134
-
.probe = p2020_rdb_pc_probe,
135
-
.setup_arch = mpc85xx_rdb_setup_arch,
136
-
.init_IRQ = mpc85xx_rdb_pic_init,
137
-
#ifdef CONFIG_PCI
138
-
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
139
-
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
140
-
#endif
141
-
.get_irq = mpic_get_irq,
142
-
.calibrate_decr = generic_calibrate_decr,
143
221
.progress = udbg_progress,
144
222
};
145
223
146
224
define_machine(p1025_rdb) {
147
225
.name = "P1025 RDB",
148
-
.probe = p1025_rdb_probe,
226
+
.compatible = "fsl,P1025RDB",
149
227
.setup_arch = mpc85xx_rdb_setup_arch,
150
228
.init_IRQ = mpc85xx_rdb_pic_init,
151
229
#ifdef CONFIG_PCI
···
138
246
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
139
247
#endif
140
248
.get_irq = mpic_get_irq,
141
-
.calibrate_decr = generic_calibrate_decr,
142
249
.progress = udbg_progress,
143
250
};
144
251
145
252
define_machine(p1020_mbg_pc) {
146
253
.name = "P1020 MBG-PC",
147
-
.probe = p1020_mbg_pc_probe,
254
+
.compatible = "fsl,P1020MBG-PC",
148
255
.setup_arch = mpc85xx_rdb_setup_arch,
149
256
.init_IRQ = mpc85xx_rdb_pic_init,
150
257
#ifdef CONFIG_PCI
···
151
260
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
152
261
#endif
153
262
.get_irq = mpic_get_irq,
154
-
.calibrate_decr = generic_calibrate_decr,
155
263
.progress = udbg_progress,
156
264
};
157
265
158
266
define_machine(p1020_utm_pc) {
159
267
.name = "P1020 UTM-PC",
160
-
.probe = p1020_utm_pc_probe,
268
+
.compatible = "fsl,P1020UTM-PC",
161
269
.setup_arch = mpc85xx_rdb_setup_arch,
162
270
.init_IRQ = mpc85xx_rdb_pic_init,
163
271
#ifdef CONFIG_PCI
···
164
274
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
165
275
#endif
166
276
.get_irq = mpic_get_irq,
167
-
.calibrate_decr = generic_calibrate_decr,
168
277
.progress = udbg_progress,
169
278
};
170
279
171
280
define_machine(p1020_rdb_pc) {
172
281
.name = "P1020RDB-PC",
173
-
.probe = p1020_rdb_pc_probe,
282
+
.compatible = "fsl,P1020RDB-PC",
174
283
.setup_arch = mpc85xx_rdb_setup_arch,
175
284
.init_IRQ = mpc85xx_rdb_pic_init,
176
285
#ifdef CONFIG_PCI
···
177
288
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
178
289
#endif
179
290
.get_irq = mpic_get_irq,
180
-
.calibrate_decr = generic_calibrate_decr,
181
291
.progress = udbg_progress,
182
292
};
183
293
184
294
define_machine(p1020_rdb_pd) {
185
295
.name = "P1020RDB-PD",
186
-
.probe = p1020_rdb_pd_probe,
296
+
.compatible = "fsl,P1020RDB-PD",
187
297
.setup_arch = mpc85xx_rdb_setup_arch,
188
298
.init_IRQ = mpc85xx_rdb_pic_init,
189
299
#ifdef CONFIG_PCI
···
190
302
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
191
303
#endif
192
304
.get_irq = mpic_get_irq,
193
-
.calibrate_decr = generic_calibrate_decr,
194
305
.progress = udbg_progress,
195
306
};
196
307
197
308
define_machine(p1024_rdb) {
198
309
.name = "P1024 RDB",
199
-
.probe = p1024_rdb_probe,
310
+
.compatible = "fsl,P1024RDB",
200
311
.setup_arch = mpc85xx_rdb_setup_arch,
201
312
.init_IRQ = mpc85xx_rdb_pic_init,
202
313
#ifdef CONFIG_PCI
···
203
316
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
204
317
#endif
205
318
.get_irq = mpic_get_irq,
206
-
.calibrate_decr = generic_calibrate_decr,
207
319
.progress = udbg_progress,
208
320
};
+1
-10
arch/powerpc/platforms/85xx/mvme2500.c
+1
-10
arch/powerpc/platforms/85xx/mvme2500.c
···
43
43
44
44
machine_arch_initcall(mvme2500, mpc85xx_common_publish_devices);
45
45
46
-
/*
47
-
* Called very early, device-tree isn't unflattened
48
-
*/
49
-
static int __init mvme2500_probe(void)
50
-
{
51
-
return of_machine_is_compatible("artesyn,MVME2500");
52
-
}
53
-
54
46
define_machine(mvme2500) {
55
47
.name = "MVME2500",
56
-
.probe = mvme2500_probe,
48
+
.compatible = "artesyn,MVME2500",
57
49
.setup_arch = mvme2500_setup_arch,
58
50
.init_IRQ = mvme2500_pic_init,
59
51
#ifdef CONFIG_PCI
···
53
61
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
54
62
#endif
55
63
.get_irq = mpic_get_irq,
56
-
.calibrate_decr = generic_calibrate_decr,
57
64
.progress = udbg_progress,
58
65
};
-1
arch/powerpc/platforms/85xx/p1010rdb.c
-1
arch/powerpc/platforms/85xx/p1010rdb.c
+1
-10
arch/powerpc/platforms/85xx/p1022_ds.c
+1
-10
arch/powerpc/platforms/85xx/p1022_ds.c
···
549
549
550
550
machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices);
551
551
552
-
/*
553
-
* Called very early, device-tree isn't unflattened
554
-
*/
555
-
static int __init p1022_ds_probe(void)
556
-
{
557
-
return of_machine_is_compatible("fsl,p1022ds");
558
-
}
559
-
560
552
define_machine(p1022_ds) {
561
553
.name = "P1022 DS",
562
-
.probe = p1022_ds_probe,
554
+
.compatible = "fsl,p1022ds",
563
555
.setup_arch = p1022_ds_setup_arch,
564
556
.init_IRQ = p1022_ds_pic_init,
565
557
#ifdef CONFIG_PCI
···
559
567
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
560
568
#endif
561
569
.get_irq = mpic_get_irq,
562
-
.calibrate_decr = generic_calibrate_decr,
563
570
.progress = udbg_progress,
564
571
};
+1
-10
arch/powerpc/platforms/85xx/p1022_rdk.c
+1
-10
arch/powerpc/platforms/85xx/p1022_rdk.c
···
129
129
130
130
machine_arch_initcall(p1022_rdk, mpc85xx_common_publish_devices);
131
131
132
-
/*
133
-
* Called very early, device-tree isn't unflattened
134
-
*/
135
-
static int __init p1022_rdk_probe(void)
136
-
{
137
-
return of_machine_is_compatible("fsl,p1022rdk");
138
-
}
139
-
140
132
define_machine(p1022_rdk) {
141
133
.name = "P1022 RDK",
142
-
.probe = p1022_rdk_probe,
134
+
.compatible = "fsl,p1022rdk",
143
135
.setup_arch = p1022_rdk_setup_arch,
144
136
.init_IRQ = p1022_rdk_pic_init,
145
137
#ifdef CONFIG_PCI
···
139
147
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
140
148
#endif
141
149
.get_irq = mpic_get_irq,
142
-
.calibrate_decr = generic_calibrate_decr,
143
150
.progress = udbg_progress,
144
151
};
+5
-12
arch/powerpc/platforms/85xx/p1023_rdb.c
+5
-12
arch/powerpc/platforms/85xx/p1023_rdb.c
···
37
37
* Setup the architecture
38
38
*
39
39
*/
40
-
static void __init mpc85xx_rdb_setup_arch(void)
40
+
static void __init p1023_rdb_setup_arch(void)
41
41
{
42
42
struct device_node *np;
43
43
···
83
83
84
84
machine_arch_initcall(p1023_rdb, mpc85xx_common_publish_devices);
85
85
86
-
static void __init mpc85xx_rdb_pic_init(void)
86
+
static void __init p1023_rdb_pic_init(void)
87
87
{
88
88
struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
89
89
MPIC_SINGLE_DEST_CPU,
···
94
94
mpic_init(mpic);
95
95
}
96
96
97
-
static int __init p1023_rdb_probe(void)
98
-
{
99
-
return of_machine_is_compatible("fsl,P1023RDB");
100
-
101
-
}
102
-
103
97
define_machine(p1023_rdb) {
104
98
.name = "P1023 RDB",
105
-
.probe = p1023_rdb_probe,
106
-
.setup_arch = mpc85xx_rdb_setup_arch,
107
-
.init_IRQ = mpc85xx_rdb_pic_init,
99
+
.compatible = "fsl,P1023RDB",
100
+
.setup_arch = p1023_rdb_setup_arch,
101
+
.init_IRQ = p1023_rdb_pic_init,
108
102
.get_irq = mpic_get_irq,
109
-
.calibrate_decr = generic_calibrate_decr,
110
103
.progress = udbg_progress,
111
104
#ifdef CONFIG_PCI
112
105
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+81
arch/powerpc/platforms/85xx/p2020.c
+81
arch/powerpc/platforms/85xx/p2020.c
···
1
+
// SPDX-License-Identifier: GPL-2.0-or-later
2
+
/*
3
+
* Freescale P2020 board Setup
4
+
*
5
+
* Copyright 2007,2009,2012-2013 Freescale Semiconductor Inc.
6
+
* Copyright 2022-2023 Pali Rohár <pali@kernel.org>
7
+
*/
8
+
9
+
#include <linux/stddef.h>
10
+
#include <linux/kernel.h>
11
+
#include <linux/of.h>
12
+
13
+
#include <asm/machdep.h>
14
+
#include <asm/udbg.h>
15
+
#include <asm/mpic.h>
16
+
#include <asm/swiotlb.h>
17
+
#include <asm/ppc-pci.h>
18
+
19
+
#include <sysdev/fsl_pci.h>
20
+
21
+
#include "smp.h"
22
+
#include "mpc85xx.h"
23
+
24
+
static void __init p2020_pic_init(void)
25
+
{
26
+
struct mpic *mpic;
27
+
int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU;
28
+
29
+
mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
30
+
31
+
if (WARN_ON(!mpic))
32
+
return;
33
+
34
+
mpic_init(mpic);
35
+
mpc85xx_8259_init();
36
+
}
37
+
38
+
/*
39
+
* Setup the architecture
40
+
*/
41
+
static void __init p2020_setup_arch(void)
42
+
{
43
+
swiotlb_detect_4g();
44
+
fsl_pci_assign_primary();
45
+
uli_init();
46
+
mpc85xx_smp_init();
47
+
mpc85xx_qe_par_io_init();
48
+
}
49
+
50
+
/*
51
+
* Called very early, device-tree isn't unflattened
52
+
*/
53
+
static int __init p2020_probe(void)
54
+
{
55
+
struct device_node *p2020_cpu;
56
+
57
+
/*
58
+
* There is no common compatible string for all P2020 boards.
59
+
* The only common thing is "PowerPC,P2020@0" cpu node.
60
+
* So check for P2020 board via this cpu node.
61
+
*/
62
+
p2020_cpu = of_find_node_by_path("/cpus/PowerPC,P2020@0");
63
+
of_node_put(p2020_cpu);
64
+
65
+
return !!p2020_cpu;
66
+
}
67
+
68
+
machine_arch_initcall(p2020, mpc85xx_common_publish_devices);
69
+
70
+
define_machine(p2020) {
71
+
.name = "Freescale P2020",
72
+
.probe = p2020_probe,
73
+
.setup_arch = p2020_setup_arch,
74
+
.init_IRQ = p2020_pic_init,
75
+
#ifdef CONFIG_PCI
76
+
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77
+
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
78
+
#endif
79
+
.get_irq = mpic_get_irq,
80
+
.progress = udbg_progress,
81
+
};
+1
-10
arch/powerpc/platforms/85xx/ppa8548.c
+1
-10
arch/powerpc/platforms/85xx/ppa8548.c
···
72
72
}
73
73
machine_device_initcall(ppa8548, declare_of_platform_devices);
74
74
75
-
/*
76
-
* Called very early, device-tree isn't unflattened
77
-
*/
78
-
static int __init ppa8548_probe(void)
79
-
{
80
-
return of_machine_is_compatible("ppa8548");
81
-
}
82
-
83
75
define_machine(ppa8548) {
84
76
.name = "ppa8548",
85
-
.probe = ppa8548_probe,
77
+
.compatible = "ppa8548",
86
78
.setup_arch = ppa8548_setup_arch,
87
79
.init_IRQ = ppa8548_pic_init,
88
80
.show_cpuinfo = ppa8548_show_cpuinfo,
89
81
.get_irq = mpic_get_irq,
90
-
.calibrate_decr = generic_calibrate_decr,
91
82
.progress = udbg_progress,
92
83
};
+1
-10
arch/powerpc/platforms/85xx/qemu_e500.c
+1
-10
arch/powerpc/platforms/85xx/qemu_e500.c
···
46
46
mpc85xx_smp_init();
47
47
}
48
48
49
-
/*
50
-
* Called very early, device-tree isn't unflattened
51
-
*/
52
-
static int __init qemu_e500_probe(void)
53
-
{
54
-
return !!of_machine_is_compatible("fsl,qemu-e500");
55
-
}
56
-
57
49
machine_arch_initcall(qemu_e500, mpc85xx_common_publish_devices);
58
50
59
51
define_machine(qemu_e500) {
60
52
.name = "QEMU e500",
61
-
.probe = qemu_e500_probe,
53
+
.compatible = "fsl,qemu-e500",
62
54
.setup_arch = qemu_e500_setup_arch,
63
55
.init_IRQ = qemu_e500_pic_init,
64
56
#ifdef CONFIG_PCI
···
58
66
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
59
67
#endif
60
68
.get_irq = mpic_get_coreint_irq,
61
-
.calibrate_decr = generic_calibrate_decr,
62
69
.progress = udbg_progress,
63
70
.power_save = e500_idle,
64
71
};
+1
-13
arch/powerpc/platforms/85xx/socrates.c
+1
-13
arch/powerpc/platforms/85xx/socrates.c
···
69
69
70
70
machine_arch_initcall(socrates, mpc85xx_common_publish_devices);
71
71
72
-
/*
73
-
* Called very early, device-tree isn't unflattened
74
-
*/
75
-
static int __init socrates_probe(void)
76
-
{
77
-
if (of_machine_is_compatible("abb,socrates"))
78
-
return 1;
79
-
80
-
return 0;
81
-
}
82
-
83
72
define_machine(socrates) {
84
73
.name = "Socrates",
85
-
.probe = socrates_probe,
74
+
.compatible = "abb,socrates",
86
75
.setup_arch = socrates_setup_arch,
87
76
.init_IRQ = socrates_pic_init,
88
77
.get_irq = mpic_get_irq,
89
-
.calibrate_decr = generic_calibrate_decr,
90
78
.progress = udbg_progress,
91
79
};
+1
-10
arch/powerpc/platforms/85xx/stx_gp3.c
+1
-10
arch/powerpc/platforms/85xx/stx_gp3.c
···
83
83
84
84
machine_arch_initcall(stx_gp3, mpc85xx_common_publish_devices);
85
85
86
-
/*
87
-
* Called very early, device-tree isn't unflattened
88
-
*/
89
-
static int __init stx_gp3_probe(void)
90
-
{
91
-
return of_machine_is_compatible("stx,gp3-8560");
92
-
}
93
-
94
86
define_machine(stx_gp3) {
95
87
.name = "STX GP3",
96
-
.probe = stx_gp3_probe,
88
+
.compatible = "stx,gp3-8560",
97
89
.setup_arch = stx_gp3_setup_arch,
98
90
.init_IRQ = stx_gp3_pic_init,
99
91
.show_cpuinfo = stx_gp3_show_cpuinfo,
100
92
.get_irq = mpic_get_irq,
101
-
.calibrate_decr = generic_calibrate_decr,
102
93
.progress = udbg_progress,
103
94
};
-1
arch/powerpc/platforms/85xx/tqm85xx.c
-1
arch/powerpc/platforms/85xx/tqm85xx.c
+1
-7
arch/powerpc/platforms/85xx/twr_p102x.c
+1
-7
arch/powerpc/platforms/85xx/twr_p102x.c
···
103
103
104
104
machine_arch_initcall(twr_p1025, mpc85xx_common_publish_devices);
105
105
106
-
static int __init twr_p1025_probe(void)
107
-
{
108
-
return of_machine_is_compatible("fsl,TWR-P1025");
109
-
}
110
-
111
106
define_machine(twr_p1025) {
112
107
.name = "TWR-P1025",
113
-
.probe = twr_p1025_probe,
108
+
.compatible = "fsl,TWR-P1025",
114
109
.setup_arch = twr_p1025_setup_arch,
115
110
.init_IRQ = twr_p1025_pic_init,
116
111
#ifdef CONFIG_PCI
117
112
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
118
113
#endif
119
114
.get_irq = mpic_get_irq,
120
-
.calibrate_decr = generic_calibrate_decr,
121
115
.progress = udbg_progress,
122
116
};
+3
-24
arch/powerpc/platforms/85xx/xes_mpc85xx.c
+3
-24
arch/powerpc/platforms/85xx/xes_mpc85xx.c
···
136
136
machine_arch_initcall(xes_mpc8548, mpc85xx_common_publish_devices);
137
137
machine_arch_initcall(xes_mpc8540, mpc85xx_common_publish_devices);
138
138
139
-
/*
140
-
* Called very early, device-tree isn't unflattened
141
-
*/
142
-
static int __init xes_mpc8572_probe(void)
143
-
{
144
-
return of_machine_is_compatible("xes,MPC8572");
145
-
}
146
-
147
-
static int __init xes_mpc8548_probe(void)
148
-
{
149
-
return of_machine_is_compatible("xes,MPC8548");
150
-
}
151
-
152
-
static int __init xes_mpc8540_probe(void)
153
-
{
154
-
return of_machine_is_compatible("xes,MPC8540");
155
-
}
156
-
157
139
define_machine(xes_mpc8572) {
158
140
.name = "X-ES MPC8572",
159
-
.probe = xes_mpc8572_probe,
141
+
.compatible = "xes,MPC8572",
160
142
.setup_arch = xes_mpc85xx_setup_arch,
161
143
.init_IRQ = xes_mpc85xx_pic_init,
162
144
#ifdef CONFIG_PCI
···
146
164
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
147
165
#endif
148
166
.get_irq = mpic_get_irq,
149
-
.calibrate_decr = generic_calibrate_decr,
150
167
.progress = udbg_progress,
151
168
};
152
169
153
170
define_machine(xes_mpc8548) {
154
171
.name = "X-ES MPC8548",
155
-
.probe = xes_mpc8548_probe,
172
+
.compatible = "xes,MPC8548",
156
173
.setup_arch = xes_mpc85xx_setup_arch,
157
174
.init_IRQ = xes_mpc85xx_pic_init,
158
175
#ifdef CONFIG_PCI
···
159
178
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
160
179
#endif
161
180
.get_irq = mpic_get_irq,
162
-
.calibrate_decr = generic_calibrate_decr,
163
181
.progress = udbg_progress,
164
182
};
165
183
166
184
define_machine(xes_mpc8540) {
167
185
.name = "X-ES MPC8540",
168
-
.probe = xes_mpc8540_probe,
186
+
.compatible = "xes,MPC8540",
169
187
.setup_arch = xes_mpc85xx_setup_arch,
170
188
.init_IRQ = xes_mpc85xx_pic_init,
171
189
#ifdef CONFIG_PCI
···
172
192
.pcibios_fixup_phb = fsl_pcibios_fixup_phb,
173
193
#endif
174
194
.get_irq = mpic_get_irq,
175
-
.calibrate_decr = generic_calibrate_decr,
176
195
.progress = udbg_progress,
177
196
};
+1
-19
arch/powerpc/platforms/86xx/Kconfig
+1
-19
arch/powerpc/platforms/86xx/Kconfig
···
10
10
11
11
if PPC_86xx
12
12
13
-
config MPC8641_HPCN
14
-
bool "Freescale MPC8641 HPCN"
15
-
select PPC_I8259
16
-
select DEFAULT_UIMAGE
17
-
select FSL_ULI1575 if PCI
18
-
select HAVE_RAPIDIO
19
-
select SWIOTLB
20
-
help
21
-
This option enables support for the MPC8641 HPCN board.
22
-
23
-
config MPC8610_HPCD
24
-
bool "Freescale MPC8610 HPCD"
25
-
select DEFAULT_UIMAGE
26
-
select FSL_ULI1575 if PCI
27
-
help
28
-
This option enables support for the MPC8610 HPCD board.
29
-
30
13
config GEF_PPC9A
31
14
bool "GE PPC9A"
32
15
select DEFAULT_UIMAGE
···
51
68
select FSL_PCI if PCI
52
69
select PPC_UDBG_16550
53
70
select MPIC
54
-
default y if MPC8641_HPCN || GEF_SBC610 || GEF_SBC310 || GEF_PPC9A \
71
+
default y if GEF_SBC610 || GEF_SBC310 || GEF_PPC9A \
55
72
|| MVME7100
56
73
57
74
config MPC8610
···
60
77
select FSL_PCI if PCI
61
78
select PPC_UDBG_16550
62
79
select MPIC
63
-
default y if MPC8610_HPCD
-2
arch/powerpc/platforms/86xx/Makefile
-2
arch/powerpc/platforms/86xx/Makefile
···
5
5
6
6
obj-y := pic.o common.o
7
7
obj-$(CONFIG_SMP) += mpc86xx_smp.o
8
-
obj-$(CONFIG_MPC8641_HPCN) += mpc86xx_hpcn.o
9
-
obj-$(CONFIG_MPC8610_HPCD) += mpc8610_hpcd.o
10
8
obj-$(CONFIG_GEF_SBC610) += gef_sbc610.o
11
9
obj-$(CONFIG_GEF_SBC310) += gef_sbc310.o
12
10
obj-$(CONFIG_GEF_PPC9A) += gef_ppc9a.o
+1
-18
arch/powerpc/platforms/86xx/gef_ppc9a.c
+1
-18
arch/powerpc/platforms/86xx/gef_ppc9a.c
···
175
175
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
176
176
gef_ppc9a_nec_fixup);
177
177
178
-
/*
179
-
* Called very early, device-tree isn't unflattened
180
-
*
181
-
* This function is called to determine whether the BSP is compatible with the
182
-
* supplied device-tree, which is assumed to be the correct one for the actual
183
-
* board. It is expected that, in the future, a kernel may support multiple
184
-
* boards.
185
-
*/
186
-
static int __init gef_ppc9a_probe(void)
187
-
{
188
-
if (of_machine_is_compatible("gef,ppc9a"))
189
-
return 1;
190
-
191
-
return 0;
192
-
}
193
-
194
178
machine_arch_initcall(gef_ppc9a, mpc86xx_common_publish_devices);
195
179
196
180
define_machine(gef_ppc9a) {
197
181
.name = "GE PPC9A",
198
-
.probe = gef_ppc9a_probe,
182
+
.compatible = "gef,ppc9a",
199
183
.setup_arch = gef_ppc9a_setup_arch,
200
184
.init_IRQ = gef_ppc9a_init_irq,
201
185
.show_cpuinfo = gef_ppc9a_show_cpuinfo,
202
186
.get_irq = mpic_get_irq,
203
187
.time_init = mpc86xx_time_init,
204
-
.calibrate_decr = generic_calibrate_decr,
205
188
.progress = udbg_progress,
206
189
#ifdef CONFIG_PCI
207
190
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+1
-18
arch/powerpc/platforms/86xx/gef_sbc310.c
+1
-18
arch/powerpc/platforms/86xx/gef_sbc310.c
···
162
162
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
163
163
gef_sbc310_nec_fixup);
164
164
165
-
/*
166
-
* Called very early, device-tree isn't unflattened
167
-
*
168
-
* This function is called to determine whether the BSP is compatible with the
169
-
* supplied device-tree, which is assumed to be the correct one for the actual
170
-
* board. It is expected that, in the future, a kernel may support multiple
171
-
* boards.
172
-
*/
173
-
static int __init gef_sbc310_probe(void)
174
-
{
175
-
if (of_machine_is_compatible("gef,sbc310"))
176
-
return 1;
177
-
178
-
return 0;
179
-
}
180
-
181
165
machine_arch_initcall(gef_sbc310, mpc86xx_common_publish_devices);
182
166
183
167
define_machine(gef_sbc310) {
184
168
.name = "GE SBC310",
185
-
.probe = gef_sbc310_probe,
169
+
.compatible = "gef,sbc310",
186
170
.setup_arch = gef_sbc310_setup_arch,
187
171
.init_IRQ = gef_sbc310_init_irq,
188
172
.show_cpuinfo = gef_sbc310_show_cpuinfo,
189
173
.get_irq = mpic_get_irq,
190
174
.time_init = mpc86xx_time_init,
191
-
.calibrate_decr = generic_calibrate_decr,
192
175
.progress = udbg_progress,
193
176
#ifdef CONFIG_PCI
194
177
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
+1
-18
arch/powerpc/platforms/86xx/gef_sbc610.c
+1
-18
arch/powerpc/platforms/86xx/gef_sbc610.c
···
152
152
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB,
153
153
gef_sbc610_nec_fixup);
154
154
155
-
/*
156
-
* Called very early, device-tree isn't unflattened
157
-
*
158
-
* This function is called to determine whether the BSP is compatible with the
159
-
* supplied device-tree, which is assumed to be the correct one for the actual
160
-
* board. It is expected that, in the future, a kernel may support multiple
161
-
* boards.
162
-
*/
163
-
static int __init gef_sbc610_probe(void)
164
-
{
165
-
if (of_machine_is_compatible("gef,sbc610"))
166
-
return 1;
167
-
168
-
return 0;
169
-
}
170
-
171
155
machine_arch_initcall(gef_sbc610, mpc86xx_common_publish_devices);
172
156
173
157
define_machine(gef_sbc610) {
174
158
.name = "GE SBC610",
175
-
.probe = gef_sbc610_probe,
159
+
.compatible = "gef,sbc610",
176
160
.setup_arch = gef_sbc610_setup_arch,
177
161
.init_IRQ = gef_sbc610_init_irq,
178
162
.show_cpuinfo = gef_sbc610_show_cpuinfo,
179
163
.get_irq = mpic_get_irq,
180
164
.time_init = mpc86xx_time_init,
181
-
.calibrate_decr = generic_calibrate_decr,
182
165
.progress = udbg_progress,
183
166
#ifdef CONFIG_PCI
184
167
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
-333
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
-333
arch/powerpc/platforms/86xx/mpc8610_hpcd.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC8610 HPCD board specific routines
4
-
*
5
-
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
6
-
* Recode: Jason Jin <jason.jin@freescale.com>
7
-
* York Sun <yorksun@freescale.com>
8
-
*
9
-
* Rewrite the interrupt routing. remove the 8259PIC support,
10
-
* All the integrated device in ULI use sideband interrupt.
11
-
*
12
-
* Copyright 2008 Freescale Semiconductor Inc.
13
-
*/
14
-
15
-
#include <linux/stddef.h>
16
-
#include <linux/kernel.h>
17
-
#include <linux/pci.h>
18
-
#include <linux/interrupt.h>
19
-
#include <linux/kdev_t.h>
20
-
#include <linux/delay.h>
21
-
#include <linux/seq_file.h>
22
-
#include <linux/of.h>
23
-
#include <linux/of_address.h>
24
-
#include <linux/of_irq.h>
25
-
#include <linux/fsl/guts.h>
26
-
27
-
#include <asm/time.h>
28
-
#include <asm/machdep.h>
29
-
#include <asm/pci-bridge.h>
30
-
#include <mm/mmu_decl.h>
31
-
#include <asm/udbg.h>
32
-
33
-
#include <asm/mpic.h>
34
-
35
-
#include <linux/of_platform.h>
36
-
#include <sysdev/fsl_pci.h>
37
-
#include <sysdev/fsl_soc.h>
38
-
39
-
#include "mpc86xx.h"
40
-
41
-
static struct device_node *pixis_node;
42
-
static unsigned char *pixis_bdcfg0, *pixis_arch;
43
-
44
-
/* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
45
-
#define CLKDVDR_PXCKEN 0x80000000
46
-
#define CLKDVDR_PXCKINV 0x10000000
47
-
#define CLKDVDR_PXCKDLY 0x06000000
48
-
#define CLKDVDR_PXCLK_MASK 0x001F0000
49
-
50
-
#ifdef CONFIG_SUSPEND
51
-
static irqreturn_t mpc8610_sw9_irq(int irq, void *data)
52
-
{
53
-
pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__);
54
-
return IRQ_HANDLED;
55
-
}
56
-
57
-
static void __init mpc8610_suspend_init(void)
58
-
{
59
-
int irq;
60
-
int ret;
61
-
62
-
if (!pixis_node)
63
-
return;
64
-
65
-
irq = irq_of_parse_and_map(pixis_node, 0);
66
-
if (!irq) {
67
-
pr_err("%s: can't map pixis event IRQ.\n", __func__);
68
-
return;
69
-
}
70
-
71
-
ret = request_irq(irq, mpc8610_sw9_irq, 0, "sw9:wakeup", NULL);
72
-
if (ret) {
73
-
pr_err("%s: can't request pixis event IRQ: %d\n",
74
-
__func__, ret);
75
-
irq_dispose_mapping(irq);
76
-
}
77
-
78
-
enable_irq_wake(irq);
79
-
}
80
-
#else
81
-
static inline void mpc8610_suspend_init(void) { }
82
-
#endif /* CONFIG_SUSPEND */
83
-
84
-
static const struct of_device_id mpc8610_ids[] __initconst = {
85
-
{ .compatible = "fsl,mpc8610-immr", },
86
-
{ .compatible = "fsl,mpc8610-guts", },
87
-
/* So that the DMA channel nodes can be probed individually: */
88
-
{ .compatible = "fsl,eloplus-dma", },
89
-
/* PCI controllers */
90
-
{ .compatible = "fsl,mpc8610-pci", },
91
-
{}
92
-
};
93
-
94
-
static int __init mpc8610_declare_of_platform_devices(void)
95
-
{
96
-
/* Enable wakeup on PIXIS' event IRQ. */
97
-
mpc8610_suspend_init();
98
-
99
-
mpc86xx_common_publish_devices();
100
-
101
-
/* Without this call, the SSI device driver won't get probed. */
102
-
of_platform_bus_probe(NULL, mpc8610_ids, NULL);
103
-
104
-
return 0;
105
-
}
106
-
machine_arch_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
107
-
108
-
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
109
-
110
-
/*
111
-
* DIU Area Descriptor
112
-
*
113
-
* The MPC8610 reference manual shows the bits of the AD register in
114
-
* little-endian order, which causes the BLUE_C field to be split into two
115
-
* parts. To simplify the definition of the MAKE_AD() macro, we define the
116
-
* fields in big-endian order and byte-swap the result.
117
-
*
118
-
* So even though the registers don't look like they're in the
119
-
* same bit positions as they are on the P1022, the same value is written to
120
-
* the AD register on the MPC8610 and on the P1022.
121
-
*/
122
-
#define AD_BYTE_F 0x10000000
123
-
#define AD_ALPHA_C_MASK 0x0E000000
124
-
#define AD_ALPHA_C_SHIFT 25
125
-
#define AD_BLUE_C_MASK 0x01800000
126
-
#define AD_BLUE_C_SHIFT 23
127
-
#define AD_GREEN_C_MASK 0x00600000
128
-
#define AD_GREEN_C_SHIFT 21
129
-
#define AD_RED_C_MASK 0x00180000
130
-
#define AD_RED_C_SHIFT 19
131
-
#define AD_PALETTE 0x00040000
132
-
#define AD_PIXEL_S_MASK 0x00030000
133
-
#define AD_PIXEL_S_SHIFT 16
134
-
#define AD_COMP_3_MASK 0x0000F000
135
-
#define AD_COMP_3_SHIFT 12
136
-
#define AD_COMP_2_MASK 0x00000F00
137
-
#define AD_COMP_2_SHIFT 8
138
-
#define AD_COMP_1_MASK 0x000000F0
139
-
#define AD_COMP_1_SHIFT 4
140
-
#define AD_COMP_0_MASK 0x0000000F
141
-
#define AD_COMP_0_SHIFT 0
142
-
143
-
#define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
144
-
cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
145
-
(blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
146
-
(red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
147
-
(c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
148
-
(c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
149
-
150
-
u32 mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port,
151
-
unsigned int bits_per_pixel)
152
-
{
153
-
static const u32 pixelformat[][3] = {
154
-
{
155
-
MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
156
-
MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
157
-
MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
158
-
},
159
-
{
160
-
MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
161
-
MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
162
-
MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
163
-
},
164
-
};
165
-
unsigned int arch_monitor;
166
-
167
-
/* The DVI port is mis-wired on revision 1 of this board. */
168
-
arch_monitor =
169
-
((*pixis_arch == 0x01) && (port == FSL_DIU_PORT_DVI)) ? 0 : 1;
170
-
171
-
switch (bits_per_pixel) {
172
-
case 32:
173
-
return pixelformat[arch_monitor][0];
174
-
case 24:
175
-
return pixelformat[arch_monitor][1];
176
-
case 16:
177
-
return pixelformat[arch_monitor][2];
178
-
default:
179
-
pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel);
180
-
return 0;
181
-
}
182
-
}
183
-
184
-
void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port,
185
-
char *gamma_table_base)
186
-
{
187
-
int i;
188
-
if (port == FSL_DIU_PORT_DLVDS) {
189
-
for (i = 0; i < 256*3; i++)
190
-
gamma_table_base[i] = (gamma_table_base[i] << 2) |
191
-
((gamma_table_base[i] >> 6) & 0x03);
192
-
}
193
-
}
194
-
195
-
#define PX_BRDCFG0_DVISEL (1 << 3)
196
-
#define PX_BRDCFG0_DLINK (1 << 4)
197
-
#define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
198
-
199
-
void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port)
200
-
{
201
-
switch (port) {
202
-
case FSL_DIU_PORT_DVI:
203
-
clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
204
-
PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK);
205
-
break;
206
-
case FSL_DIU_PORT_LVDS:
207
-
clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
208
-
PX_BRDCFG0_DLINK);
209
-
break;
210
-
case FSL_DIU_PORT_DLVDS:
211
-
clrbits8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK);
212
-
break;
213
-
}
214
-
}
215
-
216
-
/**
217
-
* mpc8610hpcd_set_pixel_clock: program the DIU's clock
218
-
*
219
-
* @pixclock: the wavelength, in picoseconds, of the clock
220
-
*/
221
-
void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
222
-
{
223
-
struct device_node *guts_np = NULL;
224
-
struct ccsr_guts __iomem *guts;
225
-
unsigned long freq;
226
-
u64 temp;
227
-
u32 pxclk;
228
-
229
-
/* Map the global utilities registers. */
230
-
guts_np = of_find_compatible_node(NULL, NULL, "fsl,mpc8610-guts");
231
-
if (!guts_np) {
232
-
pr_err("mpc8610hpcd: missing global utilities device node\n");
233
-
return;
234
-
}
235
-
236
-
guts = of_iomap(guts_np, 0);
237
-
of_node_put(guts_np);
238
-
if (!guts) {
239
-
pr_err("mpc8610hpcd: could not map global utilities device\n");
240
-
return;
241
-
}
242
-
243
-
/* Convert pixclock from a wavelength to a frequency */
244
-
temp = 1000000000000ULL;
245
-
do_div(temp, pixclock);
246
-
freq = temp;
247
-
248
-
/*
249
-
* 'pxclk' is the ratio of the platform clock to the pixel clock.
250
-
* On the MPC8610, the value programmed into CLKDVDR is the ratio
251
-
* minus one. The valid range of values is 2-31.
252
-
*/
253
-
pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq) - 1;
254
-
pxclk = clamp_t(u32, pxclk, 2, 31);
255
-
256
-
/* Disable the pixel clock, and set it to non-inverted and no delay */
257
-
clrbits32(&guts->clkdvdr,
258
-
CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
259
-
260
-
/* Enable the clock and set the pxclk */
261
-
setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
262
-
263
-
iounmap(guts);
264
-
}
265
-
266
-
enum fsl_diu_monitor_port
267
-
mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port)
268
-
{
269
-
return port;
270
-
}
271
-
272
-
#endif
273
-
274
-
static void __init mpc86xx_hpcd_setup_arch(void)
275
-
{
276
-
struct resource r;
277
-
unsigned char *pixis;
278
-
279
-
if (ppc_md.progress)
280
-
ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
281
-
282
-
fsl_pci_assign_primary();
283
-
284
-
#if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
285
-
diu_ops.get_pixel_format = mpc8610hpcd_get_pixel_format;
286
-
diu_ops.set_gamma_table = mpc8610hpcd_set_gamma_table;
287
-
diu_ops.set_monitor_port = mpc8610hpcd_set_monitor_port;
288
-
diu_ops.set_pixel_clock = mpc8610hpcd_set_pixel_clock;
289
-
diu_ops.valid_monitor_port = mpc8610hpcd_valid_monitor_port;
290
-
#endif
291
-
292
-
pixis_node = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
293
-
if (pixis_node) {
294
-
of_address_to_resource(pixis_node, 0, &r);
295
-
of_node_put(pixis_node);
296
-
pixis = ioremap(r.start, 32);
297
-
if (!pixis) {
298
-
printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
299
-
return;
300
-
}
301
-
pixis_bdcfg0 = pixis + 8;
302
-
pixis_arch = pixis + 1;
303
-
} else
304
-
printk(KERN_ERR "Err: "
305
-
"can't find device node 'fsl,fpga-pixis'\n");
306
-
307
-
printk("MPC86xx HPCD board from Freescale Semiconductor\n");
308
-
}
309
-
310
-
/*
311
-
* Called very early, device-tree isn't unflattened
312
-
*/
313
-
static int __init mpc86xx_hpcd_probe(void)
314
-
{
315
-
if (of_machine_is_compatible("fsl,MPC8610HPCD"))
316
-
return 1; /* Looks good */
317
-
318
-
return 0;
319
-
}
320
-
321
-
define_machine(mpc86xx_hpcd) {
322
-
.name = "MPC86xx HPCD",
323
-
.probe = mpc86xx_hpcd_probe,
324
-
.setup_arch = mpc86xx_hpcd_setup_arch,
325
-
.init_IRQ = mpc86xx_init_irq,
326
-
.get_irq = mpic_get_irq,
327
-
.time_init = mpc86xx_time_init,
328
-
.calibrate_decr = generic_calibrate_decr,
329
-
.progress = udbg_progress,
330
-
#ifdef CONFIG_PCI
331
-
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
332
-
#endif
333
-
};
-127
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
-127
arch/powerpc/platforms/86xx/mpc86xx_hpcn.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* MPC86xx HPCN board specific routines
4
-
*
5
-
* Recode: ZHANG WEI <wei.zhang@freescale.com>
6
-
* Initial author: Xianghua Xiao <x.xiao@freescale.com>
7
-
*
8
-
* Copyright 2006 Freescale Semiconductor Inc.
9
-
*/
10
-
11
-
#include <linux/stddef.h>
12
-
#include <linux/kernel.h>
13
-
#include <linux/pci.h>
14
-
#include <linux/kdev_t.h>
15
-
#include <linux/delay.h>
16
-
#include <linux/seq_file.h>
17
-
#include <linux/of_platform.h>
18
-
19
-
#include <asm/time.h>
20
-
#include <asm/machdep.h>
21
-
#include <asm/pci-bridge.h>
22
-
#include <mm/mmu_decl.h>
23
-
#include <asm/udbg.h>
24
-
#include <asm/swiotlb.h>
25
-
26
-
#include <asm/mpic.h>
27
-
28
-
#include <sysdev/fsl_pci.h>
29
-
#include <sysdev/fsl_soc.h>
30
-
31
-
#include "mpc86xx.h"
32
-
33
-
#undef DEBUG
34
-
35
-
#ifdef DEBUG
36
-
#define DBG(fmt...) do { printk(KERN_ERR fmt); } while(0)
37
-
#else
38
-
#define DBG(fmt...) do { } while(0)
39
-
#endif
40
-
41
-
#ifdef CONFIG_PCI
42
-
extern int uli_exclude_device(struct pci_controller *hose,
43
-
u_char bus, u_char devfn);
44
-
45
-
static int mpc86xx_exclude_device(struct pci_controller *hose,
46
-
u_char bus, u_char devfn)
47
-
{
48
-
if (hose->dn == fsl_pci_primary)
49
-
return uli_exclude_device(hose, bus, devfn);
50
-
51
-
return PCIBIOS_SUCCESSFUL;
52
-
}
53
-
#endif /* CONFIG_PCI */
54
-
55
-
56
-
static void __init
57
-
mpc86xx_hpcn_setup_arch(void)
58
-
{
59
-
if (ppc_md.progress)
60
-
ppc_md.progress("mpc86xx_hpcn_setup_arch()", 0);
61
-
62
-
#ifdef CONFIG_PCI
63
-
ppc_md.pci_exclude_device = mpc86xx_exclude_device;
64
-
#endif
65
-
66
-
printk("MPC86xx HPCN board from Freescale Semiconductor\n");
67
-
68
-
#ifdef CONFIG_SMP
69
-
mpc86xx_smp_init();
70
-
#endif
71
-
72
-
fsl_pci_assign_primary();
73
-
74
-
swiotlb_detect_4g();
75
-
}
76
-
77
-
78
-
static void
79
-
mpc86xx_hpcn_show_cpuinfo(struct seq_file *m)
80
-
{
81
-
uint svid = mfspr(SPRN_SVR);
82
-
83
-
seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
84
-
85
-
seq_printf(m, "SVR\t\t: 0x%x\n", svid);
86
-
}
87
-
88
-
89
-
/*
90
-
* Called very early, device-tree isn't unflattened
91
-
*/
92
-
static int __init mpc86xx_hpcn_probe(void)
93
-
{
94
-
if (of_machine_is_compatible("fsl,mpc8641hpcn"))
95
-
return 1; /* Looks good */
96
-
97
-
return 0;
98
-
}
99
-
100
-
static const struct of_device_id of_bus_ids[] __initconst = {
101
-
{ .compatible = "fsl,srio", },
102
-
{},
103
-
};
104
-
105
-
static int __init declare_of_platform_devices(void)
106
-
{
107
-
mpc86xx_common_publish_devices();
108
-
of_platform_bus_probe(NULL, of_bus_ids, NULL);
109
-
110
-
return 0;
111
-
}
112
-
machine_arch_initcall(mpc86xx_hpcn, declare_of_platform_devices);
113
-
114
-
define_machine(mpc86xx_hpcn) {
115
-
.name = "MPC86xx HPCN",
116
-
.probe = mpc86xx_hpcn_probe,
117
-
.setup_arch = mpc86xx_hpcn_setup_arch,
118
-
.init_IRQ = mpc86xx_init_irq,
119
-
.show_cpuinfo = mpc86xx_hpcn_show_cpuinfo,
120
-
.get_irq = mpic_get_irq,
121
-
.time_init = mpc86xx_time_init,
122
-
.calibrate_decr = generic_calibrate_decr,
123
-
.progress = udbg_progress,
124
-
#ifdef CONFIG_PCI
125
-
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
126
-
#endif
127
-
};
-1
arch/powerpc/platforms/86xx/mvme7100.c
-1
arch/powerpc/platforms/86xx/mvme7100.c
+1
-7
arch/powerpc/platforms/8xx/adder875.c
+1
-7
arch/powerpc/platforms/8xx/adder875.c
···
83
83
init_ioports();
84
84
}
85
85
86
-
static int __init adder875_probe(void)
87
-
{
88
-
return of_machine_is_compatible("analogue-and-micro,adder875");
89
-
}
90
-
91
86
static const struct of_device_id of_bus_ids[] __initconst = {
92
87
{ .compatible = "simple-bus", },
93
88
{},
···
97
102
98
103
define_machine(adder875) {
99
104
.name = "Adder MPC875",
100
-
.probe = adder875_probe,
105
+
.compatible = "analogue-and-micro,adder875",
101
106
.setup_arch = adder875_setup,
102
107
.init_IRQ = mpc8xx_pic_init,
103
108
.get_irq = mpc8xx_get_irq,
104
109
.restart = mpc8xx_restart,
105
-
.calibrate_decr = generic_calibrate_decr,
106
110
.progress = udbg_progress,
107
111
};
+1
-6
arch/powerpc/platforms/8xx/ep88xc.c
+1
-6
arch/powerpc/platforms/8xx/ep88xc.c
···
142
142
BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
143
143
}
144
144
145
-
static int __init ep88xc_probe(void)
146
-
{
147
-
return of_machine_is_compatible("fsl,ep88xc");
148
-
}
149
-
150
145
static const struct of_device_id of_bus_ids[] __initconst = {
151
146
{ .name = "soc", },
152
147
{ .name = "cpm", },
···
160
165
161
166
define_machine(ep88xc) {
162
167
.name = "Embedded Planet EP88xC",
163
-
.probe = ep88xc_probe,
168
+
.compatible = "fsl,ep88xc",
164
169
.setup_arch = ep88xc_setup_arch,
165
170
.init_IRQ = mpc8xx_pic_init,
166
171
.get_irq = mpc8xx_get_irq,
+1
-6
arch/powerpc/platforms/8xx/mpc86xads_setup.c
+1
-6
arch/powerpc/platforms/8xx/mpc86xads_setup.c
···
117
117
iounmap(bcsr_io);
118
118
}
119
119
120
-
static int __init mpc86xads_probe(void)
121
-
{
122
-
return of_machine_is_compatible("fsl,mpc866ads");
123
-
}
124
-
125
120
static const struct of_device_id of_bus_ids[] __initconst = {
126
121
{ .name = "soc", },
127
122
{ .name = "cpm", },
···
134
139
135
140
define_machine(mpc86x_ads) {
136
141
.name = "MPC86x ADS",
137
-
.probe = mpc86xads_probe,
142
+
.compatible = "fsl,mpc866ads",
138
143
.setup_arch = mpc86xads_setup_arch,
139
144
.init_IRQ = mpc8xx_pic_init,
140
145
.get_irq = mpc8xx_get_irq,
+1
-6
arch/powerpc/platforms/8xx/mpc885ads_setup.c
+1
-6
arch/powerpc/platforms/8xx/mpc885ads_setup.c
···
192
192
}
193
193
}
194
194
195
-
static int __init mpc885ads_probe(void)
196
-
{
197
-
return of_machine_is_compatible("fsl,mpc885ads");
198
-
}
199
-
200
195
static const struct of_device_id of_bus_ids[] __initconst = {
201
196
{ .name = "soc", },
202
197
{ .name = "cpm", },
···
210
215
211
216
define_machine(mpc885_ads) {
212
217
.name = "Freescale MPC885 ADS",
213
-
.probe = mpc885ads_probe,
218
+
.compatible = "fsl,mpc885ads",
214
219
.setup_arch = mpc885ads_setup_arch,
215
220
.init_IRQ = mpc8xx_pic_init,
216
221
.get_irq = mpc8xx_get_irq,
+1
-6
arch/powerpc/platforms/8xx/tqm8xx_setup.c
+1
-6
arch/powerpc/platforms/8xx/tqm8xx_setup.c
···
121
121
init_ioports();
122
122
}
123
123
124
-
static int __init tqm8xx_probe(void)
125
-
{
126
-
return of_machine_is_compatible("tqc,tqm8xx");
127
-
}
128
-
129
124
static const struct of_device_id of_bus_ids[] __initconst = {
130
125
{ .name = "soc", },
131
126
{ .name = "cpm", },
···
139
144
140
145
define_machine(tqm8xx) {
141
146
.name = "TQM8xx",
142
-
.probe = tqm8xx_probe,
147
+
.compatible = "tqc,tqm8xx",
143
148
.setup_arch = tqm8xx_setup_arch,
144
149
.init_IRQ = mpc8xx_pic_init,
145
150
.get_irq = mpc8xx_get_irq,
+3
-1
arch/powerpc/platforms/Kconfig
+3
-1
arch/powerpc/platforms/Kconfig
···
263
263
on it (826x, 827x, 8560).
264
264
265
265
config FSL_ULI1575
266
-
bool
266
+
bool "ULI1575 PCIe south bridge support"
267
+
depends on FSL_SOC_BOOKE || PPC_86xx
268
+
select FSL_PCI
267
269
select GENERIC_ISA_DMA
268
270
help
269
271
Supports for the ULI1575 PCIe south bridge that exists on some
+38
arch/powerpc/platforms/Kconfig.cputype
+38
arch/powerpc/platforms/Kconfig.cputype
···
180
180
bool "POWER10"
181
181
depends on PPC_BOOK3S_64
182
182
select ARCH_HAS_FAST_MULTIPLIER
183
+
select PPC_HAVE_PREFIXED_SUPPORT
184
+
select PPC_HAVE_PCREL_SUPPORT
183
185
184
186
config E5500_CPU
185
187
bool "Freescale e5500"
···
456
454
457
455
If you're unsure, say Y.
458
456
457
+
config PPC_KERNEL_PREFIXED
458
+
depends on PPC_HAVE_PREFIXED_SUPPORT
459
+
depends on CC_HAS_PREFIXED
460
+
default n
461
+
bool "Build Kernel with Prefixed Instructions"
462
+
help
463
+
POWER10 and later CPUs support prefixed instructions, 8 byte
464
+
instructions that include large immediate, pc relative addressing,
465
+
and various floating point, vector, MMA.
466
+
467
+
This option builds the kernel with prefixed instructions, and
468
+
allows a pc relative addressing option to be selected.
469
+
470
+
Kernel support for prefixed instructions in applications and guests
471
+
is not affected by this option.
472
+
473
+
config PPC_KERNEL_PCREL
474
+
depends on PPC_HAVE_PCREL_SUPPORT
475
+
depends on PPC_HAVE_PREFIXED_SUPPORT
476
+
depends on CC_HAS_PCREL
477
+
default n
478
+
select PPC_KERNEL_PREFIXED
479
+
bool "Build Kernel with PC-Relative addressing model"
480
+
help
481
+
POWER10 and later CPUs support pc relative addressing. Recent
482
+
compilers have support for an ELF ABI extension for a pc relative
483
+
ABI.
484
+
485
+
This option builds the kernel with the pc relative ABI model.
486
+
459
487
config PPC_KUEP
460
488
bool "Kernel Userspace Execution Prevention" if !40x
461
489
default y if !40x
···
520
488
depends on !PPC_BOOK3S
521
489
522
490
config PPC_HAVE_PMU_SUPPORT
491
+
bool
492
+
493
+
config PPC_HAVE_PREFIXED_SUPPORT
494
+
bool
495
+
496
+
config PPC_HAVE_PCREL_SUPPORT
523
497
bool
524
498
525
499
config PMU_SYSFS
+9
-13
arch/powerpc/platforms/amigaone/setup.c
+9
-13
arch/powerpc/platforms/amigaone/setup.c
···
143
143
144
144
static int __init amigaone_probe(void)
145
145
{
146
-
if (of_machine_is_compatible("eyetech,amigaone")) {
147
-
/*
148
-
* Coherent memory access cause complete system lockup! Thus
149
-
* disable this CPU feature, even if the CPU needs it.
150
-
*/
151
-
cur_cpu_spec->cpu_features &= ~CPU_FTR_NEED_COHERENT;
146
+
/*
147
+
* Coherent memory access cause complete system lockup! Thus
148
+
* disable this CPU feature, even if the CPU needs it.
149
+
*/
150
+
cur_cpu_spec->cpu_features &= ~CPU_FTR_NEED_COHERENT;
152
151
153
-
DMA_MODE_READ = 0x44;
154
-
DMA_MODE_WRITE = 0x48;
152
+
DMA_MODE_READ = 0x44;
153
+
DMA_MODE_WRITE = 0x48;
155
154
156
-
return 1;
157
-
}
158
-
159
-
return 0;
155
+
return 1;
160
156
}
161
157
162
158
define_machine(amigaone) {
163
159
.name = "AmigaOne",
160
+
.compatible = "eyetech,amigaone",
164
161
.probe = amigaone_probe,
165
162
.setup_arch = amigaone_setup_arch,
166
163
.discover_phbs = amigaone_discover_phbs,
167
164
.show_cpuinfo = amigaone_show_cpuinfo,
168
165
.init_IRQ = amigaone_init_IRQ,
169
166
.restart = amigaone_restart,
170
-
.calibrate_decr = generic_calibrate_decr,
171
167
.progress = udbg_progress,
172
168
};
+4
-5
arch/powerpc/platforms/cell/axon_msi.c
+4
-5
arch/powerpc/platforms/cell/axon_msi.c
···
460
460
void axon_msi_debug_setup(struct device_node *dn, struct axon_msic *msic)
461
461
{
462
462
char name[8];
463
-
u64 addr;
463
+
struct resource res;
464
464
465
-
addr = of_translate_address(dn, of_get_property(dn, "reg", NULL));
466
-
if (addr == OF_BAD_ADDR) {
467
-
pr_devel("axon_msi: couldn't translate reg property\n");
465
+
if (of_address_to_resource(dn, 0, &res)) {
466
+
pr_devel("axon_msi: couldn't get reg property\n");
468
467
return;
469
468
}
470
469
471
-
msic->trigger = ioremap(addr, 0x4);
470
+
msic->trigger = ioremap(res.start, 0x4);
472
471
if (!msic->trigger) {
473
472
pr_devel("axon_msi: ioremap failed\n");
474
473
return;
-1
arch/powerpc/platforms/cell/setup.c
-1
arch/powerpc/platforms/cell/setup.c
+1
-1
arch/powerpc/platforms/cell/spu_manage.c
+1
-1
arch/powerpc/platforms/cell/spu_manage.c
-1
arch/powerpc/platforms/chrp/setup.c
-1
arch/powerpc/platforms/chrp/setup.c
-10
arch/powerpc/platforms/embedded6xx/Kconfig
-10
arch/powerpc/platforms/embedded6xx/Kconfig
···
29
29
Select STORCENTER if configuring for the iomega StorCenter
30
30
with an 8241 CPU in it.
31
31
32
-
config MPC7448HPC2
33
-
bool "Freescale MPC7448HPC2(Taiga)"
34
-
depends on EMBEDDED6xx
35
-
select TSI108_BRIDGE
36
-
select DEFAULT_UIMAGE
37
-
select PPC_UDBG_16550
38
-
help
39
-
Select MPC7448HPC2 if configuring for Freescale MPC7448HPC2 (Taiga)
40
-
platform
41
-
42
32
config PPC_HOLLY
43
33
bool "PPC750GX/CL with TSI10x bridge (Hickory/Holly)"
44
34
depends on EMBEDDED6xx
-1
arch/powerpc/platforms/embedded6xx/Makefile
-1
arch/powerpc/platforms/embedded6xx/Makefile
+1
-1
arch/powerpc/platforms/embedded6xx/flipper-pic.c
+1
-1
arch/powerpc/platforms/embedded6xx/flipper-pic.c
+2
-8
arch/powerpc/platforms/embedded6xx/gamecube.c
+2
-8
arch/powerpc/platforms/embedded6xx/gamecube.c
···
50
50
51
51
static int __init gamecube_probe(void)
52
52
{
53
-
if (!of_machine_is_compatible("nintendo,gamecube"))
54
-
return 0;
55
-
56
53
pm_power_off = gamecube_power_off;
57
54
58
55
ug_udbg_init();
···
64
67
65
68
define_machine(gamecube) {
66
69
.name = "gamecube",
70
+
.compatible = "nintendo,gamecube",
67
71
.probe = gamecube_probe,
68
72
.restart = gamecube_restart,
69
73
.halt = gamecube_halt,
70
74
.init_IRQ = flipper_pic_probe,
71
75
.get_irq = flipper_pic_get_irq,
72
-
.calibrate_decr = generic_calibrate_decr,
73
76
.progress = udbg_progress,
74
77
.machine_shutdown = gamecube_shutdown,
75
78
};
···
82
85
83
86
static int __init gamecube_device_probe(void)
84
87
{
85
-
if (!machine_is(gamecube))
86
-
return 0;
87
-
88
88
of_platform_bus_probe(NULL, gamecube_of_bus, NULL);
89
89
return 0;
90
90
}
91
-
device_initcall(gamecube_device_probe);
91
+
machine_device_initcall(gamecube, gamecube_device_probe);
92
92
+1
-1
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+1
-1
arch/powerpc/platforms/embedded6xx/hlwd-pic.c
+4
-16
arch/powerpc/platforms/embedded6xx/holly.c
+4
-16
arch/powerpc/platforms/embedded6xx/holly.c
···
205
205
__be32 __iomem *ocn_bar1 = NULL;
206
206
unsigned long bar;
207
207
struct device_node *bridge = NULL;
208
-
const void *prop;
209
-
int size;
208
+
struct resource res;
210
209
phys_addr_t addr = 0xc0000000;
211
210
212
211
local_irq_disable();
213
212
214
213
bridge = of_find_node_by_type(NULL, "tsi-bridge");
215
214
if (bridge) {
216
-
prop = of_get_property(bridge, "reg", &size);
217
-
addr = of_translate_address(bridge, prop);
215
+
of_address_to_resource(bridge, 0, &res);
216
+
addr = res.start;
218
217
of_node_put(bridge);
219
218
}
220
219
addr += (TSI108_PB_OFFSET + 0x414);
···
240
241
for (;;) ;
241
242
}
242
243
243
-
/*
244
-
* Called very early, device-tree isn't unflattened
245
-
*/
246
-
static int __init holly_probe(void)
247
-
{
248
-
if (!of_machine_is_compatible("ibm,holly"))
249
-
return 0;
250
-
return 1;
251
-
}
252
-
253
244
static int ppc750_machine_check_exception(struct pt_regs *regs)
254
245
{
255
246
const struct exception_table_entry *entry;
···
256
267
257
268
define_machine(holly){
258
269
.name = "PPC750 GX/CL TSI",
259
-
.probe = holly_probe,
270
+
.compatible = "ibm,holly",
260
271
.setup_arch = holly_setup_arch,
261
272
.discover_phbs = holly_init_pci,
262
273
.init_IRQ = holly_init_IRQ,
263
274
.show_cpuinfo = holly_show_cpuinfo,
264
275
.get_irq = mpic_get_irq,
265
276
.restart = holly_restart,
266
-
.calibrate_decr = generic_calibrate_decr,
267
277
.machine_check_exception = ppc750_machine_check_exception,
268
278
.progress = udbg_progress,
269
279
};
+1
-4
arch/powerpc/platforms/embedded6xx/linkstation.c
+1
-4
arch/powerpc/platforms/embedded6xx/linkstation.c
···
143
143
144
144
static int __init linkstation_probe(void)
145
145
{
146
-
if (!of_machine_is_compatible("linkstation"))
147
-
return 0;
148
-
149
146
pm_power_off = linkstation_power_off;
150
147
151
148
return 1;
···
150
153
151
154
define_machine(linkstation){
152
155
.name = "Buffalo Linkstation",
156
+
.compatible = "linkstation",
153
157
.probe = linkstation_probe,
154
158
.setup_arch = linkstation_setup_arch,
155
159
.discover_phbs = linkstation_setup_pci,
···
159
161
.get_irq = mpic_get_irq,
160
162
.restart = linkstation_restart,
161
163
.halt = linkstation_halt,
162
-
.calibrate_decr = generic_calibrate_decr,
163
164
};
+10
-7
arch/powerpc/platforms/embedded6xx/ls_uart.c
+10
-7
arch/powerpc/platforms/embedded6xx/ls_uart.c
···
15
15
#include <linux/serial_reg.h>
16
16
#include <linux/serial_8250.h>
17
17
#include <linux/of.h>
18
+
#include <linux/of_address.h>
18
19
#include <asm/io.h>
19
20
#include <asm/termbits.h>
20
21
···
115
114
static int __init ls_uarts_init(void)
116
115
{
117
116
struct device_node *avr;
118
-
phys_addr_t phys_addr;
119
-
int len;
117
+
struct resource res;
118
+
int len, ret;
120
119
121
120
avr = of_find_node_by_path("/soc10x/serial@80004500");
122
121
if (!avr)
123
122
return -EINVAL;
124
123
125
124
avr_clock = *(u32*)of_get_property(avr, "clock-frequency", &len);
126
-
phys_addr = ((u32*)of_get_property(avr, "reg", &len))[0];
125
+
if (!avr_clock)
126
+
return -EINVAL;
127
+
128
+
ret = of_address_to_resource(avr, 0, &res);
129
+
if (ret)
130
+
return ret;
127
131
128
132
of_node_put(avr);
129
133
130
-
if (!avr_clock || !phys_addr)
131
-
return -EINVAL;
132
-
133
-
avr_addr = ioremap(phys_addr, 32);
134
+
avr_addr = ioremap(res.start, 32);
134
135
if (!avr_addr)
135
136
return -EFAULT;
136
137
-198
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
-198
arch/powerpc/platforms/embedded6xx/mpc7448_hpc2.c
···
1
-
// SPDX-License-Identifier: GPL-2.0-or-later
2
-
/*
3
-
* mpc7448_hpc2.c
4
-
*
5
-
* Board setup routines for the Freescale mpc7448hpc2(taiga) platform
6
-
*
7
-
* Author: Jacob Pan
8
-
* jacob.pan@freescale.com
9
-
* Author: Xianghua Xiao
10
-
* x.xiao@freescale.com
11
-
* Maintainer: Roy Zang <tie-fei.zang@freescale.com>
12
-
* Add Flat Device Tree support fot mpc7448hpc2 board
13
-
*
14
-
* Copyright 2004-2006 Freescale Semiconductor, Inc.
15
-
*/
16
-
17
-
#include <linux/stddef.h>
18
-
#include <linux/kernel.h>
19
-
#include <linux/pci.h>
20
-
#include <linux/kdev_t.h>
21
-
#include <linux/console.h>
22
-
#include <linux/extable.h>
23
-
#include <linux/delay.h>
24
-
#include <linux/irq.h>
25
-
#include <linux/seq_file.h>
26
-
#include <linux/root_dev.h>
27
-
#include <linux/serial.h>
28
-
#include <linux/tty.h>
29
-
#include <linux/serial_core.h>
30
-
#include <linux/of_irq.h>
31
-
32
-
#include <asm/time.h>
33
-
#include <asm/machdep.h>
34
-
#include <asm/udbg.h>
35
-
#include <asm/tsi108.h>
36
-
#include <asm/pci-bridge.h>
37
-
#include <asm/reg.h>
38
-
#include <mm/mmu_decl.h>
39
-
#include <asm/tsi108_pci.h>
40
-
#include <asm/tsi108_irq.h>
41
-
#include <asm/mpic.h>
42
-
43
-
#undef DEBUG
44
-
#ifdef DEBUG
45
-
#define DBG(fmt...) do { printk(fmt); } while(0)
46
-
#else
47
-
#define DBG(fmt...) do { } while(0)
48
-
#endif
49
-
50
-
#define MPC7448HPC2_PCI_CFG_PHYS 0xfb000000
51
-
52
-
int mpc7448_hpc2_exclude_device(struct pci_controller *hose,
53
-
u_char bus, u_char devfn)
54
-
{
55
-
if (bus == 0 && PCI_SLOT(devfn) == 0)
56
-
return PCIBIOS_DEVICE_NOT_FOUND;
57
-
else
58
-
return PCIBIOS_SUCCESSFUL;
59
-
}
60
-
61
-
static void __init mpc7448_hpc2_setup_pci(void)
62
-
{
63
-
#ifdef CONFIG_PCI
64
-
struct device_node *np;
65
-
if (ppc_md.progress)
66
-
ppc_md.progress("mpc7448_hpc2_setup_pci():set_bridge", 0);
67
-
68
-
/* setup PCI host bridge */
69
-
for_each_compatible_node(np, "pci", "tsi108-pci")
70
-
tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0);
71
-
72
-
ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
73
-
if (ppc_md.progress)
74
-
ppc_md.progress("tsi108: resources set", 0x100);
75
-
#endif
76
-
}
77
-
78
-
static void __init mpc7448_hpc2_setup_arch(void)
79
-
{
80
-
tsi108_csr_vir_base = get_vir_csrbase();
81
-
82
-
printk(KERN_INFO "MPC7448HPC2 (TAIGA) Platform\n");
83
-
printk(KERN_INFO
84
-
"Jointly ported by Freescale and Tundra Semiconductor\n");
85
-
printk(KERN_INFO
86
-
"Enabling L2 cache then enabling the HID0 prefetch engine.\n");
87
-
}
88
-
89
-
/*
90
-
* Interrupt setup and service. Interrupts on the mpc7448_hpc2 come
91
-
* from the four external INT pins, PCI interrupts are routed via
92
-
* PCI interrupt control registers, it generates internal IRQ23
93
-
*
94
-
* Interrupt routing on the Taiga Board:
95
-
* TSI108:PB_INT[0] -> CPU0:INT#
96
-
* TSI108:PB_INT[1] -> CPU0:MCP#
97
-
* TSI108:PB_INT[2] -> N/C
98
-
* TSI108:PB_INT[3] -> N/C
99
-
*/
100
-
static void __init mpc7448_hpc2_init_IRQ(void)
101
-
{
102
-
struct mpic *mpic;
103
-
#ifdef CONFIG_PCI
104
-
unsigned int cascade_pci_irq;
105
-
struct device_node *tsi_pci;
106
-
struct device_node *cascade_node = NULL;
107
-
#endif
108
-
109
-
mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
110
-
MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
111
-
24, 0,
112
-
"Tsi108_PIC");
113
-
114
-
BUG_ON(mpic == NULL);
115
-
116
-
mpic_assign_isu(mpic, 0, mpic->paddr + 0x100);
117
-
118
-
mpic_init(mpic);
119
-
120
-
#ifdef CONFIG_PCI
121
-
tsi_pci = of_find_node_by_type(NULL, "pci");
122
-
if (tsi_pci == NULL) {
123
-
printk("%s: No tsi108 pci node found !\n", __func__);
124
-
return;
125
-
}
126
-
cascade_node = of_find_node_by_type(NULL, "pic-router");
127
-
if (cascade_node == NULL) {
128
-
printk("%s: No tsi108 pci cascade node found !\n", __func__);
129
-
return;
130
-
}
131
-
132
-
cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
133
-
DBG("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__,
134
-
(u32) cascade_pci_irq);
135
-
tsi108_pci_int_init(cascade_node);
136
-
irq_set_handler_data(cascade_pci_irq, mpic);
137
-
irq_set_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
138
-
139
-
of_node_put(tsi_pci);
140
-
of_node_put(cascade_node);
141
-
#endif
142
-
/* Configure MPIC outputs to CPU0 */
143
-
tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
144
-
}
145
-
146
-
void mpc7448_hpc2_show_cpuinfo(struct seq_file *m)
147
-
{
148
-
seq_printf(m, "vendor\t\t: Freescale Semiconductor\n");
149
-
}
150
-
151
-
static void __noreturn mpc7448_hpc2_restart(char *cmd)
152
-
{
153
-
local_irq_disable();
154
-
155
-
/* Set exception prefix high - to the firmware */
156
-
mtmsr(mfmsr() | MSR_IP);
157
-
isync();
158
-
159
-
for (;;) ; /* Spin until reset happens */
160
-
}
161
-
162
-
/*
163
-
* Called very early, device-tree isn't unflattened
164
-
*/
165
-
static int __init mpc7448_hpc2_probe(void)
166
-
{
167
-
if (!of_machine_is_compatible("mpc74xx"))
168
-
return 0;
169
-
return 1;
170
-
}
171
-
172
-
static int mpc7448_machine_check_exception(struct pt_regs *regs)
173
-
{
174
-
const struct exception_table_entry *entry;
175
-
176
-
/* Are we prepared to handle this fault */
177
-
if ((entry = search_exception_tables(regs->nip)) != NULL) {
178
-
tsi108_clear_pci_cfg_error();
179
-
regs_set_recoverable(regs);
180
-
regs_set_return_ip(regs, extable_fixup(entry));
181
-
return 1;
182
-
}
183
-
return 0;
184
-
}
185
-
186
-
define_machine(mpc7448_hpc2){
187
-
.name = "MPC7448 HPC2",
188
-
.probe = mpc7448_hpc2_probe,
189
-
.setup_arch = mpc7448_hpc2_setup_arch,
190
-
.discover_phbs = mpc7448_hpc2_setup_pci,
191
-
.init_IRQ = mpc7448_hpc2_init_IRQ,
192
-
.show_cpuinfo = mpc7448_hpc2_show_cpuinfo,
193
-
.get_irq = mpic_get_irq,
194
-
.restart = mpc7448_hpc2_restart,
195
-
.calibrate_decr = generic_calibrate_decr,
196
-
.machine_check_exception= mpc7448_machine_check_exception,
197
-
.progress = udbg_progress,
198
-
};
+1
-10
arch/powerpc/platforms/embedded6xx/mvme5100.c
+1
-10
arch/powerpc/platforms/embedded6xx/mvme5100.c
···
186
186
;
187
187
}
188
188
189
-
/*
190
-
* Called very early, device-tree isn't unflattened
191
-
*/
192
-
static int __init mvme5100_probe(void)
193
-
{
194
-
return of_machine_is_compatible("MVME5100");
195
-
}
196
-
197
189
static int __init probe_of_platform_devices(void)
198
190
{
199
191
···
197
205
198
206
define_machine(mvme5100) {
199
207
.name = "MVME5100",
200
-
.probe = mvme5100_probe,
208
+
.compatible = "MVME5100",
201
209
.setup_arch = mvme5100_setup_arch,
202
210
.discover_phbs = mvme5100_setup_pci,
203
211
.init_IRQ = mvme5100_pic_init,
204
212
.show_cpuinfo = mvme5100_show_cpuinfo,
205
213
.get_irq = mpic_get_irq,
206
214
.restart = mvme5100_restart,
207
-
.calibrate_decr = generic_calibrate_decr,
208
215
.progress = udbg_progress,
209
216
};
+1
-7
arch/powerpc/platforms/embedded6xx/storcenter.c
+1
-7
arch/powerpc/platforms/embedded6xx/storcenter.c
···
110
110
for (;;) ;
111
111
}
112
112
113
-
static int __init storcenter_probe(void)
114
-
{
115
-
return of_machine_is_compatible("iomega,storcenter");
116
-
}
117
-
118
113
define_machine(storcenter){
119
114
.name = "IOMEGA StorCenter",
120
-
.probe = storcenter_probe,
115
+
.compatible = "iomega,storcenter",
121
116
.setup_arch = storcenter_setup_arch,
122
117
.discover_phbs = storcenter_setup_pci,
123
118
.init_IRQ = storcenter_init_IRQ,
124
119
.get_irq = mpic_get_irq,
125
120
.restart = storcenter_restart,
126
-
.calibrate_decr = generic_calibrate_decr,
127
121
};
+1
-19
arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
+1
-19
arch/powerpc/platforms/embedded6xx/usbgecko_udbg.c
···
193
193
}
194
194
195
195
/*
196
-
* Retrieves and prepares the virtual address needed to access the hardware.
197
-
*/
198
-
static void __iomem *__init ug_udbg_setup_exi_io_base(struct device_node *np)
199
-
{
200
-
void __iomem *exi_io_base = NULL;
201
-
phys_addr_t paddr;
202
-
const unsigned int *reg;
203
-
204
-
reg = of_get_property(np, "reg", NULL);
205
-
if (reg) {
206
-
paddr = of_translate_address(np, reg);
207
-
if (paddr)
208
-
exi_io_base = ioremap(paddr, reg[1]);
209
-
}
210
-
return exi_io_base;
211
-
}
212
-
213
-
/*
214
196
* Checks if a USB Gecko adapter is inserted in any memory card slot.
215
197
*/
216
198
static void __iomem *__init ug_udbg_probe(void __iomem *exi_io_base)
···
228
246
goto out;
229
247
}
230
248
231
-
exi_io_base = ug_udbg_setup_exi_io_base(np);
249
+
exi_io_base = of_iomap(np, 0);
232
250
if (!exi_io_base) {
233
251
udbg_printf("%s: failed to setup EXI io base\n", __func__);
234
252
goto done;
+4
-10
arch/powerpc/platforms/embedded6xx/wii.c
+4
-10
arch/powerpc/platforms/embedded6xx/wii.c
···
74
74
75
75
hw_regs = ioremap(res.start, resource_size(&res));
76
76
if (hw_regs) {
77
-
pr_info("%s at 0x%08x mapped to 0x%p\n", name,
78
-
res.start, hw_regs);
77
+
pr_info("%s at 0x%pa mapped to 0x%p\n", name,
78
+
&res.start, hw_regs);
79
79
}
80
80
81
81
out_put:
···
141
141
142
142
static int __init wii_probe(void)
143
143
{
144
-
if (!of_machine_is_compatible("nintendo,wii"))
145
-
return 0;
146
-
147
144
pm_power_off = wii_power_off;
148
145
149
146
ug_udbg_init();
···
161
164
162
165
static int __init wii_device_probe(void)
163
166
{
164
-
if (!machine_is(wii))
165
-
return 0;
166
-
167
167
of_platform_populate(NULL, wii_of_bus, NULL, NULL);
168
168
return 0;
169
169
}
170
-
device_initcall(wii_device_probe);
170
+
machine_device_initcall(wii, wii_device_probe);
171
171
172
172
define_machine(wii) {
173
173
.name = "wii",
174
+
.compatible = "nintendo,wii",
174
175
.probe = wii_probe,
175
176
.setup_arch = wii_setup_arch,
176
177
.restart = wii_restart,
177
178
.halt = wii_halt,
178
179
.init_IRQ = wii_pic_probe,
179
180
.get_irq = flipper_pic_get_irq,
180
-
.calibrate_decr = generic_calibrate_decr,
181
181
.progress = udbg_progress,
182
182
.machine_shutdown = wii_shutdown,
183
183
};
+25
-4
arch/powerpc/platforms/fsl_uli1575.c
+25
-4
arch/powerpc/platforms/fsl_uli1575.c
···
13
13
#include <linux/of_irq.h>
14
14
15
15
#include <asm/pci-bridge.h>
16
+
#include <asm/ppc-pci.h>
17
+
18
+
#include <sysdev/fsl_pci.h>
16
19
17
20
#define ULI_PIRQA 0x08
18
21
#define ULI_PIRQB 0x09
···
39
36
#define ULI_8259_IRQ14 0x0d
40
37
#define ULI_8259_IRQ15 0x0f
41
38
42
-
u8 uli_pirq_to_irq[8] = {
39
+
static u8 uli_pirq_to_irq[8] = {
43
40
ULI_8259_IRQ9, /* PIRQA */
44
41
ULI_8259_IRQ10, /* PIRQB */
45
42
ULI_8259_IRQ11, /* PIRQC */
···
344
341
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x5229, hpcd_quirk_uli5229);
345
342
DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, 0x5288, hpcd_final_uli5288);
346
343
347
-
int uli_exclude_device(struct pci_controller *hose,
348
-
u_char bus, u_char devfn)
344
+
static int uli_exclude_device(struct pci_controller *hose, u_char bus, u_char devfn)
349
345
{
350
-
if (bus == (hose->first_busno + 2)) {
346
+
if (hose->dn == fsl_pci_primary && bus == (hose->first_busno + 2)) {
351
347
/* exclude Modem controller */
352
348
if ((PCI_SLOT(devfn) == 29) && (PCI_FUNC(devfn) == 1))
353
349
return PCIBIOS_DEVICE_NOT_FOUND;
···
357
355
}
358
356
359
357
return PCIBIOS_SUCCESSFUL;
358
+
}
359
+
360
+
void __init uli_init(void)
361
+
{
362
+
struct device_node *node;
363
+
struct device_node *pci_with_uli;
364
+
365
+
/* See if we have a ULI under the primary */
366
+
367
+
node = of_find_node_by_name(NULL, "uli1575");
368
+
while ((pci_with_uli = of_get_parent(node))) {
369
+
of_node_put(node);
370
+
node = pci_with_uli;
371
+
372
+
if (pci_with_uli == fsl_pci_primary) {
373
+
ppc_md.pci_exclude_device = uli_exclude_device;
374
+
break;
375
+
}
376
+
}
360
377
}
+1
-2
arch/powerpc/platforms/maple/setup.c
+1
-2
arch/powerpc/platforms/maple/setup.c
···
235
235
BUG_ON(openpic_addr == 0);
236
236
237
237
/* Check for a big endian MPIC */
238
-
if (of_get_property(np, "big-endian", NULL) != NULL)
238
+
if (of_property_read_bool(np, "big-endian"))
239
239
flags |= MPIC_BIG_ENDIAN;
240
240
241
241
/* XXX Maple specific bits */
···
357
357
.get_boot_time = maple_get_boot_time,
358
358
.set_rtc_time = maple_set_rtc_time,
359
359
.get_rtc_time = maple_get_rtc_time,
360
-
.calibrate_decr = generic_calibrate_decr,
361
360
.progress = maple_progress,
362
361
.power_save = power4_idle,
363
362
};
+1
-7
arch/powerpc/platforms/microwatt/setup.c
+1
-7
arch/powerpc/platforms/microwatt/setup.c
···
23
23
xics_init();
24
24
}
25
25
26
-
static int __init microwatt_probe(void)
27
-
{
28
-
return of_machine_is_compatible("microwatt-soc");
29
-
}
30
-
31
26
static int __init microwatt_populate(void)
32
27
{
33
28
return of_platform_default_populate(NULL, NULL, NULL);
···
36
41
37
42
define_machine(microwatt) {
38
43
.name = "microwatt",
39
-
.probe = microwatt_probe,
44
+
.compatible = "microwatt-soc",
40
45
.init_IRQ = microwatt_init_IRQ,
41
46
.setup_arch = microwatt_setup_arch,
42
47
.progress = udbg_progress,
43
-
.calibrate_decr = generic_calibrate_decr,
44
48
};
+1
-1
arch/powerpc/platforms/pasemi/iommu.c
+1
-1
arch/powerpc/platforms/pasemi/iommu.c
-1
arch/powerpc/platforms/pasemi/setup.c
-1
arch/powerpc/platforms/pasemi/setup.c
+7
-11
arch/powerpc/platforms/powermac/feature.c
+7
-11
arch/powerpc/platforms/powermac/feature.c
···
2506
2506
int cpu_count = 1;
2507
2507
2508
2508
/* Nap mode not supported on SMP */
2509
-
if (of_get_property(np, "flush-on-lock", NULL) ||
2509
+
if (of_property_read_bool(np, "flush-on-lock") ||
2510
2510
(cpu_count > 1)) {
2511
2511
powersave_nap = 0;
2512
2512
of_node_put(np);
···
2545
2545
*/
2546
2546
static void __init probe_uninorth(void)
2547
2547
{
2548
-
const u32 *addrp;
2549
-
phys_addr_t address;
2548
+
struct resource res;
2550
2549
unsigned long actrl;
2551
2550
2552
2551
/* Locate core99 Uni-N */
···
2567
2568
return;
2568
2569
}
2569
2570
2570
-
addrp = of_get_property(uninorth_node, "reg", NULL);
2571
-
if (addrp == NULL)
2571
+
if (of_address_to_resource(uninorth_node, 0, &res))
2572
2572
return;
2573
-
address = of_translate_address(uninorth_node, addrp);
2574
-
if (address == 0)
2575
-
return;
2576
-
uninorth_base = ioremap(address, 0x40000);
2573
+
2574
+
uninorth_base = ioremap(res.start, 0x40000);
2577
2575
if (uninorth_base == NULL)
2578
2576
return;
2579
2577
uninorth_rev = in_be32(UN_REG(UNI_N_VERSION));
2580
2578
if (uninorth_maj == 3 || uninorth_maj == 4) {
2581
-
u3_ht_base = ioremap(address + U3_HT_CONFIG_BASE, 0x1000);
2579
+
u3_ht_base = ioremap(res.start + U3_HT_CONFIG_BASE, 0x1000);
2582
2580
if (u3_ht_base == NULL) {
2583
2581
iounmap(uninorth_base);
2584
2582
return;
···
2585
2589
printk(KERN_INFO "Found %s memory controller & host bridge"
2586
2590
" @ 0x%08x revision: 0x%02x\n", uninorth_maj == 3 ? "U3" :
2587
2591
uninorth_maj == 4 ? "U4" : "UniNorth",
2588
-
(unsigned int)address, uninorth_rev);
2592
+
(unsigned int)res.start, uninorth_rev);
2589
2593
printk(KERN_INFO "Mapped at 0x%08lx\n", (unsigned long)uninorth_base);
2590
2594
2591
2595
/* Set the arbitrer QAck delay according to what Apple does
+3
-4
arch/powerpc/platforms/powermac/pic.c
+3
-4
arch/powerpc/platforms/powermac/pic.c
···
450
450
451
451
pmac_call_feature(PMAC_FTR_ENABLE_MPIC, np, 0, 0);
452
452
453
-
if (of_get_property(np, "big-endian", NULL))
453
+
if (of_property_read_bool(np, "big-endian"))
454
454
flags |= MPIC_BIG_ENDIAN;
455
455
456
456
/* Primary Big Endian means HT interrupts. This is quite dodgy
···
475
475
476
476
/* We can have up to 2 MPICs cascaded */
477
477
for_each_node_by_type(np, "open-pic") {
478
-
if (master == NULL &&
479
-
of_get_property(np, "interrupts", NULL) == NULL)
478
+
if (master == NULL && !of_property_present(np, "interrupts"))
480
479
master = of_node_get(np);
481
480
else if (slave == NULL)
482
481
slave = of_node_get(np);
···
527
528
#ifdef CONFIG_PPC32
528
529
if (!pmac_newworld)
529
530
of_irq_workarounds |= OF_IMAP_OLDWORLD_MAC;
530
-
if (of_get_property(of_chosen, "linux,bootx", NULL) != NULL)
531
+
if (of_property_read_bool(of_chosen, "linux,bootx"))
531
532
of_irq_workarounds |= OF_IMAP_NO_PHANDLE;
532
533
533
534
/* If we don't have phandles on a newworld, then try to locate a
+1
-1
arch/powerpc/platforms/powermac/setup.c
+1
-1
arch/powerpc/platforms/powermac/setup.c
···
137
137
of_get_property(np, "d-cache-size", NULL);
138
138
seq_printf(m, "L2 cache\t:");
139
139
has_l2cache = 1;
140
-
if (of_get_property(np, "cache-unified", NULL) && dc) {
140
+
if (of_property_read_bool(np, "cache-unified") && dc) {
141
141
seq_printf(m, " %dK unified", *dc / 1024);
142
142
} else {
143
143
if (ic)
+1
-1
arch/powerpc/platforms/powermac/smp.c
+1
-1
arch/powerpc/platforms/powermac/smp.c
···
706
706
struct device_node *cpus =
707
707
of_find_node_by_path("/cpus");
708
708
if (cpus &&
709
-
of_get_property(cpus, "platform-cpu-timebase", NULL)) {
709
+
of_property_read_bool(cpus, "platform-cpu-timebase")) {
710
710
pmac_tb_freeze = smp_core99_pfunc_tb_freeze;
711
711
printk(KERN_INFO "Processor timebase sync using"
712
712
" platform function\n");
+1
-1
arch/powerpc/platforms/powernv/opal-lpc.c
+1
-1
arch/powerpc/platforms/powernv/opal-lpc.c
···
403
403
return;
404
404
405
405
/* Does it support direct mapping ? */
406
-
if (of_get_property(np, "ranges", NULL)) {
406
+
if (of_property_present(np, "ranges")) {
407
407
pr_info("OPAL: Found memory mapped LPC bus on chip %d\n",
408
408
opal_lpc_chip_id);
409
409
isa_bridge_init_non_pci(np);
+41
-1
arch/powerpc/platforms/powernv/pci-ioda.c
+41
-1
arch/powerpc/platforms/powernv/pci-ioda.c
···
1554
1554
if (WARN_ON(!tbl))
1555
1555
return;
1556
1556
1557
+
#ifdef CONFIG_IOMMU_API
1558
+
pe->table_group.ops = &spapr_tce_table_group_ops;
1559
+
pe->table_group.pgsizes = SZ_4K;
1560
+
#endif
1557
1561
iommu_register_group(&pe->table_group, phb->hose->global_number,
1558
1562
pe->pe_number);
1559
1563
pnv_pci_link_table_and_group(phb->hose->node, 0, tbl, &pe->table_group);
···
1892
1888
}
1893
1889
}
1894
1890
1895
-
static void pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
1891
+
static long pnv_ioda2_take_ownership(struct iommu_table_group *table_group)
1896
1892
{
1897
1893
struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1898
1894
table_group);
1899
1895
/* Store @tbl as pnv_pci_ioda2_unset_window() resets it */
1900
1896
struct iommu_table *tbl = pe->table_group.tables[0];
1897
+
1898
+
/*
1899
+
* iommu_ops transfers the ownership per a device and we mode
1900
+
* the group ownership with the first device in the group.
1901
+
*/
1902
+
if (!tbl)
1903
+
return 0;
1901
1904
1902
1905
pnv_pci_ioda2_set_bypass(pe, false);
1903
1906
pnv_pci_ioda2_unset_window(&pe->table_group, 0);
···
1913
1902
else if (pe->pdev)
1914
1903
set_iommu_table_base(&pe->pdev->dev, NULL);
1915
1904
iommu_tce_table_put(tbl);
1905
+
1906
+
return 0;
1916
1907
}
1917
1908
1918
1909
static void pnv_ioda2_release_ownership(struct iommu_table_group *table_group)
···
1922
1909
struct pnv_ioda_pe *pe = container_of(table_group, struct pnv_ioda_pe,
1923
1910
table_group);
1924
1911
1912
+
/* See the comment about iommu_ops above */
1913
+
if (pe->table_group.tables[0])
1914
+
return;
1925
1915
pnv_pci_ioda2_setup_default_config(pe);
1926
1916
if (pe->pbus)
1927
1917
pnv_ioda_setup_bus_dma(pe, pe->pbus);
···
2931
2915
}
2932
2916
}
2933
2917
2918
+
#ifdef CONFIG_IOMMU_API
2919
+
static struct iommu_group *pnv_pci_device_group(struct pci_controller *hose,
2920
+
struct pci_dev *pdev)
2921
+
{
2922
+
struct pnv_phb *phb = hose->private_data;
2923
+
struct pnv_ioda_pe *pe;
2924
+
2925
+
if (WARN_ON(!phb))
2926
+
return ERR_PTR(-ENODEV);
2927
+
2928
+
pe = pnv_pci_bdfn_to_pe(phb, pdev->devfn | (pdev->bus->number << 8));
2929
+
if (!pe)
2930
+
return ERR_PTR(-ENODEV);
2931
+
2932
+
if (!pe->table_group.group)
2933
+
return ERR_PTR(-ENODEV);
2934
+
2935
+
return iommu_group_ref_get(pe->table_group.group);
2936
+
}
2937
+
#endif
2938
+
2934
2939
static const struct pci_controller_ops pnv_pci_ioda_controller_ops = {
2935
2940
.dma_dev_setup = pnv_pci_ioda_dma_dev_setup,
2936
2941
.dma_bus_setup = pnv_pci_ioda_dma_bus_setup,
···
2962
2925
.setup_bridge = pnv_pci_fixup_bridge_resources,
2963
2926
.reset_secondary_bus = pnv_pci_reset_secondary_bus,
2964
2927
.shutdown = pnv_pci_ioda_shutdown,
2928
+
#ifdef CONFIG_IOMMU_API
2929
+
.device_group = pnv_pci_device_group,
2930
+
#endif
2965
2931
};
2966
2932
2967
2933
static const struct pci_controller_ops pnv_npu_ocapi_ioda_controller_ops = {
+1
-4
arch/powerpc/platforms/powernv/setup.c
+1
-4
arch/powerpc/platforms/powernv/setup.c
···
512
512
513
513
static int __init pnv_probe(void)
514
514
{
515
-
if (!of_machine_is_compatible("ibm,powernv"))
516
-
return 0;
517
-
518
515
if (firmware_has_feature(FW_FEATURE_OPAL))
519
516
pnv_setup_machdep_opal();
520
517
···
575
578
576
579
define_machine(powernv) {
577
580
.name = "PowerNV",
581
+
.compatible = "ibm,powernv",
578
582
.probe = pnv_probe,
579
583
.setup_arch = pnv_setup_arch,
580
584
.init_IRQ = pnv_init_IRQ,
···
585
587
.progress = pnv_progress,
586
588
.machine_shutdown = pnv_shutdown,
587
589
.power_save = NULL,
588
-
.calibrate_decr = generic_calibrate_decr,
589
590
.machine_check_early = pnv_machine_check_early,
590
591
#ifdef CONFIG_KEXEC_CORE
591
592
.kexec_cpu_down = pnv_kexec_cpu_down,
+1
-3
arch/powerpc/platforms/ps3/setup.c
+1
-3
arch/powerpc/platforms/ps3/setup.c
···
264
264
{
265
265
DBG(" -> %s:%d\n", __func__, __LINE__);
266
266
267
-
if (!of_machine_is_compatible("sony,ps3"))
268
-
return 0;
269
-
270
267
ps3_os_area_save_params();
271
268
272
269
pm_power_off = ps3_power_off;
···
288
291
289
292
define_machine(ps3) {
290
293
.name = "PS3",
294
+
.compatible = "sony,ps3",
291
295
.probe = ps3_probe,
292
296
.setup_arch = ps3_setup_arch,
293
297
.init_IRQ = ps3_init_IRQ,
+1
arch/powerpc/platforms/pseries/firmware.c
+1
arch/powerpc/platforms/pseries/firmware.c
+1
-1
arch/powerpc/platforms/pseries/hotplug-cpu.c
+1
-1
arch/powerpc/platforms/pseries/hotplug-cpu.c
···
493
493
bool found = false;
494
494
int rc, index;
495
495
496
-
if (of_find_property(parent, "ibm,drc-info", NULL))
496
+
if (of_property_present(parent, "ibm,drc-info"))
497
497
return drc_info_valid_index(parent, drc_index);
498
498
499
499
/* Note that the format of the ibm,drc-indexes array is
+10
-35
arch/powerpc/platforms/pseries/hotplug-memory.c
+10
-35
arch/powerpc/platforms/pseries/hotplug-memory.c
···
311
311
312
312
static int pseries_remove_mem_node(struct device_node *np)
313
313
{
314
-
const __be32 *prop;
315
-
unsigned long base;
316
-
unsigned long lmb_size;
317
-
int ret = -EINVAL;
318
-
int addr_cells, size_cells;
314
+
int ret;
315
+
struct resource res;
319
316
320
317
/*
321
318
* Check to see if we are actually removing memory
···
323
326
/*
324
327
* Find the base address and size of the memblock
325
328
*/
326
-
prop = of_get_property(np, "reg", NULL);
327
-
if (!prop)
329
+
ret = of_address_to_resource(np, 0, &res);
330
+
if (ret)
328
331
return ret;
329
332
330
-
addr_cells = of_n_addr_cells(np);
331
-
size_cells = of_n_size_cells(np);
332
-
333
-
/*
334
-
* "reg" property represents (addr,size) tuple.
335
-
*/
336
-
base = of_read_number(prop, addr_cells);
337
-
prop += addr_cells;
338
-
lmb_size = of_read_number(prop, size_cells);
339
-
340
-
pseries_remove_memblock(base, lmb_size);
333
+
pseries_remove_memblock(res.start, resource_size(&res));
341
334
return 0;
342
335
}
343
336
···
916
929
917
930
static int pseries_add_mem_node(struct device_node *np)
918
931
{
919
-
const __be32 *prop;
920
-
unsigned long base;
921
-
unsigned long lmb_size;
922
-
int ret = -EINVAL;
923
-
int addr_cells, size_cells;
932
+
int ret;
933
+
struct resource res;
924
934
925
935
/*
926
936
* Check to see if we are actually adding memory
···
928
944
/*
929
945
* Find the base and size of the memblock
930
946
*/
931
-
prop = of_get_property(np, "reg", NULL);
932
-
if (!prop)
947
+
ret = of_address_to_resource(np, 0, &res);
948
+
if (ret)
933
949
return ret;
934
-
935
-
addr_cells = of_n_addr_cells(np);
936
-
size_cells = of_n_size_cells(np);
937
-
/*
938
-
* "reg" property represents (addr,size) tuple.
939
-
*/
940
-
base = of_read_number(prop, addr_cells);
941
-
prop += addr_cells;
942
-
lmb_size = of_read_number(prop, size_cells);
943
950
944
951
/*
945
952
* Update memory region to represent the memory add
946
953
*/
947
-
ret = memblock_add(base, lmb_size);
954
+
ret = memblock_add(res.start, resource_size(&res));
948
955
return (ret < 0) ? -EINVAL : 0;
949
956
}
950
957
+2
-2
arch/powerpc/platforms/pseries/hvCall.S
+2
-2
arch/powerpc/platforms/pseries/hvCall.S
···
44
44
std r0,16(r1); \
45
45
addi r4,r1,STK_PARAM(FIRST_REG); \
46
46
stdu r1,-STACK_FRAME_MIN_SIZE(r1); \
47
-
bl __trace_hcall_entry; \
47
+
bl CFUNC(__trace_hcall_entry); \
48
48
ld r3,STACK_FRAME_MIN_SIZE+STK_PARAM(R3)(r1); \
49
49
ld r4,STACK_FRAME_MIN_SIZE+STK_PARAM(R4)(r1); \
50
50
ld r5,STACK_FRAME_MIN_SIZE+STK_PARAM(R5)(r1); \
···
63
63
std r3,STACK_FRAME_MIN_SIZE+STK_PARAM(R3)(r1); \
64
64
mr r4,r3; \
65
65
mr r3,r0; \
66
-
bl __trace_hcall_exit; \
66
+
bl CFUNC(__trace_hcall_exit); \
67
67
ld r0,STACK_FRAME_MIN_SIZE+16(r1); \
68
68
addi r1,r1,STACK_FRAME_MIN_SIZE; \
69
69
ld r3,STK_PARAM(R3)(r1); \
+35
-16
arch/powerpc/platforms/pseries/iommu.c
+35
-16
arch/powerpc/platforms/pseries/iommu.c
···
22
22
#include <linux/crash_dump.h>
23
23
#include <linux/memory.h>
24
24
#include <linux/of.h>
25
+
#include <linux/of_address.h>
25
26
#include <linux/iommu.h>
26
27
#include <linux/rculist.h>
27
28
#include <asm/io.h>
···
74
73
table_group = kzalloc_node(sizeof(*table_group), GFP_KERNEL, node);
75
74
if (!table_group)
76
75
return NULL;
76
+
77
+
#ifdef CONFIG_IOMMU_API
78
+
table_group->ops = &spapr_tce_table_group_ops;
79
+
table_group->pgsizes = SZ_4K;
80
+
#endif
77
81
78
82
table_group->tables[0] = iommu_pseries_alloc_table(node);
79
83
if (table_group->tables[0])
···
480
474
* Set up the page with TCE data, looping through and setting
481
475
* the values.
482
476
*/
483
-
limit = min_t(long, num_tce, 4096/TCE_ENTRY_SIZE);
477
+
limit = min_t(long, num_tce, 4096 / TCE_ENTRY_SIZE);
484
478
dma_offset = next + be64_to_cpu(maprange->dma_base);
485
479
486
480
for (l = 0; l < limit; l++) {
···
1117
1111
1118
1112
static phys_addr_t ddw_memory_hotplug_max(void)
1119
1113
{
1120
-
phys_addr_t max_addr = memory_hotplug_max();
1114
+
resource_size_t max_addr = memory_hotplug_max();
1121
1115
struct device_node *memory;
1122
1116
1123
1117
for_each_node_by_type(memory, "memory") {
1124
-
unsigned long start, size;
1125
-
int n_mem_addr_cells, n_mem_size_cells, len;
1126
-
const __be32 *memcell_buf;
1118
+
struct resource res;
1127
1119
1128
-
memcell_buf = of_get_property(memory, "reg", &len);
1129
-
if (!memcell_buf || len <= 0)
1120
+
if (of_address_to_resource(memory, 0, &res))
1130
1121
continue;
1131
1122
1132
-
n_mem_addr_cells = of_n_addr_cells(memory);
1133
-
n_mem_size_cells = of_n_size_cells(memory);
1134
-
1135
-
start = of_read_number(memcell_buf, n_mem_addr_cells);
1136
-
memcell_buf += n_mem_addr_cells;
1137
-
size = of_read_number(memcell_buf, n_mem_size_cells);
1138
-
memcell_buf += n_mem_size_cells;
1139
-
1140
-
max_addr = max_t(phys_addr_t, max_addr, start + size);
1123
+
max_addr = max_t(resource_size_t, max_addr, res.end + 1);
1141
1124
}
1142
1125
1143
1126
return max_addr;
···
1719
1724
return 0;
1720
1725
}
1721
1726
machine_subsys_initcall_sync(pseries, tce_iommu_bus_notifier_init);
1727
+
1728
+
#ifdef CONFIG_SPAPR_TCE_IOMMU
1729
+
struct iommu_group *pSeries_pci_device_group(struct pci_controller *hose,
1730
+
struct pci_dev *pdev)
1731
+
{
1732
+
struct device_node *pdn, *dn = pdev->dev.of_node;
1733
+
struct iommu_group *grp;
1734
+
struct pci_dn *pci;
1735
+
1736
+
pdn = pci_dma_find(dn, NULL);
1737
+
if (!pdn || !PCI_DN(pdn))
1738
+
return ERR_PTR(-ENODEV);
1739
+
1740
+
pci = PCI_DN(pdn);
1741
+
if (!pci->table_group)
1742
+
return ERR_PTR(-ENODEV);
1743
+
1744
+
grp = pci->table_group->group;
1745
+
if (!grp)
1746
+
return ERR_PTR(-ENODEV);
1747
+
1748
+
return iommu_group_ref_get(grp);
1749
+
}
1750
+
#endif
+1
-9
arch/powerpc/platforms/pseries/mobility.c
+1
-9
arch/powerpc/platforms/pseries/mobility.c
···
62
62
},
63
63
{}
64
64
};
65
-
static struct ctl_table nmi_wd_lpm_factor_sysctl_root[] = {
66
-
{
67
-
.procname = "kernel",
68
-
.mode = 0555,
69
-
.child = nmi_wd_lpm_factor_ctl_table,
70
-
},
71
-
{}
72
-
};
73
65
74
66
static int __init register_nmi_wd_lpm_factor_sysctl(void)
75
67
{
76
-
register_sysctl_table(nmi_wd_lpm_factor_sysctl_root);
68
+
register_sysctl("kernel", nmi_wd_lpm_factor_ctl_table);
77
69
78
70
return 0;
79
71
}
+4
-1
arch/powerpc/platforms/pseries/plpks.c
+4
-1
arch/powerpc/platforms/pseries/plpks.c
···
378
378
{
379
379
int rc;
380
380
381
-
if (!firmware_has_feature(FW_FEATURE_LPAR))
381
+
if (!firmware_has_feature(FW_FEATURE_PLPKS))
382
382
return false;
383
383
384
384
rc = _plpks_get_config();
···
689
689
static __init int pseries_plpks_init(void)
690
690
{
691
691
int rc;
692
+
693
+
if (!firmware_has_feature(FW_FEATURE_PLPKS))
694
+
return -ENODEV;
692
695
693
696
rc = _plpks_get_config();
694
697
+4
arch/powerpc/platforms/pseries/pseries.h
+4
arch/powerpc/platforms/pseries/pseries.h
+3
-1
arch/powerpc/platforms/pseries/setup.c
+3
-1
arch/powerpc/platforms/pseries/setup.c
···
1118
1118
1119
1119
struct pci_controller_ops pseries_pci_controller_ops = {
1120
1120
.probe_mode = pSeries_pci_probe_mode,
1121
+
#ifdef CONFIG_SPAPR_TCE_IOMMU
1122
+
.device_group = pSeries_pci_device_group,
1123
+
#endif
1121
1124
};
1122
1125
1123
1126
define_machine(pseries) {
···
1138
1135
.get_boot_time = rtas_get_boot_time,
1139
1136
.get_rtc_time = rtas_get_rtc_time,
1140
1137
.set_rtc_time = rtas_set_rtc_time,
1141
-
.calibrate_decr = generic_calibrate_decr,
1142
1138
.progress = rtas_progress,
1143
1139
.system_reset_exception = pSeries_system_reset_exception,
1144
1140
.machine_check_early = pseries_machine_check_realmode,
+2
-2
arch/powerpc/platforms/pseries/vio.c
+2
-2
arch/powerpc/platforms/pseries/vio.c
···
1381
1381
}
1382
1382
1383
1383
if (family == PFO) {
1384
-
if (of_get_property(of_node, "interrupt-controller", NULL)) {
1384
+
if (of_property_read_bool(of_node, "interrupt-controller")) {
1385
1385
pr_debug("%s: Skipping the interrupt controller %pOFn.\n",
1386
1386
__func__, of_node);
1387
1387
return NULL;
···
1440
1440
viodev->dev.bus = &vio_bus_type;
1441
1441
viodev->dev.release = vio_dev_release;
1442
1442
1443
-
if (of_get_property(viodev->dev.of_node, "ibm,my-dma-window", NULL)) {
1443
+
if (of_property_present(viodev->dev.of_node, "ibm,my-dma-window")) {
1444
1444
if (firmware_has_feature(FW_FEATURE_CMO))
1445
1445
vio_cmo_set_dma_ops(viodev);
1446
1446
else
+1
-1
arch/powerpc/sysdev/dcr.c
+1
-1
arch/powerpc/sysdev/dcr.c
+1
-5
arch/powerpc/sysdev/ehv_pic.c
+1
-5
arch/powerpc/sysdev/ehv_pic.c
···
256
256
{
257
257
struct device_node *np, *np2;
258
258
struct ehv_pic *ehv_pic;
259
-
int coreint_flag = 1;
260
259
261
260
np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
262
261
if (!np) {
263
262
pr_err("ehv_pic_init: could not find epapr,hv-pic node\n");
264
263
return;
265
264
}
266
-
267
-
if (!of_find_property(np, "has-external-proxy", NULL))
268
-
coreint_flag = 0;
269
265
270
266
ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
271
267
if (!ehv_pic) {
···
288
292
289
293
ehv_pic->hc_irq = ehv_pic_irq_chip;
290
294
ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
291
-
ehv_pic->coreint_flag = coreint_flag;
295
+
ehv_pic->coreint_flag = of_property_read_bool(np, "has-external-proxy");
292
296
293
297
global_ehv_pic = ehv_pic;
294
298
irq_set_default_host(global_ehv_pic->irqhost);
+3
-20
arch/powerpc/sysdev/fsl_rio.c
+3
-20
arch/powerpc/sysdev/fsl_rio.c
···
450
450
int rc = 0;
451
451
const u32 *dt_range, *cell, *port_index;
452
452
u32 active_ports = 0;
453
-
struct resource regs, rmu_regs;
454
453
struct device_node *np, *rmu_node;
455
454
int rlen;
456
455
u32 ccsr;
···
464
465
return -ENODEV;
465
466
}
466
467
467
-
rc = of_address_to_resource(dev->dev.of_node, 0, ®s);
468
-
if (rc) {
469
-
dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
470
-
dev->dev.of_node);
471
-
return -EFAULT;
472
-
}
473
-
dev_info(&dev->dev, "Of-device full name %pOF\n",
474
-
dev->dev.of_node);
475
-
dev_info(&dev->dev, "Regs: %pR\n", ®s);
476
-
477
-
rio_regs_win = ioremap(regs.start, resource_size(®s));
468
+
rio_regs_win = of_iomap(dev->dev.of_node, 0);
478
469
if (!rio_regs_win) {
479
470
dev_err(&dev->dev, "Unable to map rio register window\n");
480
471
rc = -ENOMEM;
···
498
509
rc = -ENOENT;
499
510
goto err_rmu;
500
511
}
501
-
rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
502
-
if (rc) {
503
-
dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
504
-
rmu_node);
505
-
of_node_put(rmu_node);
506
-
goto err_rmu;
507
-
}
512
+
rmu_regs_win = of_iomap(rmu_node, 0);
513
+
508
514
of_node_put(rmu_node);
509
-
rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
510
515
if (!rmu_regs_win) {
511
516
dev_err(&dev->dev, "Unable to map rmu register window\n");
512
517
rc = -ENOMEM;
+1
-1
arch/powerpc/sysdev/fsl_soc.c
+1
-1
arch/powerpc/sysdev/fsl_soc.c
···
174
174
};
175
175
176
176
for_each_node_by_name(np, "global-utilities") {
177
-
if ((of_get_property(np, "fsl,has-rstcr", NULL))) {
177
+
if (of_property_read_bool(np, "fsl,has-rstcr")) {
178
178
rstcr = of_iomap(np, 0) + 0xb0;
179
179
if (!rstcr) {
180
180
printk (KERN_ERR "Error: reset control "
+3
-3
arch/powerpc/sysdev/mpic.c
+3
-3
arch/powerpc/sysdev/mpic.c
···
1260
1260
}
1261
1261
1262
1262
/* Read extra device-tree properties into the flags variable */
1263
-
if (of_get_property(node, "big-endian", NULL))
1263
+
if (of_property_read_bool(node, "big-endian"))
1264
1264
flags |= MPIC_BIG_ENDIAN;
1265
-
if (of_get_property(node, "pic-no-reset", NULL))
1265
+
if (of_property_read_bool(node, "pic-no-reset"))
1266
1266
flags |= MPIC_NO_RESET;
1267
-
if (of_get_property(node, "single-cpu-affinity", NULL))
1267
+
if (of_property_read_bool(node, "single-cpu-affinity"))
1268
1268
flags |= MPIC_SINGLE_DEST_CPU;
1269
1269
if (of_device_is_compatible(node, "fsl,mpic")) {
1270
1270
flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
+1
-1
arch/powerpc/sysdev/mpic_msgr.c
+1
-1
arch/powerpc/sysdev/mpic_msgr.c
+4
-4
arch/powerpc/sysdev/tsi108_dev.c
+4
-4
arch/powerpc/sysdev/tsi108_dev.c
···
45
45
46
46
tsi = of_find_node_by_type(NULL, "tsi-bridge");
47
47
if (tsi) {
48
-
unsigned int size;
49
-
const void *prop = of_get_property(tsi, "reg", &size);
50
-
tsi108_csr_base = of_translate_address(tsi, prop);
48
+
struct resource res;
49
+
of_address_to_resource(tsi, 0, &res);
50
+
tsi108_csr_base = res.start;
51
51
of_node_put(tsi);
52
52
}
53
53
return tsi108_csr_base;
···
132
132
* driver itself to phylib and use a non-misleading
133
133
* name for the workaround flag - it's not actually to
134
134
* do with the model of PHY in use */
135
-
if (of_get_property(phy, "txc-rxc-delay-disable", NULL))
135
+
if (of_property_read_bool(phy, "txc-rxc-delay-disable"))
136
136
tsi_eth_data.phy_type = TSI108_PHY_BCM54XX;
137
137
of_node_put(phy);
138
138
+2
-3
arch/powerpc/sysdev/tsi108_pci.c
+2
-3
arch/powerpc/sysdev/tsi108_pci.c
···
217
217
218
218
(hose)->ops = &tsi108_direct_pci_ops;
219
219
220
-
printk(KERN_INFO "Found tsi108 PCI host bridge at 0x%08x. "
221
-
"Firmware bus number: %d->%d\n",
222
-
rsrc.start, hose->first_busno, hose->last_busno);
220
+
pr_info("Found tsi108 PCI host bridge at 0x%pa. Firmware bus number: %d->%d\n",
221
+
&rsrc.start, hose->first_busno, hose->last_busno);
223
222
224
223
/* Interpret the "ranges" property */
225
224
/* This also maps the I/O region and sets isa_io/mem_base */
+5
-12
arch/powerpc/sysdev/xics/icp-native.c
+5
-12
arch/powerpc/sysdev/xics/icp-native.c
···
259
259
unsigned int ilen;
260
260
const __be32 *ireg;
261
261
int i;
262
-
int reg_tuple_size;
262
+
int num_reg;
263
263
int num_servers = 0;
264
264
265
265
/* This code does the theorically broken assumption that the interrupt
···
280
280
num_servers = of_read_number(ireg + 1, 1);
281
281
}
282
282
283
-
ireg = of_get_property(np, "reg", &ilen);
284
-
if (!ireg) {
285
-
pr_err("icp_native: Can't find interrupt reg property");
286
-
return -1;
287
-
}
288
-
289
-
reg_tuple_size = (of_n_addr_cells(np) + of_n_size_cells(np)) * 4;
290
-
if (((ilen % reg_tuple_size) != 0)
291
-
|| (num_servers && (num_servers != (ilen / reg_tuple_size)))) {
283
+
num_reg = of_address_count(np);
284
+
if (num_servers && (num_servers != num_reg)) {
292
285
pr_err("icp_native: ICP reg len (%d) != num servers (%d)",
293
-
ilen / reg_tuple_size, num_servers);
286
+
num_reg, num_servers);
294
287
return -1;
295
288
}
296
289
297
-
for (i = 0; i < (ilen / reg_tuple_size); i++) {
290
+
for (i = 0; i < num_reg; i++) {
298
291
struct resource r;
299
292
int err;
300
293
+2
-4
arch/powerpc/sysdev/xive/native.c
+2
-4
arch/powerpc/sysdev/xive/native.c
···
599
599
}
600
600
601
601
/* Do we support single escalation */
602
-
if (of_get_property(np, "single-escalation-support", NULL) != NULL)
603
-
xive_has_single_esc = true;
602
+
xive_has_single_esc = of_property_read_bool(np, "single-escalation-support");
604
603
605
-
if (of_get_property(np, "vp-save-restore", NULL))
606
-
xive_has_save_restore = true;
604
+
xive_has_save_restore = of_property_read_bool(np, "vp-save-restore");
607
605
608
606
/* Configure Thread Management areas for KVM */
609
607
for_each_possible_cpu(cpu)
+2
arch/powerpc/xmon/xmon.c
+2
arch/powerpc/xmon/xmon.c
···
2634
2634
2635
2635
DUMP(p, lock_token, "%#-*x");
2636
2636
DUMP(p, paca_index, "%#-*x");
2637
+
#ifndef CONFIG_PPC_KERNEL_PCREL
2637
2638
DUMP(p, kernel_toc, "%#-*llx");
2639
+
#endif
2638
2640
DUMP(p, kernelbase, "%#-*llx");
2639
2641
DUMP(p, kernel_msr, "%#-*llx");
2640
2642
DUMP(p, emergency_sp, "%-*px");
+14
-14
drivers/cpuidle/cpuidle-pseries.c
+14
-14
drivers/cpuidle/cpuidle-pseries.c
···
33
33
static u64 snooze_timeout __read_mostly;
34
34
static bool snooze_timeout_en __read_mostly;
35
35
36
-
static int snooze_loop(struct cpuidle_device *dev,
37
-
struct cpuidle_driver *drv,
38
-
int index)
36
+
static __cpuidle
37
+
int snooze_loop(struct cpuidle_device *dev, struct cpuidle_driver *drv,
38
+
int index)
39
39
{
40
40
u64 snooze_exit_time;
41
41
42
42
set_thread_flag(TIF_POLLING_NRFLAG);
43
43
44
44
pseries_idle_prolog();
45
-
local_irq_enable();
45
+
raw_local_irq_enable();
46
46
snooze_exit_time = get_tb() + snooze_timeout;
47
47
dev->poll_time_limit = false;
48
48
···
65
65
HMT_medium();
66
66
clear_thread_flag(TIF_POLLING_NRFLAG);
67
67
68
-
local_irq_disable();
68
+
raw_local_irq_disable();
69
69
70
70
pseries_idle_epilog();
71
71
72
72
return index;
73
73
}
74
74
75
-
static void check_and_cede_processor(void)
75
+
static __cpuidle void check_and_cede_processor(void)
76
76
{
77
77
/*
78
78
* Ensure our interrupt state is properly tracked,
···
216
216
#define NR_DEDICATED_STATES 2 /* snooze, CEDE */
217
217
static u8 cede_latency_hint[NR_DEDICATED_STATES];
218
218
219
-
static int dedicated_cede_loop(struct cpuidle_device *dev,
220
-
struct cpuidle_driver *drv,
221
-
int index)
219
+
static __cpuidle
220
+
int dedicated_cede_loop(struct cpuidle_device *dev, struct cpuidle_driver *drv,
221
+
int index)
222
222
{
223
223
u8 old_latency_hint;
224
224
···
230
230
HMT_medium();
231
231
check_and_cede_processor();
232
232
233
-
local_irq_disable();
233
+
raw_local_irq_disable();
234
234
get_lppaca()->donate_dedicated_cpu = 0;
235
235
get_lppaca()->cede_latency_hint = old_latency_hint;
236
236
···
239
239
return index;
240
240
}
241
241
242
-
static int shared_cede_loop(struct cpuidle_device *dev,
243
-
struct cpuidle_driver *drv,
244
-
int index)
242
+
static __cpuidle
243
+
int shared_cede_loop(struct cpuidle_device *dev, struct cpuidle_driver *drv,
244
+
int index)
245
245
{
246
246
247
247
pseries_idle_prolog();
···
255
255
*/
256
256
check_and_cede_processor();
257
257
258
-
local_irq_disable();
258
+
raw_local_irq_disable();
259
259
pseries_idle_epilog();
260
260
261
261
return index;
+1
-1
drivers/gpu/drm/amd/display/Kconfig
+1
-1
drivers/gpu/drm/amd/display/Kconfig
···
8
8
depends on BROKEN || !CC_IS_CLANG || X86_64 || SPARC64 || ARM64
9
9
select SND_HDA_COMPONENT if SND_HDA_CORE
10
10
# !CC_IS_CLANG: https://github.com/ClangBuiltLinux/linux/issues/1752
11
-
select DRM_AMD_DC_FP if (X86 || PPC64 || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG))
11
+
select DRM_AMD_DC_FP if (X86 || (PPC64 && ALTIVEC) || (ARM64 && KERNEL_MODE_NEON && !CC_IS_CLANG))
12
12
help
13
13
Choose this option if you want to use the new display engine
14
14
support for AMDGPU. This adds required support for Vega and
+1
drivers/macintosh/Kconfig
+1
drivers/macintosh/Kconfig
+1
-1
drivers/macintosh/rack-meter.c
+1
-1
drivers/macintosh/rack-meter.c
+1
-1
drivers/macintosh/therm_adt746x.c
+1
-1
drivers/macintosh/therm_adt746x.c
···
483
483
if (vers != 1)
484
484
return -ENXIO;
485
485
486
-
if (of_get_property(np, "hwsensor-location", NULL)) {
486
+
if (of_property_present(np, "hwsensor-location")) {
487
487
for (i = 0; i < 3; i++) {
488
488
sensor_location[i] = of_get_property(np,
489
489
"hwsensor-location", NULL) + offset;
+1
drivers/macintosh/windfarm_smu_sat.c
+1
drivers/macintosh/windfarm_smu_sat.c
+13
-83
drivers/vfio/vfio_iommu_spapr_tce.c
+13
-83
drivers/vfio/vfio_iommu_spapr_tce.c
···
1190
1190
static void tce_iommu_release_ownership(struct tce_container *container,
1191
1191
struct iommu_table_group *table_group)
1192
1192
{
1193
-
int i;
1194
-
1195
-
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
1196
-
struct iommu_table *tbl = container->tables[i];
1197
-
1198
-
if (!tbl)
1199
-
continue;
1200
-
1201
-
tce_iommu_clear(container, tbl, tbl->it_offset, tbl->it_size);
1202
-
if (tbl->it_map)
1203
-
iommu_release_ownership(tbl);
1204
-
1205
-
container->tables[i] = NULL;
1206
-
}
1207
-
}
1208
-
1209
-
static int tce_iommu_take_ownership(struct tce_container *container,
1210
-
struct iommu_table_group *table_group)
1211
-
{
1212
-
int i, j, rc = 0;
1213
-
1214
-
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
1215
-
struct iommu_table *tbl = table_group->tables[i];
1216
-
1217
-
if (!tbl || !tbl->it_map)
1218
-
continue;
1219
-
1220
-
rc = iommu_take_ownership(tbl);
1221
-
if (rc) {
1222
-
for (j = 0; j < i; ++j)
1223
-
iommu_release_ownership(
1224
-
table_group->tables[j]);
1225
-
1226
-
return rc;
1227
-
}
1228
-
}
1229
-
1230
-
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i)
1231
-
container->tables[i] = table_group->tables[i];
1232
-
1233
-
return 0;
1234
-
}
1235
-
1236
-
static void tce_iommu_release_ownership_ddw(struct tce_container *container,
1237
-
struct iommu_table_group *table_group)
1238
-
{
1239
1193
long i;
1240
1194
1241
1195
if (!table_group->ops->unset_window) {
···
1200
1246
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i)
1201
1247
if (container->tables[i])
1202
1248
table_group->ops->unset_window(table_group, i);
1203
-
1204
-
table_group->ops->release_ownership(table_group);
1205
1249
}
1206
1250
1207
-
static long tce_iommu_take_ownership_ddw(struct tce_container *container,
1251
+
static long tce_iommu_take_ownership(struct tce_container *container,
1208
1252
struct iommu_table_group *table_group)
1209
1253
{
1210
1254
long i, ret = 0;
1211
-
1212
-
if (!table_group->ops->create_table || !table_group->ops->set_window ||
1213
-
!table_group->ops->release_ownership) {
1214
-
WARN_ON_ONCE(1);
1215
-
return -EFAULT;
1216
-
}
1217
-
1218
-
table_group->ops->take_ownership(table_group);
1219
1255
1220
1256
/* Set all windows to the new group */
1221
1257
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i) {
···
1224
1280
release_exit:
1225
1281
for (i = 0; i < IOMMU_TABLE_GROUP_MAX_TABLES; ++i)
1226
1282
table_group->ops->unset_window(table_group, i);
1227
-
1228
-
table_group->ops->release_ownership(table_group);
1229
1283
1230
1284
return ret;
1231
1285
}
···
1249
1307
goto unlock_exit;
1250
1308
}
1251
1309
1252
-
if (tce_groups_attached(container) && (!table_group->ops ||
1253
-
!table_group->ops->take_ownership ||
1254
-
!table_group->ops->release_ownership)) {
1310
+
/* v2 requires full support of dynamic DMA windows */
1311
+
if (container->v2 && table_group->max_dynamic_windows_supported == 0) {
1312
+
ret = -EINVAL;
1313
+
goto unlock_exit;
1314
+
}
1315
+
1316
+
/* v1 reuses TCE tables and does not share them among PEs */
1317
+
if (!container->v2 && tce_groups_attached(container)) {
1255
1318
ret = -EBUSY;
1256
1319
goto unlock_exit;
1257
1320
}
···
1291
1344
goto unlock_exit;
1292
1345
}
1293
1346
1294
-
if (!table_group->ops || !table_group->ops->take_ownership ||
1295
-
!table_group->ops->release_ownership) {
1296
-
if (container->v2) {
1297
-
ret = -EPERM;
1298
-
goto free_exit;
1299
-
}
1300
-
ret = tce_iommu_take_ownership(container, table_group);
1301
-
} else {
1302
-
if (!container->v2) {
1303
-
ret = -EPERM;
1304
-
goto free_exit;
1305
-
}
1306
-
ret = tce_iommu_take_ownership_ddw(container, table_group);
1307
-
if (!tce_groups_attached(container) && !container->tables[0])
1308
-
container->def_window_pending = true;
1309
-
}
1347
+
ret = tce_iommu_take_ownership(container, table_group);
1348
+
if (!tce_groups_attached(container) && !container->tables[0])
1349
+
container->def_window_pending = true;
1310
1350
1311
1351
if (!ret) {
1312
1352
tcegrp->grp = iommu_group;
1313
1353
list_add(&tcegrp->next, &container->group_list);
1314
1354
}
1315
1355
1316
-
free_exit:
1317
1356
if (ret && tcegrp)
1318
1357
kfree(tcegrp);
1319
1358
···
1338
1405
table_group = iommu_group_get_iommudata(iommu_group);
1339
1406
BUG_ON(!table_group);
1340
1407
1341
-
if (!table_group->ops || !table_group->ops->release_ownership)
1342
-
tce_iommu_release_ownership(container, table_group);
1343
-
else
1344
-
tce_iommu_release_ownership_ddw(container, table_group);
1408
+
tce_iommu_release_ownership(container, table_group);
1345
1409
1346
1410
unlock_exit:
1347
1411
mutex_unlock(&container->lock);
+4
-4
tools/testing/selftests/powerpc/Makefile
+4
-4
tools/testing/selftests/powerpc/Makefile
···
45
45
include ../lib.mk
46
46
47
47
override define RUN_TESTS
48
-
@for TARGET in $(SUB_DIRS); do \
48
+
+@for TARGET in $(SUB_DIRS); do \
49
49
BUILD_TARGET=$(OUTPUT)/$$TARGET; \
50
50
$(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests;\
51
51
done;
52
52
endef
53
53
54
54
override define INSTALL_RULE
55
-
@for TARGET in $(SUB_DIRS); do \
55
+
+@for TARGET in $(SUB_DIRS); do \
56
56
BUILD_TARGET=$(OUTPUT)/$$TARGET; \
57
57
$(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install;\
58
58
done;
59
59
endef
60
60
61
61
override define EMIT_TESTS
62
-
@for TARGET in $(SUB_DIRS); do \
62
+
+@for TARGET in $(SUB_DIRS); do \
63
63
BUILD_TARGET=$(OUTPUT)/$$TARGET; \
64
64
$(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests;\
65
65
done;
66
66
endef
67
67
68
68
override define CLEAN
69
-
@for TARGET in $(SUB_DIRS); do \
69
+
+@for TARGET in $(SUB_DIRS); do \
70
70
BUILD_TARGET=$(OUTPUT)/$$TARGET; \
71
71
$(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean; \
72
72
done;
+1
tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
+1
tools/testing/selftests/powerpc/copyloops/asm/ppc_asm.h
+1
-2
tools/testing/selftests/powerpc/dscr/Makefile
+1
-2
tools/testing/selftests/powerpc/dscr/Makefile
···
3
3
dscr_inherit_test dscr_inherit_exec_test dscr_sysfs_test \
4
4
dscr_sysfs_thread_test
5
5
6
-
TEST_FILES := settings
7
-
8
6
top_srcdir = ../../../../..
9
7
include ../../lib.mk
10
8
11
9
$(OUTPUT)/dscr_default_test: LDLIBS += -lpthread
10
+
$(OUTPUT)/dscr_explicit_test: LDLIBS += -lpthread
12
11
13
12
$(TEST_GEN_PROGS): ../harness.c ../utils.c
-4
tools/testing/selftests/powerpc/dscr/dscr.h
-4
tools/testing/selftests/powerpc/dscr/dscr.h
+133
-90
tools/testing/selftests/powerpc/dscr/dscr_default_test.c
+133
-90
tools/testing/selftests/powerpc/dscr/dscr_default_test.c
···
9
9
* Copyright 2012, Anton Blanchard, IBM Corporation.
10
10
* Copyright 2015, Anshuman Khandual, IBM Corporation.
11
11
*/
12
+
13
+
#define _GNU_SOURCE
14
+
12
15
#include "dscr.h"
13
16
14
-
static unsigned long dscr; /* System DSCR default */
15
-
static unsigned long sequence;
16
-
static unsigned long result[THREADS];
17
+
#include <pthread.h>
18
+
#include <semaphore.h>
19
+
#include <unistd.h>
17
20
18
-
static void *do_test(void *in)
21
+
static void *dscr_default_lockstep_writer(void *arg)
19
22
{
20
-
unsigned long thread = (unsigned long)in;
21
-
unsigned long i;
23
+
sem_t *reader_sem = (sem_t *)arg;
24
+
sem_t *writer_sem = (sem_t *)arg + 1;
25
+
unsigned long expected_dscr = 0;
22
26
23
-
for (i = 0; i < COUNT; i++) {
24
-
unsigned long d, cur_dscr, cur_dscr_usr;
25
-
unsigned long s1, s2;
27
+
for (int i = 0; i < COUNT; i++) {
28
+
FAIL_IF_EXIT(sem_wait(writer_sem));
26
29
27
-
s1 = READ_ONCE(sequence);
28
-
if (s1 & 1)
29
-
continue;
30
-
rmb();
30
+
set_default_dscr(expected_dscr);
31
+
expected_dscr = (expected_dscr + 1) % DSCR_MAX;
31
32
32
-
d = dscr;
33
-
cur_dscr = get_dscr();
34
-
cur_dscr_usr = get_dscr_usr();
35
-
36
-
rmb();
37
-
s2 = sequence;
38
-
39
-
if (s1 != s2)
40
-
continue;
41
-
42
-
if (cur_dscr != d) {
43
-
fprintf(stderr, "thread %ld kernel DSCR should be %ld "
44
-
"but is %ld\n", thread, d, cur_dscr);
45
-
result[thread] = 1;
46
-
pthread_exit(&result[thread]);
47
-
}
48
-
49
-
if (cur_dscr_usr != d) {
50
-
fprintf(stderr, "thread %ld user DSCR should be %ld "
51
-
"but is %ld\n", thread, d, cur_dscr_usr);
52
-
result[thread] = 1;
53
-
pthread_exit(&result[thread]);
54
-
}
33
+
FAIL_IF_EXIT(sem_post(reader_sem));
55
34
}
56
-
result[thread] = 0;
57
-
pthread_exit(&result[thread]);
35
+
36
+
return NULL;
58
37
}
59
38
60
-
int dscr_default(void)
39
+
int dscr_default_lockstep_test(void)
61
40
{
62
-
pthread_t threads[THREADS];
63
-
unsigned long i, *status[THREADS];
64
-
unsigned long orig_dscr_default;
41
+
pthread_t writer;
42
+
sem_t rw_semaphores[2];
43
+
sem_t *reader_sem = &rw_semaphores[0];
44
+
sem_t *writer_sem = &rw_semaphores[1];
45
+
unsigned long expected_dscr = 0;
65
46
66
47
SKIP_IF(!have_hwcap2(PPC_FEATURE2_DSCR));
67
48
68
-
orig_dscr_default = get_default_dscr();
49
+
FAIL_IF(sem_init(reader_sem, 0, 0));
50
+
FAIL_IF(sem_init(writer_sem, 0, 1)); /* writer starts first */
51
+
FAIL_IF(bind_to_cpu(BIND_CPU_ANY) < 0);
52
+
FAIL_IF(pthread_create(&writer, NULL, dscr_default_lockstep_writer, (void *)rw_semaphores));
69
53
70
-
/* Initial DSCR default */
71
-
dscr = 1;
72
-
set_default_dscr(dscr);
54
+
for (int i = 0; i < COUNT ; i++) {
55
+
FAIL_IF(sem_wait(reader_sem));
73
56
74
-
/* Spawn all testing threads */
75
-
for (i = 0; i < THREADS; i++) {
76
-
if (pthread_create(&threads[i], NULL, do_test, (void *)i)) {
77
-
perror("pthread_create() failed");
78
-
goto fail;
79
-
}
57
+
FAIL_IF(get_dscr() != expected_dscr);
58
+
FAIL_IF(get_dscr_usr() != expected_dscr);
59
+
60
+
expected_dscr = (expected_dscr + 1) % DSCR_MAX;
61
+
62
+
FAIL_IF(sem_post(writer_sem));
80
63
}
81
64
82
-
srand(getpid());
65
+
FAIL_IF(pthread_join(writer, NULL));
66
+
FAIL_IF(sem_destroy(reader_sem));
67
+
FAIL_IF(sem_destroy(writer_sem));
83
68
84
-
/* Keep changing the DSCR default */
85
-
for (i = 0; i < COUNT; i++) {
86
-
double ret = uniform_deviate(rand());
87
-
88
-
if (ret < 0.0001) {
89
-
sequence++;
90
-
wmb();
91
-
92
-
dscr++;
93
-
if (dscr > DSCR_MAX)
94
-
dscr = 0;
95
-
96
-
set_default_dscr(dscr);
97
-
98
-
wmb();
99
-
sequence++;
100
-
}
101
-
}
102
-
103
-
/* Individual testing thread exit status */
104
-
for (i = 0; i < THREADS; i++) {
105
-
if (pthread_join(threads[i], (void **)&(status[i]))) {
106
-
perror("pthread_join() failed");
107
-
goto fail;
108
-
}
109
-
110
-
if (*status[i]) {
111
-
printf("%ldth thread failed to join with %ld status\n",
112
-
i, *status[i]);
113
-
goto fail;
114
-
}
115
-
}
116
-
set_default_dscr(orig_dscr_default);
117
69
return 0;
118
-
fail:
119
-
set_default_dscr(orig_dscr_default);
120
-
return 1;
70
+
}
71
+
72
+
struct random_thread_args {
73
+
pthread_t thread_id;
74
+
unsigned long *expected_system_dscr;
75
+
pthread_rwlock_t *rw_lock;
76
+
pthread_barrier_t *barrier;
77
+
};
78
+
79
+
static void *dscr_default_random_thread(void *in)
80
+
{
81
+
struct random_thread_args *args = (struct random_thread_args *)in;
82
+
unsigned long *expected_dscr_p = args->expected_system_dscr;
83
+
pthread_rwlock_t *rw_lock = args->rw_lock;
84
+
int err;
85
+
86
+
srand(gettid());
87
+
88
+
err = pthread_barrier_wait(args->barrier);
89
+
FAIL_IF_EXIT(err != 0 && err != PTHREAD_BARRIER_SERIAL_THREAD);
90
+
91
+
for (int i = 0; i < COUNT; i++) {
92
+
unsigned long expected_dscr;
93
+
unsigned long current_dscr;
94
+
unsigned long current_dscr_usr;
95
+
96
+
FAIL_IF_EXIT(pthread_rwlock_rdlock(rw_lock));
97
+
expected_dscr = *expected_dscr_p;
98
+
current_dscr = get_dscr();
99
+
current_dscr_usr = get_dscr_usr();
100
+
FAIL_IF_EXIT(pthread_rwlock_unlock(rw_lock));
101
+
102
+
FAIL_IF_EXIT(current_dscr != expected_dscr);
103
+
FAIL_IF_EXIT(current_dscr_usr != expected_dscr);
104
+
105
+
if (rand() % 10 == 0) {
106
+
unsigned long next_dscr;
107
+
108
+
FAIL_IF_EXIT(pthread_rwlock_wrlock(rw_lock));
109
+
next_dscr = (*expected_dscr_p + 1) % DSCR_MAX;
110
+
set_default_dscr(next_dscr);
111
+
*expected_dscr_p = next_dscr;
112
+
FAIL_IF_EXIT(pthread_rwlock_unlock(rw_lock));
113
+
}
114
+
}
115
+
116
+
pthread_exit((void *)0);
117
+
}
118
+
119
+
int dscr_default_random_test(void)
120
+
{
121
+
struct random_thread_args threads[THREADS];
122
+
unsigned long expected_system_dscr = 0;
123
+
pthread_rwlockattr_t rwlock_attr;
124
+
pthread_rwlock_t rw_lock;
125
+
pthread_barrier_t barrier;
126
+
127
+
SKIP_IF(!have_hwcap2(PPC_FEATURE2_DSCR));
128
+
129
+
FAIL_IF(pthread_rwlockattr_setkind_np(&rwlock_attr,
130
+
PTHREAD_RWLOCK_PREFER_WRITER_NONRECURSIVE_NP));
131
+
FAIL_IF(pthread_rwlock_init(&rw_lock, &rwlock_attr));
132
+
FAIL_IF(pthread_barrier_init(&barrier, NULL, THREADS));
133
+
134
+
set_default_dscr(expected_system_dscr);
135
+
136
+
for (int i = 0; i < THREADS; i++) {
137
+
threads[i].expected_system_dscr = &expected_system_dscr;
138
+
threads[i].rw_lock = &rw_lock;
139
+
threads[i].barrier = &barrier;
140
+
141
+
FAIL_IF(pthread_create(&threads[i].thread_id, NULL,
142
+
dscr_default_random_thread, (void *)&threads[i]));
143
+
}
144
+
145
+
for (int i = 0; i < THREADS; i++)
146
+
FAIL_IF(pthread_join(threads[i].thread_id, NULL));
147
+
148
+
FAIL_IF(pthread_barrier_destroy(&barrier));
149
+
FAIL_IF(pthread_rwlock_destroy(&rw_lock));
150
+
151
+
return 0;
121
152
}
122
153
123
154
int main(int argc, char *argv[])
124
155
{
125
-
return test_harness(dscr_default, "dscr_default_test");
156
+
unsigned long orig_dscr_default = 0;
157
+
int err = 0;
158
+
159
+
if (have_hwcap2(PPC_FEATURE2_DSCR))
160
+
orig_dscr_default = get_default_dscr();
161
+
162
+
err |= test_harness(dscr_default_lockstep_test, "dscr_default_lockstep_test");
163
+
err |= test_harness(dscr_default_random_test, "dscr_default_random_test");
164
+
165
+
if (have_hwcap2(PPC_FEATURE2_DSCR))
166
+
set_default_dscr(orig_dscr_default);
167
+
168
+
return err;
126
169
}
+138
-35
tools/testing/selftests/powerpc/dscr/dscr_explicit_test.c
+138
-35
tools/testing/selftests/powerpc/dscr/dscr_explicit_test.c
···
7
7
* privilege state SPR and the problem state SPR for this purpose.
8
8
*
9
9
* When using the privilege state SPR, the instructions such as
10
-
* mfspr or mtspr are priviledged and the kernel emulates them
11
-
* for us. Instructions using problem state SPR can be exuecuted
10
+
* mfspr or mtspr are privileged and the kernel emulates them
11
+
* for us. Instructions using problem state SPR can be executed
12
12
* directly without any emulation if the HW supports them. Else
13
13
* they also get emulated by the kernel.
14
14
*
15
15
* Copyright 2012, Anton Blanchard, IBM Corporation.
16
16
* Copyright 2015, Anshuman Khandual, IBM Corporation.
17
17
*/
18
-
#include "dscr.h"
19
18
20
-
int dscr_explicit(void)
19
+
#define _GNU_SOURCE
20
+
21
+
#include "dscr.h"
22
+
#include "utils.h"
23
+
24
+
#include <pthread.h>
25
+
#include <sched.h>
26
+
#include <semaphore.h>
27
+
28
+
void *dscr_explicit_lockstep_thread(void *args)
21
29
{
22
-
unsigned long i, dscr = 0;
30
+
sem_t *prev = (sem_t *)args;
31
+
sem_t *next = (sem_t *)args + 1;
32
+
unsigned long expected_dscr = 0;
33
+
34
+
set_dscr(expected_dscr);
35
+
srand(gettid());
36
+
37
+
for (int i = 0; i < COUNT; i++) {
38
+
FAIL_IF_EXIT(sem_wait(prev));
39
+
40
+
FAIL_IF_EXIT(expected_dscr != get_dscr());
41
+
FAIL_IF_EXIT(expected_dscr != get_dscr_usr());
42
+
43
+
expected_dscr = (expected_dscr + 1) % DSCR_MAX;
44
+
set_dscr(expected_dscr);
45
+
46
+
FAIL_IF_EXIT(sem_post(next));
47
+
}
48
+
49
+
return NULL;
50
+
}
51
+
52
+
int dscr_explicit_lockstep_test(void)
53
+
{
54
+
pthread_t thread;
55
+
sem_t semaphores[2];
56
+
sem_t *prev = &semaphores[1]; /* reversed prev/next than for the other thread */
57
+
sem_t *next = &semaphores[0];
58
+
unsigned long expected_dscr = 0;
23
59
24
60
SKIP_IF(!have_hwcap2(PPC_FEATURE2_DSCR));
25
61
26
-
srand(getpid());
27
-
set_dscr(dscr);
62
+
srand(gettid());
63
+
set_dscr(expected_dscr);
28
64
29
-
for (i = 0; i < COUNT; i++) {
30
-
unsigned long cur_dscr, cur_dscr_usr;
31
-
double ret = uniform_deviate(rand());
65
+
FAIL_IF(sem_init(prev, 0, 0));
66
+
FAIL_IF(sem_init(next, 0, 1)); /* other thread starts first */
67
+
FAIL_IF(bind_to_cpu(BIND_CPU_ANY) < 0);
68
+
FAIL_IF(pthread_create(&thread, NULL, dscr_explicit_lockstep_thread, (void *)semaphores));
32
69
33
-
if (ret < 0.001) {
34
-
dscr++;
35
-
if (dscr > DSCR_MAX)
36
-
dscr = 0;
70
+
for (int i = 0; i < COUNT; i++) {
71
+
FAIL_IF(sem_wait(prev));
37
72
38
-
set_dscr(dscr);
73
+
FAIL_IF(expected_dscr != get_dscr());
74
+
FAIL_IF(expected_dscr != get_dscr_usr());
75
+
76
+
expected_dscr = (expected_dscr - 1) % DSCR_MAX;
77
+
set_dscr(expected_dscr);
78
+
79
+
FAIL_IF(sem_post(next));
80
+
}
81
+
82
+
FAIL_IF(pthread_join(thread, NULL));
83
+
FAIL_IF(sem_destroy(prev));
84
+
FAIL_IF(sem_destroy(next));
85
+
86
+
return 0;
87
+
}
88
+
89
+
struct random_thread_args {
90
+
pthread_t thread_id;
91
+
bool do_yields;
92
+
pthread_barrier_t *barrier;
93
+
};
94
+
95
+
void *dscr_explicit_random_thread(void *in)
96
+
{
97
+
struct random_thread_args *args = (struct random_thread_args *)in;
98
+
unsigned long expected_dscr = 0;
99
+
int err;
100
+
101
+
srand(gettid());
102
+
103
+
err = pthread_barrier_wait(args->barrier);
104
+
FAIL_IF_EXIT(err != 0 && err != PTHREAD_BARRIER_SERIAL_THREAD);
105
+
106
+
for (int i = 0; i < COUNT; i++) {
107
+
expected_dscr = rand() % DSCR_MAX;
108
+
set_dscr(expected_dscr);
109
+
110
+
for (int j = rand() % 5; j > 0; --j) {
111
+
FAIL_IF_EXIT(get_dscr() != expected_dscr);
112
+
FAIL_IF_EXIT(get_dscr_usr() != expected_dscr);
113
+
114
+
if (args->do_yields && rand() % 2)
115
+
sched_yield();
39
116
}
40
117
41
-
cur_dscr = get_dscr();
42
-
if (cur_dscr != dscr) {
43
-
fprintf(stderr, "Kernel DSCR should be %ld but "
44
-
"is %ld\n", dscr, cur_dscr);
45
-
return 1;
46
-
}
118
+
expected_dscr = rand() % DSCR_MAX;
119
+
set_dscr_usr(expected_dscr);
47
120
48
-
ret = uniform_deviate(rand());
49
-
if (ret < 0.001) {
50
-
dscr++;
51
-
if (dscr > DSCR_MAX)
52
-
dscr = 0;
121
+
for (int j = rand() % 5; j > 0; --j) {
122
+
FAIL_IF_EXIT(get_dscr() != expected_dscr);
123
+
FAIL_IF_EXIT(get_dscr_usr() != expected_dscr);
53
124
54
-
set_dscr_usr(dscr);
55
-
}
56
-
57
-
cur_dscr_usr = get_dscr_usr();
58
-
if (cur_dscr_usr != dscr) {
59
-
fprintf(stderr, "User DSCR should be %ld but "
60
-
"is %ld\n", dscr, cur_dscr_usr);
61
-
return 1;
125
+
if (args->do_yields && rand() % 2)
126
+
sched_yield();
62
127
}
63
128
}
129
+
130
+
return NULL;
131
+
}
132
+
133
+
int dscr_explicit_random_test(void)
134
+
{
135
+
struct random_thread_args threads[THREADS];
136
+
pthread_barrier_t barrier;
137
+
138
+
SKIP_IF(!have_hwcap2(PPC_FEATURE2_DSCR));
139
+
140
+
FAIL_IF(pthread_barrier_init(&barrier, NULL, THREADS));
141
+
142
+
for (int i = 0; i < THREADS; i++) {
143
+
threads[i].do_yields = i % 2 == 0;
144
+
threads[i].barrier = &barrier;
145
+
146
+
FAIL_IF(pthread_create(&threads[i].thread_id, NULL,
147
+
dscr_explicit_random_thread, (void *)&threads[i]));
148
+
}
149
+
150
+
for (int i = 0; i < THREADS; i++)
151
+
FAIL_IF(pthread_join(threads[i].thread_id, NULL));
152
+
153
+
FAIL_IF(pthread_barrier_destroy(&barrier));
154
+
64
155
return 0;
65
156
}
66
157
67
158
int main(int argc, char *argv[])
68
159
{
69
-
return test_harness(dscr_explicit, "dscr_explicit_test");
160
+
unsigned long orig_dscr_default = 0;
161
+
int err = 0;
162
+
163
+
if (have_hwcap2(PPC_FEATURE2_DSCR))
164
+
orig_dscr_default = get_default_dscr();
165
+
166
+
err |= test_harness(dscr_explicit_lockstep_test, "dscr_explicit_lockstep_test");
167
+
err |= test_harness(dscr_explicit_random_test, "dscr_explicit_random_test");
168
+
169
+
if (have_hwcap2(PPC_FEATURE2_DSCR))
170
+
set_default_dscr(orig_dscr_default);
171
+
172
+
return err;
70
173
}
+2
-2
tools/testing/selftests/powerpc/dscr/dscr_inherit_test.c
+2
-2
tools/testing/selftests/powerpc/dscr/dscr_inherit_test.c
···
7
7
* value using mfspr.
8
8
*
9
9
* When using the privilege state SPR, the instructions such as
10
-
* mfspr or mtspr are priviledged and the kernel emulates them
11
-
* for us. Instructions using problem state SPR can be exuecuted
10
+
* mfspr or mtspr are privileged and the kernel emulates them
11
+
* for us. Instructions using problem state SPR can be executed
12
12
* directly without any emulation if the HW supports them. Else
13
13
* they also get emulated by the kernel.
14
14
*
+4
-7
tools/testing/selftests/powerpc/dscr/dscr_sysfs_test.c
+4
-7
tools/testing/selftests/powerpc/dscr/dscr_sysfs_test.c
···
67
67
int dscr_sysfs(void)
68
68
{
69
69
unsigned long orig_dscr_default;
70
-
int i, j;
71
70
72
71
SKIP_IF(!have_hwcap2(PPC_FEATURE2_DSCR));
73
72
74
73
orig_dscr_default = get_default_dscr();
75
-
for (i = 0; i < COUNT; i++) {
76
-
for (j = 0; j < DSCR_MAX; j++) {
77
-
set_default_dscr(j);
78
-
if (check_all_cpu_dscr_defaults(j))
79
-
goto fail;
80
-
}
74
+
for (int i = 0; i < DSCR_MAX; i++) {
75
+
set_default_dscr(i);
76
+
if (check_all_cpu_dscr_defaults(i))
77
+
goto fail;
81
78
}
82
79
set_default_dscr(orig_dscr_default);
83
80
return 0;
+2
-2
tools/testing/selftests/powerpc/dscr/dscr_user_test.c
+2
-2
tools/testing/selftests/powerpc/dscr/dscr_user_test.c
···
8
8
* numbers.
9
9
*
10
10
* When using the privilege state SPR, the instructions such as
11
-
* mfspr or mtspr are priviledged and the kernel emulates them
12
-
* for us. Instructions using problem state SPR can be exuecuted
11
+
* mfspr or mtspr are privileged and the kernel emulates them
12
+
* for us. Instructions using problem state SPR can be executed
13
13
* directly without any emulation if the HW supports them. Else
14
14
* they also get emulated by the kernel.
15
15
*
-1
tools/testing/selftests/powerpc/dscr/settings
-1
tools/testing/selftests/powerpc/dscr/settings
···
1
-
timeout=0
+3
tools/testing/selftests/powerpc/include/utils.h
+3
tools/testing/selftests/powerpc/include/utils.h
···
31
31
void *find_auxv_entry(int type, char *auxv);
32
32
void *get_auxv_entry(int type);
33
33
34
+
#define BIND_CPU_ANY (-1)
35
+
34
36
int pick_online_cpu(void);
37
+
int bind_to_cpu(int cpu);
35
38
36
39
int parse_intmax(const char *buffer, size_t count, intmax_t *result, int base);
37
40
int parse_uintmax(const char *buffer, size_t count, uintmax_t *result, int base);
+1
tools/testing/selftests/powerpc/math/vmx_signal.c
+1
tools/testing/selftests/powerpc/math/vmx_signal.c
+1
-1
tools/testing/selftests/powerpc/mm/Makefile
+1
-1
tools/testing/selftests/powerpc/mm/Makefile
+17
-14
tools/testing/selftests/powerpc/pmu/Makefile
+17
-14
tools/testing/selftests/powerpc/pmu/Makefile
···
25
25
DEFAULT_RUN_TESTS := $(RUN_TESTS)
26
26
override define RUN_TESTS
27
27
$(DEFAULT_RUN_TESTS)
28
-
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
29
-
TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
30
-
TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
28
+
+TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
29
+
+TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
30
+
+TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET run_tests
31
31
endef
32
32
33
33
DEFAULT_EMIT_TESTS := $(EMIT_TESTS)
34
34
override define EMIT_TESTS
35
35
$(DEFAULT_EMIT_TESTS)
36
-
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
37
-
TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
38
-
TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
36
+
+TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
37
+
+TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
38
+
+TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -s -C $$TARGET emit_tests
39
39
endef
40
40
41
41
DEFAULT_INSTALL_RULE := $(INSTALL_RULE)
42
42
override define INSTALL_RULE
43
43
$(DEFAULT_INSTALL_RULE)
44
-
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
45
-
TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
46
-
TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
44
+
+TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
45
+
+TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
46
+
+TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET install
47
47
endef
48
48
49
-
clean:
49
+
DEFAULT_CLEAN := $(CLEAN)
50
+
override define CLEAN
51
+
$(DEFAULT_CLEAN)
50
52
$(RM) $(TEST_GEN_PROGS) $(OUTPUT)/loop.o
51
-
TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
52
-
TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
53
-
TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
53
+
+TARGET=ebb; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
54
+
+TARGET=sampling_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
55
+
+TARGET=event_code_tests; BUILD_TARGET=$$OUTPUT/$$TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -C $$TARGET clean
56
+
endef
54
57
55
58
ebb:
56
59
TARGET=$@; BUILD_TARGET=$$OUTPUT/$$TARGET; mkdir -p $$BUILD_TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -k -C $$TARGET all
···
64
61
event_code_tests:
65
62
TARGET=$@; BUILD_TARGET=$$OUTPUT/$$TARGET; mkdir -p $$BUILD_TARGET; $(MAKE) OUTPUT=$$BUILD_TARGET -k -C $$TARGET all
66
63
67
-
.PHONY: all run_tests clean ebb sampling_tests event_code_tests
64
+
.PHONY: all run_tests ebb sampling_tests event_code_tests
+1
-2
tools/testing/selftests/powerpc/pmu/ebb/cpu_event_pinned_vs_ebb_test.c
+1
-2
tools/testing/selftests/powerpc/pmu/ebb/cpu_event_pinned_vs_ebb_test.c
+1
-2
tools/testing/selftests/powerpc/pmu/ebb/cpu_event_vs_ebb_test.c
+1
-2
tools/testing/selftests/powerpc/pmu/ebb/cpu_event_vs_ebb_test.c
+1
-2
tools/testing/selftests/powerpc/pmu/ebb/ebb_vs_cpu_event_test.c
+1
-2
tools/testing/selftests/powerpc/pmu/ebb/ebb_vs_cpu_event_test.c
+2
-4
tools/testing/selftests/powerpc/pmu/ebb/multi_ebb_procs_test.c
+2
-4
tools/testing/selftests/powerpc/pmu/ebb/multi_ebb_procs_test.c
···
75
75
int multi_ebb_procs(void)
76
76
{
77
77
pid_t pids[NR_CHILDREN];
78
-
int cpu, rc, i;
78
+
int rc, i;
79
79
80
80
SKIP_IF(!ebb_is_supported());
81
81
82
-
cpu = pick_online_cpu();
83
-
FAIL_IF(cpu < 0);
84
-
FAIL_IF(bind_to_cpu(cpu));
82
+
FAIL_IF(bind_to_cpu(BIND_CPU_ANY) < 0);
85
83
86
84
for (i = 0; i < NR_CHILDREN; i++) {
87
85
pids[i] = fork();
+2
-17
tools/testing/selftests/powerpc/pmu/lib.c
+2
-17
tools/testing/selftests/powerpc/pmu/lib.c
···
14
14
#include "utils.h"
15
15
#include "lib.h"
16
16
17
-
18
-
int bind_to_cpu(int cpu)
19
-
{
20
-
cpu_set_t mask;
21
-
22
-
printf("Binding to cpu %d\n", cpu);
23
-
24
-
CPU_ZERO(&mask);
25
-
CPU_SET(cpu, &mask);
26
-
27
-
return sched_setaffinity(0, sizeof(mask), &mask);
28
-
}
29
-
30
17
#define PARENT_TOKEN 0xAA
31
18
#define CHILD_TOKEN 0x55
32
19
···
103
116
pid_t eat_cpu(int (test_function)(void))
104
117
{
105
118
union pipe read_pipe, write_pipe;
106
-
int cpu, rc;
119
+
int rc;
107
120
pid_t pid;
108
121
109
-
cpu = pick_online_cpu();
110
-
FAIL_IF(cpu < 0);
111
-
FAIL_IF(bind_to_cpu(cpu));
122
+
FAIL_IF(bind_to_cpu(BIND_CPU_ANY) < 0);
112
123
113
124
if (pipe(read_pipe.fds) == -1)
114
125
return -1;
-1
tools/testing/selftests/powerpc/pmu/lib.h
-1
tools/testing/selftests/powerpc/pmu/lib.h
+2
-2
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c
+2
-2
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c
···
63
63
get_mmcra_thd_stop(get_reg_value(intr_regs, "MMCRA"), 4));
64
64
FAIL_IF(EV_CODE_EXTRACT(event.attr.config, marked) !=
65
65
get_mmcra_marked(get_reg_value(intr_regs, "MMCRA"), 4));
66
-
FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample >> 2) !=
66
+
FAIL_IF((EV_CODE_EXTRACT(event.attr.config, sample) >> 2) !=
67
67
get_mmcra_rand_samp_elig(get_reg_value(intr_regs, "MMCRA"), 4));
68
-
FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sample & 0x3) !=
68
+
FAIL_IF((EV_CODE_EXTRACT(event.attr.config, sample) & 0x3) !=
69
69
get_mmcra_sample_mode(get_reg_value(intr_regs, "MMCRA"), 4));
70
70
FAIL_IF(EV_CODE_EXTRACT(event.attr.config, sm) !=
71
71
get_mmcra_sm(get_reg_value(intr_regs, "MMCRA"), 4));
+1
tools/testing/selftests/powerpc/stringloops/asm/ppc_asm.h
+1
tools/testing/selftests/powerpc/stringloops/asm/ppc_asm.h
+23
tools/testing/selftests/powerpc/utils.c
+23
tools/testing/selftests/powerpc/utils.c
···
452
452
return cpu;
453
453
}
454
454
455
+
int bind_to_cpu(int cpu)
456
+
{
457
+
cpu_set_t mask;
458
+
int err;
459
+
460
+
if (cpu == BIND_CPU_ANY) {
461
+
cpu = pick_online_cpu();
462
+
if (cpu < 0)
463
+
return cpu;
464
+
}
465
+
466
+
printf("Binding to cpu %d\n", cpu);
467
+
468
+
CPU_ZERO(&mask);
469
+
CPU_SET(cpu, &mask);
470
+
471
+
err = sched_setaffinity(0, sizeof(mask), &mask);
472
+
if (err)
473
+
return err;
474
+
475
+
return cpu;
476
+
}
477
+
455
478
bool is_ppc64le(void)
456
479
{
457
480
struct utsname uts;