Linux kernel mirror (for testing)
git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
kernel
os
linux
Merge tag 'usb-4.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB/PHY fixes from Greg KH:
"Here are some USB and PHY driver fixes for 4.8-rc5
Nothing major, lots of little fixes for reported bugs, and a build fix
for a missing .h file that the phy drivers needed. All of these have
been in linux-next for a while with no reported issues"
* tag 'usb-4.8-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (24 commits)
usb: musb: Fix locking errors for host only mode
usb: dwc3: gadget: always decrement by 1
usb: dwc3: debug: fix ep name on trace output
usb: gadget: udc: core: don't starve DMA resources
USB: serial: option: add WeTelecom 0x6802 and 0x6803 products
USB: avoid left shift by -1
USB: fix typo in wMaxPacketSize validation
usb: gadget: Add the gserial port checking in gs_start_tx()
usb: dwc3: gadget: don't rely on jiffies while holding spinlock
usb: gadget: fsl_qe_udc: signedness bug in qe_get_frame()
usb: gadget: function: f_rndis: socket buffer may be NULL
usb: gadget: function: f_eem: socket buffer may be NULL
usb: renesas_usbhs: gadget: fix return value check in usbhs_mod_gadget_probe()
usb: dwc2: Add reset control to dwc2
usb: dwc3: core: allow device to runtime_suspend several times
usb: dwc3: pci: runtime_resume child device
USB: serial: option: add WeTelecom WM-D200
usb: chipidea: udc: don't touch DP when controller is in host mode
USB: serial: mos7840: fix non-atomic allocation in write path
USB: serial: mos7720: fix non-atomic allocation in write path
...
+294
-57
+1
-1
drivers/phy/phy-brcm-sata.c
+1
-1
drivers/phy/phy-brcm-sata.c
+46
-22
drivers/phy/phy-sun4i-usb.c
+46
-22
drivers/phy/phy-sun4i-usb.c
···
40
40
#include <linux/power_supply.h>
41
41
#include <linux/regulator/consumer.h>
42
42
#include <linux/reset.h>
43
+
#include <linux/usb/of.h>
43
44
#include <linux/workqueue.h>
44
45
45
46
#define REG_ISCR 0x00
···
111
110
struct sun4i_usb_phy_data {
112
111
void __iomem *base;
113
112
const struct sun4i_usb_phy_cfg *cfg;
113
+
enum usb_dr_mode dr_mode;
114
114
struct mutex mutex;
115
115
struct sun4i_usb_phy {
116
116
struct phy *phy;
···
122
120
bool regulator_on;
123
121
int index;
124
122
} phys[MAX_PHYS];
123
+
int first_phy;
125
124
/* phy0 / otg related variables */
126
125
struct extcon_dev *extcon;
127
126
bool phy0_init;
···
288
285
sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_DPDM_PULLUP_EN);
289
286
sun4i_usb_phy0_update_iscr(_phy, 0, ISCR_ID_PULLUP_EN);
290
287
291
-
if (data->id_det_gpio) {
292
-
/* OTG mode, force ISCR and cable state updates */
293
-
data->id_det = -1;
294
-
data->vbus_det = -1;
295
-
queue_delayed_work(system_wq, &data->detect, 0);
296
-
} else {
297
-
/* Host only mode */
298
-
sun4i_usb_phy0_set_id_detect(_phy, 0);
299
-
sun4i_usb_phy0_set_vbus_detect(_phy, 1);
300
-
}
288
+
/* Force ISCR and cable state updates */
289
+
data->id_det = -1;
290
+
data->vbus_det = -1;
291
+
queue_delayed_work(system_wq, &data->detect, 0);
301
292
}
302
293
303
294
return 0;
···
314
317
clk_disable_unprepare(phy->clk);
315
318
316
319
return 0;
320
+
}
321
+
322
+
static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
323
+
{
324
+
switch (data->dr_mode) {
325
+
case USB_DR_MODE_OTG:
326
+
return gpiod_get_value_cansleep(data->id_det_gpio);
327
+
case USB_DR_MODE_HOST:
328
+
return 0;
329
+
case USB_DR_MODE_PERIPHERAL:
330
+
default:
331
+
return 1;
332
+
}
317
333
}
318
334
319
335
static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
···
442
432
struct phy *phy0 = data->phys[0].phy;
443
433
int id_det, vbus_det, id_notify = 0, vbus_notify = 0;
444
434
445
-
id_det = gpiod_get_value_cansleep(data->id_det_gpio);
435
+
if (phy0 == NULL)
436
+
return;
437
+
438
+
id_det = sun4i_usb_phy0_get_id_det(data);
446
439
vbus_det = sun4i_usb_phy0_get_vbus_det(data);
447
440
448
441
mutex_lock(&phy0->mutex);
···
461
448
* without vbus detection report vbus low for long enough for
462
449
* the musb-ip to end the current device session.
463
450
*/
464
-
if (!sun4i_usb_phy0_have_vbus_det(data) && id_det == 0) {
451
+
if (data->dr_mode == USB_DR_MODE_OTG &&
452
+
!sun4i_usb_phy0_have_vbus_det(data) && id_det == 0) {
465
453
sun4i_usb_phy0_set_vbus_detect(phy0, 0);
466
454
msleep(200);
467
455
sun4i_usb_phy0_set_vbus_detect(phy0, 1);
···
488
474
* without vbus detection report vbus low for long enough to
489
475
* the musb-ip to end the current host session.
490
476
*/
491
-
if (!sun4i_usb_phy0_have_vbus_det(data) && id_det == 1) {
477
+
if (data->dr_mode == USB_DR_MODE_OTG &&
478
+
!sun4i_usb_phy0_have_vbus_det(data) && id_det == 1) {
492
479
mutex_lock(&phy0->mutex);
493
480
sun4i_usb_phy0_set_vbus_detect(phy0, 0);
494
481
msleep(1000);
···
534
519
{
535
520
struct sun4i_usb_phy_data *data = dev_get_drvdata(dev);
536
521
537
-
if (args->args[0] >= data->cfg->num_phys)
522
+
if (args->args[0] < data->first_phy ||
523
+
args->args[0] >= data->cfg->num_phys)
538
524
return ERR_PTR(-ENODEV);
539
525
540
526
return data->phys[args->args[0]].phy;
···
609
593
return -EPROBE_DEFER;
610
594
}
611
595
612
-
/* vbus_det without id_det makes no sense, and is not supported */
613
-
if (sun4i_usb_phy0_have_vbus_det(data) && !data->id_det_gpio) {
614
-
dev_err(dev, "usb0_id_det missing or invalid\n");
615
-
return -ENODEV;
616
-
}
617
-
618
-
if (data->id_det_gpio) {
596
+
data->dr_mode = of_usb_get_dr_mode_by_phy(np, 0);
597
+
switch (data->dr_mode) {
598
+
case USB_DR_MODE_OTG:
599
+
/* otg without id_det makes no sense, and is not supported */
600
+
if (!data->id_det_gpio) {
601
+
dev_err(dev, "usb0_id_det missing or invalid\n");
602
+
return -ENODEV;
603
+
}
604
+
/* fall through */
605
+
case USB_DR_MODE_HOST:
606
+
case USB_DR_MODE_PERIPHERAL:
619
607
data->extcon = devm_extcon_dev_allocate(dev,
620
608
sun4i_usb_phy0_cable);
621
609
if (IS_ERR(data->extcon))
···
630
610
dev_err(dev, "failed to register extcon: %d\n", ret);
631
611
return ret;
632
612
}
613
+
break;
614
+
default:
615
+
dev_info(dev, "dr_mode unknown, not registering usb phy0\n");
616
+
data->first_phy = 1;
633
617
}
634
618
635
-
for (i = 0; i < data->cfg->num_phys; i++) {
619
+
for (i = data->first_phy; i < data->cfg->num_phys; i++) {
636
620
struct sun4i_usb_phy *phy = data->phys + i;
637
621
char name[16];
638
622
+2
-2
drivers/phy/phy-sun9i-usb.c
+2
-2
drivers/phy/phy-sun9i-usb.c
···
141
141
}
142
142
143
143
phy->hsic_clk = devm_clk_get(dev, "hsic_12M");
144
-
if (IS_ERR(phy->clk)) {
144
+
if (IS_ERR(phy->hsic_clk)) {
145
145
dev_err(dev, "failed to get hsic_12M clock\n");
146
-
return PTR_ERR(phy->clk);
146
+
return PTR_ERR(phy->hsic_clk);
147
147
}
148
148
149
149
phy->reset = devm_reset_control_get(dev, "hsic");
+5
-2
drivers/usb/chipidea/udc.c
+5
-2
drivers/usb/chipidea/udc.c
···
1596
1596
{
1597
1597
struct ci_hdrc *ci = container_of(_gadget, struct ci_hdrc, gadget);
1598
1598
1599
-
/* Data+ pullup controlled by OTG state machine in OTG fsm mode */
1600
-
if (ci_otg_is_fsm_mode(ci))
1599
+
/*
1600
+
* Data+ pullup controlled by OTG state machine in OTG fsm mode;
1601
+
* and don't touch Data+ in host mode for dual role config.
1602
+
*/
1603
+
if (ci_otg_is_fsm_mode(ci) || ci->role == CI_ROLE_HOST)
1601
1604
return 0;
1602
1605
1603
1606
pm_runtime_get_sync(&ci->gadget.dev);
+1
-1
drivers/usb/core/config.c
+1
-1
drivers/usb/core/config.c
···
187
187
[USB_ENDPOINT_XFER_CONTROL] = 64,
188
188
[USB_ENDPOINT_XFER_ISOC] = 1024,
189
189
[USB_ENDPOINT_XFER_BULK] = 512,
190
-
[USB_ENDPOINT_XFER_INT] = 1023,
190
+
[USB_ENDPOINT_XFER_INT] = 1024,
191
191
};
192
192
static const unsigned short super_speed_maxpacket_maxes[4] = {
193
193
[USB_ENDPOINT_XFER_CONTROL] = 512,
+11
-5
drivers/usb/core/devio.c
+11
-5
drivers/usb/core/devio.c
···
1709
1709
as->urb->start_frame = uurb->start_frame;
1710
1710
as->urb->number_of_packets = number_of_packets;
1711
1711
as->urb->stream_id = stream_id;
1712
-
if (uurb->type == USBDEVFS_URB_TYPE_ISO ||
1713
-
ps->dev->speed == USB_SPEED_HIGH)
1714
-
as->urb->interval = 1 << min(15, ep->desc.bInterval - 1);
1715
-
else
1716
-
as->urb->interval = ep->desc.bInterval;
1712
+
1713
+
if (ep->desc.bInterval) {
1714
+
if (uurb->type == USBDEVFS_URB_TYPE_ISO ||
1715
+
ps->dev->speed == USB_SPEED_HIGH ||
1716
+
ps->dev->speed >= USB_SPEED_SUPER)
1717
+
as->urb->interval = 1 <<
1718
+
min(15, ep->desc.bInterval - 1);
1719
+
else
1720
+
as->urb->interval = ep->desc.bInterval;
1721
+
}
1722
+
1717
1723
as->urb->context = as;
1718
1724
as->urb->complete = async_completed;
1719
1725
for (totlen = u = 0; u < number_of_packets; u++) {
+1
drivers/usb/dwc2/core.h
+1
drivers/usb/dwc2/core.h
+22
drivers/usb/dwc2/platform.c
+22
drivers/usb/dwc2/platform.c
···
45
45
#include <linux/platform_device.h>
46
46
#include <linux/phy/phy.h>
47
47
#include <linux/platform_data/s3c-hsotg.h>
48
+
#include <linux/reset.h>
48
49
49
50
#include <linux/usb/of.h>
50
51
···
338
337
{
339
338
int i, ret;
340
339
340
+
hsotg->reset = devm_reset_control_get_optional(hsotg->dev, "dwc2");
341
+
if (IS_ERR(hsotg->reset)) {
342
+
ret = PTR_ERR(hsotg->reset);
343
+
switch (ret) {
344
+
case -ENOENT:
345
+
case -ENOTSUPP:
346
+
hsotg->reset = NULL;
347
+
break;
348
+
default:
349
+
dev_err(hsotg->dev, "error getting reset control %d\n",
350
+
ret);
351
+
return ret;
352
+
}
353
+
}
354
+
355
+
if (hsotg->reset)
356
+
reset_control_deassert(hsotg->reset);
357
+
341
358
/* Set default UTMI width */
342
359
hsotg->phyif = GUSBCFG_PHYIF16;
343
360
···
452
433
453
434
if (hsotg->ll_hw_enabled)
454
435
dwc2_lowlevel_hw_disable(hsotg);
436
+
437
+
if (hsotg->reset)
438
+
reset_control_assert(hsotg->reset);
455
439
456
440
return 0;
457
441
}
+1
drivers/usb/dwc3/core.c
+1
drivers/usb/dwc3/core.c
+1
-1
drivers/usb/dwc3/debug.h
+1
-1
drivers/usb/dwc3/debug.h
+8
-1
drivers/usb/dwc3/dwc3-pci.c
+8
-1
drivers/usb/dwc3/dwc3-pci.c
···
243
243
return -EBUSY;
244
244
}
245
245
246
+
static int dwc3_pci_runtime_resume(struct device *dev)
247
+
{
248
+
struct platform_device *dwc3 = dev_get_drvdata(dev);
249
+
250
+
return pm_runtime_get(&dwc3->dev);
251
+
}
252
+
246
253
static int dwc3_pci_pm_dummy(struct device *dev)
247
254
{
248
255
/*
···
266
259
267
260
static struct dev_pm_ops dwc3_pci_dev_pm_ops = {
268
261
SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_pm_dummy, dwc3_pci_pm_dummy)
269
-
SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_pm_dummy,
262
+
SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
270
263
NULL)
271
264
};
272
265
+4
-7
drivers/usb/dwc3/gadget.c
+4
-7
drivers/usb/dwc3/gadget.c
···
884
884
return DWC3_TRB_NUM - 1;
885
885
}
886
886
887
-
trbs_left = dep->trb_dequeue - dep->trb_enqueue;
887
+
trbs_left = dep->trb_dequeue - dep->trb_enqueue - 1;
888
888
trbs_left &= (DWC3_TRB_NUM - 1);
889
-
890
-
if (dep->trb_dequeue < dep->trb_enqueue)
891
-
trbs_left--;
892
889
893
890
return trbs_left;
894
891
}
···
1430
1433
1431
1434
static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1432
1435
{
1433
-
unsigned long timeout;
1436
+
int retries;
1434
1437
1435
1438
int ret;
1436
1439
u32 reg;
···
1481
1484
}
1482
1485
1483
1486
/* poll until Link State changes to ON */
1484
-
timeout = jiffies + msecs_to_jiffies(100);
1487
+
retries = 20000;
1485
1488
1486
-
while (!time_after(jiffies, timeout)) {
1489
+
while (retries--) {
1487
1490
reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1488
1491
1489
1492
/* in HS, means ON */
+7
-3
drivers/usb/gadget/function/f_eem.c
+7
-3
drivers/usb/gadget/function/f_eem.c
···
341
341
{
342
342
struct sk_buff *skb2 = NULL;
343
343
struct usb_ep *in = port->in_ep;
344
-
int padlen = 0;
344
+
int headroom, tailroom, padlen = 0;
345
345
u16 len = skb->len;
346
346
347
-
int headroom = skb_headroom(skb);
348
-
int tailroom = skb_tailroom(skb);
347
+
if (!skb)
348
+
return NULL;
349
+
350
+
len = skb->len;
351
+
headroom = skb_headroom(skb);
352
+
tailroom = skb_tailroom(skb);
349
353
350
354
/* When (len + EEM_HLEN + ETH_FCS_LEN) % in->maxpacket) is 0,
351
355
* stick two bytes of zero-length EEM packet on the end.
+3
drivers/usb/gadget/function/f_rndis.c
+3
drivers/usb/gadget/function/f_rndis.c
+6
-1
drivers/usb/gadget/function/u_serial.c
+6
-1
drivers/usb/gadget/function/u_serial.c
···
375
375
*/
376
376
{
377
377
struct list_head *pool = &port->write_pool;
378
-
struct usb_ep *in = port->port_usb->in;
378
+
struct usb_ep *in;
379
379
int status = 0;
380
380
bool do_tty_wake = false;
381
+
382
+
if (!port->port_usb)
383
+
return status;
384
+
385
+
in = port->port_usb->in;
381
386
382
387
while (!port->write_busy && !list_empty(pool)) {
383
388
struct usb_request *req;
+1
-1
drivers/usb/gadget/udc/core.c
+1
-1
drivers/usb/gadget/udc/core.c
+2
-5
drivers/usb/gadget/udc/fsl_qe_udc.c
+2
-5
drivers/usb/gadget/udc/fsl_qe_udc.c
···
1878
1878
1879
1879
tmp = in_be16(&udc->usb_param->frame_n);
1880
1880
if (tmp & 0x8000)
1881
-
tmp = tmp & 0x07ff;
1882
-
else
1883
-
tmp = -EINVAL;
1884
-
1885
-
return (int)tmp;
1881
+
return tmp & 0x07ff;
1882
+
return -EINVAL;
1886
1883
}
1887
1884
1888
1885
static int fsl_qe_start(struct usb_gadget *gadget,
+6
-1
drivers/usb/musb/musb_virthub.c
+6
-1
drivers/usb/musb/musb_virthub.c
···
290
290
u32 temp;
291
291
int retval = 0;
292
292
unsigned long flags;
293
+
bool start_musb = false;
293
294
294
295
spin_lock_irqsave(&musb->lock, flags);
295
296
···
391
390
* logic relating to VBUS power-up.
392
391
*/
393
392
if (!hcd->self.is_b_host && musb_has_gadget(musb))
394
-
musb_start(musb);
393
+
start_musb = true;
395
394
break;
396
395
case USB_PORT_FEAT_RESET:
397
396
musb_port_reset(musb, true);
···
452
451
retval = -EPIPE;
453
452
}
454
453
spin_unlock_irqrestore(&musb->lock, flags);
454
+
455
+
if (start_musb)
456
+
musb_start(musb);
457
+
455
458
return retval;
456
459
}
+1
-1
drivers/usb/renesas_usbhs/mod_gadget.c
+1
-1
drivers/usb/renesas_usbhs/mod_gadget.c
+1
-1
drivers/usb/serial/mos7720.c
+1
-1
drivers/usb/serial/mos7720.c
+2
-2
drivers/usb/serial/mos7840.c
+2
-2
drivers/usb/serial/mos7840.c
···
1340
1340
}
1341
1341
1342
1342
if (urb->transfer_buffer == NULL) {
1343
-
urb->transfer_buffer =
1344
-
kmalloc(URB_TRANSFER_BUFFER_SIZE, GFP_KERNEL);
1343
+
urb->transfer_buffer = kmalloc(URB_TRANSFER_BUFFER_SIZE,
1344
+
GFP_ATOMIC);
1345
1345
if (!urb->transfer_buffer)
1346
1346
goto exit;
1347
1347
}
+9
drivers/usb/serial/option.c
+9
drivers/usb/serial/option.c
···
525
525
#define VIATELECOM_VENDOR_ID 0x15eb
526
526
#define VIATELECOM_PRODUCT_CDS7 0x0001
527
527
528
+
/* WeTelecom products */
529
+
#define WETELECOM_VENDOR_ID 0x22de
530
+
#define WETELECOM_PRODUCT_WMD200 0x6801
531
+
#define WETELECOM_PRODUCT_6802 0x6802
532
+
#define WETELECOM_PRODUCT_WMD300 0x6803
533
+
528
534
struct option_blacklist_info {
529
535
/* bitmask of interface numbers blacklisted for send_setup */
530
536
const unsigned long sendsetup;
···
1997
1991
{ USB_DEVICE_INTERFACE_CLASS(0x2020, 0x4000, 0xff) }, /* OLICARD300 - MT6225 */
1998
1992
{ USB_DEVICE(INOVIA_VENDOR_ID, INOVIA_SEW858) },
1999
1993
{ USB_DEVICE(VIATELECOM_VENDOR_ID, VIATELECOM_PRODUCT_CDS7) },
1994
+
{ USB_DEVICE_AND_INTERFACE_INFO(WETELECOM_VENDOR_ID, WETELECOM_PRODUCT_WMD200, 0xff, 0xff, 0xff) },
1995
+
{ USB_DEVICE_AND_INTERFACE_INFO(WETELECOM_VENDOR_ID, WETELECOM_PRODUCT_6802, 0xff, 0xff, 0xff) },
1996
+
{ USB_DEVICE_AND_INTERFACE_INFO(WETELECOM_VENDOR_ID, WETELECOM_PRODUCT_WMD300, 0xff, 0xff, 0xff) },
2000
1997
{ } /* Terminating entry */
2001
1998
};
2002
1999
MODULE_DEVICE_TABLE(usb, option_ids);
+153
include/linux/mfd/da8xx-cfgchip.h
+153
include/linux/mfd/da8xx-cfgchip.h
···
1
+
/*
2
+
* TI DaVinci DA8xx CHIPCFGx registers for syscon consumers.
3
+
*
4
+
* Copyright (C) 2016 David Lechner <david@lechnology.com>
5
+
*
6
+
* This program is free software; you can redistribute it and/or modify
7
+
* it under the terms of the GNU General Public License as published by
8
+
* the Free Software Foundation; either version 2 of the License, or
9
+
* (at your option) any later version.
10
+
*
11
+
* This program is distributed in the hope that it will be useful,
12
+
* but WITHOUT ANY WARRANTY; without even the implied warranty of
13
+
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14
+
* GNU General Public License for more details.
15
+
*/
16
+
17
+
#ifndef __LINUX_MFD_DA8XX_CFGCHIP_H
18
+
#define __LINUX_MFD_DA8XX_CFGCHIP_H
19
+
20
+
#include <linux/bitops.h>
21
+
22
+
/* register offset (32-bit registers) */
23
+
#define CFGCHIP(n) ((n) * 4)
24
+
25
+
/* CFGCHIP0 (PLL0/EDMA3_0) register bits */
26
+
#define CFGCHIP0_PLL_MASTER_LOCK BIT(4)
27
+
#define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2)
28
+
#define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3)
29
+
#define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0)
30
+
#define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1)
31
+
#define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2)
32
+
#define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0)
33
+
#define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3)
34
+
#define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0)
35
+
#define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1)
36
+
#define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2)
37
+
38
+
/* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */
39
+
#define CFGCHIP1_CAP2SRC(n) ((n) << 27)
40
+
#define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f)
41
+
#define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0)
42
+
#define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1)
43
+
#define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2)
44
+
#define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7)
45
+
#define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8)
46
+
#define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9)
47
+
#define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa)
48
+
#define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb)
49
+
#define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc)
50
+
#define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd)
51
+
#define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe)
52
+
#define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf)
53
+
#define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10)
54
+
#define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11)
55
+
#define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12)
56
+
#define CFGCHIP1_CAP1SRC(n) ((n) << 22)
57
+
#define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f)
58
+
#define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0)
59
+
#define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1)
60
+
#define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2)
61
+
#define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7)
62
+
#define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8)
63
+
#define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9)
64
+
#define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa)
65
+
#define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb)
66
+
#define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc)
67
+
#define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd)
68
+
#define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe)
69
+
#define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf)
70
+
#define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10)
71
+
#define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11)
72
+
#define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12)
73
+
#define CFGCHIP1_CAP0SRC(n) ((n) << 17)
74
+
#define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f)
75
+
#define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0)
76
+
#define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1)
77
+
#define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2)
78
+
#define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7)
79
+
#define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8)
80
+
#define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9)
81
+
#define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa)
82
+
#define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb)
83
+
#define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc)
84
+
#define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd)
85
+
#define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe)
86
+
#define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf)
87
+
#define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10)
88
+
#define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11)
89
+
#define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12)
90
+
#define CFGCHIP1_HPIBYTEAD BIT(16)
91
+
#define CFGCHIP1_HPIENA BIT(15)
92
+
#define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13)
93
+
#define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3)
94
+
#define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0)
95
+
#define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1)
96
+
#define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2)
97
+
#define CFGCHIP1_TBCLKSYNC BIT(12)
98
+
#define CFGCHIP1_AMUTESEL0(n) ((n) << 0)
99
+
#define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf)
100
+
#define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0)
101
+
#define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1)
102
+
#define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2)
103
+
#define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3)
104
+
#define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4)
105
+
#define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5)
106
+
#define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6)
107
+
#define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7)
108
+
#define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8)
109
+
110
+
/* CFGCHIP2 (USB PHY) register bits */
111
+
#define CFGCHIP2_PHYCLKGD BIT(17)
112
+
#define CFGCHIP2_VBUSSENSE BIT(16)
113
+
#define CFGCHIP2_RESET BIT(15)
114
+
#define CFGCHIP2_OTGMODE(n) ((n) << 13)
115
+
#define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3)
116
+
#define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0)
117
+
#define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1)
118
+
#define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2)
119
+
#define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3)
120
+
#define CFGCHIP2_USB1PHYCLKMUX BIT(12)
121
+
#define CFGCHIP2_USB2PHYCLKMUX BIT(11)
122
+
#define CFGCHIP2_PHYPWRDN BIT(10)
123
+
#define CFGCHIP2_OTGPWRDN BIT(9)
124
+
#define CFGCHIP2_DATPOL BIT(8)
125
+
#define CFGCHIP2_USB1SUSPENDM BIT(7)
126
+
#define CFGCHIP2_PHY_PLLON BIT(6)
127
+
#define CFGCHIP2_SESENDEN BIT(5)
128
+
#define CFGCHIP2_VBDTCTEN BIT(4)
129
+
#define CFGCHIP2_REFFREQ(n) ((n) << 0)
130
+
#define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf)
131
+
#define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1)
132
+
#define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2)
133
+
#define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3)
134
+
#define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4)
135
+
#define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5)
136
+
#define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6)
137
+
#define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7)
138
+
#define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8)
139
+
#define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9)
140
+
141
+
/* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */
142
+
#define CFGCHIP3_RMII_SEL BIT(8)
143
+
#define CFGCHIP3_UPP_TX_CLKSRC BIT(6)
144
+
#define CFGCHIP3_PLL1_MASTER_LOCK BIT(5)
145
+
#define CFGCHIP3_ASYNC3_CLKSRC BIT(4)
146
+
#define CFGCHIP3_PRUEVTSEL BIT(3)
147
+
#define CFGCHIP3_DIV45PENA BIT(2)
148
+
#define CFGCHIP3_EMA_CLKSRC BIT(1)
149
+
150
+
/* CFGCHIP4 (McASP0 AMUNTEIN) register bits */
151
+
#define CFGCHIP4_AMUTECLR0 BIT(0)
152
+
153
+
#endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */