Merge tag 'timers-clocksource-2025-09-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

-38

Documentation/devicetree/bindings/timer/faraday,fttmr010.txt

··· 1 - Faraday Technology timer 2 - 3 - This timer is a generic IP block from Faraday Technology, embedded in the 4 - Cortina Systems Gemini SoCs and other designs. 5 - 6 - Required properties: 7 - 8 - - compatible : Must be one of 9 - "faraday,fttmr010" 10 - "cortina,gemini-timer", "faraday,fttmr010" 11 - "moxa,moxart-timer", "faraday,fttmr010" 12 - "aspeed,ast2400-timer" 13 - "aspeed,ast2500-timer" 14 - "aspeed,ast2600-timer" 15 - 16 - - reg : Should contain registers location and length 17 - - interrupts : Should contain the three timer interrupts usually with 18 - flags for falling edge 19 - 20 - Optionally required properties: 21 - 22 - - clocks : a clock to provide the tick rate for "faraday,fttmr010" 23 - - clock-names : should be "EXTCLK" and "PCLK" for the external tick timer 24 - and peripheral clock respectively, for "faraday,fttmr010" 25 - - syscon : a phandle to the global Gemini system controller if the compatible 26 - type is "cortina,gemini-timer" 27 - 28 - Example: 29 - 30 - timer@43000000 { 31 - compatible = "faraday,fttmr010"; 32 - reg = <0x43000000 0x1000>; 33 - interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ 34 - <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ 35 - <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ 36 - clocks = <&extclk>, <&pclk>; 37 - clock-names = "EXTCLK", "PCLK"; 38 - };

+89

Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/timer/faraday,fttmr010.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Faraday FTTMR010 timer 8 + 9 + maintainers: 10 + - Joel Stanley <joel@jms.id.au> 11 + - Linus Walleij <linus.walleij@linaro.org> 12 + 13 + description: 14 + This timer is a generic IP block from Faraday Technology, embedded in the 15 + Cortina Systems Gemini SoCs and other designs. 16 + 17 + properties: 18 + compatible: 19 + oneOf: 20 + - items: 21 + - const: moxa,moxart-timer 22 + - const: faraday,fttmr010 23 + - enum: 24 + - aspeed,ast2400-timer 25 + - aspeed,ast2500-timer 26 + - aspeed,ast2600-timer 27 + - cortina,gemini-timer 28 + - faraday,fttmr010 29 + 30 + reg: 31 + maxItems: 1 32 + 33 + interrupts: 34 + minItems: 1 35 + maxItems: 8 36 + description: One interrupt per timer 37 + 38 + clocks: 39 + minItems: 1 40 + items: 41 + - description: Peripheral clock 42 + - description: External tick clock 43 + 44 + clock-names: 45 + minItems: 1 46 + items: 47 + - const: PCLK 48 + - const: EXTCLK 49 + 50 + resets: 51 + maxItems: 1 52 + 53 + syscon: 54 + description: System controller phandle for Gemini systems 55 + $ref: /schemas/types.yaml#/definitions/phandle 56 + 57 + required: 58 + - compatible 59 + - reg 60 + - interrupts 61 + 62 + allOf: 63 + - if: 64 + properties: 65 + compatible: 66 + contains: 67 + const: cortina,gemini-timer 68 + then: 69 + required: 70 + - syscon 71 + else: 72 + properties: 73 + syscon: false 74 + 75 + additionalProperties: false 76 + 77 + examples: 78 + - | 79 + #include <dt-bindings/interrupt-controller/irq.h> 80 + 81 + timer@43000000 { 82 + compatible = "faraday,fttmr010"; 83 + reg = <0x43000000 0x1000>; 84 + interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ 85 + <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ 86 + <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ 87 + clocks = <&pclk>, <&extclk>; 88 + clock-names = "PCLK", "EXTCLK"; 89 + };

+5 -2

Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml

··· 14 14 const: fsl,ftm-timer 15 15 16 16 reg: 17 - maxItems: 1 17 + items: 18 + - description: clock event device 19 + - description: clock source device 18 20 19 21 interrupts: 20 22 maxItems: 1 ··· 52 50 53 51 ftm@400b8000 { 54 52 compatible = "fsl,ftm-timer"; 55 - reg = <0x400b8000 0x1000>; 53 + reg = <0x400b8000 0x1000>, 54 + <0x400b9000 0x1000>; 56 55 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 57 56 clock-names = "ftm-evt", "ftm-src", "ftm-evt-counter-en", "ftm-src-counter-en"; 58 57 clocks = <&clks VF610_CLK_FTM2>, <&clks VF610_CLK_FTM3>,

+48

Documentation/devicetree/bindings/timer/fsl,timrot.yaml

··· 1 + # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/timer/fsl,timrot.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Freescale MXS Timer 8 + 9 + maintainers: 10 + - Frank Li <Frank.Li@nxp.com> 11 + 12 + properties: 13 + compatible: 14 + items: 15 + - enum: 16 + - fsl,imx23-timrot 17 + - fsl,imx28-timrot 18 + - const: fsl,timrot 19 + 20 + reg: 21 + maxItems: 1 22 + 23 + interrupts: 24 + items: 25 + - description: irq for timer0 26 + - description: irq for timer1 27 + - description: irq for timer2 28 + - description: irq for timer3 29 + 30 + clocks: 31 + maxItems: 1 32 + 33 + required: 34 + - compatible 35 + - reg 36 + - interrupts 37 + - clocks 38 + 39 + additionalProperties: false 40 + 41 + examples: 42 + - | 43 + timer: timer@80068000 { 44 + compatible = "fsl,imx28-timrot", "fsl,timrot"; 45 + reg = <0x80068000 0x2000>; 46 + interrupts = <48>, <49>, <50>, <51>; 47 + clocks = <&clks 26>; 48 + };

+7 -2

Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml

··· 15 15 16 16 properties: 17 17 compatible: 18 - enum: 19 - - fsl,vf610-pit 18 + oneOf: 19 + - enum: 20 + - fsl,vf610-pit 21 + - nxp,s32g2-pit 22 + - items: 23 + - const: nxp,s32g3-pit 24 + - const: nxp,s32g2-pit 20 25 21 26 reg: 22 27 maxItems: 1

+2

Documentation/devicetree/bindings/timer/mediatek,timer.yaml

··· 26 26 - items: 27 27 - enum: 28 28 - mediatek,mt2701-timer 29 + - mediatek,mt6572-timer 29 30 - mediatek,mt6580-timer 30 31 - mediatek,mt6582-timer 31 32 - mediatek,mt6589-timer ··· 45 44 - mediatek,mt8188-timer 46 45 - mediatek,mt8192-timer 47 46 - mediatek,mt8195-timer 47 + - mediatek,mt8196-timer 48 48 - mediatek,mt8365-systimer 49 49 - const: mediatek,mt6765-timer 50 50

+2

Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml

··· 26 26 - items: 27 27 - enum: 28 28 - axis,artpec8-mct 29 + - axis,artpec9-mct 29 30 - google,gs101-mct 30 31 - samsung,exynos2200-mct-peris 31 32 - samsung,exynos3250-mct ··· 132 131 contains: 133 132 enum: 134 133 - axis,artpec8-mct 134 + - axis,artpec9-mct 135 135 - google,gs101-mct 136 136 - samsung,exynos2200-mct-peris 137 137 - samsung,exynos5260-mct

+1

MAINTAINERS

··· 1989 1989 F: arch/arm/include/asm/arch_timer.h 1990 1990 F: arch/arm64/include/asm/arch_timer.h 1991 1991 F: drivers/clocksource/arm_arch_timer.c 1992 + F: drivers/clocksource/arm_arch_timer_mmio.c 1992 1993 1993 1994 ARM GENERIC INTERRUPT CONTROLLER DRIVERS 1994 1995 M: Marc Zyngier <maz@kernel.org>

+25 -4

drivers/acpi/arm64/gtdt.c

··· 388 388 return 0; 389 389 } 390 390 391 - static int __init gtdt_sbsa_gwdt_init(void) 391 + static int __init gtdt_platform_timer_init(void) 392 392 { 393 393 void *platform_timer; 394 394 struct acpi_table_header *table; 395 - int ret, timer_count, gwdt_count = 0; 395 + int ret, timer_count, gwdt_count = 0, mmio_timer_count = 0; 396 396 397 397 if (acpi_disabled) 398 398 return 0; ··· 414 414 goto out_put_gtdt; 415 415 416 416 for_each_platform_timer(platform_timer) { 417 + ret = 0; 418 + 417 419 if (is_non_secure_watchdog(platform_timer)) { 418 420 ret = gtdt_import_sbsa_gwdt(platform_timer, gwdt_count); 419 421 if (ret) 420 - break; 422 + continue; 421 423 gwdt_count++; 424 + } else if (is_timer_block(platform_timer)) { 425 + struct arch_timer_mem atm = {}; 426 + struct platform_device *pdev; 427 + 428 + ret = gtdt_parse_timer_block(platform_timer, &atm); 429 + if (ret) 430 + continue; 431 + 432 + pdev = platform_device_register_data(NULL, "gtdt-arm-mmio-timer", 433 + gwdt_count, &atm, 434 + sizeof(atm)); 435 + if (IS_ERR(pdev)) { 436 + pr_err("Can't register timer %d\n", gwdt_count); 437 + continue; 438 + } 439 + 440 + mmio_timer_count++; 422 441 } 423 442 } 424 443 425 444 if (gwdt_count) 426 445 pr_info("found %d SBSA generic Watchdog(s).\n", gwdt_count); 446 + if (mmio_timer_count) 447 + pr_info("found %d Generic MMIO timer(s).\n", mmio_timer_count); 427 448 428 449 out_put_gtdt: 429 450 acpi_put_table(table); 430 451 return ret; 431 452 } 432 453 433 - device_initcall(gtdt_sbsa_gwdt_init); 454 + device_initcall(gtdt_platform_timer_init);

+8 -5

drivers/clocksource/Kconfig

··· 395 395 396 396 config ARM_GT_INITIAL_PRESCALER_VAL 397 397 int "ARM global timer initial prescaler value" 398 - default 2 if ARCH_ZYNQ 399 - default 1 398 + default 0 400 399 depends on ARM_GLOBAL_TIMER 401 400 help 402 401 When the ARM global timer initializes, its current rate is declared ··· 405 406 bounds about how much the parent clock is allowed to decrease or 406 407 increase wrt the initial clock value. 407 408 This affects CPU_FREQ max delta from the initial frequency. 409 + Use 0 to use auto-detection in the driver. 408 410 409 411 config ARM_TIMER_SP804 410 412 bool "Support for Dual Timer SP804 module" ··· 474 474 help 475 475 Support for Freescale FlexTimer Module (FTM) timer. 476 476 477 - config VF_PIT_TIMER 478 - bool 477 + config NXP_PIT_TIMER 478 + bool "NXP Periodic Interrupt Timer" if COMPILE_TEST 479 479 select CLKSRC_MMIO 480 480 help 481 - Support for Periodic Interrupt Timer on Freescale Vybrid Family SoCs. 481 + Support for Periodic Interrupt Timer on Freescale / NXP 482 + SoCs. This periodic timer is found on the Vybrid Family and 483 + the Automotive S32G2/3 platforms. It contains 4 channels 484 + where two can be coupled to form a 64 bits channel. 482 485 483 486 config SYS_SUPPORTS_SH_CMT 484 487 bool

+2 -1

drivers/clocksource/Makefile

··· 49 49 obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o 50 50 obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o 51 51 obj-$(CONFIG_FSL_FTM_TIMER) += timer-fsl-ftm.o 52 - obj-$(CONFIG_VF_PIT_TIMER) += timer-vf-pit.o 52 + obj-$(CONFIG_NXP_PIT_TIMER) += timer-nxp-pit.o 53 53 obj-$(CONFIG_CLKSRC_QCOM) += timer-qcom.o 54 54 obj-$(CONFIG_MTK_TIMER) += timer-mediatek.o 55 55 obj-$(CONFIG_MTK_CPUX_TIMER) += timer-mediatek-cpux.o ··· 64 64 65 65 obj-$(CONFIG_ARC_TIMERS) += arc_timer.o 66 66 obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer.o 67 + obj-$(CONFIG_ARM_ARCH_TIMER) += arm_arch_timer_mmio.o 67 68 obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o 68 69 obj-$(CONFIG_ARMV7M_SYSTICK) += armv7m_systick.o 69 70 obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp804.o

+65 -621

drivers/clocksource/arm_arch_timer.c

··· 34 34 35 35 #include <clocksource/arm_arch_timer.h> 36 36 37 - #define CNTTIDR 0x08 38 - #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) 39 - 40 - #define CNTACR(n) (0x40 + ((n) * 4)) 41 - #define CNTACR_RPCT BIT(0) 42 - #define CNTACR_RVCT BIT(1) 43 - #define CNTACR_RFRQ BIT(2) 44 - #define CNTACR_RVOFF BIT(3) 45 - #define CNTACR_RWVT BIT(4) 46 - #define CNTACR_RWPT BIT(5) 47 - 48 - #define CNTPCT_LO 0x00 49 - #define CNTVCT_LO 0x08 50 - #define CNTFRQ 0x10 51 - #define CNTP_CVAL_LO 0x20 52 - #define CNTP_CTL 0x2c 53 - #define CNTV_CVAL_LO 0x30 54 - #define CNTV_CTL 0x3c 55 - 56 37 /* 57 38 * The minimum amount of time a generic counter is guaranteed to not roll over 58 39 * (40 years) 59 40 */ 60 41 #define MIN_ROLLOVER_SECS (40ULL * 365 * 24 * 3600) 61 - 62 - static unsigned arch_timers_present __initdata; 63 - 64 - struct arch_timer { 65 - void __iomem *base; 66 - struct clock_event_device evt; 67 - }; 68 - 69 - static struct arch_timer *arch_timer_mem __ro_after_init; 70 - 71 - #define to_arch_timer(e) container_of(e, struct arch_timer, evt) 72 42 73 43 static u32 arch_timer_rate __ro_after_init; 74 44 static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init; ··· 55 85 56 86 static enum arch_timer_ppi_nr arch_timer_uses_ppi __ro_after_init = ARCH_TIMER_VIRT_PPI; 57 87 static bool arch_timer_c3stop __ro_after_init; 58 - static bool arch_timer_mem_use_virtual __ro_after_init; 59 88 static bool arch_counter_suspend_stop __ro_after_init; 60 89 #ifdef CONFIG_GENERIC_GETTIMEOFDAY 61 90 static enum vdso_clock_mode vdso_default = VDSO_CLOCKMODE_ARCHTIMER; ··· 90 121 /* 91 122 * Architected system timer support. 92 123 */ 93 - 94 - static __always_inline 95 - void arch_timer_reg_write(int access, enum arch_timer_reg reg, u64 val, 96 - struct clock_event_device *clk) 97 - { 98 - if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { 99 - struct arch_timer *timer = to_arch_timer(clk); 100 - switch (reg) { 101 - case ARCH_TIMER_REG_CTRL: 102 - writel_relaxed((u32)val, timer->base + CNTP_CTL); 103 - break; 104 - case ARCH_TIMER_REG_CVAL: 105 - /* 106 - * Not guaranteed to be atomic, so the timer 107 - * must be disabled at this point. 108 - */ 109 - writeq_relaxed(val, timer->base + CNTP_CVAL_LO); 110 - break; 111 - default: 112 - BUILD_BUG(); 113 - } 114 - } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { 115 - struct arch_timer *timer = to_arch_timer(clk); 116 - switch (reg) { 117 - case ARCH_TIMER_REG_CTRL: 118 - writel_relaxed((u32)val, timer->base + CNTV_CTL); 119 - break; 120 - case ARCH_TIMER_REG_CVAL: 121 - /* Same restriction as above */ 122 - writeq_relaxed(val, timer->base + CNTV_CVAL_LO); 123 - break; 124 - default: 125 - BUILD_BUG(); 126 - } 127 - } else { 128 - arch_timer_reg_write_cp15(access, reg, val); 129 - } 130 - } 131 - 132 - static __always_inline 133 - u32 arch_timer_reg_read(int access, enum arch_timer_reg reg, 134 - struct clock_event_device *clk) 135 - { 136 - u32 val; 137 - 138 - if (access == ARCH_TIMER_MEM_PHYS_ACCESS) { 139 - struct arch_timer *timer = to_arch_timer(clk); 140 - switch (reg) { 141 - case ARCH_TIMER_REG_CTRL: 142 - val = readl_relaxed(timer->base + CNTP_CTL); 143 - break; 144 - default: 145 - BUILD_BUG(); 146 - } 147 - } else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) { 148 - struct arch_timer *timer = to_arch_timer(clk); 149 - switch (reg) { 150 - case ARCH_TIMER_REG_CTRL: 151 - val = readl_relaxed(timer->base + CNTV_CTL); 152 - break; 153 - default: 154 - BUILD_BUG(); 155 - } 156 - } else { 157 - val = arch_timer_reg_read_cp15(access, reg); 158 - } 159 - 160 - return val; 161 - } 162 - 163 124 static noinstr u64 raw_counter_get_cntpct_stable(void) 164 125 { 165 126 return __arch_counter_get_cntpct_stable(); ··· 323 424 unsigned long ctrl; 324 425 u64 cval; 325 426 326 - ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); 427 + ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL); 327 428 ctrl |= ARCH_TIMER_CTRL_ENABLE; 328 429 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; 329 430 ··· 335 436 write_sysreg(cval, cntv_cval_el0); 336 437 } 337 438 338 - arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); 439 + arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl); 339 440 } 340 441 341 442 static __maybe_unused int erratum_set_next_event_virt(unsigned long evt, ··· 566 667 { 567 668 unsigned long ctrl; 568 669 569 - ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt); 670 + ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL); 570 671 if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { 571 672 ctrl |= ARCH_TIMER_CTRL_IT_MASK; 572 - arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt); 673 + arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl); 573 674 evt->event_handler(evt); 574 675 return IRQ_HANDLED; 575 676 } ··· 591 692 return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt); 592 693 } 593 694 594 - static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id) 595 - { 596 - struct clock_event_device *evt = dev_id; 597 - 598 - return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt); 599 - } 600 - 601 - static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id) 602 - { 603 - struct clock_event_device *evt = dev_id; 604 - 605 - return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt); 606 - } 607 - 608 695 static __always_inline int arch_timer_shutdown(const int access, 609 696 struct clock_event_device *clk) 610 697 { 611 698 unsigned long ctrl; 612 699 613 - ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); 700 + ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL); 614 701 ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 615 - arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); 702 + arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl); 616 703 617 704 return 0; 618 705 } ··· 613 728 return arch_timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk); 614 729 } 615 730 616 - static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk) 617 - { 618 - return arch_timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk); 619 - } 620 - 621 - static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk) 622 - { 623 - return arch_timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk); 624 - } 625 - 626 731 static __always_inline void set_next_event(const int access, unsigned long evt, 627 732 struct clock_event_device *clk) 628 733 { 629 734 unsigned long ctrl; 630 735 u64 cnt; 631 736 632 - ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); 737 + ctrl = arch_timer_reg_read_cp15(access, ARCH_TIMER_REG_CTRL); 633 738 ctrl |= ARCH_TIMER_CTRL_ENABLE; 634 739 ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; 635 740 ··· 628 753 else 629 754 cnt = __arch_counter_get_cntvct(); 630 755 631 - arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk); 632 - arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); 756 + arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CVAL, evt + cnt); 757 + arch_timer_reg_write_cp15(access, ARCH_TIMER_REG_CTRL, ctrl); 633 758 } 634 759 635 760 static int arch_timer_set_next_event_virt(unsigned long evt, ··· 643 768 struct clock_event_device *clk) 644 769 { 645 770 set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk); 646 - return 0; 647 - } 648 - 649 - static noinstr u64 arch_counter_get_cnt_mem(struct arch_timer *t, int offset_lo) 650 - { 651 - u32 cnt_lo, cnt_hi, tmp_hi; 652 - 653 - do { 654 - cnt_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4)); 655 - cnt_lo = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo)); 656 - tmp_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4)); 657 - } while (cnt_hi != tmp_hi); 658 - 659 - return ((u64) cnt_hi << 32) | cnt_lo; 660 - } 661 - 662 - static __always_inline void set_next_event_mem(const int access, unsigned long evt, 663 - struct clock_event_device *clk) 664 - { 665 - struct arch_timer *timer = to_arch_timer(clk); 666 - unsigned long ctrl; 667 - u64 cnt; 668 - 669 - ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk); 670 - 671 - /* Timer must be disabled before programming CVAL */ 672 - if (ctrl & ARCH_TIMER_CTRL_ENABLE) { 673 - ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 674 - arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); 675 - } 676 - 677 - ctrl |= ARCH_TIMER_CTRL_ENABLE; 678 - ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; 679 - 680 - if (access == ARCH_TIMER_MEM_VIRT_ACCESS) 681 - cnt = arch_counter_get_cnt_mem(timer, CNTVCT_LO); 682 - else 683 - cnt = arch_counter_get_cnt_mem(timer, CNTPCT_LO); 684 - 685 - arch_timer_reg_write(access, ARCH_TIMER_REG_CVAL, evt + cnt, clk); 686 - arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk); 687 - } 688 - 689 - static int arch_timer_set_next_event_virt_mem(unsigned long evt, 690 - struct clock_event_device *clk) 691 - { 692 - set_next_event_mem(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk); 693 - return 0; 694 - } 695 - 696 - static int arch_timer_set_next_event_phys_mem(unsigned long evt, 697 - struct clock_event_device *clk) 698 - { 699 - set_next_event_mem(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk); 700 771 return 0; 701 772 } 702 773 ··· 671 850 return CLOCKSOURCE_MASK(arch_counter_get_width()); 672 851 } 673 852 674 - static void __arch_timer_setup(unsigned type, 675 - struct clock_event_device *clk) 853 + static void __arch_timer_setup(struct clock_event_device *clk) 676 854 { 855 + typeof(clk->set_next_event) sne; 677 856 u64 max_delta; 678 857 679 858 clk->features = CLOCK_EVT_FEAT_ONESHOT; 680 859 681 - if (type == ARCH_TIMER_TYPE_CP15) { 682 - typeof(clk->set_next_event) sne; 860 + arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); 683 861 684 - arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL); 685 - 686 - if (arch_timer_c3stop) 687 - clk->features |= CLOCK_EVT_FEAT_C3STOP; 688 - clk->name = "arch_sys_timer"; 689 - clk->rating = 450; 690 - clk->cpumask = cpumask_of(smp_processor_id()); 691 - clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; 692 - switch (arch_timer_uses_ppi) { 693 - case ARCH_TIMER_VIRT_PPI: 694 - clk->set_state_shutdown = arch_timer_shutdown_virt; 695 - clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; 696 - sne = erratum_handler(set_next_event_virt); 697 - break; 698 - case ARCH_TIMER_PHYS_SECURE_PPI: 699 - case ARCH_TIMER_PHYS_NONSECURE_PPI: 700 - case ARCH_TIMER_HYP_PPI: 701 - clk->set_state_shutdown = arch_timer_shutdown_phys; 702 - clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; 703 - sne = erratum_handler(set_next_event_phys); 704 - break; 705 - default: 706 - BUG(); 707 - } 708 - 709 - clk->set_next_event = sne; 710 - max_delta = __arch_timer_check_delta(); 711 - } else { 712 - clk->features |= CLOCK_EVT_FEAT_DYNIRQ; 713 - clk->name = "arch_mem_timer"; 714 - clk->rating = 400; 715 - clk->cpumask = cpu_possible_mask; 716 - if (arch_timer_mem_use_virtual) { 717 - clk->set_state_shutdown = arch_timer_shutdown_virt_mem; 718 - clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem; 719 - clk->set_next_event = 720 - arch_timer_set_next_event_virt_mem; 721 - } else { 722 - clk->set_state_shutdown = arch_timer_shutdown_phys_mem; 723 - clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem; 724 - clk->set_next_event = 725 - arch_timer_set_next_event_phys_mem; 726 - } 727 - 728 - max_delta = CLOCKSOURCE_MASK(56); 862 + if (arch_timer_c3stop) 863 + clk->features |= CLOCK_EVT_FEAT_C3STOP; 864 + clk->name = "arch_sys_timer"; 865 + clk->rating = 450; 866 + clk->cpumask = cpumask_of(smp_processor_id()); 867 + clk->irq = arch_timer_ppi[arch_timer_uses_ppi]; 868 + switch (arch_timer_uses_ppi) { 869 + case ARCH_TIMER_VIRT_PPI: 870 + clk->set_state_shutdown = arch_timer_shutdown_virt; 871 + clk->set_state_oneshot_stopped = arch_timer_shutdown_virt; 872 + sne = erratum_handler(set_next_event_virt); 873 + break; 874 + case ARCH_TIMER_PHYS_SECURE_PPI: 875 + case ARCH_TIMER_PHYS_NONSECURE_PPI: 876 + case ARCH_TIMER_HYP_PPI: 877 + clk->set_state_shutdown = arch_timer_shutdown_phys; 878 + clk->set_state_oneshot_stopped = arch_timer_shutdown_phys; 879 + sne = erratum_handler(set_next_event_phys); 880 + break; 881 + default: 882 + BUG(); 729 883 } 884 + 885 + clk->set_next_event = sne; 886 + max_delta = __arch_timer_check_delta(); 730 887 731 888 clk->set_state_shutdown(clk); 732 889 ··· 828 1029 struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt); 829 1030 u32 flags; 830 1031 831 - __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk); 1032 + __arch_timer_setup(clk); 832 1033 833 1034 flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]); 834 1035 enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags); ··· 874 1075 pr_warn("frequency not available\n"); 875 1076 } 876 1077 877 - static void __init arch_timer_banner(unsigned type) 1078 + static void __init arch_timer_banner(void) 878 1079 { 879 - pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n", 880 - type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "", 881 - type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? 882 - " and " : "", 883 - type & ARCH_TIMER_TYPE_MEM ? "mmio" : "", 1080 + pr_info("cp15 timer running at %lu.%02luMHz (%s).\n", 884 1081 (unsigned long)arch_timer_rate / 1000000, 885 1082 (unsigned long)(arch_timer_rate / 10000) % 100, 886 - type & ARCH_TIMER_TYPE_CP15 ? 887 - (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" : 888 - "", 889 - type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "", 890 - type & ARCH_TIMER_TYPE_MEM ? 891 - arch_timer_mem_use_virtual ? "virt" : "phys" : 892 - ""); 1083 + (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys"); 893 1084 } 894 1085 895 1086 u32 arch_timer_get_rate(void) ··· 897 1108 return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available); 898 1109 } 899 1110 900 - static noinstr u64 arch_counter_get_cntvct_mem(void) 901 - { 902 - return arch_counter_get_cnt_mem(arch_timer_mem, CNTVCT_LO); 903 - } 904 - 905 1111 static struct arch_timer_kvm_info arch_timer_kvm_info; 906 1112 907 1113 struct arch_timer_kvm_info *arch_timer_get_kvm_info(void) ··· 904 1120 return &arch_timer_kvm_info; 905 1121 } 906 1122 907 - static void __init arch_counter_register(unsigned type) 1123 + static void __init arch_counter_register(void) 908 1124 { 909 1125 u64 (*scr)(void); 1126 + u64 (*rd)(void); 910 1127 u64 start_count; 911 1128 int width; 912 1129 913 - /* Register the CP15 based counter if we have one */ 914 - if (type & ARCH_TIMER_TYPE_CP15) { 915 - u64 (*rd)(void); 916 - 917 - if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || 918 - arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) { 919 - if (arch_timer_counter_has_wa()) { 920 - rd = arch_counter_get_cntvct_stable; 921 - scr = raw_counter_get_cntvct_stable; 922 - } else { 923 - rd = arch_counter_get_cntvct; 924 - scr = arch_counter_get_cntvct; 925 - } 1130 + if ((IS_ENABLED(CONFIG_ARM64) && !is_hyp_mode_available()) || 1131 + arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) { 1132 + if (arch_timer_counter_has_wa()) { 1133 + rd = arch_counter_get_cntvct_stable; 1134 + scr = raw_counter_get_cntvct_stable; 926 1135 } else { 927 - if (arch_timer_counter_has_wa()) { 928 - rd = arch_counter_get_cntpct_stable; 929 - scr = raw_counter_get_cntpct_stable; 930 - } else { 931 - rd = arch_counter_get_cntpct; 932 - scr = arch_counter_get_cntpct; 933 - } 1136 + rd = arch_counter_get_cntvct; 1137 + scr = arch_counter_get_cntvct; 934 1138 } 935 - 936 - arch_timer_read_counter = rd; 937 - clocksource_counter.vdso_clock_mode = vdso_default; 938 1139 } else { 939 - arch_timer_read_counter = arch_counter_get_cntvct_mem; 940 - scr = arch_counter_get_cntvct_mem; 1140 + if (arch_timer_counter_has_wa()) { 1141 + rd = arch_counter_get_cntpct_stable; 1142 + scr = raw_counter_get_cntpct_stable; 1143 + } else { 1144 + rd = arch_counter_get_cntpct; 1145 + scr = arch_counter_get_cntpct; 1146 + } 941 1147 } 1148 + 1149 + arch_timer_read_counter = rd; 1150 + clocksource_counter.vdso_clock_mode = vdso_default; 942 1151 943 1152 width = arch_counter_get_width(); 944 1153 clocksource_counter.mask = CLOCKSOURCE_MASK(width); ··· 1080 1303 return err; 1081 1304 } 1082 1305 1083 - static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq) 1084 - { 1085 - int ret; 1086 - irq_handler_t func; 1087 - 1088 - arch_timer_mem = kzalloc(sizeof(*arch_timer_mem), GFP_KERNEL); 1089 - if (!arch_timer_mem) 1090 - return -ENOMEM; 1091 - 1092 - arch_timer_mem->base = base; 1093 - arch_timer_mem->evt.irq = irq; 1094 - __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &arch_timer_mem->evt); 1095 - 1096 - if (arch_timer_mem_use_virtual) 1097 - func = arch_timer_handler_virt_mem; 1098 - else 1099 - func = arch_timer_handler_phys_mem; 1100 - 1101 - ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &arch_timer_mem->evt); 1102 - if (ret) { 1103 - pr_err("Failed to request mem timer irq\n"); 1104 - kfree(arch_timer_mem); 1105 - arch_timer_mem = NULL; 1106 - } 1107 - 1108 - return ret; 1109 - } 1110 - 1111 - static const struct of_device_id arch_timer_of_match[] __initconst = { 1112 - { .compatible = "arm,armv7-timer", }, 1113 - { .compatible = "arm,armv8-timer", }, 1114 - {}, 1115 - }; 1116 - 1117 - static const struct of_device_id arch_timer_mem_of_match[] __initconst = { 1118 - { .compatible = "arm,armv7-timer-mem", }, 1119 - {}, 1120 - }; 1121 - 1122 - static bool __init arch_timer_needs_of_probing(void) 1123 - { 1124 - struct device_node *dn; 1125 - bool needs_probing = false; 1126 - unsigned int mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM; 1127 - 1128 - /* We have two timers, and both device-tree nodes are probed. */ 1129 - if ((arch_timers_present & mask) == mask) 1130 - return false; 1131 - 1132 - /* 1133 - * Only one type of timer is probed, 1134 - * check if we have another type of timer node in device-tree. 1135 - */ 1136 - if (arch_timers_present & ARCH_TIMER_TYPE_CP15) 1137 - dn = of_find_matching_node(NULL, arch_timer_mem_of_match); 1138 - else 1139 - dn = of_find_matching_node(NULL, arch_timer_of_match); 1140 - 1141 - if (dn && of_device_is_available(dn)) 1142 - needs_probing = true; 1143 - 1144 - of_node_put(dn); 1145 - 1146 - return needs_probing; 1147 - } 1148 - 1149 1306 static int __init arch_timer_common_init(void) 1150 1307 { 1151 - arch_timer_banner(arch_timers_present); 1152 - arch_counter_register(arch_timers_present); 1308 + arch_timer_banner(); 1309 + arch_counter_register(); 1153 1310 return arch_timer_arch_init(); 1154 1311 } 1155 1312 ··· 1132 1421 u32 rate; 1133 1422 bool has_names; 1134 1423 1135 - if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { 1424 + if (arch_timer_evt) { 1136 1425 pr_warn("multiple nodes in dt, skipping\n"); 1137 1426 return 0; 1138 1427 } 1139 - 1140 - arch_timers_present |= ARCH_TIMER_TYPE_CP15; 1141 1428 1142 1429 has_names = of_property_present(np, "interrupt-names"); 1143 1430 ··· 1181 1472 if (ret) 1182 1473 return ret; 1183 1474 1184 - if (arch_timer_needs_of_probing()) 1185 - return 0; 1186 - 1187 1475 return arch_timer_common_init(); 1188 1476 } 1189 1477 TIMER_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init); 1190 1478 TIMER_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init); 1191 1479 1192 - static u32 __init 1193 - arch_timer_mem_frame_get_cntfrq(struct arch_timer_mem_frame *frame) 1194 - { 1195 - void __iomem *base; 1196 - u32 rate; 1197 - 1198 - base = ioremap(frame->cntbase, frame->size); 1199 - if (!base) { 1200 - pr_err("Unable to map frame @ %pa\n", &frame->cntbase); 1201 - return 0; 1202 - } 1203 - 1204 - rate = readl_relaxed(base + CNTFRQ); 1205 - 1206 - iounmap(base); 1207 - 1208 - return rate; 1209 - } 1210 - 1211 - static struct arch_timer_mem_frame * __init 1212 - arch_timer_mem_find_best_frame(struct arch_timer_mem *timer_mem) 1213 - { 1214 - struct arch_timer_mem_frame *frame, *best_frame = NULL; 1215 - void __iomem *cntctlbase; 1216 - u32 cnttidr; 1217 - int i; 1218 - 1219 - cntctlbase = ioremap(timer_mem->cntctlbase, timer_mem->size); 1220 - if (!cntctlbase) { 1221 - pr_err("Can't map CNTCTLBase @ %pa\n", 1222 - &timer_mem->cntctlbase); 1223 - return NULL; 1224 - } 1225 - 1226 - cnttidr = readl_relaxed(cntctlbase + CNTTIDR); 1227 - 1228 - /* 1229 - * Try to find a virtual capable frame. Otherwise fall back to a 1230 - * physical capable frame. 1231 - */ 1232 - for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) { 1233 - u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | 1234 - CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; 1235 - 1236 - frame = &timer_mem->frame[i]; 1237 - if (!frame->valid) 1238 - continue; 1239 - 1240 - /* Try enabling everything, and see what sticks */ 1241 - writel_relaxed(cntacr, cntctlbase + CNTACR(i)); 1242 - cntacr = readl_relaxed(cntctlbase + CNTACR(i)); 1243 - 1244 - if ((cnttidr & CNTTIDR_VIRT(i)) && 1245 - !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) { 1246 - best_frame = frame; 1247 - arch_timer_mem_use_virtual = true; 1248 - break; 1249 - } 1250 - 1251 - if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) 1252 - continue; 1253 - 1254 - best_frame = frame; 1255 - } 1256 - 1257 - iounmap(cntctlbase); 1258 - 1259 - return best_frame; 1260 - } 1261 - 1262 - static int __init 1263 - arch_timer_mem_frame_register(struct arch_timer_mem_frame *frame) 1264 - { 1265 - void __iomem *base; 1266 - int ret, irq; 1267 - 1268 - if (arch_timer_mem_use_virtual) 1269 - irq = frame->virt_irq; 1270 - else 1271 - irq = frame->phys_irq; 1272 - 1273 - if (!irq) { 1274 - pr_err("Frame missing %s irq.\n", 1275 - arch_timer_mem_use_virtual ? "virt" : "phys"); 1276 - return -EINVAL; 1277 - } 1278 - 1279 - if (!request_mem_region(frame->cntbase, frame->size, 1280 - "arch_mem_timer")) 1281 - return -EBUSY; 1282 - 1283 - base = ioremap(frame->cntbase, frame->size); 1284 - if (!base) { 1285 - pr_err("Can't map frame's registers\n"); 1286 - return -ENXIO; 1287 - } 1288 - 1289 - ret = arch_timer_mem_register(base, irq); 1290 - if (ret) { 1291 - iounmap(base); 1292 - return ret; 1293 - } 1294 - 1295 - arch_timers_present |= ARCH_TIMER_TYPE_MEM; 1296 - 1297 - return 0; 1298 - } 1299 - 1300 - static int __init arch_timer_mem_of_init(struct device_node *np) 1301 - { 1302 - struct arch_timer_mem *timer_mem; 1303 - struct arch_timer_mem_frame *frame; 1304 - struct resource res; 1305 - int ret = -EINVAL; 1306 - u32 rate; 1307 - 1308 - timer_mem = kzalloc(sizeof(*timer_mem), GFP_KERNEL); 1309 - if (!timer_mem) 1310 - return -ENOMEM; 1311 - 1312 - if (of_address_to_resource(np, 0, &res)) 1313 - goto out; 1314 - timer_mem->cntctlbase = res.start; 1315 - timer_mem->size = resource_size(&res); 1316 - 1317 - for_each_available_child_of_node_scoped(np, frame_node) { 1318 - u32 n; 1319 - struct arch_timer_mem_frame *frame; 1320 - 1321 - if (of_property_read_u32(frame_node, "frame-number", &n)) { 1322 - pr_err(FW_BUG "Missing frame-number.\n"); 1323 - goto out; 1324 - } 1325 - if (n >= ARCH_TIMER_MEM_MAX_FRAMES) { 1326 - pr_err(FW_BUG "Wrong frame-number, only 0-%u are permitted.\n", 1327 - ARCH_TIMER_MEM_MAX_FRAMES - 1); 1328 - goto out; 1329 - } 1330 - frame = &timer_mem->frame[n]; 1331 - 1332 - if (frame->valid) { 1333 - pr_err(FW_BUG "Duplicated frame-number.\n"); 1334 - goto out; 1335 - } 1336 - 1337 - if (of_address_to_resource(frame_node, 0, &res)) 1338 - goto out; 1339 - 1340 - frame->cntbase = res.start; 1341 - frame->size = resource_size(&res); 1342 - 1343 - frame->virt_irq = irq_of_parse_and_map(frame_node, 1344 - ARCH_TIMER_VIRT_SPI); 1345 - frame->phys_irq = irq_of_parse_and_map(frame_node, 1346 - ARCH_TIMER_PHYS_SPI); 1347 - 1348 - frame->valid = true; 1349 - } 1350 - 1351 - frame = arch_timer_mem_find_best_frame(timer_mem); 1352 - if (!frame) { 1353 - pr_err("Unable to find a suitable frame in timer @ %pa\n", 1354 - &timer_mem->cntctlbase); 1355 - ret = -EINVAL; 1356 - goto out; 1357 - } 1358 - 1359 - rate = arch_timer_mem_frame_get_cntfrq(frame); 1360 - arch_timer_of_configure_rate(rate, np); 1361 - 1362 - ret = arch_timer_mem_frame_register(frame); 1363 - if (!ret && !arch_timer_needs_of_probing()) 1364 - ret = arch_timer_common_init(); 1365 - out: 1366 - kfree(timer_mem); 1367 - return ret; 1368 - } 1369 - TIMER_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem", 1370 - arch_timer_mem_of_init); 1371 - 1372 1480 #ifdef CONFIG_ACPI_GTDT 1373 - static int __init 1374 - arch_timer_mem_verify_cntfrq(struct arch_timer_mem *timer_mem) 1375 - { 1376 - struct arch_timer_mem_frame *frame; 1377 - u32 rate; 1378 - int i; 1379 - 1380 - for (i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) { 1381 - frame = &timer_mem->frame[i]; 1382 - 1383 - if (!frame->valid) 1384 - continue; 1385 - 1386 - rate = arch_timer_mem_frame_get_cntfrq(frame); 1387 - if (rate == arch_timer_rate) 1388 - continue; 1389 - 1390 - pr_err(FW_BUG "CNTFRQ mismatch: frame @ %pa: (0x%08lx), CPU: (0x%08lx)\n", 1391 - &frame->cntbase, 1392 - (unsigned long)rate, (unsigned long)arch_timer_rate); 1393 - 1394 - return -EINVAL; 1395 - } 1396 - 1397 - return 0; 1398 - } 1399 - 1400 - static int __init arch_timer_mem_acpi_init(int platform_timer_count) 1401 - { 1402 - struct arch_timer_mem *timers, *timer; 1403 - struct arch_timer_mem_frame *frame, *best_frame = NULL; 1404 - int timer_count, i, ret = 0; 1405 - 1406 - timers = kcalloc(platform_timer_count, sizeof(*timers), 1407 - GFP_KERNEL); 1408 - if (!timers) 1409 - return -ENOMEM; 1410 - 1411 - ret = acpi_arch_timer_mem_init(timers, &timer_count); 1412 - if (ret || !timer_count) 1413 - goto out; 1414 - 1415 - /* 1416 - * While unlikely, it's theoretically possible that none of the frames 1417 - * in a timer expose the combination of feature we want. 1418 - */ 1419 - for (i = 0; i < timer_count; i++) { 1420 - timer = &timers[i]; 1421 - 1422 - frame = arch_timer_mem_find_best_frame(timer); 1423 - if (!best_frame) 1424 - best_frame = frame; 1425 - 1426 - ret = arch_timer_mem_verify_cntfrq(timer); 1427 - if (ret) { 1428 - pr_err("Disabling MMIO timers due to CNTFRQ mismatch\n"); 1429 - goto out; 1430 - } 1431 - 1432 - if (!best_frame) /* implies !frame */ 1433 - /* 1434 - * Only complain about missing suitable frames if we 1435 - * haven't already found one in a previous iteration. 1436 - */ 1437 - pr_err("Unable to find a suitable frame in timer @ %pa\n", 1438 - &timer->cntctlbase); 1439 - } 1440 - 1441 - if (best_frame) 1442 - ret = arch_timer_mem_frame_register(best_frame); 1443 - out: 1444 - kfree(timers); 1445 - return ret; 1446 - } 1447 - 1448 - /* Initialize per-processor generic timer and memory-mapped timer(if present) */ 1449 1481 static int __init arch_timer_acpi_init(struct acpi_table_header *table) 1450 1482 { 1451 - int ret, platform_timer_count; 1483 + int ret; 1452 1484 1453 - if (arch_timers_present & ARCH_TIMER_TYPE_CP15) { 1485 + if (arch_timer_evt) { 1454 1486 pr_warn("already initialized, skipping\n"); 1455 1487 return -EINVAL; 1456 1488 } 1457 1489 1458 - arch_timers_present |= ARCH_TIMER_TYPE_CP15; 1459 - 1460 - ret = acpi_gtdt_init(table, &platform_timer_count); 1490 + ret = acpi_gtdt_init(table, NULL); 1461 1491 if (ret) 1462 1492 return ret; 1463 1493 ··· 1237 1789 ret = arch_timer_register(); 1238 1790 if (ret) 1239 1791 return ret; 1240 - 1241 - if (platform_timer_count && 1242 - arch_timer_mem_acpi_init(platform_timer_count)) 1243 - pr_err("Failed to initialize memory-mapped timer.\n"); 1244 1792 1245 1793 return arch_timer_common_init(); 1246 1794 }

+440

drivers/clocksource/arm_arch_timer_mmio.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-only 2 + /* 3 + * ARM Generic Memory Mapped Timer support 4 + * 5 + * Split from drivers/clocksource/arm_arch_timer.c 6 + * 7 + * Copyright (C) 2011 ARM Ltd. 8 + * All Rights Reserved 9 + */ 10 + 11 + #define pr_fmt(fmt) "arch_timer_mmio: " fmt 12 + 13 + #include <linux/clockchips.h> 14 + #include <linux/interrupt.h> 15 + #include <linux/io-64-nonatomic-lo-hi.h> 16 + #include <linux/of_irq.h> 17 + #include <linux/of_address.h> 18 + #include <linux/platform_device.h> 19 + 20 + #include <clocksource/arm_arch_timer.h> 21 + 22 + #define CNTTIDR 0x08 23 + #define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4)) 24 + 25 + #define CNTACR(n) (0x40 + ((n) * 4)) 26 + #define CNTACR_RPCT BIT(0) 27 + #define CNTACR_RVCT BIT(1) 28 + #define CNTACR_RFRQ BIT(2) 29 + #define CNTACR_RVOFF BIT(3) 30 + #define CNTACR_RWVT BIT(4) 31 + #define CNTACR_RWPT BIT(5) 32 + 33 + #define CNTPCT_LO 0x00 34 + #define CNTVCT_LO 0x08 35 + #define CNTFRQ 0x10 36 + #define CNTP_CVAL_LO 0x20 37 + #define CNTP_CTL 0x2c 38 + #define CNTV_CVAL_LO 0x30 39 + #define CNTV_CTL 0x3c 40 + 41 + enum arch_timer_access { 42 + PHYS_ACCESS, 43 + VIRT_ACCESS, 44 + }; 45 + 46 + struct arch_timer { 47 + struct clock_event_device evt; 48 + struct clocksource cs; 49 + struct arch_timer_mem *gt_block; 50 + void __iomem *base; 51 + enum arch_timer_access access; 52 + u32 rate; 53 + }; 54 + 55 + #define evt_to_arch_timer(e) container_of(e, struct arch_timer, evt) 56 + #define cs_to_arch_timer(c) container_of(c, struct arch_timer, cs) 57 + 58 + static void arch_timer_mmio_write(struct arch_timer *timer, 59 + enum arch_timer_reg reg, u64 val) 60 + { 61 + switch (timer->access) { 62 + case PHYS_ACCESS: 63 + switch (reg) { 64 + case ARCH_TIMER_REG_CTRL: 65 + writel_relaxed((u32)val, timer->base + CNTP_CTL); 66 + return; 67 + case ARCH_TIMER_REG_CVAL: 68 + /* 69 + * Not guaranteed to be atomic, so the timer 70 + * must be disabled at this point. 71 + */ 72 + writeq_relaxed(val, timer->base + CNTP_CVAL_LO); 73 + return; 74 + } 75 + break; 76 + case VIRT_ACCESS: 77 + switch (reg) { 78 + case ARCH_TIMER_REG_CTRL: 79 + writel_relaxed((u32)val, timer->base + CNTV_CTL); 80 + return; 81 + case ARCH_TIMER_REG_CVAL: 82 + /* Same restriction as above */ 83 + writeq_relaxed(val, timer->base + CNTV_CVAL_LO); 84 + return; 85 + } 86 + break; 87 + } 88 + 89 + /* Should never be here */ 90 + WARN_ON_ONCE(1); 91 + } 92 + 93 + static u32 arch_timer_mmio_read(struct arch_timer *timer, enum arch_timer_reg reg) 94 + { 95 + switch (timer->access) { 96 + case PHYS_ACCESS: 97 + switch (reg) { 98 + case ARCH_TIMER_REG_CTRL: 99 + return readl_relaxed(timer->base + CNTP_CTL); 100 + default: 101 + break; 102 + } 103 + break; 104 + case VIRT_ACCESS: 105 + switch (reg) { 106 + case ARCH_TIMER_REG_CTRL: 107 + return readl_relaxed(timer->base + CNTV_CTL); 108 + default: 109 + break; 110 + } 111 + break; 112 + } 113 + 114 + /* Should never be here */ 115 + WARN_ON_ONCE(1); 116 + return 0; 117 + } 118 + 119 + static noinstr u64 arch_counter_mmio_get_cnt(struct arch_timer *t) 120 + { 121 + int offset_lo = t->access == VIRT_ACCESS ? CNTVCT_LO : CNTPCT_LO; 122 + u32 cnt_lo, cnt_hi, tmp_hi; 123 + 124 + do { 125 + cnt_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4)); 126 + cnt_lo = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo)); 127 + tmp_hi = __le32_to_cpu((__le32 __force)__raw_readl(t->base + offset_lo + 4)); 128 + } while (cnt_hi != tmp_hi); 129 + 130 + return ((u64) cnt_hi << 32) | cnt_lo; 131 + } 132 + 133 + static u64 arch_mmio_counter_read(struct clocksource *cs) 134 + { 135 + struct arch_timer *at = cs_to_arch_timer(cs); 136 + 137 + return arch_counter_mmio_get_cnt(at); 138 + } 139 + 140 + static int arch_timer_mmio_shutdown(struct clock_event_device *clk) 141 + { 142 + struct arch_timer *at = evt_to_arch_timer(clk); 143 + unsigned long ctrl; 144 + 145 + ctrl = arch_timer_mmio_read(at, ARCH_TIMER_REG_CTRL); 146 + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 147 + arch_timer_mmio_write(at, ARCH_TIMER_REG_CTRL, ctrl); 148 + 149 + return 0; 150 + } 151 + 152 + static int arch_timer_mmio_set_next_event(unsigned long evt, 153 + struct clock_event_device *clk) 154 + { 155 + struct arch_timer *timer = evt_to_arch_timer(clk); 156 + unsigned long ctrl; 157 + u64 cnt; 158 + 159 + ctrl = arch_timer_mmio_read(timer, ARCH_TIMER_REG_CTRL); 160 + 161 + /* Timer must be disabled before programming CVAL */ 162 + if (ctrl & ARCH_TIMER_CTRL_ENABLE) { 163 + ctrl &= ~ARCH_TIMER_CTRL_ENABLE; 164 + arch_timer_mmio_write(timer, ARCH_TIMER_REG_CTRL, ctrl); 165 + } 166 + 167 + ctrl |= ARCH_TIMER_CTRL_ENABLE; 168 + ctrl &= ~ARCH_TIMER_CTRL_IT_MASK; 169 + 170 + cnt = arch_counter_mmio_get_cnt(timer); 171 + 172 + arch_timer_mmio_write(timer, ARCH_TIMER_REG_CVAL, evt + cnt); 173 + arch_timer_mmio_write(timer, ARCH_TIMER_REG_CTRL, ctrl); 174 + return 0; 175 + } 176 + 177 + static irqreturn_t arch_timer_mmio_handler(int irq, void *dev_id) 178 + { 179 + struct clock_event_device *evt = dev_id; 180 + struct arch_timer *at = evt_to_arch_timer(evt); 181 + unsigned long ctrl; 182 + 183 + ctrl = arch_timer_mmio_read(at, ARCH_TIMER_REG_CTRL); 184 + if (ctrl & ARCH_TIMER_CTRL_IT_STAT) { 185 + ctrl |= ARCH_TIMER_CTRL_IT_MASK; 186 + arch_timer_mmio_write(at, ARCH_TIMER_REG_CTRL, ctrl); 187 + evt->event_handler(evt); 188 + return IRQ_HANDLED; 189 + } 190 + 191 + return IRQ_NONE; 192 + } 193 + 194 + static struct arch_timer_mem_frame *find_best_frame(struct platform_device *pdev) 195 + { 196 + struct arch_timer_mem_frame *frame, *best_frame = NULL; 197 + struct arch_timer *at = platform_get_drvdata(pdev); 198 + void __iomem *cntctlbase; 199 + u32 cnttidr; 200 + 201 + cntctlbase = ioremap(at->gt_block->cntctlbase, at->gt_block->size); 202 + if (!cntctlbase) { 203 + dev_err(&pdev->dev, "Can't map CNTCTLBase @ %pa\n", 204 + &at->gt_block->cntctlbase); 205 + return NULL; 206 + } 207 + 208 + cnttidr = readl_relaxed(cntctlbase + CNTTIDR); 209 + 210 + /* 211 + * Try to find a virtual capable frame. Otherwise fall back to a 212 + * physical capable frame. 213 + */ 214 + for (int i = 0; i < ARCH_TIMER_MEM_MAX_FRAMES; i++) { 215 + u32 cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT | 216 + CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT; 217 + 218 + frame = &at->gt_block->frame[i]; 219 + if (!frame->valid) 220 + continue; 221 + 222 + /* Try enabling everything, and see what sticks */ 223 + writel_relaxed(cntacr, cntctlbase + CNTACR(i)); 224 + cntacr = readl_relaxed(cntctlbase + CNTACR(i)); 225 + 226 + /* Pick a suitable frame for which we have an IRQ */ 227 + if ((cnttidr & CNTTIDR_VIRT(i)) && 228 + !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT)) && 229 + frame->virt_irq) { 230 + best_frame = frame; 231 + at->access = VIRT_ACCESS; 232 + break; 233 + } 234 + 235 + if ((~cntacr & (CNTACR_RWPT | CNTACR_RPCT)) || 236 + !frame->phys_irq) 237 + continue; 238 + 239 + at->access = PHYS_ACCESS; 240 + best_frame = frame; 241 + } 242 + 243 + iounmap(cntctlbase); 244 + 245 + return best_frame; 246 + } 247 + 248 + static void arch_timer_mmio_setup(struct arch_timer *at, int irq) 249 + { 250 + at->evt = (struct clock_event_device) { 251 + .features = (CLOCK_EVT_FEAT_ONESHOT | 252 + CLOCK_EVT_FEAT_DYNIRQ), 253 + .name = "arch_mem_timer", 254 + .rating = 400, 255 + .cpumask = cpu_possible_mask, 256 + .irq = irq, 257 + .set_next_event = arch_timer_mmio_set_next_event, 258 + .set_state_oneshot_stopped = arch_timer_mmio_shutdown, 259 + .set_state_shutdown = arch_timer_mmio_shutdown, 260 + }; 261 + 262 + at->evt.set_state_shutdown(&at->evt); 263 + 264 + clockevents_config_and_register(&at->evt, at->rate, 0xf, 265 + (unsigned long)CLOCKSOURCE_MASK(56)); 266 + 267 + enable_irq(at->evt.irq); 268 + 269 + at->cs = (struct clocksource) { 270 + .name = "arch_mmio_counter", 271 + .rating = 300, 272 + .read = arch_mmio_counter_read, 273 + .mask = CLOCKSOURCE_MASK(56), 274 + .flags = CLOCK_SOURCE_IS_CONTINUOUS, 275 + }; 276 + 277 + clocksource_register_hz(&at->cs, at->rate); 278 + } 279 + 280 + static int arch_timer_mmio_frame_register(struct platform_device *pdev, 281 + struct arch_timer_mem_frame *frame) 282 + { 283 + struct arch_timer *at = platform_get_drvdata(pdev); 284 + struct device_node *np = pdev->dev.of_node; 285 + int ret, irq; 286 + u32 rate; 287 + 288 + if (!devm_request_mem_region(&pdev->dev, frame->cntbase, frame->size, 289 + "arch_mem_timer")) 290 + return -EBUSY; 291 + 292 + at->base = devm_ioremap(&pdev->dev, frame->cntbase, frame->size); 293 + if (!at->base) { 294 + dev_err(&pdev->dev, "Can't map frame's registers\n"); 295 + return -ENXIO; 296 + } 297 + 298 + /* 299 + * Allow "clock-frequency" to override the probed rate. If neither 300 + * lead to something useful, use the CPU timer frequency as the 301 + * fallback. The nice thing about that last point is that we woudn't 302 + * made it here if we didn't have a valid frequency. 303 + */ 304 + rate = readl_relaxed(at->base + CNTFRQ); 305 + 306 + if (!np || of_property_read_u32(np, "clock-frequency", &at->rate)) 307 + at->rate = rate; 308 + 309 + if (!at->rate) 310 + at->rate = arch_timer_get_rate(); 311 + 312 + irq = at->access == VIRT_ACCESS ? frame->virt_irq : frame->phys_irq; 313 + ret = devm_request_irq(&pdev->dev, irq, arch_timer_mmio_handler, 314 + IRQF_TIMER | IRQF_NO_AUTOEN, "arch_mem_timer", 315 + &at->evt); 316 + if (ret) { 317 + dev_err(&pdev->dev, "Failed to request mem timer irq\n"); 318 + return ret; 319 + } 320 + 321 + /* Afer this point, we're not allowed to fail anymore */ 322 + arch_timer_mmio_setup(at, irq); 323 + return 0; 324 + } 325 + 326 + static int of_populate_gt_block(struct platform_device *pdev, 327 + struct arch_timer *at) 328 + { 329 + struct resource res; 330 + 331 + if (of_address_to_resource(pdev->dev.of_node, 0, &res)) 332 + return -EINVAL; 333 + 334 + at->gt_block->cntctlbase = res.start; 335 + at->gt_block->size = resource_size(&res); 336 + 337 + for_each_available_child_of_node_scoped(pdev->dev.of_node, frame_node) { 338 + struct arch_timer_mem_frame *frame; 339 + u32 n; 340 + 341 + if (of_property_read_u32(frame_node, "frame-number", &n)) { 342 + dev_err(&pdev->dev, FW_BUG "Missing frame-number\n"); 343 + return -EINVAL; 344 + } 345 + if (n >= ARCH_TIMER_MEM_MAX_FRAMES) { 346 + dev_err(&pdev->dev, 347 + FW_BUG "Wrong frame-number, only 0-%u are permitted\n", 348 + ARCH_TIMER_MEM_MAX_FRAMES - 1); 349 + return -EINVAL; 350 + } 351 + 352 + frame = &at->gt_block->frame[n]; 353 + 354 + if (frame->valid) { 355 + dev_err(&pdev->dev, FW_BUG "Duplicated frame-number\n"); 356 + return -EINVAL; 357 + } 358 + 359 + if (of_address_to_resource(frame_node, 0, &res)) 360 + return -EINVAL; 361 + 362 + frame->cntbase = res.start; 363 + frame->size = resource_size(&res); 364 + 365 + frame->phys_irq = irq_of_parse_and_map(frame_node, 0); 366 + frame->virt_irq = irq_of_parse_and_map(frame_node, 1); 367 + 368 + frame->valid = true; 369 + } 370 + 371 + return 0; 372 + } 373 + 374 + static int arch_timer_mmio_probe(struct platform_device *pdev) 375 + { 376 + struct arch_timer_mem_frame *frame; 377 + struct arch_timer *at; 378 + struct device_node *np; 379 + int ret; 380 + 381 + np = pdev->dev.of_node; 382 + 383 + at = devm_kmalloc(&pdev->dev, sizeof(*at), GFP_KERNEL | __GFP_ZERO); 384 + if (!at) 385 + return -ENOMEM; 386 + 387 + if (np) { 388 + at->gt_block = devm_kmalloc(&pdev->dev, sizeof(*at->gt_block), 389 + GFP_KERNEL | __GFP_ZERO); 390 + if (!at->gt_block) 391 + return -ENOMEM; 392 + ret = of_populate_gt_block(pdev, at); 393 + if (ret) 394 + return ret; 395 + } else { 396 + at->gt_block = dev_get_platdata(&pdev->dev); 397 + } 398 + 399 + platform_set_drvdata(pdev, at); 400 + 401 + frame = find_best_frame(pdev); 402 + if (!frame) { 403 + dev_err(&pdev->dev, 404 + "Unable to find a suitable frame in timer @ %pa\n", 405 + &at->gt_block->cntctlbase); 406 + return -EINVAL; 407 + } 408 + 409 + ret = arch_timer_mmio_frame_register(pdev, frame); 410 + if (!ret) 411 + dev_info(&pdev->dev, 412 + "mmio timer running at %lu.%02luMHz (%s)\n", 413 + (unsigned long)at->rate / 1000000, 414 + (unsigned long)(at->rate / 10000) % 100, 415 + at->access == VIRT_ACCESS ? "virt" : "phys"); 416 + 417 + return ret; 418 + } 419 + 420 + static const struct of_device_id arch_timer_mmio_of_table[] = { 421 + { .compatible = "arm,armv7-timer-mem", }, 422 + {} 423 + }; 424 + 425 + static struct platform_driver arch_timer_mmio_drv = { 426 + .driver = { 427 + .name = "arch-timer-mmio", 428 + .of_match_table = arch_timer_mmio_of_table, 429 + }, 430 + .probe = arch_timer_mmio_probe, 431 + }; 432 + builtin_platform_driver(arch_timer_mmio_drv); 433 + 434 + static struct platform_driver arch_timer_mmio_acpi_drv = { 435 + .driver = { 436 + .name = "gtdt-arm-mmio-timer", 437 + }, 438 + .probe = arch_timer_mmio_probe, 439 + }; 440 + builtin_platform_driver(arch_timer_mmio_acpi_drv);

+39 -5

drivers/clocksource/arm_global_timer.c

··· 263 263 register_current_timer_delay(&gt_delay_timer); 264 264 } 265 265 266 - static int __init gt_clocksource_init(void) 266 + static int __init gt_clocksource_init(unsigned int psv) 267 267 { 268 268 writel(0, gt_base + GT_CONTROL); 269 269 writel(0, gt_base + GT_COUNTER0); 270 270 writel(0, gt_base + GT_COUNTER1); 271 271 /* set prescaler and enable timer on all the cores */ 272 - writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, 273 - CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) | 272 + writel(FIELD_PREP(GT_CONTROL_PRESCALER_MASK, psv - 1) | 274 273 GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL); 275 274 276 275 #ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK ··· 337 338 return NOTIFY_DONE; 338 339 } 339 340 341 + struct gt_prescaler_config { 342 + const char *compatible; 343 + unsigned long prescaler; 344 + }; 345 + 346 + static const struct gt_prescaler_config gt_prescaler_configs[] = { 347 + /* 348 + * On am43 the global timer clock is a child of the clock used for CPU 349 + * OPPs, so the initial prescaler has to be compatible with all OPPs 350 + * which are 300, 600, 720, 800 and 1000 with a fixed divider of 2, this 351 + * gives us a GCD of 10. Initial frequency is 1000, so the prescaler is 352 + * 50. 353 + */ 354 + { .compatible = "ti,am43", .prescaler = 50 }, 355 + { .compatible = "xlnx,zynq-7000", .prescaler = 2 }, 356 + { .compatible = NULL } 357 + }; 358 + 359 + static unsigned long gt_get_initial_prescaler_value(struct device_node *np) 360 + { 361 + const struct gt_prescaler_config *config; 362 + 363 + if (CONFIG_ARM_GT_INITIAL_PRESCALER_VAL != 0) 364 + return CONFIG_ARM_GT_INITIAL_PRESCALER_VAL; 365 + 366 + for (config = gt_prescaler_configs; config->compatible; config++) { 367 + if (of_machine_is_compatible(config->compatible)) 368 + return config->prescaler; 369 + } 370 + 371 + return 1; 372 + } 373 + 340 374 static int __init global_timer_of_register(struct device_node *np) 341 375 { 342 376 struct clk *gt_clk; 343 377 static unsigned long gt_clk_rate; 344 378 int err; 379 + unsigned long psv; 345 380 346 381 /* 347 382 * In A9 r2p0 the comparators for each processor with the global timer ··· 411 378 goto out_unmap; 412 379 } 413 380 381 + psv = gt_get_initial_prescaler_value(np); 414 382 gt_clk_rate = clk_get_rate(gt_clk); 415 - gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL; 383 + gt_target_rate = gt_clk_rate / psv; 416 384 gt_clk_rate_change_nb.notifier_call = 417 385 gt_clk_rate_change_cb; 418 386 err = clk_notifier_register(gt_clk, &gt_clk_rate_change_nb); ··· 438 404 } 439 405 440 406 /* Register and immediately configure the timer on the boot CPU */ 441 - err = gt_clocksource_init(); 407 + err = gt_clocksource_init(psv); 442 408 if (err) 443 409 goto out_irq; 444 410

+16 -7

drivers/clocksource/clps711x-timer.c

··· 78 78 unsigned int irq = irq_of_parse_and_map(np, 0); 79 79 struct clk *clock = of_clk_get(np, 0); 80 80 void __iomem *base = of_iomap(np, 0); 81 + int ret = 0; 81 82 82 83 if (!base) 83 84 return -ENOMEM; 84 - if (!irq) 85 - return -EINVAL; 86 - if (IS_ERR(clock)) 87 - return PTR_ERR(clock); 85 + if (!irq) { 86 + ret = -EINVAL; 87 + goto unmap_io; 88 + } 89 + if (IS_ERR(clock)) { 90 + ret = PTR_ERR(clock); 91 + goto unmap_io; 92 + } 88 93 89 94 switch (of_alias_get_id(np, "timer")) { 90 95 case CLPS711X_CLKSRC_CLOCKSOURCE: 91 96 clps711x_clksrc_init(clock, base); 92 97 break; 93 98 case CLPS711X_CLKSRC_CLOCKEVENT: 94 - return _clps711x_clkevt_init(clock, base, irq); 99 + ret = _clps711x_clkevt_init(clock, base, irq); 100 + break; 95 101 default: 96 - return -EINVAL; 102 + ret = -EINVAL; 103 + break; 97 104 } 98 105 99 - return 0; 106 + unmap_io: 107 + iounmap(base); 108 + return ret; 100 109 } 101 110 TIMER_OF_DECLARE(clps711x, "cirrus,ep7209-timer", clps711x_timer_init);

+16 -11

drivers/clocksource/ingenic-sysost.c

··· 127 127 return 2; /* /16 divider */ 128 128 } 129 129 130 - static long ingenic_ost_round_rate(struct clk_hw *hw, unsigned long req_rate, 131 - unsigned long *parent_rate) 130 + static int ingenic_ost_determine_rate(struct clk_hw *hw, 131 + struct clk_rate_request *req) 132 132 { 133 - unsigned long rate = *parent_rate; 133 + unsigned long rate = req->best_parent_rate; 134 134 u8 prescale; 135 135 136 - if (req_rate > rate) 137 - return rate; 136 + if (req->rate > rate) { 137 + req->rate = rate; 138 138 139 - prescale = ingenic_ost_get_prescale(rate, req_rate); 139 + return 0; 140 + } 140 141 141 - return rate >> (prescale * 2); 142 + prescale = ingenic_ost_get_prescale(rate, req->rate); 143 + 144 + req->rate = rate >> (prescale * 2); 145 + 146 + return 0; 142 147 } 143 148 144 149 static int ingenic_ost_percpu_timer_set_rate(struct clk_hw *hw, unsigned long req_rate, ··· 180 175 181 176 static const struct clk_ops ingenic_ost_percpu_timer_ops = { 182 177 .recalc_rate = ingenic_ost_percpu_timer_recalc_rate, 183 - .round_rate = ingenic_ost_round_rate, 184 - .set_rate = ingenic_ost_percpu_timer_set_rate, 178 + .determine_rate = ingenic_ost_determine_rate, 179 + .set_rate = ingenic_ost_percpu_timer_set_rate, 185 180 }; 186 181 187 182 static const struct clk_ops ingenic_ost_global_timer_ops = { 188 183 .recalc_rate = ingenic_ost_global_timer_recalc_rate, 189 - .round_rate = ingenic_ost_round_rate, 190 - .set_rate = ingenic_ost_global_timer_set_rate, 184 + .determine_rate = ingenic_ost_determine_rate, 185 + .set_rate = ingenic_ost_global_timer_set_rate, 191 186 }; 192 187 193 188 static const char * const ingenic_ost_clk_parents[] = { "ext" };

+1

drivers/clocksource/scx200_hrt.c

··· 52 52 .mask = CLOCKSOURCE_MASK(32), 53 53 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 54 54 /* mult, shift are set based on mhz27 flag */ 55 + .owner = THIS_MODULE, 55 56 }; 56 57 57 58 static int __init init_hrt_clocksource(void)

+63 -29

drivers/clocksource/sh_cmt.c

··· 578 578 return IRQ_HANDLED; 579 579 } 580 580 581 - static int sh_cmt_start(struct sh_cmt_channel *ch, unsigned long flag) 581 + static int sh_cmt_start_clocksource(struct sh_cmt_channel *ch) 582 582 { 583 583 int ret = 0; 584 584 unsigned long flags; 585 585 586 - if (flag & FLAG_CLOCKSOURCE) 587 - pm_runtime_get_sync(&ch->cmt->pdev->dev); 586 + pm_runtime_get_sync(&ch->cmt->pdev->dev); 588 587 589 588 raw_spin_lock_irqsave(&ch->lock, flags); 590 589 591 - if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 592 - if (flag & FLAG_CLOCKEVENT) 593 - pm_runtime_get_sync(&ch->cmt->pdev->dev); 590 + if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 594 591 ret = sh_cmt_enable(ch); 595 - } 596 592 597 593 if (ret) 598 594 goto out; 599 - ch->flags |= flag; 595 + 596 + ch->flags |= FLAG_CLOCKSOURCE; 600 597 601 598 /* setup timeout if no clockevent */ 602 - if (ch->cmt->num_channels == 1 && 603 - flag == FLAG_CLOCKSOURCE && (!(ch->flags & FLAG_CLOCKEVENT))) 599 + if (ch->cmt->num_channels == 1 && !(ch->flags & FLAG_CLOCKEVENT)) 604 600 __sh_cmt_set_next(ch, ch->max_match_value); 605 - out: 601 + out: 606 602 raw_spin_unlock_irqrestore(&ch->lock, flags); 607 603 608 604 return ret; 609 605 } 610 606 611 - static void sh_cmt_stop(struct sh_cmt_channel *ch, unsigned long flag) 607 + static void sh_cmt_stop_clocksource(struct sh_cmt_channel *ch) 612 608 { 613 609 unsigned long flags; 614 610 unsigned long f; ··· 612 616 raw_spin_lock_irqsave(&ch->lock, flags); 613 617 614 618 f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); 615 - ch->flags &= ~flag; 616 619 617 - if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 620 + ch->flags &= ~FLAG_CLOCKSOURCE; 621 + 622 + if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) 618 623 sh_cmt_disable(ch); 619 - if (flag & FLAG_CLOCKEVENT) 620 - pm_runtime_put(&ch->cmt->pdev->dev); 621 - } 622 - 623 - /* adjust the timeout to maximum if only clocksource left */ 624 - if ((flag == FLAG_CLOCKEVENT) && (ch->flags & FLAG_CLOCKSOURCE)) 625 - __sh_cmt_set_next(ch, ch->max_match_value); 626 624 627 625 raw_spin_unlock_irqrestore(&ch->lock, flags); 628 626 629 - if (flag & FLAG_CLOCKSOURCE) 627 + pm_runtime_put(&ch->cmt->pdev->dev); 628 + } 629 + 630 + static int sh_cmt_start_clockevent(struct sh_cmt_channel *ch) 631 + { 632 + int ret = 0; 633 + unsigned long flags; 634 + 635 + raw_spin_lock_irqsave(&ch->lock, flags); 636 + 637 + if (!(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 638 + pm_runtime_get_sync(&ch->cmt->pdev->dev); 639 + ret = sh_cmt_enable(ch); 640 + } 641 + 642 + if (ret) 643 + goto out; 644 + 645 + ch->flags |= FLAG_CLOCKEVENT; 646 + out: 647 + raw_spin_unlock_irqrestore(&ch->lock, flags); 648 + 649 + return ret; 650 + } 651 + 652 + static void sh_cmt_stop_clockevent(struct sh_cmt_channel *ch) 653 + { 654 + unsigned long flags; 655 + unsigned long f; 656 + 657 + raw_spin_lock_irqsave(&ch->lock, flags); 658 + 659 + f = ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE); 660 + 661 + ch->flags &= ~FLAG_CLOCKEVENT; 662 + 663 + if (f && !(ch->flags & (FLAG_CLOCKEVENT | FLAG_CLOCKSOURCE))) { 664 + sh_cmt_disable(ch); 630 665 pm_runtime_put(&ch->cmt->pdev->dev); 666 + } 667 + 668 + /* adjust the timeout to maximum if only clocksource left */ 669 + if (ch->flags & FLAG_CLOCKSOURCE) 670 + __sh_cmt_set_next(ch, ch->max_match_value); 671 + 672 + raw_spin_unlock_irqrestore(&ch->lock, flags); 631 673 } 632 674 633 675 static struct sh_cmt_channel *cs_to_sh_cmt(struct clocksource *cs) ··· 706 672 707 673 ch->total_cycles = 0; 708 674 709 - ret = sh_cmt_start(ch, FLAG_CLOCKSOURCE); 675 + ret = sh_cmt_start_clocksource(ch); 710 676 if (!ret) 711 677 ch->cs_enabled = true; 712 678 ··· 719 685 720 686 WARN_ON(!ch->cs_enabled); 721 687 722 - sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 688 + sh_cmt_stop_clocksource(ch); 723 689 ch->cs_enabled = false; 724 690 } 725 691 ··· 730 696 if (!ch->cs_enabled) 731 697 return; 732 698 733 - sh_cmt_stop(ch, FLAG_CLOCKSOURCE); 699 + sh_cmt_stop_clocksource(ch); 734 700 dev_pm_genpd_suspend(&ch->cmt->pdev->dev); 735 701 } 736 702 ··· 742 708 return; 743 709 744 710 dev_pm_genpd_resume(&ch->cmt->pdev->dev); 745 - sh_cmt_start(ch, FLAG_CLOCKSOURCE); 711 + sh_cmt_start_clocksource(ch); 746 712 } 747 713 748 714 static int sh_cmt_register_clocksource(struct sh_cmt_channel *ch, ··· 774 740 775 741 static void sh_cmt_clock_event_start(struct sh_cmt_channel *ch, int periodic) 776 742 { 777 - sh_cmt_start(ch, FLAG_CLOCKEVENT); 743 + sh_cmt_start_clockevent(ch); 778 744 779 745 if (periodic) 780 746 sh_cmt_set_next(ch, ((ch->cmt->rate + HZ/2) / HZ) - 1); ··· 786 752 { 787 753 struct sh_cmt_channel *ch = ced_to_sh_cmt(ced); 788 754 789 - sh_cmt_stop(ch, FLAG_CLOCKEVENT); 755 + sh_cmt_stop_clockevent(ch); 790 756 return 0; 791 757 } 792 758 ··· 797 763 798 764 /* deal with old setting first */ 799 765 if (clockevent_state_oneshot(ced) || clockevent_state_periodic(ced)) 800 - sh_cmt_stop(ch, FLAG_CLOCKEVENT); 766 + sh_cmt_stop_clockevent(ch); 801 767 802 768 dev_info(&ch->cmt->pdev->dev, "ch%u: used for %s clock events\n", 803 769 ch->index, periodic ? "periodic" : "oneshot");

+1

drivers/clocksource/timer-cs5535.c

··· 101 101 .tick_resume = mfgpt_shutdown, 102 102 .set_next_event = mfgpt_next_event, 103 103 .rating = 250, 104 + .owner = THIS_MODULE, 104 105 }; 105 106 106 107 static irqreturn_t mfgpt_tick(int irq, void *dev_id)

+1 -1

drivers/clocksource/timer-econet-en751221.c

··· 146 146 for_each_possible_cpu(i) { 147 147 struct clock_event_device *cd = &per_cpu(econet_timer_pcpu, i); 148 148 149 - cd->rating = 310, 149 + cd->rating = 310; 150 150 cd->features = CLOCK_EVT_FEAT_ONESHOT | 151 151 CLOCK_EVT_FEAT_C3STOP | 152 152 CLOCK_EVT_FEAT_PERCPU;

+382

drivers/clocksource/timer-nxp-pit.c

··· 1 + // SPDX-License-Identifier: GPL-2.0-or-later 2 + /* 3 + * Copyright 2012-2013 Freescale Semiconductor, Inc. 4 + * Copyright 2018,2021-2025 NXP 5 + */ 6 + #include <linux/interrupt.h> 7 + #include <linux/clockchips.h> 8 + #include <linux/cpuhotplug.h> 9 + #include <linux/clk.h> 10 + #include <linux/of_address.h> 11 + #include <linux/of_irq.h> 12 + #include <linux/sched_clock.h> 13 + #include <linux/platform_device.h> 14 + 15 + /* 16 + * Each pit takes 0x10 Bytes register space 17 + */ 18 + #define PIT0_OFFSET 0x100 19 + #define PIT_CH(n) (PIT0_OFFSET + 0x10 * (n)) 20 + 21 + #define PITMCR(__base) (__base) 22 + 23 + #define PITMCR_FRZ BIT(0) 24 + #define PITMCR_MDIS BIT(1) 25 + 26 + #define PITLDVAL(__base) (__base) 27 + #define PITTCTRL(__base) ((__base) + 0x08) 28 + 29 + #define PITCVAL_OFFSET 0x04 30 + #define PITCVAL(__base) ((__base) + 0x04) 31 + 32 + #define PITTCTRL_TEN BIT(0) 33 + #define PITTCTRL_TIE BIT(1) 34 + 35 + #define PITTFLG(__base) ((__base) + 0x0c) 36 + 37 + #define PITTFLG_TIF BIT(0) 38 + 39 + struct pit_timer { 40 + void __iomem *clksrc_base; 41 + void __iomem *clkevt_base; 42 + struct clock_event_device ced; 43 + struct clocksource cs; 44 + int rate; 45 + }; 46 + 47 + struct pit_timer_data { 48 + int max_pit_instances; 49 + }; 50 + 51 + static DEFINE_PER_CPU(struct pit_timer *, pit_timers); 52 + 53 + /* 54 + * Global structure for multiple PITs initialization 55 + */ 56 + static int pit_instances; 57 + static int max_pit_instances = 1; 58 + 59 + static void __iomem *sched_clock_base; 60 + 61 + static inline struct pit_timer *ced_to_pit(struct clock_event_device *ced) 62 + { 63 + return container_of(ced, struct pit_timer, ced); 64 + } 65 + 66 + static inline struct pit_timer *cs_to_pit(struct clocksource *cs) 67 + { 68 + return container_of(cs, struct pit_timer, cs); 69 + } 70 + 71 + static inline void pit_module_enable(void __iomem *base) 72 + { 73 + writel(0, PITMCR(base)); 74 + } 75 + 76 + static inline void pit_module_disable(void __iomem *base) 77 + { 78 + writel(PITMCR_MDIS, PITMCR(base)); 79 + } 80 + 81 + static inline void pit_timer_enable(void __iomem *base, bool tie) 82 + { 83 + u32 val = PITTCTRL_TEN | (tie ? PITTCTRL_TIE : 0); 84 + 85 + writel(val, PITTCTRL(base)); 86 + } 87 + 88 + static inline void pit_timer_disable(void __iomem *base) 89 + { 90 + writel(0, PITTCTRL(base)); 91 + } 92 + 93 + static inline void pit_timer_set_counter(void __iomem *base, unsigned int cnt) 94 + { 95 + writel(cnt, PITLDVAL(base)); 96 + } 97 + 98 + static inline void pit_timer_irqack(struct pit_timer *pit) 99 + { 100 + writel(PITTFLG_TIF, PITTFLG(pit->clkevt_base)); 101 + } 102 + 103 + static u64 notrace pit_read_sched_clock(void) 104 + { 105 + return ~readl(sched_clock_base); 106 + } 107 + 108 + static u64 pit_timer_clocksource_read(struct clocksource *cs) 109 + { 110 + struct pit_timer *pit = cs_to_pit(cs); 111 + 112 + return (u64)~readl(PITCVAL(pit->clksrc_base)); 113 + } 114 + 115 + static int pit_clocksource_init(struct pit_timer *pit, const char *name, 116 + void __iomem *base, unsigned long rate) 117 + { 118 + /* 119 + * The channels 0 and 1 can be chained to build a 64-bit 120 + * timer. Let's use the channel 2 as a clocksource and leave 121 + * the channels 0 and 1 unused for anyone else who needs them 122 + */ 123 + pit->clksrc_base = base + PIT_CH(2); 124 + pit->cs.name = name; 125 + pit->cs.rating = 300; 126 + pit->cs.read = pit_timer_clocksource_read; 127 + pit->cs.mask = CLOCKSOURCE_MASK(32); 128 + pit->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; 129 + 130 + /* set the max load value and start the clock source counter */ 131 + pit_timer_disable(pit->clksrc_base); 132 + pit_timer_set_counter(pit->clksrc_base, ~0); 133 + pit_timer_enable(pit->clksrc_base, 0); 134 + 135 + sched_clock_base = pit->clksrc_base + PITCVAL_OFFSET; 136 + sched_clock_register(pit_read_sched_clock, 32, rate); 137 + 138 + return clocksource_register_hz(&pit->cs, rate); 139 + } 140 + 141 + static int pit_set_next_event(unsigned long delta, struct clock_event_device *ced) 142 + { 143 + struct pit_timer *pit = ced_to_pit(ced); 144 + 145 + /* 146 + * set a new value to PITLDVAL register will not restart the timer, 147 + * to abort the current cycle and start a timer period with the new 148 + * value, the timer must be disabled and enabled again. 149 + * and the PITLAVAL should be set to delta minus one according to pit 150 + * hardware requirement. 151 + */ 152 + pit_timer_disable(pit->clkevt_base); 153 + pit_timer_set_counter(pit->clkevt_base, delta - 1); 154 + pit_timer_enable(pit->clkevt_base, true); 155 + 156 + return 0; 157 + } 158 + 159 + static int pit_shutdown(struct clock_event_device *ced) 160 + { 161 + struct pit_timer *pit = ced_to_pit(ced); 162 + 163 + pit_timer_disable(pit->clkevt_base); 164 + 165 + return 0; 166 + } 167 + 168 + static int pit_set_periodic(struct clock_event_device *ced) 169 + { 170 + struct pit_timer *pit = ced_to_pit(ced); 171 + 172 + pit_set_next_event(pit->rate / HZ, ced); 173 + 174 + return 0; 175 + } 176 + 177 + static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) 178 + { 179 + struct clock_event_device *ced = dev_id; 180 + struct pit_timer *pit = ced_to_pit(ced); 181 + 182 + pit_timer_irqack(pit); 183 + 184 + /* 185 + * pit hardware doesn't support oneshot, it will generate an interrupt 186 + * and reload the counter value from PITLDVAL when PITCVAL reach zero, 187 + * and start the counter again. So software need to disable the timer 188 + * to stop the counter loop in ONESHOT mode. 189 + */ 190 + if (likely(clockevent_state_oneshot(ced))) 191 + pit_timer_disable(pit->clkevt_base); 192 + 193 + ced->event_handler(ced); 194 + 195 + return IRQ_HANDLED; 196 + } 197 + 198 + static int pit_clockevent_per_cpu_init(struct pit_timer *pit, const char *name, 199 + void __iomem *base, unsigned long rate, 200 + int irq, unsigned int cpu) 201 + { 202 + int ret; 203 + 204 + /* 205 + * The channels 0 and 1 can be chained to build a 64-bit 206 + * timer. Let's use the channel 3 as a clockevent and leave 207 + * the channels 0 and 1 unused for anyone else who needs them 208 + */ 209 + pit->clkevt_base = base + PIT_CH(3); 210 + pit->rate = rate; 211 + 212 + pit_timer_disable(pit->clkevt_base); 213 + 214 + pit_timer_irqack(pit); 215 + 216 + ret = request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_NOBALANCING, 217 + name, &pit->ced); 218 + if (ret) 219 + return ret; 220 + 221 + pit->ced.cpumask = cpumask_of(cpu); 222 + pit->ced.irq = irq; 223 + 224 + pit->ced.name = name; 225 + pit->ced.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 226 + pit->ced.set_state_shutdown = pit_shutdown; 227 + pit->ced.set_state_periodic = pit_set_periodic; 228 + pit->ced.set_next_event = pit_set_next_event; 229 + pit->ced.rating = 300; 230 + 231 + per_cpu(pit_timers, cpu) = pit; 232 + 233 + return 0; 234 + } 235 + 236 + static void pit_clockevent_per_cpu_exit(struct pit_timer *pit, unsigned int cpu) 237 + { 238 + pit_timer_disable(pit->clkevt_base); 239 + free_irq(pit->ced.irq, &pit->ced); 240 + per_cpu(pit_timers, cpu) = NULL; 241 + } 242 + 243 + static int pit_clockevent_starting_cpu(unsigned int cpu) 244 + { 245 + struct pit_timer *pit = per_cpu(pit_timers, cpu); 246 + int ret; 247 + 248 + if (!pit) 249 + return 0; 250 + 251 + ret = irq_force_affinity(pit->ced.irq, cpumask_of(cpu)); 252 + if (ret) { 253 + pit_clockevent_per_cpu_exit(pit, cpu); 254 + return ret; 255 + } 256 + 257 + /* 258 + * The value for the LDVAL register trigger is calculated as: 259 + * LDVAL trigger = (period / clock period) - 1 260 + * The pit is a 32-bit down count timer, when the counter value 261 + * reaches 0, it will generate an interrupt, thus the minimal 262 + * LDVAL trigger value is 1. And then the min_delta is 263 + * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit. 264 + */ 265 + clockevents_config_and_register(&pit->ced, pit->rate, 2, 0xffffffff); 266 + 267 + return 0; 268 + } 269 + 270 + static int pit_timer_init(struct device_node *np) 271 + { 272 + struct pit_timer *pit; 273 + struct clk *pit_clk; 274 + void __iomem *timer_base; 275 + const char *name = of_node_full_name(np); 276 + unsigned long clk_rate; 277 + int irq, ret; 278 + 279 + pit = kzalloc(sizeof(*pit), GFP_KERNEL); 280 + if (!pit) 281 + return -ENOMEM; 282 + 283 + ret = -ENXIO; 284 + timer_base = of_iomap(np, 0); 285 + if (!timer_base) { 286 + pr_err("Failed to iomap\n"); 287 + goto out_kfree; 288 + } 289 + 290 + ret = -EINVAL; 291 + irq = irq_of_parse_and_map(np, 0); 292 + if (irq <= 0) { 293 + pr_err("Failed to irq_of_parse_and_map\n"); 294 + goto out_iounmap; 295 + } 296 + 297 + pit_clk = of_clk_get(np, 0); 298 + if (IS_ERR(pit_clk)) { 299 + ret = PTR_ERR(pit_clk); 300 + goto out_irq_dispose_mapping; 301 + } 302 + 303 + ret = clk_prepare_enable(pit_clk); 304 + if (ret) 305 + goto out_clk_put; 306 + 307 + clk_rate = clk_get_rate(pit_clk); 308 + 309 + pit_module_disable(timer_base); 310 + 311 + ret = pit_clocksource_init(pit, name, timer_base, clk_rate); 312 + if (ret) { 313 + pr_err("Failed to initialize clocksource '%pOF'\n", np); 314 + goto out_pit_module_disable; 315 + } 316 + 317 + ret = pit_clockevent_per_cpu_init(pit, name, timer_base, clk_rate, irq, pit_instances); 318 + if (ret) { 319 + pr_err("Failed to initialize clockevent '%pOF'\n", np); 320 + goto out_pit_clocksource_unregister; 321 + } 322 + 323 + /* enable the pit module */ 324 + pit_module_enable(timer_base); 325 + 326 + pit_instances++; 327 + 328 + if (pit_instances == max_pit_instances) { 329 + ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "PIT timer:starting", 330 + pit_clockevent_starting_cpu, NULL); 331 + if (ret < 0) 332 + goto out_pit_clocksource_unregister; 333 + } 334 + 335 + return 0; 336 + 337 + out_pit_clocksource_unregister: 338 + clocksource_unregister(&pit->cs); 339 + out_pit_module_disable: 340 + pit_module_disable(timer_base); 341 + clk_disable_unprepare(pit_clk); 342 + out_clk_put: 343 + clk_put(pit_clk); 344 + out_irq_dispose_mapping: 345 + irq_dispose_mapping(irq); 346 + out_iounmap: 347 + iounmap(timer_base); 348 + out_kfree: 349 + kfree(pit); 350 + 351 + return ret; 352 + } 353 + 354 + static int pit_timer_probe(struct platform_device *pdev) 355 + { 356 + const struct pit_timer_data *pit_timer_data; 357 + 358 + pit_timer_data = of_device_get_match_data(&pdev->dev); 359 + if (pit_timer_data) 360 + max_pit_instances = pit_timer_data->max_pit_instances; 361 + 362 + return pit_timer_init(pdev->dev.of_node); 363 + } 364 + 365 + static struct pit_timer_data s32g2_data = { .max_pit_instances = 2 }; 366 + 367 + static const struct of_device_id pit_timer_of_match[] = { 368 + { .compatible = "nxp,s32g2-pit", .data = &s32g2_data }, 369 + { } 370 + }; 371 + MODULE_DEVICE_TABLE(of, pit_timer_of_match); 372 + 373 + static struct platform_driver nxp_pit_driver = { 374 + .driver = { 375 + .name = "nxp-pit", 376 + .of_match_table = pit_timer_of_match, 377 + }, 378 + .probe = pit_timer_probe, 379 + }; 380 + module_platform_driver(nxp_pit_driver); 381 + 382 + TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);

+2

drivers/clocksource/timer-nxp-stm.c

··· 201 201 stm_timer->cs.resume = nxp_stm_clocksource_resume; 202 202 stm_timer->cs.mask = CLOCKSOURCE_MASK(32); 203 203 stm_timer->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; 204 + stm_timer->cs.owner = THIS_MODULE; 204 205 205 206 ret = clocksource_register_hz(&stm_timer->cs, stm_timer->rate); 206 207 if (ret) ··· 315 314 stm_timer->ced.cpumask = cpumask_of(cpu); 316 315 stm_timer->ced.rating = 460; 317 316 stm_timer->ced.irq = irq; 317 + stm_timer->ced.owner = THIS_MODULE; 318 318 319 319 per_cpu(stm_timers, cpu) = stm_timer; 320 320

+27 -15

drivers/clocksource/timer-rtl-otto.c

··· 38 38 #define RTTM_BIT_COUNT 28 39 39 #define RTTM_MIN_DELTA 8 40 40 #define RTTM_MAX_DELTA CLOCKSOURCE_MASK(28) 41 + #define RTTM_MAX_DIVISOR GENMASK(15, 0) 41 42 42 43 /* 43 - * Timers are derived from the LXB clock frequency. Usually this is a fixed 44 - * multiple of the 25 MHz oscillator. The 930X SOC is an exception from that. 45 - * Its LXB clock has only dividers and uses the switch PLL of 2.45 GHz as its 46 - * base. The only meaningful frequencies we can achieve from that are 175.000 47 - * MHz and 153.125 MHz. The greatest common divisor of all explained possible 48 - * speeds is 3125000. Pin the timers to this 3.125 MHz reference frequency. 44 + * Timers are derived from the lexra bus (LXB) clock frequency. This is 175 MHz 45 + * on RTL930x and 200 MHz on the other platforms. With 3.125 MHz choose a common 46 + * divisor to have enough range and detail. This provides comparability between 47 + * the different platforms. 49 48 */ 50 49 #define RTTM_TICKS_PER_SEC 3125000 51 50 ··· 54 55 }; 55 56 56 57 /* Simple internal register functions */ 57 - static inline void rttm_set_counter(void __iomem *base, unsigned int counter) 58 - { 59 - iowrite32(counter, base + RTTM_CNT); 60 - } 61 - 62 58 static inline unsigned int rttm_get_counter(void __iomem *base) 63 59 { 64 60 return ioread32(base + RTTM_CNT); ··· 106 112 return IRQ_HANDLED; 107 113 } 108 114 115 + static void rttm_bounce_timer(void __iomem *base, u32 mode) 116 + { 117 + /* 118 + * When a running timer has less than ~5us left, a stop/start sequence 119 + * might fail. While the details are unknown the most evident effect is 120 + * that the subsequent interrupt will not be fired. 121 + * 122 + * As a workaround issue an intermediate restart with a very slow 123 + * frequency of ~3kHz keeping the target counter (>=8). So the follow 124 + * up restart will always be issued outside the critical window. 125 + */ 126 + 127 + rttm_disable_timer(base); 128 + rttm_enable_timer(base, mode, RTTM_MAX_DIVISOR); 129 + } 130 + 109 131 static void rttm_stop_timer(void __iomem *base) 110 132 { 111 133 rttm_disable_timer(base); ··· 130 120 131 121 static void rttm_start_timer(struct timer_of *to, u32 mode) 132 122 { 133 - rttm_set_counter(to->of_base.base, 0); 134 123 rttm_enable_timer(to->of_base.base, mode, to->of_clk.rate / RTTM_TICKS_PER_SEC); 135 124 } 136 125 ··· 138 129 struct timer_of *to = to_timer_of(clkevt); 139 130 140 131 RTTM_DEBUG(to->of_base.base); 141 - rttm_stop_timer(to->of_base.base); 132 + rttm_bounce_timer(to->of_base.base, RTTM_CTRL_COUNTER); 133 + rttm_disable_timer(to->of_base.base); 142 134 rttm_set_period(to->of_base.base, delta); 143 135 rttm_start_timer(to, RTTM_CTRL_COUNTER); 144 136 ··· 151 141 struct timer_of *to = to_timer_of(clkevt); 152 142 153 143 RTTM_DEBUG(to->of_base.base); 154 - rttm_stop_timer(to->of_base.base); 144 + rttm_bounce_timer(to->of_base.base, RTTM_CTRL_COUNTER); 145 + rttm_disable_timer(to->of_base.base); 155 146 rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); 156 147 rttm_start_timer(to, RTTM_CTRL_COUNTER); 157 148 ··· 164 153 struct timer_of *to = to_timer_of(clkevt); 165 154 166 155 RTTM_DEBUG(to->of_base.base); 167 - rttm_stop_timer(to->of_base.base); 156 + rttm_bounce_timer(to->of_base.base, RTTM_CTRL_TIMER); 157 + rttm_disable_timer(to->of_base.base); 168 158 rttm_set_period(to->of_base.base, RTTM_TICKS_PER_SEC / HZ); 169 159 rttm_start_timer(to, RTTM_CTRL_TIMER); 170 160

+1

drivers/clocksource/timer-stm32-lp.c

··· 211 211 priv->clkevt.rating = STM32_LP_RATING; 212 212 priv->clkevt.suspend = stm32_clkevent_lp_suspend; 213 213 priv->clkevt.resume = stm32_clkevent_lp_resume; 214 + priv->clkevt.owner = THIS_MODULE; 214 215 215 216 clockevents_config_and_register(&priv->clkevt, rate, 0x1, 216 217 STM32_LPTIM_MAX_ARR);

+2

drivers/clocksource/timer-sun5i.c

··· 185 185 cs->clksrc.read = sun5i_clksrc_read; 186 186 cs->clksrc.mask = CLOCKSOURCE_MASK(32); 187 187 cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS; 188 + cs->clksrc.owner = THIS_MODULE; 188 189 189 190 ret = clocksource_register_hz(&cs->clksrc, rate); 190 191 if (ret) { ··· 215 214 ce->clkevt.rating = 340; 216 215 ce->clkevt.irq = irq; 217 216 ce->clkevt.cpumask = cpu_possible_mask; 217 + ce->clkevt.owner = THIS_MODULE; 218 218 219 219 /* Enable timer0 interrupt */ 220 220 val = readl(base + TIMER_IRQ_EN_REG);

+21 -17

drivers/clocksource/timer-tegra186.c

··· 159 159 tmr_writel(wdt->tmr, TMRCSSR_SRC_USEC, TMRCSSR); 160 160 161 161 /* configure timer (system reset happens on the fifth expiration) */ 162 - value = TMRCR_PTV(wdt->base.timeout * USEC_PER_SEC / 5) | 162 + value = TMRCR_PTV(wdt->base.timeout * (USEC_PER_SEC / 5)) | 163 163 TMRCR_PERIODIC | TMRCR_ENABLE; 164 164 tmr_writel(wdt->tmr, value, TMRCR); 165 165 ··· 231 231 { 232 232 struct tegra186_wdt *wdt = to_tegra186_wdt(wdd); 233 233 u32 expiration, val; 234 - u64 timeleft; 234 + u32 timeleft; 235 235 236 236 if (!watchdog_active(&wdt->base)) { 237 237 /* return zero if the watchdog timer is not activated. */ ··· 266 266 * Calculate the time remaining by adding the time for the 267 267 * counter value to the time of the counter expirations that 268 268 * remain. 269 + * Note: Since wdt->base.timeout is bound to 255, the maximum 270 + * value added to timeleft is 271 + * 255 * (1,000,000 / 5) * 4 272 + * = 255 * 200,000 * 4 273 + * = 204,000,000 274 + * TMRSR_PCV is a 29-bit field. 275 + * Its maximum value is 0x1fffffff = 536,870,911. 276 + * 204,000,000 + 536,870,911 = 740,870,911 = 0x2C28CAFF. 277 + * timeleft can therefore not overflow, and 64-bit calculations 278 + * are not necessary. 269 279 */ 270 - timeleft += (((u64)wdt->base.timeout * USEC_PER_SEC) / 5) * (4 - expiration); 280 + timeleft += (wdt->base.timeout * (USEC_PER_SEC / 5)) * (4 - expiration); 271 281 272 282 /* 273 283 * Convert the current counter value to seconds, 274 - * rounding up to the nearest second. Cast u64 to 275 - * u32 under the assumption that no overflow happens 276 - * when coverting to seconds. 284 + * rounding to the nearest second. 277 285 */ 278 - timeleft = DIV_ROUND_CLOSEST_ULL(timeleft, USEC_PER_SEC); 286 + timeleft = DIV_ROUND_CLOSEST(timeleft, USEC_PER_SEC); 279 287 280 - if (WARN_ON_ONCE(timeleft > U32_MAX)) 281 - return U32_MAX; 282 - 283 - return lower_32_bits(timeleft); 288 + return timeleft; 284 289 } 285 290 286 291 static const struct watchdog_ops tegra186_wdt_ops = { ··· 333 328 wdt->base.parent = tegra->dev; 334 329 335 330 err = watchdog_init_timeout(&wdt->base, 5, tegra->dev); 336 - if (err < 0) { 337 - dev_err(tegra->dev, "failed to initialize timeout: %d\n", err); 331 + if (err < 0) 338 332 return ERR_PTR(err); 339 - } 340 333 341 334 err = devm_watchdog_register_device(tegra->dev, &wdt->base); 342 - if (err < 0) { 343 - dev_err(tegra->dev, "failed to register WDT: %d\n", err); 335 + if (err < 0) 344 336 return ERR_PTR(err); 345 - } 346 337 347 338 return wdt; 348 339 } ··· 374 373 tegra->tsc.read = tegra186_timer_tsc_read; 375 374 tegra->tsc.mask = CLOCKSOURCE_MASK(56); 376 375 tegra->tsc.flags = CLOCK_SOURCE_IS_CONTINUOUS; 376 + tegra->tsc.owner = THIS_MODULE; 377 377 378 378 return clocksource_register_hz(&tegra->tsc, 31250000); 379 379 } ··· 394 392 tegra->osc.read = tegra186_timer_osc_read; 395 393 tegra->osc.mask = CLOCKSOURCE_MASK(32); 396 394 tegra->osc.flags = CLOCK_SOURCE_IS_CONTINUOUS; 395 + tegra->osc.owner = THIS_MODULE; 397 396 398 397 return clocksource_register_hz(&tegra->osc, 38400000); 399 398 } ··· 414 411 tegra->usec.read = tegra186_timer_usec_read; 415 412 tegra->usec.mask = CLOCKSOURCE_MASK(32); 416 413 tegra->usec.flags = CLOCK_SOURCE_IS_CONTINUOUS; 414 + tegra->usec.owner = THIS_MODULE; 417 415 418 416 return clocksource_register_hz(&tegra->usec, USEC_PER_SEC); 419 417 }

+117 -2

drivers/clocksource/timer-ti-dm.c

··· 31 31 #include <linux/platform_data/dmtimer-omap.h> 32 32 33 33 #include <clocksource/timer-ti-dm.h> 34 + #include <linux/delay.h> 34 35 35 36 /* 36 37 * timer errata flags ··· 837 836 return 0; 838 837 } 839 838 839 + static int omap_dm_timer_set_cap(struct omap_dm_timer *cookie, 840 + int autoreload, bool config_period) 841 + { 842 + struct dmtimer *timer; 843 + struct device *dev; 844 + int rc; 845 + u32 l; 846 + 847 + timer = to_dmtimer(cookie); 848 + if (unlikely(!timer)) 849 + return -EINVAL; 850 + 851 + dev = &timer->pdev->dev; 852 + rc = pm_runtime_resume_and_get(dev); 853 + if (rc) 854 + return rc; 855 + /* 856 + * 1. Select autoreload mode. TIMER_TCLR[1] AR bit. 857 + * 2. TIMER_TCLR[14]: Sets the functionality of the TIMER IO pin. 858 + * 3. TIMER_TCLR[13] : Capture mode select bit. 859 + * 3. TIMER_TCLR[9-8] : Select transition capture mode. 860 + */ 861 + 862 + l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 863 + 864 + if (autoreload) 865 + l |= OMAP_TIMER_CTRL_AR; 866 + 867 + l |= OMAP_TIMER_CTRL_CAPTMODE | OMAP_TIMER_CTRL_GPOCFG; 868 + 869 + if (config_period == true) 870 + l |= OMAP_TIMER_CTRL_TCM_LOWTOHIGH; /* Time Period config */ 871 + else 872 + l |= OMAP_TIMER_CTRL_TCM_BOTHEDGES; /* Duty Cycle config */ 873 + 874 + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 875 + 876 + pm_runtime_put_sync(dev); 877 + 878 + return 0; 879 + } 880 + 840 881 static int omap_dm_timer_set_pwm(struct omap_dm_timer *cookie, int def_on, 841 882 int toggle, int trigger, int autoreload) 842 883 { ··· 1066 1023 return __omap_dm_timer_read_counter(timer); 1067 1024 } 1068 1025 1026 + static inline unsigned int __omap_dm_timer_cap(struct dmtimer *timer, int idx) 1027 + { 1028 + return idx == 0 ? dmtimer_read(timer, OMAP_TIMER_CAPTURE_REG) : 1029 + dmtimer_read(timer, OMAP_TIMER_CAPTURE2_REG); 1030 + } 1031 + 1069 1032 static int omap_dm_timer_write_counter(struct omap_dm_timer *cookie, unsigned int value) 1070 1033 { 1071 1034 struct dmtimer *timer; 1035 + struct device *dev; 1072 1036 1073 1037 timer = to_dmtimer(cookie); 1074 - if (unlikely(!timer || !atomic_read(&timer->enabled))) { 1075 - pr_err("%s: timer not available or enabled.\n", __func__); 1038 + if (unlikely(!timer)) { 1039 + pr_err("%s: timer not available.\n", __func__); 1076 1040 return -EINVAL; 1077 1041 } 1078 1042 1043 + dev = &timer->pdev->dev; 1044 + 1045 + pm_runtime_resume_and_get(dev); 1079 1046 dmtimer_write(timer, OMAP_TIMER_COUNTER_REG, value); 1047 + pm_runtime_put_sync(dev); 1080 1048 1081 1049 /* Save the context */ 1082 1050 timer->context.tcrr = value; 1083 1051 return 0; 1052 + } 1053 + 1054 + /** 1055 + * omap_dm_timer_cap_counter() - Calculate the high count or period count depending on the 1056 + * configuration. 1057 + * @cookie:Pointer to OMAP DM timer 1058 + * @is_period:Whether to configure timer in period or duty cycle mode 1059 + * 1060 + * Return high count or period count if timer is enabled else appropriate error. 1061 + */ 1062 + static unsigned int omap_dm_timer_cap_counter(struct omap_dm_timer *cookie, bool is_period) 1063 + { 1064 + struct dmtimer *timer; 1065 + unsigned int cap1 = 0; 1066 + unsigned int cap2 = 0; 1067 + u32 l, ret; 1068 + 1069 + timer = to_dmtimer(cookie); 1070 + if (unlikely(!timer || !atomic_read(&timer->enabled))) { 1071 + pr_err("%s:timer is not available or enabled.%p\n", __func__, (void *)timer); 1072 + return -EINVAL; 1073 + } 1074 + 1075 + /* Stop the timer */ 1076 + omap_dm_timer_stop(cookie); 1077 + 1078 + /* Clear the timer counter value to 0 */ 1079 + ret = omap_dm_timer_write_counter(cookie, 0); 1080 + if (ret) 1081 + return ret; 1082 + 1083 + /* Sets the timer capture configuration for period/duty cycle calculation */ 1084 + ret = omap_dm_timer_set_cap(cookie, true, is_period); 1085 + if (ret) { 1086 + pr_err("%s: Failed to set timer capture configuration.\n", __func__); 1087 + return ret; 1088 + } 1089 + /* Start the timer */ 1090 + omap_dm_timer_start(cookie); 1091 + 1092 + /* 1093 + * 1 sec delay is given so as to provide 1094 + * enough time to capture low frequency signals. 1095 + */ 1096 + msleep(1000); 1097 + 1098 + cap1 = __omap_dm_timer_cap(timer, 0); 1099 + cap2 = __omap_dm_timer_cap(timer, 1); 1100 + 1101 + /* 1102 + * Clears the TCLR configuration. 1103 + * The start bit must be set to 1 as the timer is already in start mode. 1104 + */ 1105 + l = dmtimer_read(timer, OMAP_TIMER_CTRL_REG); 1106 + l &= ~(0xffff) | 0x1; 1107 + dmtimer_write(timer, OMAP_TIMER_CTRL_REG, l); 1108 + 1109 + return (cap2-cap1); 1084 1110 } 1085 1111 1086 1112 static int __maybe_unused omap_dm_timer_runtime_suspend(struct device *dev) ··· 1358 1246 .write_counter = omap_dm_timer_write_counter, 1359 1247 .read_status = omap_dm_timer_read_status, 1360 1248 .write_status = omap_dm_timer_write_status, 1249 + .set_cap = omap_dm_timer_set_cap, 1250 + .get_cap_status = omap_dm_timer_get_pwm_status, 1251 + .read_cap = omap_dm_timer_cap_counter, 1361 1252 }; 1362 1253 1363 1254 static const struct dmtimer_platform_data omap3plus_pdata = {

-194

drivers/clocksource/timer-vf-pit.c

··· 1 - // SPDX-License-Identifier: GPL-2.0-or-later 2 - /* 3 - * Copyright 2012-2013 Freescale Semiconductor, Inc. 4 - */ 5 - 6 - #include <linux/interrupt.h> 7 - #include <linux/clockchips.h> 8 - #include <linux/clk.h> 9 - #include <linux/of_address.h> 10 - #include <linux/of_irq.h> 11 - #include <linux/sched_clock.h> 12 - 13 - /* 14 - * Each pit takes 0x10 Bytes register space 15 - */ 16 - #define PITMCR 0x00 17 - #define PIT0_OFFSET 0x100 18 - #define PITn_OFFSET(n) (PIT0_OFFSET + 0x10 * (n)) 19 - #define PITLDVAL 0x00 20 - #define PITCVAL 0x04 21 - #define PITTCTRL 0x08 22 - #define PITTFLG 0x0c 23 - 24 - #define PITMCR_MDIS (0x1 << 1) 25 - 26 - #define PITTCTRL_TEN (0x1 << 0) 27 - #define PITTCTRL_TIE (0x1 << 1) 28 - #define PITCTRL_CHN (0x1 << 2) 29 - 30 - #define PITTFLG_TIF 0x1 31 - 32 - static void __iomem *clksrc_base; 33 - static void __iomem *clkevt_base; 34 - static unsigned long cycle_per_jiffy; 35 - 36 - static inline void pit_timer_enable(void) 37 - { 38 - __raw_writel(PITTCTRL_TEN | PITTCTRL_TIE, clkevt_base + PITTCTRL); 39 - } 40 - 41 - static inline void pit_timer_disable(void) 42 - { 43 - __raw_writel(0, clkevt_base + PITTCTRL); 44 - } 45 - 46 - static inline void pit_irq_acknowledge(void) 47 - { 48 - __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); 49 - } 50 - 51 - static u64 notrace pit_read_sched_clock(void) 52 - { 53 - return ~__raw_readl(clksrc_base + PITCVAL); 54 - } 55 - 56 - static int __init pit_clocksource_init(unsigned long rate) 57 - { 58 - /* set the max load value and start the clock source counter */ 59 - __raw_writel(0, clksrc_base + PITTCTRL); 60 - __raw_writel(~0UL, clksrc_base + PITLDVAL); 61 - __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); 62 - 63 - sched_clock_register(pit_read_sched_clock, 32, rate); 64 - return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, 65 - 300, 32, clocksource_mmio_readl_down); 66 - } 67 - 68 - static int pit_set_next_event(unsigned long delta, 69 - struct clock_event_device *unused) 70 - { 71 - /* 72 - * set a new value to PITLDVAL register will not restart the timer, 73 - * to abort the current cycle and start a timer period with the new 74 - * value, the timer must be disabled and enabled again. 75 - * and the PITLAVAL should be set to delta minus one according to pit 76 - * hardware requirement. 77 - */ 78 - pit_timer_disable(); 79 - __raw_writel(delta - 1, clkevt_base + PITLDVAL); 80 - pit_timer_enable(); 81 - 82 - return 0; 83 - } 84 - 85 - static int pit_shutdown(struct clock_event_device *evt) 86 - { 87 - pit_timer_disable(); 88 - return 0; 89 - } 90 - 91 - static int pit_set_periodic(struct clock_event_device *evt) 92 - { 93 - pit_set_next_event(cycle_per_jiffy, evt); 94 - return 0; 95 - } 96 - 97 - static irqreturn_t pit_timer_interrupt(int irq, void *dev_id) 98 - { 99 - struct clock_event_device *evt = dev_id; 100 - 101 - pit_irq_acknowledge(); 102 - 103 - /* 104 - * pit hardware doesn't support oneshot, it will generate an interrupt 105 - * and reload the counter value from PITLDVAL when PITCVAL reach zero, 106 - * and start the counter again. So software need to disable the timer 107 - * to stop the counter loop in ONESHOT mode. 108 - */ 109 - if (likely(clockevent_state_oneshot(evt))) 110 - pit_timer_disable(); 111 - 112 - evt->event_handler(evt); 113 - 114 - return IRQ_HANDLED; 115 - } 116 - 117 - static struct clock_event_device clockevent_pit = { 118 - .name = "VF pit timer", 119 - .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 120 - .set_state_shutdown = pit_shutdown, 121 - .set_state_periodic = pit_set_periodic, 122 - .set_next_event = pit_set_next_event, 123 - .rating = 300, 124 - }; 125 - 126 - static int __init pit_clockevent_init(unsigned long rate, int irq) 127 - { 128 - __raw_writel(0, clkevt_base + PITTCTRL); 129 - __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); 130 - 131 - BUG_ON(request_irq(irq, pit_timer_interrupt, IRQF_TIMER | IRQF_IRQPOLL, 132 - "VF pit timer", &clockevent_pit)); 133 - 134 - clockevent_pit.cpumask = cpumask_of(0); 135 - clockevent_pit.irq = irq; 136 - /* 137 - * The value for the LDVAL register trigger is calculated as: 138 - * LDVAL trigger = (period / clock period) - 1 139 - * The pit is a 32-bit down count timer, when the counter value 140 - * reaches 0, it will generate an interrupt, thus the minimal 141 - * LDVAL trigger value is 1. And then the min_delta is 142 - * minimal LDVAL trigger value + 1, and the max_delta is full 32-bit. 143 - */ 144 - clockevents_config_and_register(&clockevent_pit, rate, 2, 0xffffffff); 145 - 146 - return 0; 147 - } 148 - 149 - static int __init pit_timer_init(struct device_node *np) 150 - { 151 - struct clk *pit_clk; 152 - void __iomem *timer_base; 153 - unsigned long clk_rate; 154 - int irq, ret; 155 - 156 - timer_base = of_iomap(np, 0); 157 - if (!timer_base) { 158 - pr_err("Failed to iomap\n"); 159 - return -ENXIO; 160 - } 161 - 162 - /* 163 - * PIT0 and PIT1 can be chained to build a 64-bit timer, 164 - * so choose PIT2 as clocksource, PIT3 as clockevent device, 165 - * and leave PIT0 and PIT1 unused for anyone else who needs them. 166 - */ 167 - clksrc_base = timer_base + PITn_OFFSET(2); 168 - clkevt_base = timer_base + PITn_OFFSET(3); 169 - 170 - irq = irq_of_parse_and_map(np, 0); 171 - if (irq <= 0) 172 - return -EINVAL; 173 - 174 - pit_clk = of_clk_get(np, 0); 175 - if (IS_ERR(pit_clk)) 176 - return PTR_ERR(pit_clk); 177 - 178 - ret = clk_prepare_enable(pit_clk); 179 - if (ret) 180 - return ret; 181 - 182 - clk_rate = clk_get_rate(pit_clk); 183 - cycle_per_jiffy = clk_rate / (HZ); 184 - 185 - /* enable the pit module */ 186 - __raw_writel(~PITMCR_MDIS, timer_base + PITMCR); 187 - 188 - ret = pit_clocksource_init(clk_rate); 189 - if (ret) 190 - return ret; 191 - 192 - return pit_clockevent_init(clk_rate, irq); 193 - } 194 - TIMER_OF_DECLARE(vf610, "fsl,vf610-pit", pit_timer_init);

+1

drivers/of/irq.c

··· 519 519 520 520 return nr; 521 521 } 522 + EXPORT_SYMBOL_GPL(of_irq_count); 522 523 523 524 /** 524 525 * of_irq_to_resource_table - Fill in resource table with node's IRQ info

-5

include/clocksource/arm_arch_timer.h

··· 9 9 #include <linux/timecounter.h> 10 10 #include <linux/types.h> 11 11 12 - #define ARCH_TIMER_TYPE_CP15 BIT(0) 13 - #define ARCH_TIMER_TYPE_MEM BIT(1) 14 - 15 12 #define ARCH_TIMER_CTRL_ENABLE (1 << 0) 16 13 #define ARCH_TIMER_CTRL_IT_MASK (1 << 1) 17 14 #define ARCH_TIMER_CTRL_IT_STAT (1 << 2) ··· 48 51 49 52 #define ARCH_TIMER_PHYS_ACCESS 0 50 53 #define ARCH_TIMER_VIRT_ACCESS 1 51 - #define ARCH_TIMER_MEM_PHYS_ACCESS 2 52 - #define ARCH_TIMER_MEM_VIRT_ACCESS 3 53 54 54 55 #define ARCH_TIMER_MEM_MAX_FRAMES 8 55 56

+4

include/linux/platform_data/dmtimer-omap.h

··· 36 36 int (*set_pwm)(struct omap_dm_timer *timer, int def_on, 37 37 int toggle, int trigger, int autoreload); 38 38 int (*get_pwm_status)(struct omap_dm_timer *timer); 39 + int (*set_cap)(struct omap_dm_timer *timer, 40 + int autoreload, bool config_period); 41 + int (*get_cap_status)(struct omap_dm_timer *timer); 39 42 int (*set_prescaler)(struct omap_dm_timer *timer, int prescaler); 40 43 41 44 unsigned int (*read_counter)(struct omap_dm_timer *timer); 45 + unsigned int (*read_cap)(struct omap_dm_timer *timer, bool is_period); 42 46 int (*write_counter)(struct omap_dm_timer *timer, 43 47 unsigned int value); 44 48 unsigned int (*read_status)(struct omap_dm_timer *timer);

+2 -2

kernel/time/sched_clock.c

··· 174 174 return HRTIMER_RESTART; 175 175 } 176 176 177 - void __init 178 - sched_clock_register(u64 (*read)(void), int bits, unsigned long rate) 177 + void sched_clock_register(u64 (*read)(void), int bits, unsigned long rate) 179 178 { 180 179 u64 res, wrap, new_mask, new_epoch, cyc, ns; 181 180 u32 new_mult, new_shift; ··· 246 247 247 248 pr_debug("Registered %pS as sched_clock source\n", read); 248 249 } 250 + EXPORT_SYMBOL_GPL(sched_clock_register); 249 251 250 252 void __init generic_sched_clock_init(void) 251 253 {

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