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octeontx2-af: Workaround SQM/PSE stalls by disabling sticky

NIX SQ manager sticky mode is known to cause stalls when multiple SQs
share an SMQ and transmit concurrently. Additionally, PSE may deadlock
on transitions between sticky and non-sticky transmissions. There is
also a credit drop issue observed when certain condition clocks are
gated.

work around these hardware errata by:
- Disabling SQM sticky operation:
- Clear TM6 (bit 15)
- Clear TM11 (bit 14)
- Disabling sticky → non-sticky transition path that can deadlock PSE:
- Clear TM5 (bit 23)
- Preventing credit drops by keeping the control-flow clock enabled:
- Set TM9 (bit 21)

These changes are applied via NIX_AF_SQM_DBG_CTL_STATUS. With this
configuration the SQM/PSE maintain forward progress under load without
credit loss, at the cost of disabling sticky optimizations.

Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Reviewed-by: Simon Horman <horms@kernel.org>
Link: https://patch.msgid.link/20260127125147.1642-1-gakula@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

authored by

Geetha sowjanya and committed by
Jakub Kicinski 70e9a576 7b85c775

+9 -3
+9 -3
drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
··· 4938 4938 /* Set chan/link to backpressure TL3 instead of TL2 */ 4939 4939 rvu_write64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL, 0x01); 4940 4940 4941 - /* Disable SQ manager's sticky mode operation (set TM6 = 0) 4941 + /* Disable SQ manager's sticky mode operation (set TM6 = 0, TM11 = 0) 4942 4942 * This sticky mode is known to cause SQ stalls when multiple 4943 - * SQs are mapped to same SMQ and transmitting pkts at a time. 4943 + * SQs are mapped to same SMQ and transmitting pkts simultaneously. 4944 + * NIX PSE may deadlock when there are any sticky to non-sticky 4945 + * transmission. Hence disable it (TM5 = 0). 4944 4946 */ 4945 4947 cfg = rvu_read64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS); 4946 - cfg &= ~BIT_ULL(15); 4948 + cfg &= ~(BIT_ULL(15) | BIT_ULL(14) | BIT_ULL(23)); 4949 + /* NIX may drop credits when condition clocks are turned off. 4950 + * Hence enable control flow clk (set TM9 = 1). 4951 + */ 4952 + cfg |= BIT_ULL(21); 4947 4953 rvu_write64(rvu, blkaddr, NIX_AF_SQM_DBG_CTL_STATUS, cfg); 4948 4954 4949 4955 ltdefs = rvu->kpu.lt_def;