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dt-bindings: phy: Add QMP USB3+DP PHY for QCS615

Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
on QCS615 Platform. This PHY supports both USB3 and DP functionality
over USB-C, with PHY mode switching capability. It does not support
combo mode.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://patch.msgid.link/20251215-add-displayport-support-for-qcs615-platform-v8-1-cbc72c88a44e@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>

authored by

Xiangxu Yin and committed by
Vinod Koul 70f12a4c 434e1a0e

+111
+111
Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml
··· 1 + # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2 + %YAML 1.2 3 + --- 4 + $id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml# 5 + $schema: http://devicetree.org/meta-schemas/core.yaml# 6 + 7 + title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615) 8 + 9 + maintainers: 10 + - Xiangxu Yin <xiangxu.yin@oss.qualcomm.com> 11 + 12 + description: 13 + The QMP PHY controller supports physical layer functionality for both USB3 14 + and DisplayPort over USB-C. While it enables mode switching between USB3 and 15 + DisplayPort, but does not support combo mode. 16 + 17 + properties: 18 + compatible: 19 + enum: 20 + - qcom,qcs615-qmp-usb3-dp-phy 21 + 22 + reg: 23 + maxItems: 1 24 + 25 + clocks: 26 + maxItems: 4 27 + 28 + clock-names: 29 + items: 30 + - const: aux 31 + - const: ref 32 + - const: cfg_ahb 33 + - const: pipe 34 + 35 + resets: 36 + maxItems: 2 37 + 38 + reset-names: 39 + items: 40 + - const: phy_phy 41 + - const: dp_phy 42 + 43 + vdda-phy-supply: true 44 + 45 + vdda-pll-supply: true 46 + 47 + "#clock-cells": 48 + const: 1 49 + description: 50 + See include/dt-bindings/phy/phy-qcom-qmp.h 51 + 52 + "#phy-cells": 53 + const: 1 54 + description: 55 + See include/dt-bindings/phy/phy-qcom-qmp.h 56 + 57 + qcom,tcsr-reg: 58 + $ref: /schemas/types.yaml#/definitions/phandle-array 59 + items: 60 + - items: 61 + - description: phandle to TCSR hardware block 62 + - description: offset of the VLS CLAMP register 63 + - description: offset of the PHY mode register 64 + description: Clamp and PHY mode register present in the TCSR 65 + 66 + required: 67 + - compatible 68 + - reg 69 + - clocks 70 + - clock-names 71 + - resets 72 + - reset-names 73 + - vdda-phy-supply 74 + - vdda-pll-supply 75 + - "#clock-cells" 76 + - "#phy-cells" 77 + - qcom,tcsr-reg 78 + 79 + additionalProperties: false 80 + 81 + examples: 82 + - | 83 + #include <dt-bindings/clock/qcom,qcs615-gcc.h> 84 + #include <dt-bindings/clock/qcom,rpmh.h> 85 + 86 + phy@88e8000 { 87 + compatible = "qcom,qcs615-qmp-usb3-dp-phy"; 88 + reg = <0x88e8000 0x2000>; 89 + 90 + clocks = <&gcc GCC_USB2_SEC_PHY_AUX_CLK>, 91 + <&gcc GCC_USB3_SEC_CLKREF_CLK>, 92 + <&gcc GCC_AHB2PHY_WEST_CLK>, 93 + <&gcc GCC_USB2_SEC_PHY_PIPE_CLK>; 94 + clock-names = "aux", 95 + "ref", 96 + "cfg_ahb", 97 + "pipe"; 98 + 99 + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>, 100 + <&gcc GCC_USB3_DP_PHY_SEC_BCR>; 101 + reset-names = "phy_phy", 102 + "dp_phy"; 103 + 104 + vdda-phy-supply = <&vreg_l5a>; 105 + vdda-pll-supply = <&vreg_l12a>; 106 + 107 + #clock-cells = <1>; 108 + #phy-cells = <1>; 109 + 110 + qcom,tcsr-reg = <&tcsr 0xbff0 0xb24c>; 111 + };