Merge branch 'hisilicon-hns-deadcoding'

-109

drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.c

··· 3019 3019 3020 3020 module_platform_driver(g_dsaf_driver); 3021 3021 3022 - /** 3023 - * hns_dsaf_roce_reset - reset dsaf and roce 3024 - * @dsaf_fwnode: Pointer to framework node for the dasf 3025 - * @dereset: false - request reset , true - drop reset 3026 - * return 0 - success , negative -fail 3027 - */ 3028 - int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset) 3029 - { 3030 - struct dsaf_device *dsaf_dev; 3031 - struct platform_device *pdev; 3032 - u32 mp; 3033 - u32 sl; 3034 - u32 credit; 3035 - int i; 3036 - static const u32 port_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 3037 - {DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 3038 - {DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0, DSAF_ROCE_PORT_0}, 3039 - {DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 3040 - {DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1, DSAF_ROCE_PORT_0}, 3041 - {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 3042 - {DSAF_ROCE_PORT_4, DSAF_ROCE_PORT_2, DSAF_ROCE_PORT_1}, 3043 - {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 3044 - {DSAF_ROCE_PORT_5, DSAF_ROCE_PORT_3, DSAF_ROCE_PORT_1}, 3045 - }; 3046 - static const u32 sl_map[DSAF_ROCE_CREDIT_CHN][DSAF_ROCE_CHAN_MODE_NUM] = { 3047 - {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 3048 - {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 3049 - {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 3050 - {DSAF_ROCE_SL_0, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 3051 - {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_0}, 3052 - {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_1}, 3053 - {DSAF_ROCE_SL_0, DSAF_ROCE_SL_0, DSAF_ROCE_SL_2}, 3054 - {DSAF_ROCE_SL_1, DSAF_ROCE_SL_1, DSAF_ROCE_SL_3}, 3055 - }; 3056 - 3057 - /* find the platform device corresponding to fwnode */ 3058 - if (is_of_node(dsaf_fwnode)) { 3059 - pdev = of_find_device_by_node(to_of_node(dsaf_fwnode)); 3060 - } else if (is_acpi_device_node(dsaf_fwnode)) { 3061 - pdev = hns_dsaf_find_platform_device(dsaf_fwnode); 3062 - } else { 3063 - pr_err("fwnode is neither OF or ACPI type\n"); 3064 - return -EINVAL; 3065 - } 3066 - 3067 - /* check if we were a success in fetching pdev */ 3068 - if (!pdev) { 3069 - pr_err("couldn't find platform device for node\n"); 3070 - return -ENODEV; 3071 - } 3072 - 3073 - /* retrieve the dsaf_device from the driver data */ 3074 - dsaf_dev = dev_get_drvdata(&pdev->dev); 3075 - if (!dsaf_dev) { 3076 - dev_err(&pdev->dev, "dsaf_dev is NULL\n"); 3077 - put_device(&pdev->dev); 3078 - return -ENODEV; 3079 - } 3080 - 3081 - /* now, make sure we are running on compatible SoC */ 3082 - if (AE_IS_VER1(dsaf_dev->dsaf_ver)) { 3083 - dev_err(dsaf_dev->dev, "%s v1 chip doesn't support RoCE!\n", 3084 - dsaf_dev->ae_dev.name); 3085 - put_device(&pdev->dev); 3086 - return -ENODEV; 3087 - } 3088 - 3089 - /* do reset or de-reset according to the flag */ 3090 - if (!dereset) { 3091 - /* reset rocee-channels in dsaf and rocee */ 3092 - dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 3093 - false); 3094 - dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, false); 3095 - } else { 3096 - /* configure dsaf tx roce correspond to port map and sl map */ 3097 - mp = dsaf_read_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG); 3098 - for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 3099 - dsaf_set_field(mp, 7 << i * 3, i * 3, 3100 - port_map[i][DSAF_ROCE_6PORT_MODE]); 3101 - dsaf_set_field(mp, 3 << i * 3, i * 3, 0); 3102 - dsaf_write_dev(dsaf_dev, DSAF_ROCE_PORT_MAP_REG, mp); 3103 - 3104 - sl = dsaf_read_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG); 3105 - for (i = 0; i < DSAF_ROCE_CREDIT_CHN; i++) 3106 - dsaf_set_field(sl, 3 << i * 2, i * 2, 3107 - sl_map[i][DSAF_ROCE_6PORT_MODE]); 3108 - dsaf_write_dev(dsaf_dev, DSAF_ROCE_SL_MAP_REG, sl); 3109 - 3110 - /* de-reset rocee-channels in dsaf and rocee */ 3111 - dsaf_dev->misc_op->hns_dsaf_srst_chns(dsaf_dev, DSAF_CHNS_MASK, 3112 - true); 3113 - msleep(SRST_TIME_INTERVAL); 3114 - dsaf_dev->misc_op->hns_dsaf_roce_srst(dsaf_dev, true); 3115 - 3116 - /* enable dsaf channel rocee credit */ 3117 - credit = dsaf_read_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG); 3118 - dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 0); 3119 - dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 3120 - 3121 - dsaf_set_bit(credit, DSAF_SBM_ROCEE_CFG_CRD_EN_B, 1); 3122 - dsaf_write_dev(dsaf_dev, DSAF_SBM_ROCEE_CFG_REG_REG, credit); 3123 - } 3124 - 3125 - put_device(&pdev->dev); 3126 - 3127 - return 0; 3128 - } 3129 - EXPORT_SYMBOL(hns_dsaf_roce_reset); 3130 - 3131 3022 MODULE_LICENSE("GPL"); 3132 3023 MODULE_AUTHOR("Huawei Tech. Co., Ltd."); 3133 3024 MODULE_DESCRIPTION("HNS DSAF driver");

-28

drivers/net/ethernet/hisilicon/hns/hns_dsaf_main.h

··· 42 42 43 43 #define HNS_MAX_WAIT_CNT 10000 44 44 45 - enum dsaf_roce_port_mode { 46 - DSAF_ROCE_6PORT_MODE, 47 - DSAF_ROCE_4PORT_MODE, 48 - DSAF_ROCE_2PORT_MODE, 49 - DSAF_ROCE_CHAN_MODE_NUM, 50 - }; 51 - 52 - enum dsaf_roce_port_num { 53 - DSAF_ROCE_PORT_0, 54 - DSAF_ROCE_PORT_1, 55 - DSAF_ROCE_PORT_2, 56 - DSAF_ROCE_PORT_3, 57 - DSAF_ROCE_PORT_4, 58 - DSAF_ROCE_PORT_5, 59 - }; 60 - 61 - enum dsaf_roce_qos_sl { 62 - DSAF_ROCE_SL_0, 63 - DSAF_ROCE_SL_1, 64 - DSAF_ROCE_SL_2, 65 - DSAF_ROCE_SL_3, 66 - }; 67 - 68 45 #define DSAF_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset)))) 69 46 #define HNS_DSAF_IS_DEBUG(dev) ((dev)->dsaf_mode == DSAF_MODE_DISABLE_SP) 70 47 ··· 284 307 void (*ge_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 285 308 void (*ppe_srst)(struct dsaf_device *dsaf_dev, u32 port, bool dereset); 286 309 void (*ppe_comm_srst)(struct dsaf_device *dsaf_dev, bool dereset); 287 - void (*hns_dsaf_srst_chns)(struct dsaf_device *dsaf_dev, u32 msk, 288 - bool dereset); 289 - void (*hns_dsaf_roce_srst)(struct dsaf_device *dsaf_dev, bool dereset); 290 310 291 311 phy_interface_t (*get_phy_if)(struct hns_mac_cb *mac_cb); 292 312 int (*get_sfp_prsnt)(struct hns_mac_cb *mac_cb, int *sfp_prsnt); ··· 436 462 int hns_dsaf_clr_mac_mc_port(struct dsaf_device *dsaf_dev, 437 463 u8 mac_id, u8 port_num); 438 464 int hns_dsaf_wait_pkt_clean(struct dsaf_device *dsaf_dev, int port); 439 - 440 - int hns_dsaf_roce_reset(struct fwnode_handle *dsaf_fwnode, bool dereset); 441 465 442 466 #endif /* __HNS_DSAF_MAIN_H__ */

-67

drivers/net/ethernet/hisilicon/hns/hns_dsaf_misc.c

··· 326 326 HNS_XGE_RESET_FUNC, port, dereset); 327 327 } 328 328 329 - /** 330 - * hns_dsaf_srst_chns - reset dsaf channels 331 - * @dsaf_dev: dsaf device struct pointer 332 - * @msk: xbar channels mask value: 333 - * @dereset: false - request reset , true - drop reset 334 - * 335 - * bit0-5 for xge0-5 336 - * bit6-11 for ppe0-5 337 - * bit12-17 for roce0-5 338 - * bit18-19 for com/dfx 339 - */ 340 - static void 341 - hns_dsaf_srst_chns(struct dsaf_device *dsaf_dev, u32 msk, bool dereset) 342 - { 343 - u32 reg_addr; 344 - 345 - if (!dereset) 346 - reg_addr = DSAF_SUB_SC_DSAF_RESET_REQ_REG; 347 - else 348 - reg_addr = DSAF_SUB_SC_DSAF_RESET_DREQ_REG; 349 - 350 - dsaf_write_sub(dsaf_dev, reg_addr, msk); 351 - } 352 - 353 - /** 354 - * hns_dsaf_srst_chns_acpi - reset dsaf channels 355 - * @dsaf_dev: dsaf device struct pointer 356 - * @msk: xbar channels mask value: 357 - * @dereset: false - request reset , true - drop reset 358 - * 359 - * bit0-5 for xge0-5 360 - * bit6-11 for ppe0-5 361 - * bit12-17 for roce0-5 362 - * bit18-19 for com/dfx 363 - */ 364 - static void 365 - hns_dsaf_srst_chns_acpi(struct dsaf_device *dsaf_dev, u32 msk, bool dereset) 366 - { 367 - hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, 368 - HNS_DSAF_CHN_RESET_FUNC, 369 - msk, dereset); 370 - } 371 - 372 - static void hns_dsaf_roce_srst(struct dsaf_device *dsaf_dev, bool dereset) 373 - { 374 - if (!dereset) { 375 - dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_RESET_REQ_REG, 1); 376 - } else { 377 - dsaf_write_sub(dsaf_dev, 378 - DSAF_SUB_SC_ROCEE_CLK_DIS_REG, 1); 379 - dsaf_write_sub(dsaf_dev, 380 - DSAF_SUB_SC_ROCEE_RESET_DREQ_REG, 1); 381 - msleep(20); 382 - dsaf_write_sub(dsaf_dev, DSAF_SUB_SC_ROCEE_CLK_EN_REG, 1); 383 - } 384 - } 385 - 386 - static void hns_dsaf_roce_srst_acpi(struct dsaf_device *dsaf_dev, bool dereset) 387 - { 388 - hns_dsaf_acpi_srst_by_port(dsaf_dev, HNS_OP_RESET_FUNC, 389 - HNS_ROCE_RESET_FUNC, 0, dereset); 390 - } 391 - 392 329 static void hns_dsaf_ge_srst_by_port(struct dsaf_device *dsaf_dev, u32 port, 393 330 bool dereset) 394 331 { ··· 666 729 misc_op->ge_srst = hns_dsaf_ge_srst_by_port; 667 730 misc_op->ppe_srst = hns_ppe_srst_by_port; 668 731 misc_op->ppe_comm_srst = hns_ppe_com_srst; 669 - misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns; 670 - misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst; 671 732 672 733 misc_op->get_phy_if = hns_mac_get_phy_if; 673 734 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt; ··· 681 746 misc_op->ge_srst = hns_dsaf_ge_srst_by_port_acpi; 682 747 misc_op->ppe_srst = hns_ppe_srst_by_port_acpi; 683 748 misc_op->ppe_comm_srst = hns_ppe_com_srst; 684 - misc_op->hns_dsaf_srst_chns = hns_dsaf_srst_chns_acpi; 685 - misc_op->hns_dsaf_roce_srst = hns_dsaf_roce_srst_acpi; 686 749 687 750 misc_op->get_phy_if = hns_mac_get_phy_if_acpi; 688 751 misc_op->get_sfp_prsnt = hns_mac_get_sfp_prsnt_acpi;

-5

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.c

··· 195 195 dsaf_write_dev(q, RCB_RING_PREFETCH_EN_REG, !!val); 196 196 } 197 197 198 - void hns_rcb_start(struct hnae_queue *q, u32 val) 199 - { 200 - hns_rcb_ring_enable_hw(q, val); 201 - } 202 - 203 198 /** 204 199 *hns_rcb_common_init_commit_hw - make rcb common init completed 205 200 *@rcb_common: rcb common device

-1

drivers/net/ethernet/hisilicon/hns/hns_dsaf_rcb.h

··· 116 116 int hns_rcb_common_get_cfg(struct dsaf_device *dsaf_dev, int comm_index); 117 117 void hns_rcb_common_free_cfg(struct dsaf_device *dsaf_dev, u32 comm_index); 118 118 int hns_rcb_common_init_hw(struct rcb_common_cb *rcb_common); 119 - void hns_rcb_start(struct hnae_queue *q, u32 val); 120 119 int hns_rcb_get_cfg(struct rcb_common_cb *rcb_common); 121 120 void hns_rcb_get_queue_mode(enum dsaf_mode dsaf_mode, 122 121 u16 *max_vfn, u16 *max_q_per_vf);

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