tjh.dev / kernel
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crypto: octeontx2 - remove CPT block reset

CPT block reset in CPT PF erase all the CPT configuration which is
done in AF driver init. So, remove CPT block reset from CPT PF as
it is also being done in AF init and not required in PF.

Signed-off-by: Srujana Challa <schalla@marvell.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

authored by

Srujana Challa and committed by
Herbert Xu 711b2e2d 37c6fc32

-43
-43
drivers/crypto/marvell/octeontx2/otx2_cptpf_main.c
··· 587 587 return 0; 588 588 } 589 589 590 - static int cptx_device_reset(struct otx2_cptpf_dev *cptpf, int blkaddr) 591 - { 592 - int timeout = 10, ret; 593 - u64 reg = 0; 594 - 595 - ret = otx2_cpt_write_af_reg(&cptpf->afpf_mbox, cptpf->pdev, 596 - CPT_AF_BLK_RST, 0x1, blkaddr); 597 - if (ret) 598 - return ret; 599 - 600 - do { 601 - ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev, 602 - CPT_AF_BLK_RST, &reg, blkaddr); 603 - if (ret) 604 - return ret; 605 - 606 - if (!((reg >> 63) & 0x1)) 607 - break; 608 - 609 - usleep_range(10000, 20000); 610 - if (timeout-- < 0) 611 - return -EBUSY; 612 - } while (1); 613 - 614 - return ret; 615 - } 616 - 617 - static int cptpf_device_reset(struct otx2_cptpf_dev *cptpf) 618 - { 619 - int ret = 0; 620 - 621 - if (cptpf->has_cpt1) { 622 - ret = cptx_device_reset(cptpf, BLKADDR_CPT1); 623 - if (ret) 624 - return ret; 625 - } 626 - return cptx_device_reset(cptpf, BLKADDR_CPT0); 627 - } 628 - 629 590 static void cptpf_check_block_implemented(struct otx2_cptpf_dev *cptpf) 630 591 { 631 592 u64 cfg; ··· 604 643 605 644 /* check if 'implemented' bit is set for block BLKADDR_CPT1 */ 606 645 cptpf_check_block_implemented(cptpf); 607 - /* Reset the CPT PF device */ 608 - ret = cptpf_device_reset(cptpf); 609 - if (ret) 610 - return ret; 611 646 612 647 /* Get number of SE, IE and AE engines */ 613 648 ret = otx2_cpt_read_af_reg(&cptpf->afpf_mbox, cptpf->pdev,