drm/msm/dpu: pull format flag definitions to mdp_format.h

+49 -49

drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c

··· 44 44 .unpack_tight = 1, \ 45 45 .unpack_count = uc, \ 46 46 .bpp = bp, \ 47 - .fetch_mode = fm, \ 48 - .flags = flg, \ 47 + .base.fetch_mode = fm, \ 48 + .base.flags = flg, \ 49 49 .num_planes = np, \ 50 50 .tile_height = DPU_TILE_HEIGHT_DEFAULT \ 51 51 } ··· 63 63 .unpack_tight = 1, \ 64 64 .unpack_count = uc, \ 65 65 .bpp = bp, \ 66 - .fetch_mode = fm, \ 67 - .flags = flg, \ 66 + .base.fetch_mode = fm, \ 67 + .base.flags = flg, \ 68 68 .num_planes = np, \ 69 69 .tile_height = th \ 70 70 } ··· 83 83 .unpack_tight = 1, \ 84 84 .unpack_count = count, \ 85 85 .bpp = bp, \ 86 - .fetch_mode = fm, \ 87 - .flags = flg, \ 86 + .base.fetch_mode = fm, \ 87 + .base.flags = flg, \ 88 88 .num_planes = np, \ 89 89 .tile_height = DPU_TILE_HEIGHT_DEFAULT \ 90 90 } ··· 101 101 .unpack_tight = 1, \ 102 102 .unpack_count = 2, \ 103 103 .bpp = 2, \ 104 - .fetch_mode = fm, \ 105 - .flags = flg, \ 104 + .base.fetch_mode = fm, \ 105 + .base.flags = flg, \ 106 106 .num_planes = np, \ 107 107 .tile_height = DPU_TILE_HEIGHT_DEFAULT \ 108 108 } ··· 120 120 .unpack_tight = 1, \ 121 121 .unpack_count = 2, \ 122 122 .bpp = 2, \ 123 - .fetch_mode = fm, \ 124 - .flags = flg, \ 123 + .base.fetch_mode = fm, \ 124 + .base.flags = flg, \ 125 125 .num_planes = np, \ 126 126 .tile_height = th \ 127 127 } ··· 138 138 .unpack_tight = 0, \ 139 139 .unpack_count = 2, \ 140 140 .bpp = 2, \ 141 - .fetch_mode = fm, \ 142 - .flags = flg, \ 141 + .base.fetch_mode = fm, \ 142 + .base.flags = flg, \ 143 143 .num_planes = np, \ 144 144 .tile_height = DPU_TILE_HEIGHT_DEFAULT \ 145 145 } ··· 157 157 .unpack_tight = 0, \ 158 158 .unpack_count = 2, \ 159 159 .bpp = 2, \ 160 - .fetch_mode = fm, \ 161 - .flags = flg, \ 160 + .base.fetch_mode = fm, \ 161 + .base.flags = flg, \ 162 162 .num_planes = np, \ 163 163 .tile_height = th \ 164 164 } ··· 177 177 .unpack_tight = 1, \ 178 178 .unpack_count = 1, \ 179 179 .bpp = bp, \ 180 - .fetch_mode = fm, \ 181 - .flags = flg, \ 180 + .base.fetch_mode = fm, \ 181 + .base.flags = flg, \ 182 182 .num_planes = np, \ 183 183 .tile_height = DPU_TILE_HEIGHT_DEFAULT \ 184 184 } ··· 365 365 INTERLEAVED_RGB_FMT(BGRA1010102, 366 366 BPC8A, BPC8, BPC8, BPC8, 367 367 C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, 368 - true, 4, DPU_FORMAT_FLAG_DX, 368 + true, 4, MSM_FORMAT_FLAG_DX, 369 369 MDP_FETCH_LINEAR, 1), 370 370 371 371 INTERLEAVED_RGB_FMT(RGBA1010102, 372 372 BPC8A, BPC8, BPC8, BPC8, 373 373 C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, 374 - true, 4, DPU_FORMAT_FLAG_DX, 374 + true, 4, MSM_FORMAT_FLAG_DX, 375 375 MDP_FETCH_LINEAR, 1), 376 376 377 377 INTERLEAVED_RGB_FMT(ABGR2101010, 378 378 BPC8A, BPC8, BPC8, BPC8, 379 379 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 380 - true, 4, DPU_FORMAT_FLAG_DX, 380 + true, 4, MSM_FORMAT_FLAG_DX, 381 381 MDP_FETCH_LINEAR, 1), 382 382 383 383 INTERLEAVED_RGB_FMT(ARGB2101010, 384 384 BPC8A, BPC8, BPC8, BPC8, 385 385 C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, 386 - true, 4, DPU_FORMAT_FLAG_DX, 386 + true, 4, MSM_FORMAT_FLAG_DX, 387 387 MDP_FETCH_LINEAR, 1), 388 388 389 389 INTERLEAVED_RGB_FMT(XRGB2101010, 390 390 BPC8A, BPC8, BPC8, BPC8, 391 391 C1_B_Cb, C0_G_Y, C2_R_Cr, C3_ALPHA, 4, 392 - false, 4, DPU_FORMAT_FLAG_DX, 392 + false, 4, MSM_FORMAT_FLAG_DX, 393 393 MDP_FETCH_LINEAR, 1), 394 394 395 395 INTERLEAVED_RGB_FMT(BGRX1010102, 396 396 BPC8A, BPC8, BPC8, BPC8, 397 397 C3_ALPHA, C2_R_Cr, C0_G_Y, C1_B_Cb, 4, 398 - false, 4, DPU_FORMAT_FLAG_DX, 398 + false, 4, MSM_FORMAT_FLAG_DX, 399 399 MDP_FETCH_LINEAR, 1), 400 400 401 401 INTERLEAVED_RGB_FMT(XBGR2101010, 402 402 BPC8A, BPC8, BPC8, BPC8, 403 403 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 404 - false, 4, DPU_FORMAT_FLAG_DX, 404 + false, 4, MSM_FORMAT_FLAG_DX, 405 405 MDP_FETCH_LINEAR, 1), 406 406 407 407 INTERLEAVED_RGB_FMT(RGBX1010102, 408 408 BPC8A, BPC8, BPC8, BPC8, 409 409 C3_ALPHA, C1_B_Cb, C0_G_Y, C2_R_Cr, 4, 410 - false, 4, DPU_FORMAT_FLAG_DX, 410 + false, 4, MSM_FORMAT_FLAG_DX, 411 411 MDP_FETCH_LINEAR, 1), 412 412 413 413 PSEUDO_YUV_FMT(NV12, 414 414 0, BPC8, BPC8, BPC8, 415 415 C1_B_Cb, C2_R_Cr, 416 - CHROMA_420, DPU_FORMAT_FLAG_YUV, 416 + CHROMA_420, MSM_FORMAT_FLAG_YUV, 417 417 MDP_FETCH_LINEAR, 2), 418 418 419 419 PSEUDO_YUV_FMT(NV21, 420 420 0, BPC8, BPC8, BPC8, 421 421 C2_R_Cr, C1_B_Cb, 422 - CHROMA_420, DPU_FORMAT_FLAG_YUV, 422 + CHROMA_420, MSM_FORMAT_FLAG_YUV, 423 423 MDP_FETCH_LINEAR, 2), 424 424 425 425 PSEUDO_YUV_FMT(NV16, 426 426 0, BPC8, BPC8, BPC8, 427 427 C1_B_Cb, C2_R_Cr, 428 - CHROMA_H2V1, DPU_FORMAT_FLAG_YUV, 428 + CHROMA_H2V1, MSM_FORMAT_FLAG_YUV, 429 429 MDP_FETCH_LINEAR, 2), 430 430 431 431 PSEUDO_YUV_FMT(NV61, 432 432 0, BPC8, BPC8, BPC8, 433 433 C2_R_Cr, C1_B_Cb, 434 - CHROMA_H2V1, DPU_FORMAT_FLAG_YUV, 434 + CHROMA_H2V1, MSM_FORMAT_FLAG_YUV, 435 435 MDP_FETCH_LINEAR, 2), 436 436 437 437 PSEUDO_YUV_FMT_LOOSE(P010, 438 438 0, BPC8, BPC8, BPC8, 439 439 C1_B_Cb, C2_R_Cr, 440 - CHROMA_420, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_YUV, 440 + CHROMA_420, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_YUV, 441 441 MDP_FETCH_LINEAR, 2), 442 442 443 443 INTERLEAVED_YUV_FMT(VYUY, 444 444 0, BPC8, BPC8, BPC8, 445 445 C2_R_Cr, C0_G_Y, C1_B_Cb, C0_G_Y, 446 - false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, 446 + false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV, 447 447 MDP_FETCH_LINEAR, 2), 448 448 449 449 INTERLEAVED_YUV_FMT(UYVY, 450 450 0, BPC8, BPC8, BPC8, 451 451 C1_B_Cb, C0_G_Y, C2_R_Cr, C0_G_Y, 452 - false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, 452 + false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV, 453 453 MDP_FETCH_LINEAR, 2), 454 454 455 455 INTERLEAVED_YUV_FMT(YUYV, 456 456 0, BPC8, BPC8, BPC8, 457 457 C0_G_Y, C1_B_Cb, C0_G_Y, C2_R_Cr, 458 - false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, 458 + false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV, 459 459 MDP_FETCH_LINEAR, 2), 460 460 461 461 INTERLEAVED_YUV_FMT(YVYU, 462 462 0, BPC8, BPC8, BPC8, 463 463 C0_G_Y, C2_R_Cr, C0_G_Y, C1_B_Cb, 464 - false, CHROMA_H2V1, 4, 2, DPU_FORMAT_FLAG_YUV, 464 + false, CHROMA_H2V1, 4, 2, MSM_FORMAT_FLAG_YUV, 465 465 MDP_FETCH_LINEAR, 2), 466 466 467 467 PLANAR_YUV_FMT(YUV420, 468 468 0, BPC8, BPC8, BPC8, 469 469 C2_R_Cr, C1_B_Cb, C0_G_Y, 470 - false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV, 470 + false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV, 471 471 MDP_FETCH_LINEAR, 3), 472 472 473 473 PLANAR_YUV_FMT(YVU420, 474 474 0, BPC8, BPC8, BPC8, 475 475 C1_B_Cb, C2_R_Cr, C0_G_Y, 476 - false, CHROMA_420, 1, DPU_FORMAT_FLAG_YUV, 476 + false, CHROMA_420, 1, MSM_FORMAT_FLAG_YUV, 477 477 MDP_FETCH_LINEAR, 3), 478 478 }; 479 479 ··· 487 487 INTERLEAVED_RGB_FMT_TILED(BGR565, 488 488 0, BPC5, BPC6, BPC5, 489 489 C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3, 490 - false, 2, DPU_FORMAT_FLAG_COMPRESSED, 490 + false, 2, MSM_FORMAT_FLAG_COMPRESSED, 491 491 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 492 492 493 493 INTERLEAVED_RGB_FMT_TILED(ABGR8888, 494 494 BPC8A, BPC8, BPC8, BPC8, 495 495 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 496 - true, 4, DPU_FORMAT_FLAG_COMPRESSED, 496 + true, 4, MSM_FORMAT_FLAG_COMPRESSED, 497 497 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 498 498 499 499 /* ARGB8888 and ABGR8888 purposely have the same color ··· 503 503 INTERLEAVED_RGB_FMT_TILED(ARGB8888, 504 504 BPC8A, BPC8, BPC8, BPC8, 505 505 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 506 - true, 4, DPU_FORMAT_FLAG_COMPRESSED, 506 + true, 4, MSM_FORMAT_FLAG_COMPRESSED, 507 507 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 508 508 509 509 INTERLEAVED_RGB_FMT_TILED(XBGR8888, 510 510 BPC8A, BPC8, BPC8, BPC8, 511 511 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 512 - false, 4, DPU_FORMAT_FLAG_COMPRESSED, 512 + false, 4, MSM_FORMAT_FLAG_COMPRESSED, 513 513 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 514 514 515 515 INTERLEAVED_RGB_FMT_TILED(XRGB8888, 516 516 BPC8A, BPC8, BPC8, BPC8, 517 517 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 518 - false, 4, DPU_FORMAT_FLAG_COMPRESSED, 518 + false, 4, MSM_FORMAT_FLAG_COMPRESSED, 519 519 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 520 520 521 521 INTERLEAVED_RGB_FMT_TILED(ABGR2101010, 522 522 BPC8A, BPC8, BPC8, BPC8, 523 523 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 524 - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, 524 + true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED, 525 525 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 526 526 527 527 INTERLEAVED_RGB_FMT_TILED(XBGR2101010, 528 528 BPC8A, BPC8, BPC8, BPC8, 529 529 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 530 - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, 530 + true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED, 531 531 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 532 532 533 533 INTERLEAVED_RGB_FMT_TILED(XRGB2101010, 534 534 BPC8A, BPC8, BPC8, BPC8, 535 535 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 536 - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, 536 + true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED, 537 537 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 538 538 539 539 /* XRGB2101010 and ARGB2101010 purposely have the same color ··· 543 543 INTERLEAVED_RGB_FMT_TILED(ARGB2101010, 544 544 BPC8A, BPC8, BPC8, BPC8, 545 545 C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4, 546 - true, 4, DPU_FORMAT_FLAG_DX | DPU_FORMAT_FLAG_COMPRESSED, 546 + true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED, 547 547 MDP_FETCH_UBWC, 2, DPU_TILE_HEIGHT_UBWC), 548 548 549 549 PSEUDO_YUV_FMT_TILED(NV12, 550 550 0, BPC8, BPC8, BPC8, 551 551 C1_B_Cb, C2_R_Cr, 552 - CHROMA_420, DPU_FORMAT_FLAG_YUV | 553 - DPU_FORMAT_FLAG_COMPRESSED, 552 + CHROMA_420, MSM_FORMAT_FLAG_YUV | 553 + MSM_FORMAT_FLAG_COMPRESSED, 554 554 MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_NV12), 555 555 556 556 PSEUDO_YUV_FMT_TILED(P010, 557 557 0, BPC8, BPC8, BPC8, 558 558 C1_B_Cb, C2_R_Cr, 559 - CHROMA_420, DPU_FORMAT_FLAG_DX | 560 - DPU_FORMAT_FLAG_YUV | 561 - DPU_FORMAT_FLAG_COMPRESSED, 559 + CHROMA_420, MSM_FORMAT_FLAG_DX | 560 + MSM_FORMAT_FLAG_YUV | 561 + MSM_FORMAT_FLAG_COMPRESSED, 562 562 MDP_FETCH_UBWC, 4, DPU_TILE_HEIGHT_UBWC), 563 563 }; 564 564

+7 -24

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h

··· 9 9 #include <linux/err.h> 10 10 11 11 #include "msm_drv.h" 12 - #include "mdp_common.xml.h" 12 + 13 + #include "disp/mdp_format.h" 13 14 14 15 #define DPU_DBG_NAME "dpu" 15 16 ··· 37 36 #define DPU_MAX_DE_CURVES 3 38 37 #endif 39 38 40 - enum dpu_format_flags { 41 - DPU_FORMAT_FLAG_YUV_BIT, 42 - DPU_FORMAT_FLAG_DX_BIT, 43 - DPU_FORMAT_FLAG_COMPRESSED_BIT, 44 - }; 45 - 46 - #define DPU_FORMAT_FLAG_YUV BIT(DPU_FORMAT_FLAG_YUV_BIT) 47 - #define DPU_FORMAT_FLAG_DX BIT(DPU_FORMAT_FLAG_DX_BIT) 48 - #define DPU_FORMAT_FLAG_COMPRESSED BIT(DPU_FORMAT_FLAG_COMPRESSED_BIT) 49 - 50 - #define DPU_FORMAT_IS_YUV(X) ((X)->flags & DPU_FORMAT_FLAG_YUV) 51 - #define DPU_FORMAT_IS_DX(X) ((X)->flags & DPU_FORMAT_FLAG_DX) 52 - #define DPU_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR) 53 - #define DPU_FORMAT_IS_TILE(X) \ 54 - (((X)->fetch_mode == MDP_FETCH_UBWC) && \ 55 - !((X)->flags & DPU_FORMAT_FLAG_COMPRESSED)) 56 - #define DPU_FORMAT_IS_UBWC(X) \ 57 - (((X)->fetch_mode == MDP_FETCH_UBWC) && \ 58 - ((X)->flags & DPU_FORMAT_FLAG_COMPRESSED)) 39 + #define DPU_FORMAT_IS_YUV(X) MSM_FORMAT_IS_YUV(&(X)->base) 40 + #define DPU_FORMAT_IS_DX(X) MSM_FORMAT_IS_DX(&(X)->base) 41 + #define DPU_FORMAT_IS_LINEAR(X) MSM_FORMAT_IS_LINEAR(&(X)->base) 42 + #define DPU_FORMAT_IS_TILE(X) MSM_FORMAT_IS_TILE(&(X)->base) 43 + #define DPU_FORMAT_IS_UBWC(X) MSM_FORMAT_IS_UBWC(&(X)->base) 59 44 60 45 #define DPU_BLEND_FG_ALPHA_FG_CONST (0 << 0) 61 46 #define DPU_BLEND_FG_ALPHA_BG_CONST (1 << 0) ··· 318 331 * @bpp: bytes per pixel 319 332 * @alpha_enable: whether the format has an alpha channel 320 333 * @num_planes: number of planes (including meta data planes) 321 - * @fetch_mode: linear, tiled, or ubwc hw fetch behavior 322 - * @flags: usage bit flags 323 334 * @tile_width: format tile width 324 335 * @tile_height: format tile height 325 336 */ ··· 333 348 u8 bpp; 334 349 u8 alpha_enable; 335 350 u8 num_planes; 336 - enum mdp_fetch_mode fetch_mode; 337 - unsigned long flags; 338 351 u16 tile_width; 339 352 u16 tile_height; 340 353 };

+2 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

··· 267 267 (fmt->unpack_align_msb << 18) | 268 268 ((fmt->bpp - 1) << 9); 269 269 270 - if (fmt->fetch_mode != MDP_FETCH_LINEAR) { 270 + if (!DPU_FORMAT_IS_LINEAR(fmt)) { 271 271 if (DPU_FORMAT_IS_UBWC(fmt)) 272 272 opmode |= MDSS_MDP_OP_BWC_EN; 273 - src_format |= (fmt->fetch_mode & 3) << 30; /*FRAME_FORMAT */ 273 + src_format |= (fmt->base.fetch_mode & 3) << 30; /*FRAME_FORMAT */ 274 274 DPU_REG_WRITE(c, SSPP_FETCH_CONFIG, 275 275 DPU_FETCH_CONFIG_RESET_VALUE | 276 276 ctx->ubwc->highest_bank_bit << 18);

+2 -2

drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c

··· 294 294 295 295 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, 296 296 (fmt) ? fmt->base.pixel_format : 0, 297 - (fmt) ? fmt->fetch_mode : 0, 297 + (fmt) ? fmt->base.fetch_mode : 0, 298 298 cfg.danger_lut, 299 299 cfg.safe_lut); 300 300 301 301 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n", 302 302 pdpu->pipe - SSPP_VIG0, 303 303 fmt ? &fmt->base.pixel_format : NULL, 304 - fmt ? fmt->fetch_mode : -1, 304 + fmt ? fmt->base.fetch_mode : -1, 305 305 cfg.danger_lut, 306 306 cfg.safe_lut); 307 307

+4 -4

drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c

··· 634 634 uint32_t src, uint32_t dst, bool horz) 635 635 { 636 636 const struct drm_format_info *info = drm_format_info(format->base.pixel_format); 637 - bool scaling = format->is_yuv ? true : (src != dst); 637 + bool yuv = MDP_FORMAT_IS_YUV(format); 638 + bool scaling = yuv ? true : (src != dst); 638 639 uint32_t sub; 639 640 uint32_t ya_filter, uv_filter; 640 - bool yuv = format->is_yuv; 641 641 642 642 if (!scaling) 643 643 return 0; ··· 666 666 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX], 667 667 bool horz) 668 668 { 669 - bool scaling = format->is_yuv ? true : (src != dst); 669 + bool scaling = MDP_FORMAT_IS_YUV(format) ? true : (src != dst); 670 670 int i; 671 671 672 672 /* ··· 696 696 uint32_t roi_w = src_w; 697 697 uint32_t roi_h = src_h; 698 698 699 - if (format->is_yuv && i == COMP_1_2) { 699 + if (MDP_FORMAT_IS_YUV(format) && i == COMP_1_2) { 700 700 roi_w /= info->hsub; 701 701 roi_h /= info->vsub; 702 702 }

+4 -2

drivers/gpu/drm/msm/disp/mdp_format.c

··· 63 63 }; 64 64 65 65 #define FMT(name, a, r, g, b, e0, e1, e2, e3, alpha, tight, c, cnt, fp, cs, yuv) { \ 66 - .base = { .pixel_format = DRM_FORMAT_ ## name }, \ 66 + .base = { \ 67 + .pixel_format = DRM_FORMAT_ ## name, \ 68 + .flags = yuv ? MSM_FORMAT_FLAG_YUV : 0, \ 69 + }, \ 67 70 .bpc_a = BPC ## a ## A, \ 68 71 .bpc_r = BPC ## r, \ 69 72 .bpc_g = BPC ## g, \ ··· 78 75 .unpack_count = cnt, \ 79 76 .fetch_type = fp, \ 80 77 .chroma_sample = cs, \ 81 - .is_yuv = yuv, \ 82 78 } 83 79 84 80 #define BPC0A 0

+39

drivers/gpu/drm/msm/disp/mdp_format.h

··· 1 + /* SPDX-License-Identifier: GPL-2.0-only */ 2 + /* 3 + * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 + * Copyright (C) 2013 Red Hat 5 + * Author: Rob Clark <robdclark@gmail.com> 6 + */ 7 + 8 + #ifndef __MSM_FORMAT_H__ 9 + #define __MSM_FORMAT_H__ 10 + 11 + #include "mdp_common.xml.h" 12 + 13 + enum msm_format_flags { 14 + MSM_FORMAT_FLAG_YUV_BIT, 15 + MSM_FORMAT_FLAG_DX_BIT, 16 + MSM_FORMAT_FLAG_COMPRESSED_BIT, 17 + }; 18 + 19 + #define MSM_FORMAT_FLAG_YUV BIT(MSM_FORMAT_FLAG_YUV_BIT) 20 + #define MSM_FORMAT_FLAG_DX BIT(MSM_FORMAT_FLAG_DX_BIT) 21 + #define MSM_FORMAT_FLAG_COMPRESSED BIT(MSM_FORMAT_FLAG_COMPRESSED_BIT) 22 + 23 + struct msm_format { 24 + uint32_t pixel_format; 25 + unsigned long flags; 26 + enum mdp_fetch_mode fetch_mode; 27 + }; 28 + 29 + #define MSM_FORMAT_IS_YUV(X) ((X)->flags & MSM_FORMAT_FLAG_YUV) 30 + #define MSM_FORMAT_IS_DX(X) ((X)->flags & MSM_FORMAT_FLAG_DX) 31 + #define MSM_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == MDP_FETCH_LINEAR) 32 + #define MSM_FORMAT_IS_TILE(X) \ 33 + (((X)->fetch_mode == MDP_FETCH_UBWC) && \ 34 + !((X)->flags & MSM_FORMAT_FLAG_COMPRESSED)) 35 + #define MSM_FORMAT_IS_UBWC(X) \ 36 + (((X)->fetch_mode == MDP_FETCH_UBWC) && \ 37 + ((X)->flags & MSM_FORMAT_FLAG_COMPRESSED)) 38 + 39 + #endif

+2 -2

drivers/gpu/drm/msm/disp/mdp_kms.h

··· 11 11 #include <linux/platform_device.h> 12 12 #include <linux/regulator/consumer.h> 13 13 14 + #include "mdp_format.h" 14 15 #include "msm_drv.h" 15 16 #include "msm_kms.h" 16 17 #include "mdp_common.xml.h" ··· 87 86 uint8_t cpp, unpack_count; 88 87 enum mdp_fetch_type fetch_type; 89 88 enum mdp_chroma_samp_type chroma_sample; 90 - bool is_yuv; 91 89 }; 92 90 #define to_mdp_format(x) container_of(x, struct mdp_format, base) 93 - #define MDP_FORMAT_IS_YUV(mdp_format) ((mdp_format)->is_yuv) 91 + #define MDP_FORMAT_IS_YUV(mdp_format) (MSM_FORMAT_IS_YUV(&(mdp_format)->base)) 94 92 95 93 const struct msm_format *mdp_get_format(struct msm_kms *kms, uint32_t format, uint64_t modifier); 96 94

-4

drivers/gpu/drm/msm/msm_drv.h

··· 239 239 bool disable_err_irq; 240 240 }; 241 241 242 - struct msm_format { 243 - uint32_t pixel_format; 244 - }; 245 - 246 242 struct msm_pending_timer; 247 243 248 244 int msm_atomic_init_pending_timer(struct msm_pending_timer *timer,

Configure Feed

Configure Feed