+1 -1

drivers/gpu/drm/amd/amdgpu/amdgpu.h

reviewed

··· 380 380 381 381 int amdgpu_ip_block_resume(struct amdgpu_ip_block *ip_block); 382 382 383 383 - #define AMDGPU_MAX_IP_NUM 16 383 383 + #define AMDGPU_MAX_IP_NUM AMD_IP_BLOCK_TYPE_NUM 384 384 385 385 struct amdgpu_ip_block_status { 386 386 bool valid;

+20

drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c

reviewed

··· 107 107 #include "vcn_v5_0_1.h" 108 108 #include "jpeg_v5_0_0.h" 109 109 #include "jpeg_v5_0_1.h" 110 110 + #include "amdgpu_ras_mgr.h" 110 111 111 112 #include "amdgpu_vpe.h" 112 113 #if defined(CONFIG_DRM_AMD_ISP) ··· 2394 2393 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 2395 2394 return -EINVAL; 2396 2395 } 2396 2396 + 2397 2397 + return 0; 2398 2398 + } 2399 2399 + 2400 2400 + static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 2401 2401 + { 2402 2402 + switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2403 2403 + case IP_VERSION(13, 0, 6): 2404 2404 + case IP_VERSION(13, 0, 12): 2405 2405 + case IP_VERSION(13, 0, 14): 2406 2406 + amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 2407 2407 + break; 2408 2408 + default: 2409 2409 + break; 2410 2410 + } 2397 2411 return 0; 2398 2412 } 2399 2413 ··· 3186 3170 return r; 3187 3171 3188 3172 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 3173 3173 + if (r) 3174 3174 + return r; 3175 3175 + 3176 3176 + r = amdgpu_discovery_set_ras_ip_blocks(adev); 3189 3177 if (r) 3190 3178 return r; 3191 3179

+1

drivers/gpu/drm/amd/include/amd_shared.h

reviewed

··· 109 109 AMD_IP_BLOCK_TYPE_VPE, 110 110 AMD_IP_BLOCK_TYPE_UMSCH_MM, 111 111 AMD_IP_BLOCK_TYPE_ISP, 112 112 + AMD_IP_BLOCK_TYPE_RAS, 112 113 AMD_IP_BLOCK_TYPE_NUM, 113 114 }; 114 115

+8

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.c

reviewed

··· 381 381 .hw_fini = amdgpu_ras_mgr_hw_fini, 382 382 }; 383 383 384 384 + const struct amdgpu_ip_block_version ras_v1_0_ip_block = { 385 385 + .type = AMD_IP_BLOCK_TYPE_RAS, 386 386 + .major = 1, 387 387 + .minor = 0, 388 388 + .rev = 0, 389 389 + .funcs = &ras_v1_0_ip_funcs, 390 390 + }; 391 391 + 384 392 int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable) 385 393 { 386 394 struct amdgpu_ras_mgr *ras_mgr = amdgpu_ras_mgr_get_context(adev);

+2

drivers/gpu/drm/amd/ras/ras_mgr/amdgpu_ras_mgr.h

reviewed

··· 54 54 bool ras_is_ready; 55 55 }; 56 56 57 57 + extern const struct amdgpu_ip_block_version ras_v1_0_ip_block; 58 58 + 57 59 struct amdgpu_ras_mgr *amdgpu_ras_mgr_get_context( 58 60 struct amdgpu_device *adev); 59 61 int amdgpu_enable_uniras(struct amdgpu_device *adev, bool enable);